authorgravatar for hello@nektro.netMeghan Denny <hello@nektro.net> 2026-03-14 03:42:03 -07:00
committergravatar for hello@nektro.netMeghan Denny <hello@nektro.net> 2026-03-14 03:42:03 -07:00
logfb15bf5eb1ac5d4ced4717558401b27b481fa9a8
tree1190fcdc35b93dff788055f98889596e659653d6
parent5c44c26be7735dd3f6c95dea4c2738bc679748ad
signaturebadge-check Signed by SSH key SHA256:4hHJbtBRU58AYXwjL7fkz2fnQHdiye8x1QpTCQ0sHNw

fix another linux commit

3 files changed, 39539 insertions(+), 1 deletions(-)

git.zig+2-1
......@@ -624,7 +624,8 @@ pub fn parseTreeDiff(alloc: std.mem.Allocator, input: string) !TreeDiff {
624624 const first_line = lineiter.next().?;
625625 std.debug.assert(std.mem.startsWith(u8, first_line, "diff --git"));
626626 var i = diffs.items.len;
627 for (overview.items[0..i]) |o| i -= @intFromBool(o.action == .T);
627 var n: usize = 0;
628 while (n < i) : (n += 1) i -= @intFromBool(overview.items[n].action == .T);
628629 try diffs.append(.{
629630 .index = .{ "", "" },
630631 .before_path = overview.items[i].sub_path,
test.zig+6
......@@ -256,3 +256,9 @@ test {
256256 const alloc = arena.allocator();
257257 _ = try git.parseTreeDiff(alloc, @embedFile("./testdata/diff-a0482e3446cea426bf16571e0000423ed5b25af0")); // linux
258258}
259test {
260 var arena = std.heap.ArenaAllocator.init(std.testing.allocator);
261 defer arena.deinit();
262 const alloc = arena.allocator();
263 _ = try git.parseTreeDiff(alloc, @embedFile("./testdata/diff-e90937e756938f03d37d4cae7c82316a3a425944")); // linux
264}
testdata/diff-e90937e756938f03d37d4cae7c82316a3a425944 created+39531
......@@ -0,0 +1,39531 @@
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466:100644 100644 115357018ef7c73b81c20901badfbab4da71b243 2452b2243f42465476b65891d6a0df6bc5ffda37 M arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts
467:100644 100644 cc8ebe34c27cd35e131e7a05f66a5c5a63dca7e4 ffb473ad2e0fdbad76e43e50ddcaf3eb32f30c72 M arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
468:100644 100644 bdce5b89baece0b53738deb8ff76c18f142f986b ee4aff53a5f5dc8063bf0779e23da47fe5f4e522 M arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
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470:100644 100644 494166aee24ce3c304045075c1a0938f6fdf43f2 1ca0c8620dc5ac33118a72beb5b586ab8ff0ce2f M arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
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473:000000 100644 0000000000000000000000000000000000000000 d65f746a3f9d7843761f057840786236fc8a3abd A arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
474:000000 100644 0000000000000000000000000000000000000000 384729fa740f0b3b8863e1c7c47ddfe50fb9160c A arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
475:120000 100644 4685a8d89cba2b56bcdc24e399c79a850d799491 e66d999d9f5d3a1ab87fc398ef611ef4cf048be2 T arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi
476:120000 100644 1246db9be2a1914221d74871b1e6f303884731c6 28c5b4ed1d9500fb283876ba766d826a81c44a8d T arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi
477:100644 100644 cdc6a437dcc73d33c0aaedb28df523cda333891a b87b8316f4acaecab6e5a243f2cce8ae2f1c7d31 M arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
478:100644 100644 ef1b9e573af0f5bd2ed6792ba5c9450a64ecaa45 bf552674a834140c0d574fe8b2fd3b0613c17798 M arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
479:100644 100644 54dc28351c8cb85a0abbd4bbad554d56dbcbac79 7665fbddff280fcb4be412470e551d9409d1575e M arch/arm64/boot/dts/xilinx/zynqmp.dtsi
480:100644 100644 667806620f59273bf0720e121cc033bc2fc235c7 d86c4def6bc98ebac49c49b23d7294b59cf9da07 M arch/arm64/boot/dts/zte/Makefile
481:100644 100644 bb900d2bbcfb5e6b9ca88187fc491142f359ed31 cb2519ecd724b526ff7f342b385d026f4c5808c0 M arch/arm64/boot/dts/zte/zx296718-evb.dts
482:000000 100644 0000000000000000000000000000000000000000 e02509f7082b1d69ac918e4145b43c6dc598523d A arch/arm64/boot/dts/zte/zx296718-pcbox.dts
483:100644 100644 d83bf789c8641b73f9c973e7aa0e1bdb41a62017 6eef64761009491ba768fa69919497e24d14f384 M arch/arm64/boot/dts/zte/zx296718.dtsi
484:100644 100644 a7ea5f3da89d5357c2332f8a7fe4afa609cb9997 964489b39f6a0ed6e1a98ed28f26c676db52d0d8 M drivers/clk/meson/gxbb.c
485:100644 100644 d63e77e8433d1f73fbcf52ce0122b6350c0dd15d 5b1d4b374d1c21dfa9ded8167b5e9d32bad95b77 M drivers/clk/meson/gxbb.h
486:100644 100644 6ec512ad259805c34b57be3ee96eddef149599ee cb60a516ca82bcf85d3b8334306696531ab6a597 M drivers/clk/meson/meson8b.c
487:100644 100644 a687e02547dcc9280d7bdf3bee07efd2db110e8f c139bb3273ca74a557605c987694e53980a5fb62 M drivers/clk/meson/meson8b.h
488:100644 100644 31751482d13cb498fb4989a41cb336e8c7e92e13 9d15e2221fdb7fd5f732eaa5a800f7b66112f8a5 M include/dt-bindings/clock/gxbb-aoclkc.h
489:100644 100644 e3e9f7919c318baed4063fc7199def1a6d684018 c04a76d8facff42319d708830c985bf342427627 M include/dt-bindings/clock/gxbb-clkc.h
490:100644 100644 e29227fb52a18c66b6aba5773f38fc0c872ea97d a9c0306330b6a78e910fb5b1fb9fd3dfd107b01e M include/dt-bindings/clock/meson8b-clkc.h
491:100644 100644 ae26f81059142867a009197e1c37c8e00d3dbd21 f269d833e41a32851af31a81cf09a9ff8c2ae1b8 M include/dt-bindings/clock/rv1108-cru.h
492:100644 000000 1f31f17e19ebca5e528ad9498047ec9bd973d3c4 0000000000000000000000000000000000000000 D include/dt-bindings/genpd/k2g.h
493:100644 100644 5c75e80915fcdc5b4411984cd57b8308eb388bfb 18ec5df5a5812a9f037247b6c95de1d15fba2546 M include/dt-bindings/pinctrl/dra.h
494:000000 100644 0000000000000000000000000000000000000000 1f1b56e57346e3b939a4597b9242d2aacbcbc33d A include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
495
496diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
497index 520cdd2127cf..4e4bc0bae597 100644
498--- a/Documentation/devicetree/bindings/arm/amlogic.txt
499+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
500@@ -1,6 +1,18 @@
501 Amlogic MesonX device tree bindings
502 -------------------------------------------
503
504+Work in progress statement:
505+
506+Device tree files and bindings applying to Amlogic SoCs and boards are
507+considered "unstable". Any Amlogic device tree binding may change at
508+any time. Be sure to use a device tree binary and a kernel image
509+generated from the same source tree.
510+
511+Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
512+stable binding/ABI.
513+
514+---------------------------------------------------------------
515+
516 Boards with the Amlogic Meson6 SoC shall have the following properties:
517 Required root node property:
518 compatible: "amlogic,meson6"
519diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
520index 9c97de23919a..3e3efa046ac5 100644
521--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
522+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
523@@ -42,6 +42,10 @@ Raspberry Pi Zero
524 Required root node properties:
525 compatible = "raspberrypi,model-zero", "brcm,bcm2835";
526
527+Raspberry Pi Zero W
528+Required root node properties:
529+compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
530+
531 Generic BCM2835 board
532 Required root node properties:
533 compatible = "brcm,bcm2835";
534diff --git a/Documentation/devicetree/bindings/arm/bhf.txt b/Documentation/devicetree/bindings/arm/bhf.txt
535new file mode 100644
536index 000000000000..886b503caf9c
537--- /dev/null
538+++ b/Documentation/devicetree/bindings/arm/bhf.txt
539@@ -0,0 +1,6 @@
540+Beckhoff Automation Platforms Device Tree Bindings
541+--------------------------------------------------
542+
543+CX9020 Embedded PC
544+Required root node properties:
545+ - compatible = "bhf,cx9020", "fsl,imx53";
546diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
547index a44253cad269..b92f12bd5244 100644
548--- a/Documentation/devicetree/bindings/arm/cpus.txt
549+++ b/Documentation/devicetree/bindings/arm/cpus.txt
550@@ -200,6 +200,7 @@ described below.
551 "arm,realview-smp"
552 "brcm,bcm11351-cpu-method"
553 "brcm,bcm23550"
554+ "brcm,bcm2836-smp"
555 "brcm,bcm-nsp-smp"
556 "brcm,brahma-b15"
557 "marvell,armada-375-smp"
558diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt b/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt
559new file mode 100644
560index 000000000000..f3e9624534c6
561--- /dev/null
562+++ b/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt
563@@ -0,0 +1,15 @@
564+Marvell Armada 8KPlus Platforms Device Tree Bindings
565+----------------------------------------------------
566+
567+Boards using a SoC of the Marvell Armada 8KP families must carry
568+the following root node property:
569+
570+ - compatible, with one of the following values:
571+
572+ - "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810"
573+ when the SoC being used is the Armada 8080
574+
575+Example:
576+
577+compatible = "marvell,armada-8080-db", "marvell,armada-8080",
578+ "marvell,armada-ap810-octa", "marvell,armada-ap810"
579diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
580index da7bd138e6f2..91d517849483 100644
581--- a/Documentation/devicetree/bindings/arm/mediatek.txt
582+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
583@@ -1,12 +1,12 @@
584-MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings
585+MediaTek SoC based Platforms Device Tree Bindings
586
587-Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the
588-following property:
589+Boards with a MediaTek SoC shall have the following property:
590
591 Required root node property:
592
593 compatible: Must contain one of
594 "mediatek,mt2701"
595+ "mediatek,mt2712"
596 "mediatek,mt6580"
597 "mediatek,mt6589"
598 "mediatek,mt6592"
599@@ -14,7 +14,8 @@ compatible: Must contain one of
600 "mediatek,mt6795"
601 "mediatek,mt6797"
602 "mediatek,mt7622"
603- "mediatek,mt7623"
604+ "mediatek,mt7623" which is referred to MT7623N SoC
605+ "mediatek,mt7623a"
606 "mediatek,mt8127"
607 "mediatek,mt8135"
608 "mediatek,mt8173"
609@@ -25,6 +26,9 @@ Supported boards:
610 - Evaluation board for MT2701:
611 Required root node properties:
612 - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
613+- Evaluation board for MT2712:
614+ Required root node properties:
615+ - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
616 - Evaluation board for MT6580:
617 Required root node properties:
618 - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
619@@ -46,9 +50,11 @@ Supported boards:
620 - Reference board variant 1 for MT7622:
621 Required root node properties:
622 - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
623-- Evaluation board for MT7623:
624+- Reference board for MT7623n with NAND:
625 Required root node properties:
626- - compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
627+ - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
628+- Bananapi BPI-R2 board:
629+ - compatible = "bananapi,bpi-r2", "mediatek,mt7623";
630 - MTK mt8127 tablet moose EVB:
631 Required root node properties:
632 - compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
633diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
634index 9c6bebe43449..2ecc712bf707 100644
635--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
636+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
637@@ -157,6 +157,9 @@ Boards:
638 - AM335X phyCORE-AM335x: Development kit
639 compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"
640
641+- AM335X UC-8100-ME-T: Communication-centric industrial computing platform
642+ compatible = "moxa,uc-8100-me-t", "ti,am33xx";
643+
644 - OMAP5 EVM : Evaluation Module
645 compatible = "ti,omap5-evm", "ti,omap5"
646
647@@ -187,6 +190,9 @@ Boards:
648 - AM5718 IDK
649 compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7"
650
651+- DRA762 EVM: Software Development Board for DRA762
652+ compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"
653+
654 - DRA742 EVM: Software Development Board for DRA742
655 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
656
657diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt
658index 028d16e72186..0ed4d39d7fe1 100644
659--- a/Documentation/devicetree/bindings/arm/qcom.txt
660+++ b/Documentation/devicetree/bindings/arm/qcom.txt
661@@ -25,6 +25,7 @@ The 'SoC' element must be one of the following strings:
662 msm8994
663 msm8996
664 mdm9615
665+ ipq8074
666
667 The 'board' element must be one of the following strings:
668
669@@ -33,6 +34,7 @@ The 'board' element must be one of the following strings:
670 dragonboard
671 mtp
672 sbc
673+ hk01
674
675 The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
676 where the minor number may be omitted when it's zero, i.e. v1.0 is the same
677diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
678index 11c0ac4a2d56..b003148e2945 100644
679--- a/Documentation/devicetree/bindings/arm/rockchip.txt
680+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
681@@ -134,6 +134,10 @@ Rockchip platforms device tree bindings
682 Required root node properties:
683 - compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
684
685+- Pine64 Rock64 board:
686+ Required root node properties:
687+ - compatible = "pine64,rock64", "rockchip,rk3328";
688+
689 - Rockchip PX3 Evaluation board:
690 Required root node properties:
691 - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
692@@ -173,6 +177,14 @@ Rockchip platforms device tree bindings
693 Required root node properties:
694 - compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
695
696+- Rockchip RK3399 Sapphire Excavator board:
697+ Required root node properties:
698+ - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
699+
700+- Theobroma Systems RK3399-Q7 Haikou Baseboard:
701+ Required root node properties:
702+ - compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399";
703+
704 - Tronsmart Orion R68 Meta
705 Required root node properties:
706 - compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
707diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
708index 1a671e329864..ae75cb3b1331 100644
709--- a/Documentation/devicetree/bindings/arm/shmobile.txt
710+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
711@@ -39,6 +39,8 @@ SoCs:
712 compatible = "renesas,r8a7795"
713 - R-Car M3-W (R8A77960)
714 compatible = "renesas,r8a7796"
715+ - R-Car D3 (R8A77995)
716+ compatible = "renesas,r8a77995"
717
718
719 Boards:
720@@ -53,6 +55,8 @@ Boards:
721 compatible = "renesas,blanche", "renesas,r8a7792"
722 - BOCK-W
723 compatible = "renesas,bockw", "renesas,r8a7778"
724+ - Draak (RTP0RC77995SEB0010S)
725+ compatible = "renesas,draak", "renesas,r8a77995"
726 - Genmai (RTK772100BC00000BR)
727 compatible = "renesas,genmai", "renesas,r7s72100"
728 - GR-Peach (X28A-M01-E/F)
729@@ -64,6 +68,10 @@ Boards:
730 compatible = "renesas,h3ulcb", "renesas,r8a7795";
731 - Henninger
732 compatible = "renesas,henninger", "renesas,r8a7791"
733+ - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
734+ compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
735+ - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
736+ compatible = "iwave,g22m", "renesas,r8a7745"
737 - iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
738 compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
739 - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
740diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
741index 207682647d33..b455c5aa9139 100644
742--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
743+++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
744@@ -16,18 +16,25 @@ Required Properties:
745 mapped region.
746
747 - #clock-cells: should be 1.
748+- #reset-cells: should be 1.
749
750 Each clock is assigned an identifier and client nodes can use this identifier
751 to specify the clock which they consume. All available clocks are defined as
752 preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
753 used in device tree sources.
754
755+Similarly a preprocessor macro for each reset line is defined in
756+dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
757+device tree sources).
758+
759+
760 Example: Clock controller node:
761
762 clkc: clock-controller@c1104000 {
763- #clock-cells = <1>;
764 compatible = "amlogic,meson8b-clkc";
765 reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
766+ #clock-cells = <1>;
767+ #reset-cells = <1>;
768 };
769
770
771diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
772index cb7ffc58c564..b1a8929c2536 100644
773--- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
774+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
775@@ -13,6 +13,7 @@ Required properties:
776
777 - compatible : Shall contain one or more of
778 - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
779+ - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
780 - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX
781
782 When compatible with generic versions, nodes must list the SoC-specific
783diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt
784index c6cb96a4fa93..4bbd1e9bf3be 100644
785--- a/Documentation/devicetree/bindings/display/renesas,du.txt
786+++ b/Documentation/devicetree/bindings/display/renesas,du.txt
787@@ -36,8 +36,10 @@ Required Properties:
788 When supplied they must be named "dclkin.x" with "x" being the input
789 clock numerical index.
790
791- - vsps: A list of phandles to the VSP nodes that handle the memory
792- interfaces for the DU channels.
793+ - vsps: A list of phandle and channel index tuples to the VSPs that handle
794+ the memory interfaces for the DU channels. The phandle identifies the VSP
795+ instance that serves the DU channel, and the channel index identifies the
796+ LIF instance in that VSP.
797
798 Required nodes:
799
800@@ -59,24 +61,24 @@ corresponding to each DU output.
801 R8A7796 (M3-W) DPAD HDMI LVDS -
802
803
804-Example: R8A7790 (R-Car H2) DU
805+Example: R8A7795 (R-Car H3) ES2.0 DU
806
807- du: du@feb00000 {
808- compatible = "renesas,du-r8a7790";
809- reg = <0 0xfeb00000 0 0x70000>,
810- <0 0xfeb90000 0 0x1c>,
811- <0 0xfeb94000 0 0x1c>;
812- reg-names = "du", "lvds.0", "lvds.1";
813- interrupt-parent = <&gic>;
814- interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
815- <0 268 IRQ_TYPE_LEVEL_HIGH>,
816- <0 269 IRQ_TYPE_LEVEL_HIGH>;
817- clocks = <&mstp7_clks R8A7790_CLK_DU0>,
818- <&mstp7_clks R8A7790_CLK_DU1>,
819- <&mstp7_clks R8A7790_CLK_DU2>,
820- <&mstp7_clks R8A7790_CLK_LVDS0>,
821- <&mstp7_clks R8A7790_CLK_LVDS1>;
822- clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
823+ du: display@feb00000 {
824+ compatible = "renesas,du-r8a7795";
825+ reg = <0 0xfeb00000 0 0x80000>,
826+ <0 0xfeb90000 0 0x14>;
827+ reg-names = "du", "lvds.0";
828+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
829+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
830+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
831+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
832+ clocks = <&cpg CPG_MOD 724>,
833+ <&cpg CPG_MOD 723>,
834+ <&cpg CPG_MOD 722>,
835+ <&cpg CPG_MOD 721>,
836+ <&cpg CPG_MOD 727>;
837+ clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
838+ vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
839
840 ports {
841 #address-cells = <1>;
842@@ -89,12 +91,19 @@ Example: R8A7790 (R-Car H2) DU
843 };
844 port@1 {
845 reg = <1>;
846- du_out_lvds0: endpoint {
847+ du_out_hdmi0: endpoint {
848+ remote-endpoint = <&dw_hdmi0_in>;
849 };
850 };
851 port@2 {
852 reg = <2>;
853- du_out_lvds1: endpoint {
854+ du_out_hdmi1: endpoint {
855+ remote-endpoint = <&dw_hdmi1_in>;
856+ };
857+ };
858+ port@3 {
859+ reg = <3>;
860+ du_out_lvds0: endpoint {
861 };
862 };
863 };
864diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
865index 33d9e386dc45..41f0c1a07c56 100644
866--- a/Documentation/devicetree/bindings/dma/ti-edma.txt
867+++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
868@@ -9,7 +9,12 @@ execute the actual DMA tansfer.
869 eDMA3 Channel Controller
870
871 Required properties:
872-- compatible: "ti,edma3-tpcc" for the channel controller(s)
873+--------------------
874+- compatible: Should be:
875+ - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
876+ AM33xx and AM43xx SoCs.
877+ - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
878+ channel controller(s) on 66AK2G.
879 - #dma-cells: Should be set to <2>. The first number is the DMA request
880 number and the second is the TC the channel is serviced on.
881 - reg: Memory map of eDMA CC
882@@ -19,8 +24,19 @@ Required properties:
883 - ti,tptcs: List of TPTCs associated with the eDMA in the following form:
884 <&tptc_phandle TC_priority_number>. The highest priority is 0.
885
886+SoC-specific Required properties:
887+--------------------------------
888+The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
889+- ti,hwmods: Name of the hwmods associated to the eDMA CC.
890+
891+The following are mandatory properties for 66AK2G SoCs only:
892+- power-domains:Should contain a phandle to a PM domain provider node
893+ and an args specifier containing the device id
894+ value. This property is as per the binding,
895+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
896+
897 Optional properties:
898-- ti,hwmods: Name of the hwmods associated to the eDMA CC
899+-------------------
900 - ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
901 these channels will be SW triggered channels. See example.
902 - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
903@@ -31,17 +47,34 @@ Optional properties:
904 eDMA3 Transfer Controller
905
906 Required properties:
907-- compatible: "ti,edma3-tptc" for the transfer controller(s)
908+--------------------
909+- compatible: Should be:
910+ - "ti,edma3-tptc" for the transfer controller(s) on OMAP,
911+ AM33xx and AM43xx SoCs.
912+ - "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the
913+ transfer controller(s) on 66AK2G.
914 - reg: Memory map of eDMA TC
915 - interrupts: Interrupt number for TCerrint.
916
917+SoC-specific Required properties:
918+--------------------------------
919+The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
920+- ti,hwmods: Name of the hwmods associated to the eDMA TC.
921+
922+The following are mandatory properties for 66AK2G SoCs only:
923+- power-domains:Should contain a phandle to a PM domain provider node
924+ and an args specifier containing the device id
925+ value. This property is as per the binding,
926+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
927+
928 Optional properties:
929-- ti,hwmods: Name of the hwmods associated to the given eDMA TC
930+-------------------
931 - interrupt-names: "edma3_tcerrint"
932
933 ------------------------------------------------------------------------------
934-Example:
935+Examples:
936
937+1.
938 edma: edma@49000000 {
939 compatible = "ti,edma3-tpcc";
940 ti,hwmods = "tpcc";
941@@ -108,6 +141,58 @@ mcasp0: mcasp@48038000 {
942 dma-names = "tx", "rx";
943 };
944
945+2.
946+edma1: edma@02728000 {
947+ compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
948+ reg = <0x02728000 0x8000>;
949+ reg-names = "edma3_cc";
950+ interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
951+ <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
952+ <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
953+ interrupt-names = "edma3_ccint", "emda3_mperr",
954+ "edma3_ccerrint";
955+ dma-requests = <64>;
956+ #dma-cells = <2>;
957+
958+ ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;
959+
960+ /*
961+ * memcpy is disabled, can be enabled with:
962+ * ti,edma-memcpy-channels = <12 13 14 15>;
963+ * for example.
964+ */
965+
966+ power-domains = <&k2g_pds 0x4f>;
967+};
968+
969+edma1_tptc0: tptc@027b0000 {
970+ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
971+ reg = <0x027b0000 0x400>;
972+ power-domains = <&k2g_pds 0x4f>;
973+};
974+
975+edma1_tptc1: tptc@027b8000 {
976+ compatible = "ti, k2g-edma3-tptc", "ti,edma3-tptc";
977+ reg = <0x027b8000 0x400>;
978+ power-domains = <&k2g_pds 0x4f>;
979+};
980+
981+mmc0: mmc@23000000 {
982+ compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
983+ reg = <0x23000000 0x400>;
984+ interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
985+ dmas = <&edma1 24 0>, <&edma1 25 0>;
986+ dma-names = "tx", "rx";
987+ bus-width = <4>;
988+ ti,needs-special-reset;
989+ no-1-8-v;
990+ max-frequency = <96000000>;
991+ power-domains = <&k2g_pds 0xb>;
992+ clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
993+ clock-names = "fck", "mmchsdb_fck";
994+ status = "disabled";
995+};
996+
997 ------------------------------------------------------------------------------
998 DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
999 binding.
1000diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
1001index 5aa5926029ee..039219df05c5 100644
1002--- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
1003+++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
1004@@ -17,6 +17,7 @@ Required properties:
1005 * which must be preceded by one of the following vendor specifics:
1006 + "amlogic,meson-gxm-mali"
1007 + "rockchip,rk3288-mali"
1008+ + "rockchip,rk3399-mali"
1009
1010 - reg : Physical base address of the device and length of the register area.
1011
1012diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
1013index 11cc87aeb276..07bf0b9a5139 100644
1014--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
1015+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
1016@@ -17,6 +17,7 @@ Required properties:
1017 "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
1018 "mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
1019 "mediatek,mt6577-sysirq": for MT6577
1020+ "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
1021 "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
1022 - interrupt-controller : Identifies the node as an interrupt controller
1023 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
1024diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
1025index 0e026c151c1c..3a4ac401e6f9 100644
1026--- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
1027+++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
1028@@ -1,33 +1,55 @@
1029-* TI Highspeed MMC host controller for OMAP
1030+* TI Highspeed MMC host controller for OMAP and 66AK2G family.
1031
1032-The Highspeed MMC Host Controller on TI OMAP family
1033+The Highspeed MMC Host Controller on TI OMAP and 66AK2G family
1034 provides an interface for MMC, SD, and SDIO types of memory cards.
1035
1036 This file documents differences between the core properties described
1037 by mmc.txt and the properties used by the omap_hsmmc driver.
1038
1039 Required properties:
1040+--------------------
1041 - compatible:
1042 Should be "ti,omap2-hsmmc", for OMAP2 controllers
1043 Should be "ti,omap3-hsmmc", for OMAP3 controllers
1044 Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
1045 Should be "ti,omap4-hsmmc", for OMAP4 controllers
1046 Should be "ti,am33xx-hsmmc", for AM335x controllers
1047-- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
1048+ Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers.
1049+
1050+SoC specific required properties:
1051+---------------------------------
1052+The following are mandatory properties for OMAPs, AM33xx and AM43xx SoCs only:
1053+- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1.
1054+
1055+The following are mandatory properties for 66AK2G SoCs only:
1056+- power-domains:Should contain a phandle to a PM domain provider node
1057+ and an args specifier containing the MMC device id
1058+ value. This property is as per the binding,
1059+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
1060+- clocks: Must contain an entry for each entry in clock-names. Should
1061+ be defined as per the he appropriate clock bindings consumer
1062+ usage in Documentation/devicetree/bindings/clock/ti,sci-clk.txt
1063+- clock-names: Shall be "fck" for the functional clock,
1064+ and "mmchsdb_fck" for the debounce clock.
1065+
1066
1067 Optional properties:
1068-ti,dual-volt: boolean, supports dual voltage cards
1069-<supply-name>-supply: phandle to the regulator device tree node
1070-"supply-name" examples are "vmmc", "vmmc_aux"(deprecated)/"vqmmc" etc
1071-ti,non-removable: non-removable slot (like eMMC)
1072-ti,needs-special-reset: Requires a special softreset sequence
1073-ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
1074-dmas: List of DMA specifiers with the controller specific format
1075-as described in the generic DMA client binding. A tx and rx
1076-specifier is required.
1077-dma-names: List of DMA request names. These strings correspond
1078-1:1 with the DMA specifiers listed in dmas. The string naming is
1079-to be "rx" and "tx" for RX and TX DMA requests, respectively.
1080+--------------------
1081+- ti,dual-volt: boolean, supports dual voltage cards
1082+- <supply-name>-supply: phandle to the regulator device tree node
1083+ "supply-name" examples are "vmmc",
1084+ "vmmc_aux"(deprecated)/"vqmmc" etc
1085+- ti,non-removable: non-removable slot (like eMMC)
1086+- ti,needs-special-reset: Requires a special softreset sequence
1087+- ti,needs-special-hs-handling: HSMMC IP needs special setting
1088+ for handling High Speed
1089+- dmas: List of DMA specifiers with the controller specific
1090+ format as described in the generic DMA client
1091+ binding. A tx and rx specifier is required.
1092+- dma-names: List of DMA request names. These strings correspond
1093+ 1:1 with the DMA specifiers listed in dmas.
1094+ The string naming is to be "rx" and "tx" for
1095+ RX and TX DMA requests, respectively.
1096
1097 Examples:
1098
1099diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt
1100index 5a1d8b0c39e9..2d504256b0d8 100644
1101--- a/Documentation/devicetree/bindings/net/can/c_can.txt
1102+++ b/Documentation/devicetree/bindings/net/can/c_can.txt
1103@@ -11,9 +11,20 @@ Required properties:
1104 - interrupts : property with a value describing the interrupt
1105 number
1106
1107-Optional properties:
1108+The following are mandatory properties for DRA7x, AM33xx and AM43xx SoCs only:
1109 - ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the
1110 instance number
1111+
1112+The following are mandatory properties for Keystone 2 66AK2G SoCs only:
1113+- power-domains : Should contain a phandle to a PM domain provider node
1114+ and an args specifier containing the DCAN device id
1115+ value. This property is as per the binding,
1116+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
1117+- clocks : CAN functional clock phandle. This property is as per the
1118+ binding,
1119+ Documentation/devicetree/bindings/clock/ti,sci-clk.txt
1120+
1121+Optional properties:
1122 - syscon-raminit : Handle to system control region that contains the
1123 RAMINIT register, register offset to the RAMINIT
1124 register and the CAN instance number (0 offset).
1125diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
1126index 1d1168b805cc..214eaa9a6683 100644
1127--- a/Documentation/devicetree/bindings/net/mediatek-net.txt
1128+++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
1129@@ -20,8 +20,10 @@ Required properties:
1130 "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m",
1131 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC
1132 - power-domains: phandle to the power domain that the ethernet is part of
1133-- resets: Should contain a phandle to the ethsys reset signal
1134-- reset-names: Should contain the reset signal name "eth"
1135+- resets: Should contain phandles to the ethsys reset signals
1136+- reset-names: Should contain the names of reset signal listed in the resets
1137+ property
1138+ These are "fe", "gmac" and "ppe"
1139 - mediatek,ethsys: phandle to the syscon node that handles the port setup
1140 - mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup
1141 which is required for those SoCs equipped with SGMII such as MT7622 SoC.
1142diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
1143index 127ae1f53e5a..6173af6885f8 100644
1144--- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
1145+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
1146@@ -276,7 +276,7 @@ pcie-controller {
1147 clocks = <&gateclk 26>;
1148 };
1149
1150- pcie@10,0 {
1151+ pcie@a,0 {
1152 device_type = "pci";
1153 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
1154 reg = <0x5000 0 0 0 0>;
1155diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt
1156index 84404c9edff7..af21502e939c 100644
1157--- a/Documentation/devicetree/bindings/power/renesas,apmu.txt
1158+++ b/Documentation/devicetree/bindings/power/renesas,apmu.txt
1159@@ -1,12 +1,13 @@
1160 DT bindings for the Renesas Advanced Power Management Unit
1161
1162-Renesas R-Car line of SoCs utilize one or more APMU hardware units
1163+Renesas R-Car and RZ/G1 SoCs utilize one or more APMU hardware units
1164 for CPU core power domain control including SMP boot and CPU Hotplug.
1165
1166 Required properties:
1167
1168 - compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
1169 Examples with soctypes are:
1170+ - "renesas,r8a7743-apmu" (RZ/G1M)
1171 - "renesas,r8a7790-apmu" (R-Car H2)
1172 - "renesas,r8a7791-apmu" (R-Car M2-W)
1173 - "renesas,r8a7792-apmu" (R-Car V2H)
1174diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
1175index b6cf384597e1..f73abff3de43 100644
1176--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
1177+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
1178@@ -3,6 +3,7 @@
1179 Required properties:
1180 - compatible should contain:
1181 * "mediatek,mt2701-uart" for MT2701 compatible UARTS
1182+ * "mediatek,mt2712-uart" for MT2712 compatible UARTS
1183 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
1184 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
1185 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
1186diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
1187index cc9f05d3cbc1..7dc5ce858a0e 100644
1188--- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
1189+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
1190@@ -21,6 +21,7 @@ Required Properties:
1191 - "rockchip,rk3328-grf", "syscon": for rk3328
1192 - "rockchip,rk3368-grf", "syscon": for rk3368
1193 - "rockchip,rk3399-grf", "syscon": for rk3399
1194+ - "rockchip,rv1108-grf", "syscon": for rv1108
1195 - compatible: PMUGRF should be one of the following:
1196 - "rockchip,rk3368-pmugrf", "syscon": for rk3368
1197 - "rockchip,rk3399-pmugrf", "syscon": for rk3399
1198@@ -28,6 +29,8 @@ Required Properties:
1199 - "rockchip,rk3288-sgrf", "syscon": for rk3288
1200 - compatible: USB2PHYGRF should be one of the followings
1201 - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
1202+- compatible: USBGRF should be one of the following
1203+ - "rockchip,rv1108-usbgrf", "syscon": for rv1108
1204 - reg: physical base address of the controller and length of memory mapped
1205 region.
1206
1207diff --git a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
1208index c705db07d820..66e6265fb0aa 100644
1209--- a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
1210+++ b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
1211@@ -46,12 +46,13 @@ Required Properties:
1212 - power-domains: phandle pointing to the corresponding PM domain node
1213 and an ID representing the device.
1214
1215-See dt-bindings/genpd/k2g.h for the list of valid identifiers for k2g.
1216+See http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data for the list
1217+of valid identifiers for k2g.
1218
1219 Example (K2G):
1220 --------------------
1221 uart0: serial@02530c00 {
1222 compatible = "ns16550a";
1223 ...
1224- power-domains = <&k2g_pds K2G_DEV_UART0>;
1225+ power-domains = <&k2g_pds 0x002c>;
1226 };
1227diff --git a/Documentation/devicetree/bindings/sram/renesas,smp-sram.txt b/Documentation/devicetree/bindings/sram/renesas,smp-sram.txt
1228new file mode 100644
1229index 000000000000..712d05e3e15e
1230--- /dev/null
1231+++ b/Documentation/devicetree/bindings/sram/renesas,smp-sram.txt
1232@@ -0,0 +1,27 @@
1233+* Renesas SMP SRAM
1234+
1235+Renesas R-Car Gen2 and RZ/G1 SoCs need a small piece of SRAM for the jump stub
1236+for secondary CPU bringup and CPU hotplug.
1237+This memory is reserved by adding a child node to a "mmio-sram" node, cfr.
1238+Documentation/devicetree/bindings/sram/sram.txt.
1239+
1240+Required child node properties:
1241+ - compatible: Must be "renesas,smp-sram",
1242+ - reg: Address and length of the reserved SRAM.
1243+ The full physical (bus) address must be aligned to a 256 KiB boundary.
1244+
1245+
1246+Example:
1247+
1248+ icram1: sram@e63c0000 {
1249+ compatible = "mmio-sram";
1250+ reg = <0 0xe63c0000 0 0x1000>;
1251+ #address-cells = <1>;
1252+ #size-cells = <1>;
1253+ ranges = <0 0 0xe63c0000 0x1000>;
1254+
1255+ smp-sram@0 {
1256+ compatible = "renesas,smp-sram";
1257+ reg = <0 0x10>;
1258+ };
1259+ };
1260diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
1261index 5a79aeb620b3..69183f0fbc78 100644
1262--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
1263+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
1264@@ -48,6 +48,7 @@ avic Shanghai AVIC Optoelectronics Co., Ltd.
1265 axentia Axentia Technologies AB
1266 axis Axis Communications AB
1267 bananapi BIPAI KEJI LIMITED
1268+bhf Beckhoff Automation GmbH & Co. KG
1269 boe BOE Technology Group Co., Ltd.
1270 bosch Bosch Sensortec GmbH
1271 boundary Boundary Devices Inc.
1272diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
1273index 6a00939a059a..20ada673ab0c 100644
1274--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
1275+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
1276@@ -3,9 +3,9 @@ Mediatek SoCs Watchdog timer
1277 Required properties:
1278
1279 - compatible should contain:
1280- * "mediatek,mt2701-wdt" for MT2701 compatible watchdog timers
1281- * "mediatek,mt6589-wdt" for all compatible watchdog timers (MT2701,
1282- MT6589)
1283+ "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
1284+ "mediatek,mt6589-wdt": for MT6589
1285+ "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
1286
1287 - reg : Specifies base physical address and size of the registers.
1288
1289diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
1290index 4b17f35dc9a7..faf46abaa4a2 100644
1291--- a/arch/arm/boot/dts/Makefile
1292+++ b/arch/arm/boot/dts/Makefile
1293@@ -46,6 +46,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
1294 at91sam9x35ek.dtb
1295 dtb-$(CONFIG_SOC_SAM_V7) += \
1296 at91-kizbox2.dtb \
1297+ at91-sama5d27_som1_ek.dtb \
1298 at91-sama5d2_xplained.dtb \
1299 at91-sama5d3_xplained.dtb \
1300 at91-tse850-3.dtb \
1301@@ -73,7 +74,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
1302 bcm2835-rpi-a-plus.dtb \
1303 bcm2836-rpi-2-b.dtb \
1304 bcm2837-rpi-3-b.dtb \
1305- bcm2835-rpi-zero.dtb
1306+ bcm2835-rpi-zero.dtb \
1307+ bcm2835-rpi-zero-w.dtb
1308 dtb-$(CONFIG_ARCH_BCM_5301X) += \
1309 bcm4708-asus-rt-ac56u.dtb \
1310 bcm4708-asus-rt-ac68u.dtb \
1311@@ -106,7 +108,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
1312 bcm953012hr.dtb \
1313 bcm953012k.dtb
1314 dtb-$(CONFIG_ARCH_BCM_53573) += \
1315- bcm47189-tenda-ac9.dtb
1316+ bcm47189-tenda-ac9.dtb \
1317+ bcm947189acdbmr.dtb
1318 dtb-$(CONFIG_ARCH_BCM_63XX) += \
1319 bcm963138dvt.dtb
1320 dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
1321@@ -180,6 +183,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
1322 exynos5440-ssdk5440.dtb \
1323 exynos5800-peach-pi.dtb
1324 dtb-$(CONFIG_ARCH_GEMINI) += \
1325+ gemini-dlink-dir-685.dtb \
1326 gemini-nas4220b.dtb \
1327 gemini-rut1xx.dtb \
1328 gemini-sq201.dtb \
1329@@ -340,6 +344,7 @@ dtb-$(CONFIG_SOC_IMX51) += \
1330 imx51-ts4800.dtb
1331 dtb-$(CONFIG_SOC_IMX53) += \
1332 imx53-ard.dtb \
1333+ imx53-cx9020.dtb \
1334 imx53-m53evk.dtb \
1335 imx53-mba53.dtb \
1336 imx53-qsb.dtb \
1337@@ -391,7 +396,9 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
1338 imx6dl-udoo.dtb \
1339 imx6dl-wandboard.dtb \
1340 imx6dl-wandboard-revb1.dtb \
1341+ imx6q-apalis-eval.dtb \
1342 imx6q-apalis-ixora.dtb \
1343+ imx6q-apalis-ixora-v1.1.dtb \
1344 imx6q-apf6dev.dtb \
1345 imx6q-arm2.dtb \
1346 imx6q-b450v3.dtb \
1347@@ -466,7 +473,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
1348 imx6sx-udoo-neo-full.dtb
1349 dtb-$(CONFIG_SOC_IMX6UL) += \
1350 imx6ul-14x14-evk.dtb \
1351- imx6ul-geam-kit.dtb \
1352+ imx6ul-geam.dtb \
1353 imx6ul-isiot-emmc.dtb \
1354 imx6ul-isiot-nand.dtb \
1355 imx6ul-liteboard.dtb \
1356@@ -617,6 +624,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
1357 am335x-evmsk.dtb \
1358 am335x-icev2.dtb \
1359 am335x-lxm.dtb \
1360+ am335x-moxa-uc-8100-me-t.dtb \
1361 am335x-nano.dtb \
1362 am335x-pepper.dtb \
1363 am335x-phycore-rdk.dtb \
1364@@ -650,6 +658,7 @@ dtb-$(CONFIG_SOC_OMAP5) += \
1365 dtb-$(CONFIG_SOC_DRA7XX) += \
1366 am57xx-beagle-x15.dtb \
1367 am57xx-beagle-x15-revb1.dtb \
1368+ am57xx-beagle-x15-revc.dtb \
1369 am57xx-cl-som-am57x.dtb \
1370 am57xx-sbc-am57x.dtb \
1371 am572x-idk.dtb \
1372@@ -657,7 +666,8 @@ dtb-$(CONFIG_SOC_DRA7XX) += \
1373 dra7-evm.dtb \
1374 dra72-evm.dtb \
1375 dra72-evm-revc.dtb \
1376- dra71-evm.dtb
1377+ dra71-evm.dtb \
1378+ dra76-evm.dtb
1379 dtb-$(CONFIG_ARCH_ORION5X) += \
1380 orion5x-kuroboxpro.dtb \
1381 orion5x-lacie-d2-network.dtb \
1382@@ -903,6 +913,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
1383 sun8i-a33-q8-tablet.dtb \
1384 sun8i-a33-sinlinx-sina33.dtb \
1385 sun8i-a83t-allwinner-h8homlet-v2.dtb \
1386+ sun8i-a83t-bananapi-m3.dtb \
1387 sun8i-a83t-cubietruck-plus.dtb \
1388 sun8i-h2-plus-orangepi-zero.dtb \
1389 sun8i-h3-bananapi-m2-plus.dtb \
1390@@ -918,6 +929,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
1391 sun8i-h3-orangepi-pc-plus.dtb \
1392 sun8i-h3-orangepi-plus.dtb \
1393 sun8i-h3-orangepi-plus2e.dtb \
1394+ sun8i-r16-bananapi-m2m.dtb \
1395 sun8i-r16-parrot.dtb \
1396 sun8i-v3s-licheepi-zero.dtb \
1397 sun8i-v3s-licheepi-zero-dock.dtb
1398@@ -970,7 +982,6 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
1399 uniphier-pro4-sanji.dtb \
1400 uniphier-pxs2-gentil.dtb \
1401 uniphier-pxs2-vodka.dtb \
1402- uniphier-sld3-ref.dtb \
1403 uniphier-sld8-ref.dtb
1404 dtb-$(CONFIG_ARCH_VERSATILE) += \
1405 versatile-ab.dtb \
1406@@ -1049,7 +1060,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
1407 mt6580-evbp1.dtb \
1408 mt6589-aquaris5.dtb \
1409 mt6592-evb.dtb \
1410- mt7623-evb.dtb \
1411+ mt7623n-rfb-nand.dtb \
1412+ mt7623n-bananapi-bpi-r2.dtb \
1413 mt8127-moose.dtb \
1414 mt8135-evbp1.dtb
1415 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
1416diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
1417index 1d154444dfef..48a15fc641f2 100644
1418--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
1419+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
1420@@ -319,13 +319,10 @@ &tps {
1421 ti,pmic-shutdown-controller;
1422
1423 charger {
1424- interrupts = <0>, <1>;
1425- interrupt-names = "USB", "AC";
1426 status = "okay";
1427 };
1428
1429 pwrbutton {
1430- interrupts = <2>;
1431 status = "okay";
1432 };
1433
1434diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts
1435index d8769799772e..59431b235944 100644
1436--- a/arch/arm/boot/dts/am335x-chiliboard.dts
1437+++ b/arch/arm/boot/dts/am335x-chiliboard.dts
1438@@ -191,13 +191,10 @@ &tps {
1439 interrupts = <7>; /* NNMI */
1440
1441 charger {
1442- interrupts = <0>, <1>;
1443- interrupt-names = "USB", "AC";
1444 status = "okay";
1445 };
1446
1447 pwrbutton {
1448- interrupts = <2>;
1449 status = "okay";
1450 };
1451 };
1452diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
1453index 1c37a7c1ea17..ddd897556e03 100644
1454--- a/arch/arm/boot/dts/am335x-evm.dts
1455+++ b/arch/arm/boot/dts/am335x-evm.dts
1456@@ -531,6 +531,7 @@ nand@0,0 {
1457 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
1458 <1 IRQ_TYPE_NONE>; /* termcount */
1459 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
1460+ ti,nand-xfer-type = "prefetch-dma";
1461 ti,nand-ecc-opt = "bch8";
1462 ti,elm-id = <&elm>;
1463 nand-bus-width = <8>;
1464diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
1465new file mode 100644
1466index 000000000000..f82233cd18e0
1467--- /dev/null
1468+++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
1469@@ -0,0 +1,525 @@
1470+/*
1471+ * Copyright (C) 2017 MOXA Inc. - https://www.moxa.com/
1472+ *
1473+ * Author: SZ Lin (林上智) <sz.lin@moxa.com>
1474+ *
1475+ * This program is free software; you can redistribute it and/or modify
1476+ * it under the terms of the GNU General Public License version 2 as
1477+ * published by the Free Software Foundation.
1478+ */
1479+
1480+/dts-v1/;
1481+
1482+#include "am33xx.dtsi"
1483+
1484+/ {
1485+ model = "Moxa UC-8100-ME-T";
1486+ compatible = "moxa,uc-8100-me-t", "ti,am33xx";
1487+
1488+ cpus {
1489+ cpu@0 {
1490+ cpu0-supply = <&vdd1_reg>;
1491+ };
1492+ };
1493+
1494+ memory {
1495+ device_type = "memory";
1496+ reg = <0x80000000 0x20000000>; /* 512 MB */
1497+ };
1498+
1499+ vbat: vbat-regulator {
1500+ compatible = "regulator-fixed";
1501+ };
1502+
1503+ /* Power supply provides a fixed 3.3V @3A */
1504+ vmmcsd_fixed: vmmcsd-regulator {
1505+ compatible = "regulator-fixed";
1506+ regulator-name = "vmmcsd_fixed";
1507+ regulator-min-microvolt = <3300000>;
1508+ regulator-max-microvolt = <3300000>;
1509+ regulator-boot-on;
1510+ };
1511+
1512+ leds {
1513+ compatible = "gpio-leds";
1514+ led1 {
1515+ label = "uc8100me:CEL1";
1516+ gpios = <&gpio_xten 8 0>;
1517+ default-state = "off";
1518+ };
1519+
1520+ led2 {
1521+ label = "uc8100me:CEL2";
1522+ gpios = <&gpio_xten 9 0>;
1523+ default-state = "off";
1524+ };
1525+
1526+ led3 {
1527+ label = "uc8100me:CEL3";
1528+ gpios = <&gpio_xten 10 0>;
1529+ default-state = "off";
1530+ };
1531+
1532+ led4 {
1533+ label = "uc8100me:DIA1";
1534+ gpios = <&gpio_xten 11 0>;
1535+ default-state = "off";
1536+ };
1537+ led5 {
1538+ label = "uc8100me:DIA2";
1539+ gpios = <&gpio_xten 12 0>;
1540+ default-state = "off";
1541+ };
1542+ led6 {
1543+ label = "uc8100me:DIA3";
1544+ gpios = <&gpio_xten 13 0>;
1545+ default-state = "off";
1546+ };
1547+ led7 {
1548+ label = "uc8100me:SD";
1549+ gpios = <&gpio_xten 14 0>;
1550+ default-state = "off";
1551+ };
1552+ led8 {
1553+ label = "uc8100me:USB";
1554+ gpios = <&gpio_xten 15 0>;
1555+ default-state = "off";
1556+ };
1557+ led9 {
1558+ label = "uc8100me:USER";
1559+ gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
1560+ default-state = "off";
1561+ };
1562+ };
1563+
1564+ buttons: push_button {
1565+ compatible = "gpio-keys";
1566+ };
1567+
1568+};
1569+
1570+&am33xx_pinmux {
1571+ pinctrl-names = "default";
1572+ pinctrl-0 = <&minipcie_pins>;
1573+
1574+ minipcie_pins: pinmux_minipcie {
1575+ pinctrl-single,pins = <
1576+ AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2_24 */
1577+ AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */
1578+ AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/
1579+ >;
1580+ };
1581+
1582+ push_button_pins: pinmux_push_button {
1583+ pinctrl-single,pins = <
1584+ AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */
1585+ >;
1586+ };
1587+
1588+ i2c0_pins: pinmux_i2c0_pins {
1589+ pinctrl-single,pins = <
1590+ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
1591+ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
1592+ >;
1593+ };
1594+
1595+
1596+ i2c1_pins: pinmux_i2c1_pins {
1597+ pinctrl-single,pins = <
1598+ AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_ctsn.i2c1_sda */
1599+ AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_rtsn.i2c1_scl */
1600+ >;
1601+ };
1602+
1603+ uart0_pins: pinmux_uart0_pins {
1604+ pinctrl-single,pins = <
1605+ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
1606+ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
1607+ >;
1608+ };
1609+
1610+ uart1_pins: pinmux_uart1_pins {
1611+ pinctrl-single,pins = <
1612+ AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
1613+ AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
1614+ AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
1615+ AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */
1616+ >;
1617+ };
1618+
1619+ uart2_pins: pinmux_uart2_pins {
1620+ pinctrl-single,pins = <
1621+ AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE6) /* lcd_data14.uart5_ctsn */
1622+ AM33XX_IOPAD(0x8dc, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* lcd_data15.uart5_rtsn */
1623+ AM33XX_IOPAD(0x8c4, PIN_INPUT_PULLUP | MUX_MODE4) /* lcd_data9.uart5_rxd */
1624+ AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE4) /* lcd_data8.uart5_txd */
1625+ >;
1626+ };
1627+
1628+ cpsw_default: cpsw_default {
1629+ pinctrl-single,pins = <
1630+ /* Slave 1 */
1631+ AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
1632+ AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
1633+ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
1634+ AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
1635+ AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
1636+ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
1637+ AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
1638+ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_refclk.rmii1_refclk */
1639+
1640+ /* Slave 2 */
1641+ AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */
1642+ AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */
1643+ AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */
1644+ AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */
1645+ AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */
1646+ AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */
1647+ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */
1648+ AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */
1649+
1650+ >;
1651+ };
1652+
1653+ davinci_mdio_default: davinci_mdio_default {
1654+ pinctrl-single,pins = <
1655+ /* MDIO */
1656+ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
1657+ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
1658+ >;
1659+ };
1660+
1661+ mmc0_pins_default: pinmux_mmc0_pins {
1662+ pinctrl-single,pins = <
1663+ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
1664+ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
1665+ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
1666+ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
1667+ AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
1668+ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
1669+ AM33XX_IOPAD(0x990, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */
1670+ AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */
1671+ >;
1672+ };
1673+
1674+ mmc2_pins_default: pinmux_mmc2_pins {
1675+ pinctrl-single,pins = <
1676+ /* eMMC */
1677+ AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */
1678+ AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */
1679+ AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */
1680+ AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */
1681+ AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */
1682+ AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */
1683+ AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */
1684+ AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */
1685+ AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
1686+ AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
1687+ >;
1688+ };
1689+
1690+ spi0_pins: pinmux_spi0 {
1691+ pinctrl-single,pins = <
1692+ AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
1693+ AM33XX_IOPAD(0x95C, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
1694+ AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
1695+ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
1696+ >;
1697+ };
1698+
1699+};
1700+
1701+&uart0 {
1702+ /* Console */
1703+ status = "okay";
1704+ pinctrl-names = "default";
1705+ pinctrl-0 = <&uart0_pins>;
1706+};
1707+
1708+&uart1 {
1709+ /* UART 1 setting */
1710+ status = "okay";
1711+ pinctrl-names = "default";
1712+ pinctrl-0 = <&uart1_pins>;
1713+};
1714+
1715+&uart5 {
1716+ /* UART 2 setting */
1717+ status = "okay";
1718+ pinctrl-names = "default";
1719+ pinctrl-0 = <&uart2_pins>;
1720+};
1721+
1722+&i2c0 {
1723+ pinctrl-names = "default";
1724+ pinctrl-0 = <&i2c0_pins>;
1725+
1726+ status = "okay";
1727+ clock-frequency = <400000>;
1728+
1729+ tpm: tpm@20 {
1730+ compatible = "infineon,slb9645tt";
1731+ reg = <0x20>;
1732+ };
1733+
1734+ tps: tps@2d {
1735+ compatible = "ti,tps65910";
1736+ reg = <0x2d>;
1737+ };
1738+
1739+ eeprom: eeprom@50 {
1740+ compatible = "atmel,24c16";
1741+ pagesize = <16>;
1742+ reg = <0x50>;
1743+ };
1744+
1745+ rtc_wdt: rtc_wdt@68 {
1746+ compatible = "dallas,ds1374";
1747+ reg = <0x68>;
1748+ };
1749+};
1750+
1751+&i2c1 {
1752+ pinctrl-names = "default";
1753+ pinctrl-0 = <&i2c1_pins>;
1754+
1755+ status = "okay";
1756+ clock-frequency = <400000>;
1757+ gpio_xten: gpio_xten@27 {
1758+ compatible = "nxp,pca9535";
1759+ gpio-controller;
1760+ #gpio-cells = <2>;
1761+ reg = <0x27>;
1762+ };
1763+};
1764+
1765+&usb {
1766+ status = "okay";
1767+};
1768+
1769+&usb_ctrl_mod {
1770+ status = "okay";
1771+};
1772+
1773+&usb0_phy {
1774+ status = "okay";
1775+};
1776+
1777+&usb1_phy {
1778+ status = "okay";
1779+};
1780+
1781+&usb0 {
1782+ status = "okay";
1783+ dr_mode = "host";
1784+};
1785+
1786+&usb1 {
1787+ status = "okay";
1788+ dr_mode = "host";
1789+};
1790+
1791+&cppi41dma {
1792+ status = "okay";
1793+};
1794+
1795+#include "tps65910.dtsi"
1796+
1797+&tps {
1798+ vcc1-supply = <&vbat>;
1799+ vcc2-supply = <&vbat>;
1800+ vcc3-supply = <&vbat>;
1801+ vcc4-supply = <&vbat>;
1802+ vcc5-supply = <&vbat>;
1803+ vcc6-supply = <&vbat>;
1804+ vcc7-supply = <&vbat>;
1805+ vccio-supply = <&vbat>;
1806+
1807+ regulators {
1808+ vrtc_reg: regulator@0 {
1809+ regulator-always-on;
1810+ };
1811+
1812+ vio_reg: regulator@1 {
1813+ regulator-always-on;
1814+ };
1815+
1816+ vdd1_reg: regulator@2 {
1817+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
1818+ regulator-name = "vdd_mpu";
1819+ regulator-min-microvolt = <912500>;
1820+ regulator-max-microvolt = <1378000>;
1821+ regulator-boot-on;
1822+ regulator-always-on;
1823+ };
1824+
1825+ vdd2_reg: regulator@3 {
1826+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
1827+ regulator-name = "vdd_core";
1828+ regulator-min-microvolt = <912500>;
1829+ regulator-max-microvolt = <1150000>;
1830+ regulator-boot-on;
1831+ regulator-always-on;
1832+ };
1833+
1834+ vdd3_reg: regulator@4 {
1835+ regulator-always-on;
1836+ };
1837+
1838+ vdig1_reg: regulator@5 {
1839+ regulator-always-on;
1840+ };
1841+
1842+ vdig2_reg: regulator@6 {
1843+ regulator-always-on;
1844+ };
1845+
1846+ vpll_reg: regulator@7 {
1847+ regulator-always-on;
1848+ };
1849+
1850+ vdac_reg: regulator@8 {
1851+ regulator-always-on;
1852+ };
1853+
1854+ vaux1_reg: regulator@9 {
1855+ regulator-always-on;
1856+ };
1857+
1858+ vaux2_reg: regulator@10 {
1859+ regulator-always-on;
1860+ };
1861+
1862+ vaux33_reg: regulator@11 {
1863+ regulator-always-on;
1864+ };
1865+
1866+ vmmc_reg: regulator@12 {
1867+ compatible = "regulator-fixed";
1868+ regulator-name = "vmmc_reg";
1869+ regulator-min-microvolt = <3300000>;
1870+ regulator-max-microvolt = <3300000>;
1871+ regulator-always-on;
1872+ };
1873+ };
1874+};
1875+
1876+/* Power */
1877+&vbat {
1878+ regulator-name = "vbat";
1879+ regulator-min-microvolt = <5000000>;
1880+ regulator-max-microvolt = <5000000>;
1881+};
1882+
1883+&mac {
1884+ pinctrl-names = "default";
1885+ pinctrl-0 = <&cpsw_default>;
1886+ dual_emac = <1>;
1887+ status = "okay";
1888+};
1889+
1890+&davinci_mdio {
1891+ pinctrl-names = "default";
1892+ pinctrl-0 = <&davinci_mdio_default>;
1893+ status = "okay";
1894+};
1895+
1896+&cpsw_emac0 {
1897+ status = "okay";
1898+ phy_id = <&davinci_mdio>, <4>;
1899+ phy-mode = "rmii";
1900+ dual_emac_res_vlan = <1>;
1901+};
1902+
1903+&cpsw_emac1 {
1904+ status = "okay";
1905+ phy_id = <&davinci_mdio>, <5>;
1906+ phy-mode = "rmii";
1907+ dual_emac_res_vlan = <2>;
1908+};
1909+
1910+&phy_sel {
1911+ reg= <0x44e10650 0xf5>;
1912+ rmii-clock-ext;
1913+};
1914+
1915+&sham {
1916+ status = "okay";
1917+};
1918+
1919+&aes {
1920+ status = "okay";
1921+};
1922+
1923+&gpio0 {
1924+ ti,no-reset-on-init;
1925+};
1926+
1927+&mmc1 {
1928+ pinctrl-names = "default";
1929+ vmmc-supply = <&vmmcsd_fixed>;
1930+ bus-width = <4>;
1931+ pinctrl-0 = <&mmc0_pins_default>;
1932+ cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
1933+ wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
1934+ status = "okay";
1935+};
1936+
1937+&mmc3 {
1938+ dmas = <&edma_xbar 12 0 1
1939+ &edma_xbar 13 0 2>;
1940+ dma-names = "tx", "rx";
1941+ pinctrl-names = "default";
1942+ vmmc-supply = <&vmmcsd_fixed>;
1943+ bus-width = <8>;
1944+ pinctrl-0 = <&mmc2_pins_default>;
1945+ ti,non-removable;
1946+ status = "okay";
1947+};
1948+
1949+&buttons {
1950+ pinctrl-names = "default";
1951+ pinctrl-0 = <&push_button_pins>;
1952+ #address-cells = <1>;
1953+ #size-cells = <0>;
1954+
1955+ button@0 {
1956+ label = "push_button";
1957+ linux,code = <0x100>;
1958+ gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
1959+ };
1960+};
1961+
1962+/* SPI Busses */
1963+&spi0 {
1964+ status = "okay";
1965+ pinctrl-names = "default";
1966+ pinctrl-0 = <&spi0_pins>;
1967+
1968+ m25p80@0 {
1969+ compatible = "mx25l6405d";
1970+ spi-max-frequency = <40000000>;
1971+
1972+ reg = <0>;
1973+ spi-cpol;
1974+ spi-cpha;
1975+ #address-cells = <1>;
1976+ #size-cells = <1>;
1977+
1978+ /* reg : The partition's offset and size within the mtd bank. */
1979+ partitions@0 {
1980+ label = "MLO";
1981+ reg = <0x0 0x80000>;
1982+ };
1983+
1984+ partitions@1 {
1985+ label = "U-Boot";
1986+ reg = <0x80000 0x100000>;
1987+ };
1988+
1989+ partitions@2 {
1990+ label = "U-Boot Env";
1991+ reg = <0x180000 0x20000>;
1992+ };
1993+ };
1994+};
1995diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
1996index 29a538ecd405..afb8eb0a0a16 100644
1997--- a/arch/arm/boot/dts/am437x-gp-evm.dts
1998+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
1999@@ -149,6 +149,13 @@ sound0_master: simple-audio-card,codec {
2000 system-clock-frequency = <12000000>;
2001 };
2002 };
2003+
2004+ beeper: beeper {
2005+ compatible = "gpio-beeper";
2006+ pinctrl-names = "default";
2007+ pinctrl-0 = <&beeper_pins>;
2008+ gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
2009+ };
2010 };
2011
2012 &am43xx_pinmux {
2013@@ -510,6 +517,13 @@ AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
2014 AM4372_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
2015 >;
2016 };
2017+
2018+ beeper_pins: beeper_pins {
2019+ pinctrl-single,pins = <
2020+ AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */
2021+ >;
2022+ };
2023+
2024 };
2025
2026 &uart0 {
2027@@ -842,6 +856,7 @@ nand@0,0 {
2028 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
2029 <1 IRQ_TYPE_NONE>; /* termcount */
2030 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
2031+ ti,nand-xfer-type = "prefetch-dma";
2032 ti,nand-ecc-opt = "bch16";
2033 ti,elm-id = <&elm>;
2034 nand-bus-width = <8>;
2035diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
2036index 54f40f370011..9d276af7c539 100644
2037--- a/arch/arm/boot/dts/am43x-epos-evm.dts
2038+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
2039@@ -564,6 +564,7 @@ nand@0,0 {
2040 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
2041 <1 IRQ_TYPE_NONE>; /* termcount */
2042 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
2043+ ti,nand-xfer-type = "prefetch-dma";
2044 ti,nand-ecc-opt = "bch16";
2045 ti,elm-id = <&elm>;
2046 nand-bus-width = <8>;
2047diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts
2048index 7b207835b2d1..debf9464403e 100644
2049--- a/arch/arm/boot/dts/am571x-idk.dts
2050+++ b/arch/arm/boot/dts/am571x-idk.dts
2051@@ -11,6 +11,7 @@
2052 #include <dt-bindings/gpio/gpio.h>
2053 #include <dt-bindings/interrupt-controller/irq.h>
2054 #include "am57xx-idk-common.dtsi"
2055+#include "dra72x-mmc-iodelay.dtsi"
2056
2057 / {
2058 model = "TI AM5718 IDK";
2059@@ -64,13 +65,6 @@ mmc0-led {
2060 };
2061 };
2062
2063-&mmc1 {
2064- status = "okay";
2065- vmmc-supply = <&ldo1_reg>;
2066- bus-width = <4>;
2067- cd-gpios = <&gpio6 27 0>; /* gpio 219 */
2068-};
2069-
2070 &omap_dwc3_2 {
2071 extcon = <&extcon_usb2>;
2072 };
2073@@ -96,3 +90,30 @@ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
2074 status = "okay";
2075 };
2076 };
2077+
2078+&pcie1_rc {
2079+ status = "okay";
2080+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
2081+};
2082+
2083+&pcie1_ep {
2084+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
2085+};
2086+
2087+&mmc1 {
2088+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
2089+ pinctrl-0 = <&mmc1_pins_default>;
2090+ pinctrl-1 = <&mmc1_pins_hs>;
2091+ pinctrl-2 = <&mmc1_pins_sdr12>;
2092+ pinctrl-3 = <&mmc1_pins_sdr25>;
2093+ pinctrl-4 = <&mmc1_pins_sdr50>;
2094+ pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
2095+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
2096+};
2097+
2098+&mmc2 {
2099+ pinctrl-names = "default", "hs", "ddr_1_8v";
2100+ pinctrl-0 = <&mmc2_pins_default>;
2101+ pinctrl-1 = <&mmc2_pins_hs>;
2102+ pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
2103+};
2104diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts
2105index 9da6d83ca185..a578fe97ba3b 100644
2106--- a/arch/arm/boot/dts/am572x-idk.dts
2107+++ b/arch/arm/boot/dts/am572x-idk.dts
2108@@ -12,6 +12,7 @@
2109 #include <dt-bindings/gpio/gpio.h>
2110 #include <dt-bindings/interrupt-controller/irq.h>
2111 #include "am57xx-idk-common.dtsi"
2112+#include "dra74x-mmc-iodelay.dtsi"
2113
2114 / {
2115 model = "TI AM5728 IDK";
2116@@ -67,6 +68,24 @@ mmc0-led {
2117 };
2118 };
2119
2120+&mmc1 {
2121+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
2122+ pinctrl-0 = <&mmc1_pins_default>;
2123+ pinctrl-1 = <&mmc1_pins_hs>;
2124+ pinctrl-2 = <&mmc1_pins_sdr12>;
2125+ pinctrl-3 = <&mmc1_pins_sdr25>;
2126+ pinctrl-4 = <&mmc1_pins_sdr50>;
2127+ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
2128+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
2129+};
2130+
2131+&mmc2 {
2132+ pinctrl-names = "default", "hs", "ddr_1_8v";
2133+ pinctrl-0 = <&mmc2_pins_default>;
2134+ pinctrl-1 = <&mmc2_pins_hs>;
2135+ pinctrl-2 = <&mmc2_pins_ddr_rev20>;
2136+};
2137+
2138 &omap_dwc3_2 {
2139 extcon = <&extcon_usb2>;
2140 };
2141@@ -76,19 +95,16 @@ &extcon_usb2 {
2142 vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
2143 };
2144
2145-&mmc1 {
2146- status = "okay";
2147- vmmc-supply = <&v3_3d>;
2148- vmmc_aux-supply = <&ldo1_reg>;
2149- bus-width = <4>;
2150- cd-gpios = <&gpio6 27 0>; /* gpio 219 */
2151-};
2152-
2153 &sn65hvs882 {
2154 load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
2155 };
2156
2157-&pcie1 {
2158+&pcie1_rc {
2159+ status = "okay";
2160+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
2161+};
2162+
2163+&pcie1_ep {
2164 gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
2165 };
2166
2167diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
2168index fdfe5b16b806..49aeecd312b4 100644
2169--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
2170+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
2171@@ -9,6 +9,7 @@
2172
2173 #include "dra74x.dtsi"
2174 #include "am57xx-commercial-grade.dtsi"
2175+#include "dra74x-mmc-iodelay.dtsi"
2176 #include <dt-bindings/gpio/gpio.h>
2177 #include <dt-bindings/interrupt-controller/irq.h>
2178
2179@@ -166,34 +167,6 @@ sound0_master: simple-audio-card,codec {
2180 };
2181 };
2182
2183-&dra7_pmx_core {
2184- mmc1_pins_default: mmc1_pins_default {
2185- pinctrl-single,pins = <
2186- DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
2187- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
2188- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
2189- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
2190- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
2191- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
2192- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
2193- >;
2194- };
2195-
2196- mmc2_pins_default: mmc2_pins_default {
2197- pinctrl-single,pins = <
2198- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
2199- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
2200- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
2201- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
2202- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
2203- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
2204- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
2205- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
2206- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
2207- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
2208- >;
2209- };
2210-};
2211 &i2c1 {
2212 status = "okay";
2213 clock-frequency = <400000>;
2214@@ -570,7 +543,12 @@ hdmi_out: endpoint {
2215 };
2216 };
2217
2218-&pcie1 {
2219+&pcie1_rc {
2220+ status = "ok";
2221+ gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
2222+};
2223+
2224+&pcie1_ep {
2225 gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
2226 };
2227
2228diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts
2229index 39a92aff0a0d..5a77b334923d 100644
2230--- a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts
2231+++ b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts
2232@@ -19,8 +19,23 @@ &tpd12s015 {
2233 };
2234
2235 &mmc1 {
2236+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
2237+ pinctrl-0 = <&mmc1_pins_default>;
2238+ pinctrl-1 = <&mmc1_pins_hs>;
2239+ pinctrl-2 = <&mmc1_pins_sdr12>;
2240+ pinctrl-3 = <&mmc1_pins_sdr25>;
2241+ pinctrl-4 = <&mmc1_pins_sdr50>;
2242+ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
2243+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
2244 vmmc-supply = <&vdd_3v3>;
2245- vmmc-aux-supply = <&ldo1_reg>;
2246+ vqmmc-supply = <&ldo1_reg>;
2247+};
2248+
2249+&mmc2 {
2250+ pinctrl-names = "default", "hs", "ddr_1_8v";
2251+ pinctrl-0 = <&mmc2_pins_default>;
2252+ pinctrl-1 = <&mmc2_pins_hs>;
2253+ pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;
2254 };
2255
2256 /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
2257diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts b/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts
2258new file mode 100644
2259index 000000000000..17c41da3b55f
2260--- /dev/null
2261+++ b/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts
2262@@ -0,0 +1,39 @@
2263+/*
2264+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
2265+ *
2266+ * This program is free software; you can redistribute it and/or modify
2267+ * it under the terms of the GNU General Public License version 2 as
2268+ * published by the Free Software Foundation.
2269+ */
2270+
2271+#include "am57xx-beagle-x15-common.dtsi"
2272+
2273+/ {
2274+ model = "TI AM5728 BeagleBoard-X15 rev C";
2275+};
2276+
2277+&tpd12s015 {
2278+ gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
2279+ <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */
2280+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
2281+};
2282+
2283+&mmc1 {
2284+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
2285+ pinctrl-0 = <&mmc1_pins_default>;
2286+ pinctrl-1 = <&mmc1_pins_hs>;
2287+ pinctrl-2 = <&mmc1_pins_sdr12>;
2288+ pinctrl-3 = <&mmc1_pins_sdr25>;
2289+ pinctrl-4 = <&mmc1_pins_sdr50>;
2290+ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
2291+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
2292+ vmmc-supply = <&vdd_3v3>;
2293+ vqmmc-supply = <&ldo1_reg>;
2294+};
2295+
2296+&mmc2 {
2297+ pinctrl-names = "default", "hs", "ddr_1_8v";
2298+ pinctrl-0 = <&mmc2_pins_default>;
2299+ pinctrl-1 = <&mmc2_pins_hs>;
2300+ pinctrl-2 = <&mmc2_pins_ddr_rev20>;
2301+};
2302diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
2303index 19a60a11c198..d6689106d2a8 100644
2304--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
2305+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
2306@@ -20,9 +20,20 @@ &tpd12s015 {
2307 };
2308
2309 &mmc1 {
2310+ pinctrl-names = "default", "hs";
2311+ pinctrl-0 = <&mmc1_pins_default>;
2312+ pinctrl-1 = <&mmc1_pins_hs>;
2313+
2314 vmmc-supply = <&ldo1_reg>;
2315 };
2316
2317+&mmc2 {
2318+ pinctrl-names = "default", "hs", "ddr_1_8v";
2319+ pinctrl-0 = <&mmc2_pins_default>;
2320+ pinctrl-1 = <&mmc2_pins_hs>;
2321+ pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;
2322+};
2323+
2324 /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
2325 &phy1 {
2326 max-speed = <100>;
2327diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
2328index c536b2f5389f..97aa8e6a56da 100644
2329--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
2330+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
2331@@ -399,6 +399,14 @@ &usb2 {
2332 dr_mode = "peripheral";
2333 };
2334
2335+&mmc1 {
2336+ status = "okay";
2337+ vmmc-supply = <&v3_3d>;
2338+ vqmmc-supply = <&ldo1_reg>;
2339+ bus-width = <4>;
2340+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
2341+};
2342+
2343 &mmc2 {
2344 status = "okay";
2345 vmmc-supply = <&v3_3d>;
2346diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
2347index f9cf1273f35e..b1cf5a26f3c2 100644
2348--- a/arch/arm/boot/dts/armada-370.dtsi
2349+++ b/arch/arm/boot/dts/armada-370.dtsi
2350@@ -72,7 +72,7 @@ bootrom {
2351 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
2352 };
2353
2354- pciec: pcie-controller@82000000 {
2355+ pciec: pcie@82000000 {
2356 compatible = "marvell,armada-370-pcie";
2357 status = "disabled";
2358 device_type = "pci";
2359@@ -100,6 +100,7 @@ pcie0: pcie@1,0 {
2360 #interrupt-cells = <1>;
2361 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
2362 0x81000000 0 0 0x81000000 0x1 0 1 0>;
2363+ bus-range = <0x00 0xff>;
2364 interrupt-map-mask = <0 0 0 0>;
2365 interrupt-map = <0 0 0 0 &mpic 58>;
2366 marvell,pcie-port = <0>;
2367@@ -117,6 +118,7 @@ pcie2: pcie@2,0 {
2368 #interrupt-cells = <1>;
2369 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
2370 0x81000000 0 0 0x81000000 0x2 0 1 0>;
2371+ bus-range = <0x00 0xff>;
2372 interrupt-map-mask = <0 0 0 0>;
2373 interrupt-map = <0 0 0 0 &mpic 62>;
2374 marvell,pcie-port = <1>;
2375diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
2376index 50c5e8417802..7225c7ce9a8d 100644
2377--- a/arch/arm/boot/dts/armada-375.dtsi
2378+++ b/arch/arm/boot/dts/armada-375.dtsi
2379@@ -582,7 +582,7 @@ coredivclk: corediv-clock@e8250 {
2380 };
2381 };
2382
2383- pciec: pcie-controller@82000000 {
2384+ pciec: pcie@82000000 {
2385 compatible = "marvell,armada-370-pcie";
2386 status = "disabled";
2387 device_type = "pci";
2388@@ -610,6 +610,7 @@ pcie0: pcie@1,0 {
2389 #interrupt-cells = <1>;
2390 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
2391 0x81000000 0 0 0x81000000 0x1 0 1 0>;
2392+ bus-range = <0x00 0xff>;
2393 interrupt-map-mask = <0 0 0 0>;
2394 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
2395 marvell,pcie-port = <0>;
2396@@ -627,6 +628,7 @@ pcie1: pcie@2,0 {
2397 #interrupt-cells = <1>;
2398 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
2399 0x81000000 0 0 0x81000000 0x2 0 1 0>;
2400+ bus-range = <0x00 0xff>;
2401 interrupt-map-mask = <0 0 0 0>;
2402 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2403 marvell,pcie-port = <0>;
2404diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
2405index e392f6036f39..132596fd0860 100644
2406--- a/arch/arm/boot/dts/armada-380.dtsi
2407+++ b/arch/arm/boot/dts/armada-380.dtsi
2408@@ -71,7 +71,7 @@ pinctrl@18000 {
2409 };
2410 };
2411
2412- pcie-controller {
2413+ pcie {
2414 compatible = "marvell,armada-370-pcie";
2415 status = "disabled";
2416 device_type = "pci";
2417@@ -104,6 +104,7 @@ pcie@1,0 {
2418 #interrupt-cells = <1>;
2419 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
2420 0x81000000 0 0 0x81000000 0x1 0 1 0>;
2421+ bus-range = <0x00 0xff>;
2422 interrupt-map-mask = <0 0 0 0>;
2423 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
2424 marvell,pcie-port = <0>;
2425@@ -122,6 +123,7 @@ pcie@2,0 {
2426 #interrupt-cells = <1>;
2427 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
2428 0x81000000 0 0 0x81000000 0x2 0 1 0>;
2429+ bus-range = <0x00 0xff>;
2430 interrupt-map-mask = <0 0 0 0>;
2431 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2432 marvell,pcie-port = <1>;
2433@@ -140,6 +142,7 @@ pcie@3,0 {
2434 #interrupt-cells = <1>;
2435 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
2436 0x81000000 0 0 0x81000000 0x3 0 1 0>;
2437+ bus-range = <0x00 0xff>;
2438 interrupt-map-mask = <0 0 0 0>;
2439 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
2440 marvell,pcie-port = <2>;
2441diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
2442index db5b9f6b615d..25d2d720dc0e 100644
2443--- a/arch/arm/boot/dts/armada-385-db-ap.dts
2444+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
2445@@ -209,7 +209,7 @@ bm-bppi {
2446 status = "okay";
2447 };
2448
2449- pcie-controller {
2450+ pcie {
2451 status = "okay";
2452
2453 /*
2454diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts
2455index be16ce39fb3d..06831e1e3f80 100644
2456--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
2457+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
2458@@ -96,7 +96,7 @@ usb3@f8000 {
2459 };
2460 };
2461
2462- pcie-controller {
2463+ pcie {
2464 status = "okay";
2465
2466 pcie@1,0 {
2467diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
2468index 7fcc4c4885cf..74863aff01c6 100644
2469--- a/arch/arm/boot/dts/armada-385.dtsi
2470+++ b/arch/arm/boot/dts/armada-385.dtsi
2471@@ -70,7 +70,7 @@ cpu@1 {
2472 };
2473
2474 soc {
2475- pciec: pcie-controller {
2476+ pciec: pcie {
2477 compatible = "marvell,armada-370-pcie";
2478 status = "disabled";
2479 device_type = "pci";
2480@@ -109,6 +109,7 @@ pcie1: pcie@1,0 {
2481 #interrupt-cells = <1>;
2482 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
2483 0x81000000 0 0 0x81000000 0x1 0 1 0>;
2484+ bus-range = <0x00 0xff>;
2485 interrupt-map-mask = <0 0 0 0>;
2486 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
2487 marvell,pcie-port = <0>;
2488@@ -127,6 +128,7 @@ pcie2: pcie@2,0 {
2489 #interrupt-cells = <1>;
2490 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
2491 0x81000000 0 0 0x81000000 0x2 0 1 0>;
2492+ bus-range = <0x00 0xff>;
2493 interrupt-map-mask = <0 0 0 0>;
2494 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2495 marvell,pcie-port = <1>;
2496@@ -145,6 +147,7 @@ pcie3: pcie@3,0 {
2497 #interrupt-cells = <1>;
2498 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
2499 0x81000000 0 0 0x81000000 0x3 0 1 0>;
2500+ bus-range = <0x00 0xff>;
2501 interrupt-map-mask = <0 0 0 0>;
2502 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
2503 marvell,pcie-port = <2>;
2504@@ -166,6 +169,7 @@ pcie4: pcie@4,0 {
2505 #interrupt-cells = <1>;
2506 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
2507 0x81000000 0 0 0x81000000 0x4 0 1 0>;
2508+ bus-range = <0x00 0xff>;
2509 interrupt-map-mask = <0 0 0 0>;
2510 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
2511 marvell,pcie-port = <3>;
2512diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
2513index 0d5f1f062275..ee7b0089eff0 100644
2514--- a/arch/arm/boot/dts/armada-388-clearfog.dts
2515+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
2516@@ -62,7 +62,7 @@ usb3@f0000 {
2517 };
2518 };
2519
2520- pcie-controller {
2521+ pcie {
2522 pcie@3,0 {
2523 /* Port 2, Lane 0. CON2, nearest CPU. */
2524 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
2525diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
2526index 0f5938bede53..68acfc968706 100644
2527--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
2528+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
2529@@ -104,7 +104,7 @@ usb3@f8000 {
2530 };
2531 };
2532
2533- pcie-controller {
2534+ pcie {
2535 status = "okay";
2536 /*
2537 * The two PCIe units are accessible through
2538diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts
2539index 1ac923826445..a4ec1fa37529 100644
2540--- a/arch/arm/boot/dts/armada-388-db.dts
2541+++ b/arch/arm/boot/dts/armada-388-db.dts
2542@@ -172,7 +172,7 @@ bm-bppi {
2543 status = "okay";
2544 };
2545
2546- pcie-controller {
2547+ pcie {
2548 status = "okay";
2549 /*
2550 * The two PCIe units are accessible through
2551diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
2552index 563901e0ec07..f503955dbd3b 100644
2553--- a/arch/arm/boot/dts/armada-388-gp.dts
2554+++ b/arch/arm/boot/dts/armada-388-gp.dts
2555@@ -240,7 +240,7 @@ bm-bppi {
2556 status = "okay";
2557 };
2558
2559- pcie-controller {
2560+ pcie {
2561 status = "okay";
2562 /*
2563 * One PCIe units is accessible through
2564diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts
2565index af82f275eac2..9cc3ca0376b9 100644
2566--- a/arch/arm/boot/dts/armada-388-rd.dts
2567+++ b/arch/arm/boot/dts/armada-388-rd.dts
2568@@ -117,7 +117,7 @@ usb3@f0000 {
2569 };
2570 };
2571
2572- pcie-controller {
2573+ pcie {
2574 status = "okay";
2575 /*
2576 * One PCIe units is accessible through
2577diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
2578index af31f5d6c0e5..7ff0811e61db 100644
2579--- a/arch/arm/boot/dts/armada-38x.dtsi
2580+++ b/arch/arm/boot/dts/armada-38x.dtsi
2581@@ -154,6 +154,13 @@ scu@c000 {
2582 reg = <0xc000 0x58>;
2583 };
2584
2585+ timer@c200 {
2586+ compatible = "arm,cortex-a9-global-timer";
2587+ reg = <0xc200 0x20>;
2588+ interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
2589+ clocks = <&coreclk 2>;
2590+ };
2591+
2592 timer@c600 {
2593 compatible = "arm,cortex-a9-twd-timer";
2594 reg = <0xc600 0x20>;
2595diff --git a/arch/arm/boot/dts/armada-390-db.dts b/arch/arm/boot/dts/armada-390-db.dts
2596index 2afed2ce4741..c718a5242595 100644
2597--- a/arch/arm/boot/dts/armada-390-db.dts
2598+++ b/arch/arm/boot/dts/armada-390-db.dts
2599@@ -123,7 +123,7 @@ usb3@f8000 {
2600 };
2601 };
2602
2603- pcie-controller {
2604+ pcie {
2605 status = "okay";
2606
2607 /* CON30 */
2608diff --git a/arch/arm/boot/dts/armada-395-gp.dts b/arch/arm/boot/dts/armada-395-gp.dts
2609index 2cdbba804c1e..ef491b524fd6 100644
2610--- a/arch/arm/boot/dts/armada-395-gp.dts
2611+++ b/arch/arm/boot/dts/armada-395-gp.dts
2612@@ -139,7 +139,7 @@ usb3@f0000 {
2613 };
2614 };
2615
2616- pcie-controller {
2617+ pcie {
2618 status = "okay";
2619
2620 /*
2621diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts
2622index e8604281c3c9..f0e0379f7619 100644
2623--- a/arch/arm/boot/dts/armada-398-db.dts
2624+++ b/arch/arm/boot/dts/armada-398-db.dts
2625@@ -118,7 +118,7 @@ usb3@f8000 {
2626 };
2627 };
2628
2629- pcie-controller {
2630+ pcie {
2631 status = "okay";
2632
2633 pcie@1,0 {
2634diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
2635index 60fbfd5907c7..ea657071e278 100644
2636--- a/arch/arm/boot/dts/armada-39x.dtsi
2637+++ b/arch/arm/boot/dts/armada-39x.dtsi
2638@@ -442,7 +442,7 @@ thermal@e8078 {
2639 };
2640 };
2641
2642- pcie-controller {
2643+ pcie {
2644 compatible = "marvell,armada-370-pcie";
2645 status = "disabled";
2646 device_type = "pci";
2647@@ -481,6 +481,7 @@ pcie@1,0 {
2648 #interrupt-cells = <1>;
2649 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
2650 0x81000000 0 0 0x81000000 0x1 0 1 0>;
2651+ bus-range = <0x00 0xff>;
2652 interrupt-map-mask = <0 0 0 0>;
2653 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
2654 marvell,pcie-port = <0>;
2655@@ -499,6 +500,7 @@ pcie@2,0 {
2656 #interrupt-cells = <1>;
2657 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
2658 0x81000000 0 0 0x81000000 0x2 0 1 0>;
2659+ bus-range = <0x00 0xff>;
2660 interrupt-map-mask = <0 0 0 0>;
2661 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2662 marvell,pcie-port = <1>;
2663@@ -517,6 +519,7 @@ pcie@3,0 {
2664 #interrupt-cells = <1>;
2665 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
2666 0x81000000 0 0 0x81000000 0x3 0 1 0>;
2667+ bus-range = <0x00 0xff>;
2668 interrupt-map-mask = <0 0 0 0>;
2669 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
2670 marvell,pcie-port = <2>;
2671@@ -538,6 +541,7 @@ pcie@4,0 {
2672 #interrupt-cells = <1>;
2673 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
2674 0x81000000 0 0 0x81000000 0x4 0 1 0>;
2675+ bus-range = <0x00 0xff>;
2676 interrupt-map-mask = <0 0 0 0>;
2677 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
2678 marvell,pcie-port = <3>;
2679diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
2680index be22ec5236ac..bdd4c7a45fbf 100644
2681--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
2682+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
2683@@ -91,7 +91,7 @@ bootrom {
2684 /*
2685 * 98DX3236 has 1 x1 PCIe unit Gen2.0
2686 */
2687- pciec: pcie-controller@82000000 {
2688+ pciec: pcie@82000000 {
2689 compatible = "marvell,armada-xp-pcie";
2690 status = "disabled";
2691 device_type = "pci";
2692@@ -116,6 +116,7 @@ pcie1: pcie@1,0 {
2693 #interrupt-cells = <1>;
2694 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
2695 0x81000000 0 0 0x81000000 0x1 0 1 0>;
2696+ bus-range = <0x00 0xff>;
2697 interrupt-map-mask = <0 0 0 0>;
2698 interrupt-map = <0 0 0 0 &mpic 58>;
2699 marvell,pcie-port = <0>;
2700diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
2701index a33974254d8c..065282c21789 100644
2702--- a/arch/arm/boot/dts/armada-xp-db.dts
2703+++ b/arch/arm/boot/dts/armada-xp-db.dts
2704@@ -242,7 +242,7 @@ pcie@9,0 {
2705 /* Port 2, Lane 0 */
2706 status = "okay";
2707 };
2708- pcie@10,0 {
2709+ pcie@a,0 {
2710 /* Port 3, Lane 0 */
2711 status = "okay";
2712 };
2713diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
2714index d62bf7bea1df..ac9eab8ac186 100644
2715--- a/arch/arm/boot/dts/armada-xp-gp.dts
2716+++ b/arch/arm/boot/dts/armada-xp-gp.dts
2717@@ -227,7 +227,7 @@ pcie@9,0 {
2718 /* Port 2, Lane 0 */
2719 status = "okay";
2720 };
2721- pcie@10,0 {
2722+ pcie@a,0 {
2723 /* Port 3, Lane 0 */
2724 status = "okay";
2725 };
2726diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
2727index 9f25814077f2..129738f7973d 100644
2728--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
2729+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
2730@@ -86,7 +86,7 @@ soc {
2731 * configured as x4 or quad x1 lanes. One unit is
2732 * x1 only.
2733 */
2734- pciec: pcie-controller@82000000 {
2735+ pciec: pcie@82000000 {
2736 compatible = "marvell,armada-xp-pcie";
2737 status = "disabled";
2738 device_type = "pci";
2739@@ -123,6 +123,7 @@ pcie1: pcie@1,0 {
2740 #interrupt-cells = <1>;
2741 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
2742 0x81000000 0 0 0x81000000 0x1 0 1 0>;
2743+ bus-range = <0x00 0xff>;
2744 interrupt-map-mask = <0 0 0 0>;
2745 interrupt-map = <0 0 0 0 &mpic 58>;
2746 marvell,pcie-port = <0>;
2747@@ -140,6 +141,7 @@ pcie2: pcie@2,0 {
2748 #interrupt-cells = <1>;
2749 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
2750 0x81000000 0 0 0x81000000 0x2 0 1 0>;
2751+ bus-range = <0x00 0xff>;
2752 interrupt-map-mask = <0 0 0 0>;
2753 interrupt-map = <0 0 0 0 &mpic 59>;
2754 marvell,pcie-port = <0>;
2755@@ -157,6 +159,7 @@ pcie3: pcie@3,0 {
2756 #interrupt-cells = <1>;
2757 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
2758 0x81000000 0 0 0x81000000 0x3 0 1 0>;
2759+ bus-range = <0x00 0xff>;
2760 interrupt-map-mask = <0 0 0 0>;
2761 interrupt-map = <0 0 0 0 &mpic 60>;
2762 marvell,pcie-port = <0>;
2763@@ -174,6 +177,7 @@ pcie4: pcie@4,0 {
2764 #interrupt-cells = <1>;
2765 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
2766 0x81000000 0 0 0x81000000 0x4 0 1 0>;
2767+ bus-range = <0x00 0xff>;
2768 interrupt-map-mask = <0 0 0 0>;
2769 interrupt-map = <0 0 0 0 &mpic 61>;
2770 marvell,pcie-port = <0>;
2771@@ -191,6 +195,7 @@ pcie5: pcie@5,0 {
2772 #interrupt-cells = <1>;
2773 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
2774 0x81000000 0 0 0x81000000 0x5 0 1 0>;
2775+ bus-range = <0x00 0xff>;
2776 interrupt-map-mask = <0 0 0 0>;
2777 interrupt-map = <0 0 0 0 &mpic 62>;
2778 marvell,pcie-port = <1>;
2779diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
2780index 2bfe07aebf1a..e58d597e37b9 100644
2781--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
2782+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
2783@@ -87,7 +87,7 @@ soc {
2784 * configured as x4 or quad x1 lanes. One unit is
2785 * x4 only.
2786 */
2787- pciec: pcie-controller@82000000 {
2788+ pciec: pcie@82000000 {
2789 compatible = "marvell,armada-xp-pcie";
2790 status = "disabled";
2791 device_type = "pci";
2792@@ -138,6 +138,7 @@ pcie1: pcie@1,0 {
2793 #interrupt-cells = <1>;
2794 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
2795 0x81000000 0 0 0x81000000 0x1 0 1 0>;
2796+ bus-range = <0x00 0xff>;
2797 interrupt-map-mask = <0 0 0 0>;
2798 interrupt-map = <0 0 0 0 &mpic 58>;
2799 marvell,pcie-port = <0>;
2800@@ -155,6 +156,7 @@ pcie2: pcie@2,0 {
2801 #interrupt-cells = <1>;
2802 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
2803 0x81000000 0 0 0x81000000 0x2 0 1 0>;
2804+ bus-range = <0x00 0xff>;
2805 interrupt-map-mask = <0 0 0 0>;
2806 interrupt-map = <0 0 0 0 &mpic 59>;
2807 marvell,pcie-port = <0>;
2808@@ -172,6 +174,7 @@ pcie3: pcie@3,0 {
2809 #interrupt-cells = <1>;
2810 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
2811 0x81000000 0 0 0x81000000 0x3 0 1 0>;
2812+ bus-range = <0x00 0xff>;
2813 interrupt-map-mask = <0 0 0 0>;
2814 interrupt-map = <0 0 0 0 &mpic 60>;
2815 marvell,pcie-port = <0>;
2816@@ -189,6 +192,7 @@ pcie4: pcie@4,0 {
2817 #interrupt-cells = <1>;
2818 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
2819 0x81000000 0 0 0x81000000 0x4 0 1 0>;
2820+ bus-range = <0x00 0xff>;
2821 interrupt-map-mask = <0 0 0 0>;
2822 interrupt-map = <0 0 0 0 &mpic 61>;
2823 marvell,pcie-port = <0>;
2824@@ -206,6 +210,7 @@ pcie5: pcie@5,0 {
2825 #interrupt-cells = <1>;
2826 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
2827 0x81000000 0 0 0x81000000 0x5 0 1 0>;
2828+ bus-range = <0x00 0xff>;
2829 interrupt-map-mask = <0 0 0 0>;
2830 interrupt-map = <0 0 0 0 &mpic 62>;
2831 marvell,pcie-port = <1>;
2832@@ -223,6 +228,7 @@ pcie6: pcie@6,0 {
2833 #interrupt-cells = <1>;
2834 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
2835 0x81000000 0 0 0x81000000 0x6 0 1 0>;
2836+ bus-range = <0x00 0xff>;
2837 interrupt-map-mask = <0 0 0 0>;
2838 interrupt-map = <0 0 0 0 &mpic 63>;
2839 marvell,pcie-port = <1>;
2840@@ -240,6 +246,7 @@ pcie7: pcie@7,0 {
2841 #interrupt-cells = <1>;
2842 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
2843 0x81000000 0 0 0x81000000 0x7 0 1 0>;
2844+ bus-range = <0x00 0xff>;
2845 interrupt-map-mask = <0 0 0 0>;
2846 interrupt-map = <0 0 0 0 &mpic 64>;
2847 marvell,pcie-port = <1>;
2848@@ -257,6 +264,7 @@ pcie8: pcie@8,0 {
2849 #interrupt-cells = <1>;
2850 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
2851 0x81000000 0 0 0x81000000 0x8 0 1 0>;
2852+ bus-range = <0x00 0xff>;
2853 interrupt-map-mask = <0 0 0 0>;
2854 interrupt-map = <0 0 0 0 &mpic 65>;
2855 marvell,pcie-port = <1>;
2856@@ -274,6 +282,7 @@ pcie9: pcie@9,0 {
2857 #interrupt-cells = <1>;
2858 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
2859 0x81000000 0 0 0x81000000 0x9 0 1 0>;
2860+ bus-range = <0x00 0xff>;
2861 interrupt-map-mask = <0 0 0 0>;
2862 interrupt-map = <0 0 0 0 &mpic 99>;
2863 marvell,pcie-port = <2>;
2864diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
2865index 6c33935f7074..a5c961cee7de 100644
2866--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
2867+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
2868@@ -104,7 +104,7 @@ soc {
2869 * configured as x4 or quad x1 lanes. Two units are
2870 * x4/x1.
2871 */
2872- pciec: pcie-controller@82000000 {
2873+ pciec: pcie@82000000 {
2874 compatible = "marvell,armada-xp-pcie";
2875 status = "disabled";
2876 device_type = "pci";
2877@@ -159,6 +159,7 @@ pcie1: pcie@1,0 {
2878 #interrupt-cells = <1>;
2879 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
2880 0x81000000 0 0 0x81000000 0x1 0 1 0>;
2881+ bus-range = <0x00 0xff>;
2882 interrupt-map-mask = <0 0 0 0>;
2883 interrupt-map = <0 0 0 0 &mpic 58>;
2884 marvell,pcie-port = <0>;
2885@@ -176,6 +177,7 @@ pcie2: pcie@2,0 {
2886 #interrupt-cells = <1>;
2887 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
2888 0x81000000 0 0 0x81000000 0x2 0 1 0>;
2889+ bus-range = <0x00 0xff>;
2890 interrupt-map-mask = <0 0 0 0>;
2891 interrupt-map = <0 0 0 0 &mpic 59>;
2892 marvell,pcie-port = <0>;
2893@@ -193,6 +195,7 @@ pcie3: pcie@3,0 {
2894 #interrupt-cells = <1>;
2895 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
2896 0x81000000 0 0 0x81000000 0x3 0 1 0>;
2897+ bus-range = <0x00 0xff>;
2898 interrupt-map-mask = <0 0 0 0>;
2899 interrupt-map = <0 0 0 0 &mpic 60>;
2900 marvell,pcie-port = <0>;
2901@@ -210,6 +213,7 @@ pcie4: pcie@4,0 {
2902 #interrupt-cells = <1>;
2903 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
2904 0x81000000 0 0 0x81000000 0x4 0 1 0>;
2905+ bus-range = <0x00 0xff>;
2906 interrupt-map-mask = <0 0 0 0>;
2907 interrupt-map = <0 0 0 0 &mpic 61>;
2908 marvell,pcie-port = <0>;
2909@@ -227,6 +231,7 @@ pcie5: pcie@5,0 {
2910 #interrupt-cells = <1>;
2911 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
2912 0x81000000 0 0 0x81000000 0x5 0 1 0>;
2913+ bus-range = <0x00 0xff>;
2914 interrupt-map-mask = <0 0 0 0>;
2915 interrupt-map = <0 0 0 0 &mpic 62>;
2916 marvell,pcie-port = <1>;
2917@@ -244,6 +249,7 @@ pcie6: pcie@6,0 {
2918 #interrupt-cells = <1>;
2919 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
2920 0x81000000 0 0 0x81000000 0x6 0 1 0>;
2921+ bus-range = <0x00 0xff>;
2922 interrupt-map-mask = <0 0 0 0>;
2923 interrupt-map = <0 0 0 0 &mpic 63>;
2924 marvell,pcie-port = <1>;
2925@@ -261,6 +267,7 @@ pcie7: pcie@7,0 {
2926 #interrupt-cells = <1>;
2927 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
2928 0x81000000 0 0 0x81000000 0x7 0 1 0>;
2929+ bus-range = <0x00 0xff>;
2930 interrupt-map-mask = <0 0 0 0>;
2931 interrupt-map = <0 0 0 0 &mpic 64>;
2932 marvell,pcie-port = <1>;
2933@@ -278,6 +285,7 @@ pcie8: pcie@8,0 {
2934 #interrupt-cells = <1>;
2935 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
2936 0x81000000 0 0 0x81000000 0x8 0 1 0>;
2937+ bus-range = <0x00 0xff>;
2938 interrupt-map-mask = <0 0 0 0>;
2939 interrupt-map = <0 0 0 0 &mpic 65>;
2940 marvell,pcie-port = <1>;
2941@@ -295,6 +303,7 @@ pcie9: pcie@9,0 {
2942 #interrupt-cells = <1>;
2943 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
2944 0x81000000 0 0 0x81000000 0x9 0 1 0>;
2945+ bus-range = <0x00 0xff>;
2946 interrupt-map-mask = <0 0 0 0>;
2947 interrupt-map = <0 0 0 0 &mpic 99>;
2948 marvell,pcie-port = <2>;
2949@@ -303,7 +312,7 @@ pcie9: pcie@9,0 {
2950 status = "disabled";
2951 };
2952
2953- pcie10: pcie@10,0 {
2954+ pcie10: pcie@a,0 {
2955 device_type = "pci";
2956 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
2957 reg = <0x5000 0 0 0 0>;
2958@@ -312,6 +321,7 @@ pcie10: pcie@10,0 {
2959 #interrupt-cells = <1>;
2960 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
2961 0x81000000 0 0 0x81000000 0xa 0 1 0>;
2962+ bus-range = <0x00 0xff>;
2963 interrupt-map-mask = <0 0 0 0>;
2964 interrupt-map = <0 0 0 0 &mpic 103>;
2965 marvell,pcie-port = <3>;
2966diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
2967index 8a04c7e2d818..22b958537d31 100644
2968--- a/arch/arm/boot/dts/aspeed-g4.dtsi
2969+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
2970@@ -26,7 +26,7 @@ ahb {
2971
2972 fmc: flash-controller@1e620000 {
2973 reg = < 0x1e620000 0x94
2974- 0x20000000 0x02000000 >;
2975+ 0x20000000 0x10000000 >;
2976 #address-cells = <1>;
2977 #size-cells = <0>;
2978 compatible = "aspeed,ast2400-fmc";
2979@@ -41,7 +41,7 @@ flash@0 {
2980
2981 spi: flash-controller@1e630000 {
2982 reg = < 0x1e630000 0x18
2983- 0x30000000 0x02000000 >;
2984+ 0x30000000 0x10000000 >;
2985 #address-cells = <1>;
2986 #size-cells = <0>;
2987 compatible = "aspeed,ast2400-spi";
2988diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
2989new file mode 100644
2990index 000000000000..63a5af898165
2991--- /dev/null
2992+++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
2993@@ -0,0 +1,102 @@
2994+/*
2995+ * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board
2996+ *
2997+ * Copyright (c) 2017, Microchip Technology Inc.
2998+ * 2017 Cristian Birsan <cristian.birsan@microchip.com>
2999+ * 2017 Claudiu Beznea <claudiu.beznea@microchip.com>
3000+ *
3001+ * This file is dual-licensed: you can use it either under the terms
3002+ * of the GPL or the X11 license, at your option. Note that this dual
3003+ * licensing only applies to this file, and not this project as a
3004+ * whole.
3005+ *
3006+ * a) This file is free software; you can redistribute it and/or
3007+ * modify it under the terms of the GNU General Public License as
3008+ * published by the Free Software Foundation; either version 2 of the
3009+ * License, or (at your option) any later version.
3010+ *
3011+ * This file is distributed in the hope that it will be useful,
3012+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3013+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3014+ * GNU General Public License for more details.
3015+ *
3016+ * Or, alternatively,
3017+ *
3018+ * b) Permission is hereby granted, free of charge, to any person
3019+ * obtaining a copy of this software and associated documentation
3020+ * files (the "Software"), to deal in the Software without
3021+ * restriction, including without limitation the rights to use,
3022+ * copy, modify, merge, publish, distribute, sublicense, and/or
3023+ * sell copies of the Software, and to permit persons to whom the
3024+ * Software is furnished to do so, subject to the following
3025+ * conditions:
3026+ *
3027+ * The above copyright notice and this permission notice shall be
3028+ * included in all copies or substantial portions of the Software.
3029+ *
3030+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3031+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3032+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3033+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3034+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3035+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3036+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3037+ * OTHER DEALINGS IN THE SOFTWARE.
3038+ */
3039+#include "sama5d2.dtsi"
3040+#include "sama5d2-pinfunc.h"
3041+
3042+/ {
3043+ model = "Atmel SAMA5D27 SoM1";
3044+ compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
3045+
3046+ clocks {
3047+ slow_xtal {
3048+ clock-frequency = <32768>;
3049+ };
3050+
3051+ main_xtal {
3052+ clock-frequency = <24000000>;
3053+ };
3054+ };
3055+
3056+ ahb {
3057+ apb {
3058+ macb0: ethernet@f8008000 {
3059+ pinctrl-names = "default";
3060+ pinctrl-0 = <&pinctrl_macb0_default>;
3061+ phy-mode = "rmii";
3062+
3063+ ethernet-phy@1 {
3064+ reg = <0x1>;
3065+ interrupt-parent = <&pioA>;
3066+ interrupts = <PIN_PD31 IRQ_TYPE_LEVEL_LOW>;
3067+ pinctrl-names = "default";
3068+ pinctrl-0 = <&pinctrl_macb0_phy_irq>;
3069+ };
3070+ };
3071+
3072+ pinctrl@fc038000 {
3073+
3074+ pinctrl_macb0_default: macb0_default {
3075+ pinmux = <PIN_PD9__GTXCK>,
3076+ <PIN_PD10__GTXEN>,
3077+ <PIN_PD11__GRXDV>,
3078+ <PIN_PD12__GRXER>,
3079+ <PIN_PD13__GRX0>,
3080+ <PIN_PD14__GRX1>,
3081+ <PIN_PD15__GTX0>,
3082+ <PIN_PD16__GTX1>,
3083+ <PIN_PD17__GMDC>,
3084+ <PIN_PD18__GMDIO>;
3085+ bias-disable;
3086+ };
3087+
3088+ pinctrl_macb0_phy_irq: macb0_phy_irq {
3089+ pinmux = <PIN_PD31__GPIO>;
3090+ bias-disable;
3091+ };
3092+ };
3093+ };
3094+ };
3095+};
3096diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
3097new file mode 100644
3098index 000000000000..9c9088c99cc4
3099--- /dev/null
3100+++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
3101@@ -0,0 +1,537 @@
3102+/*
3103+ * at91-sama5d27_som1_ek.dts - Device Tree file for SAMA5D27-SOM1-EK board
3104+ *
3105+ * Copyright (c) 2017, Microchip Technology Inc.
3106+ * 2016 Nicolas Ferre <nicolas.ferre@atmel.com>
3107+ * 2017 Cristian Birsan <cristian.birsan@microchip.com>
3108+ * 2017 Claudiu Beznea <claudiu.beznea@microchip.com>
3109+ *
3110+ * This file is dual-licensed: you can use it either under the terms
3111+ * of the GPL or the X11 license, at your option. Note that this dual
3112+ * licensing only applies to this file, and not this project as a
3113+ * whole.
3114+ *
3115+ * a) This file is free software; you can redistribute it and/or
3116+ * modify it under the terms of the GNU General Public License as
3117+ * published by the Free Software Foundation; either version 2 of the
3118+ * License, or (at your option) any later version.
3119+ *
3120+ * This file is distributed in the hope that it will be useful,
3121+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3122+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3123+ * GNU General Public License for more details.
3124+ *
3125+ * Or, alternatively,
3126+ *
3127+ * b) Permission is hereby granted, free of charge, to any person
3128+ * obtaining a copy of this software and associated documentation
3129+ * files (the "Software"), to deal in the Software without
3130+ * restriction, including without limitation the rights to use,
3131+ * copy, modify, merge, publish, distribute, sublicense, and/or
3132+ * sell copies of the Software, and to permit persons to whom the
3133+ * Software is furnished to do so, subject to the following
3134+ * conditions:
3135+ *
3136+ * The above copyright notice and this permission notice shall be
3137+ * included in all copies or substantial portions of the Software.
3138+ *
3139+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3140+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3141+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3142+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3143+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3144+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3145+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3146+ * OTHER DEALINGS IN THE SOFTWARE.
3147+ */
3148+/dts-v1/;
3149+#include "at91-sama5d27_som1.dtsi"
3150+#include <dt-bindings/mfd/atmel-flexcom.h>
3151+#include <dt-bindings/gpio/gpio.h>
3152+
3153+/ {
3154+ model = "Atmel SAMA5D27 SOM1 EK";
3155+ compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
3156+
3157+ chosen {
3158+ stdout-path = "serial0:115200n8";
3159+ };
3160+
3161+ ahb {
3162+ usb0: gadget@00300000 {
3163+ atmel,vbus-gpio = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>;
3164+ pinctrl-names = "default";
3165+ pinctrl-0 = <&pinctrl_usba_vbus>;
3166+ status = "okay";
3167+ };
3168+
3169+ usb1: ohci@00400000 {
3170+ num-ports = <3>;
3171+ atmel,vbus-gpio = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>;
3172+ pinctrl-names = "default";
3173+ pinctrl-0 = <&pinctrl_usb_default>;
3174+ status = "okay";
3175+ };
3176+
3177+ usb2: ehci@00500000 {
3178+ status = "okay";
3179+ };
3180+
3181+ sdmmc0: sdio-host@a0000000 {
3182+ bus-width = <8>;
3183+ pinctrl-names = "default";
3184+ pinctrl-0 = <&pinctrl_sdmmc0_default>;
3185+ status = "okay";
3186+ };
3187+
3188+ sdmmc1: sdio-host@b0000000 {
3189+ bus-width = <4>;
3190+ pinctrl-names = "default";
3191+ pinctrl-0 = <&pinctrl_sdmmc1_default>;
3192+ status = "okay";
3193+ };
3194+
3195+ apb {
3196+ isc: isc@f0008000 {
3197+ pinctrl-names = "default";
3198+ pinctrl-0 = <&pinctrl_isc_base &pinctrl_isc_data_8bit &pinctrl_isc_data_9_10 &pinctrl_isc_data_11_12>;
3199+ status = "okay";
3200+ };
3201+
3202+ spi0: spi@f8000000 {
3203+ pinctrl-names = "default";
3204+ pinctrl-0 = <&pinctrl_spi0_default>;
3205+ status = "okay";
3206+ };
3207+
3208+ macb0: ethernet@f8008000 {
3209+ status = "okay";
3210+ };
3211+
3212+ uart1: serial@f8020000 {
3213+ pinctrl-names = "default";
3214+ pinctrl-0 = <&pinctrl_uart1_default>;
3215+ atmel,use-dma-rx;
3216+ atmel,use-dma-tx;
3217+ status = "okay";
3218+ };
3219+
3220+ uart2: serial@f8024000 {
3221+ pinctrl-names = "default";
3222+ pinctrl-0 = <&pinctrl_mikrobus2_uart>;
3223+ atmel,use-dma-rx;
3224+ atmel-use-dma-tx;
3225+ status = "okay";
3226+ };
3227+
3228+ pwm0: pwm@f802c000 {
3229+ status = "okay";
3230+ };
3231+
3232+ flx1: flexcom@f8038000 {
3233+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
3234+ status = "disabled";
3235+
3236+ i2c2: i2c@600 {
3237+ compatible = "atmel,sama5d2-i2c";
3238+ reg = <0x600 0x200>;
3239+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
3240+ dmas = <0>, <0>;
3241+ dma-names = "tx", "rx";
3242+ #address-cells = <1>;
3243+ #size-cells = <0>;
3244+ clocks = <&flx1_clk>;
3245+ pinctrl-names = "default";
3246+ pinctrl-0 = <&pinctrl_mikrobus_i2c>;
3247+ atmel,fifo-size = <16>;
3248+ status = "disabled";
3249+ };
3250+ };
3251+
3252+ shdwc@f8048010 {
3253+ atmel,shdwc-debouncer = <976>;
3254+ atmel,wakeup-rtc-timer;
3255+
3256+ input@0 {
3257+ reg = <0>;
3258+ atmel,wakeup-type = "low";
3259+ };
3260+ };
3261+
3262+ watchdog@f8048040 {
3263+ status = "okay";
3264+ };
3265+
3266+ can0: can@f8054000 {
3267+ pinctrl-names = "default";
3268+ pinctrl-0 = <&pinctrl_can0_default>;
3269+ };
3270+
3271+ uart3: serial@fc008000 {
3272+ atmel,use-dma-rx;
3273+ atmel,use-dma-tx;
3274+ pinctrl-names = "default";
3275+ pinctrl-0 = <&pinctrl_uart3_default>;
3276+ status = "disabled";
3277+ };
3278+
3279+ uart4: serial@fc00c000 {
3280+ atmel,use-dma-rx;
3281+ atmel,use-dma-tx;
3282+ pinctrl-name = "default";
3283+ pinctrl-0 = <&pinctrl_mikrobus1_uart>;
3284+ status = "okay";
3285+ };
3286+
3287+ flx3: flexcom@fc014000 {
3288+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
3289+ status = "disabled";
3290+
3291+ uart7: serial@200 {
3292+ compatible = "atmel,at91sam9260-usart";
3293+ reg = <0x200 0x200>;
3294+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
3295+ clocks = <&flx3_clk>;
3296+ clock-names = "usart";
3297+ pinctrl-names = "default";
3298+ pinctrl-0 = <&pinctrl_flx3_default>;
3299+ atmel,fifo-size = <32>;
3300+ status = "disabled";
3301+ };
3302+
3303+ spi2: spi@400 {
3304+ compatible = "atmel,at91rm9200-spi";
3305+ reg = <0x400 0x200>;
3306+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
3307+ clocks = <&flx3_clk>;
3308+ clock-names = "spi_clk";
3309+ pinctrl-names = "default";
3310+ pinctrl-0 = <&pinctrl_flx3_default>;
3311+ atmel,fifo-size = <16>;
3312+ status = "disabled";
3313+ };
3314+ };
3315+
3316+ flx4: flexcom@fc018000 {
3317+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
3318+ status = "okay";
3319+
3320+ uart6: serial@200 {
3321+ compatible = "atmel,at91sam9260-usart";
3322+ reg = <0x200 0x200>;
3323+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
3324+ clocks = <&flx4_clk>;
3325+ clock-names = "usart";
3326+ pinctrl-names = "default";
3327+ pinctrl-0 = <&pinctrl_flx4_default>;
3328+ atmel,fifo-size = <32>;
3329+ status = "disabled";
3330+ };
3331+
3332+ spi3: spi@400 {
3333+ compatible = "atmel,at91rm9200-spi";
3334+ reg = <0x400 0x200>;
3335+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
3336+ clocks = <&flx4_clk>;
3337+ clock-names = "spi_clk";
3338+ pinctrl-names = "default";
3339+ pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>;
3340+ atmel,fifo-size = <16>;
3341+ status = "okay";
3342+ };
3343+
3344+ i2c3: i2c@600 {
3345+ compatible = "atmel,sama5d2-i2c";
3346+ reg = <0x600 0x200>;
3347+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
3348+ dmas = <0>, <0>;
3349+ dma-names = "tx", "rx";
3350+ #address-cells = <1>;
3351+ #size-cells = <0>;
3352+ clocks = <&flx4_clk>;
3353+ pinctrl-names = "default";
3354+ pinctrl-0 = <&pinctrl_flx4_default>;
3355+ atmel,fifo-size = <16>;
3356+ status = "disabled";
3357+ };
3358+ };
3359+
3360+ i2c1: i2c@fc028000 {
3361+ dmas = <0>, <0>;
3362+ pinctrl-names = "default";
3363+ pinctrl-0 = <&pinctrl_i2c1_default>;
3364+ status = "okay";
3365+ };
3366+
3367+ pinctrl@fc038000 {
3368+
3369+ pinctrl_can0_default: can0_default {
3370+ pinmux = <PIN_PC10__CANTX0>,
3371+ <PIN_PC11__CANRX0>;
3372+ bias-disable;
3373+ };
3374+
3375+ pinctrl_can1_default: can1_default {
3376+ pinmux = <PIN_PC26__CANTX1>,
3377+ <PIN_PC27__CANRX1>;
3378+ bias-disable;
3379+ };
3380+
3381+ pinctrl_flx3_default: flx3_default {
3382+ pinmux = <PIN_PC20__FLEXCOM3_IO0>,
3383+ <PIN_PC19__FLEXCOM3_IO1>,
3384+ <PIN_PC18__FLEXCOM3_IO2>,
3385+ <PIN_PC21__FLEXCOM3_IO3>,
3386+ <PIN_PC22__FLEXCOM3_IO4>;
3387+ bias-disable;
3388+ };
3389+
3390+ pinctrl_i2c1_default: i2c1_default {
3391+ pinmux = <PIN_PD4__TWD1>,
3392+ <PIN_PD5__TWCK1>;
3393+ bias-disable;
3394+ };
3395+
3396+ pinctrl_isc_base: isc_base {
3397+ pinmux = <PIN_PC21__ISC_PCK>,
3398+ <PIN_PC22__ISC_VSYNC>,
3399+ <PIN_PC23__ISC_HSYNC>,
3400+ <PIN_PC24__ISC_MCK>;
3401+ bias-disable;
3402+ };
3403+
3404+ pinctrl_isc_data_8bit: isc_data_8bit {
3405+ pinmux = <PIN_PC20__ISC_D11>,
3406+ <PIN_PC19__ISC_D10>,
3407+ <PIN_PC18__ISC_D9>,
3408+ <PIN_PC17__ISC_D8>,
3409+ <PIN_PC16__ISC_D7>,
3410+ <PIN_PC15__ISC_D6>,
3411+ <PIN_PC14__ISC_D5>,
3412+ <PIN_PC13__ISC_D4>;
3413+ bias-disable;
3414+ };
3415+
3416+ pinctrl_isc_data_9_10: isc_data_9_10 {
3417+ pinmux = <PIN_PC12__ISC_D3>,
3418+ <PIN_PC11__ISC_D2>;
3419+ bias-disable;
3420+ };
3421+
3422+ pinctrl_isc_data_11_12: isc_data_11_12 {
3423+ pinmux = <PIN_PC10__ISC_D1>,
3424+ <PIN_PC9__ISC_D0>;
3425+ bias-disable;
3426+ };
3427+
3428+ pinctrl_key_gpio_default: key_gpio_default {
3429+ pinmux = <PIN_PA29__GPIO>;
3430+ bias-pull-up;
3431+ };
3432+
3433+ pinctrl_led_gpio_default: led_gpio_default {
3434+ pinmux = <PIN_PA27__GPIO>,
3435+ <PIN_PB1__GPIO>,
3436+ <PIN_PA31__GPIO>;
3437+ bias-pull-up;
3438+ };
3439+
3440+ pinctrl_sdmmc0_default: sdmmc0_default {
3441+ cmd_data {
3442+ pinmux = <PIN_PA1__SDMMC0_CMD>,
3443+ <PIN_PA2__SDMMC0_DAT0>,
3444+ <PIN_PA3__SDMMC0_DAT1>,
3445+ <PIN_PA4__SDMMC0_DAT2>,
3446+ <PIN_PA5__SDMMC0_DAT3>,
3447+ <PIN_PA6__SDMMC0_DAT4>,
3448+ <PIN_PA7__SDMMC0_DAT5>,
3449+ <PIN_PA8__SDMMC0_DAT6>,
3450+ <PIN_PA9__SDMMC0_DAT7>;
3451+ bias-pull-up;
3452+ };
3453+
3454+ ck_cd_vddsel {
3455+ pinmux = <PIN_PA0__SDMMC0_CK>,
3456+ <PIN_PA11__SDMMC0_VDDSEL>,
3457+ <PIN_PA13__SDMMC0_CD>;
3458+ bias-disable;
3459+ };
3460+ };
3461+
3462+ pinctrl_sdmmc1_default: sdmmc1_default {
3463+ cmd_data {
3464+ pinmux = <PIN_PA28__SDMMC1_CMD>,
3465+ <PIN_PA18__SDMMC1_DAT0>,
3466+ <PIN_PA19__SDMMC1_DAT1>,
3467+ <PIN_PA20__SDMMC1_DAT2>,
3468+ <PIN_PA21__SDMMC1_DAT3>;
3469+ bias-pull-up;
3470+ };
3471+
3472+ conf-ck_cd {
3473+ pinmux = <PIN_PA22__SDMMC1_CK>,
3474+ <PIN_PA30__SDMMC1_CD>;
3475+ bias-disable;
3476+ };
3477+ };
3478+
3479+ pinctrl_spi0_default: spi0_default {
3480+ pinmux = <PIN_PA14__SPI0_SPCK>,
3481+ <PIN_PA15__SPI0_MOSI>,
3482+ <PIN_PA16__SPI0_MISO>,
3483+ <PIN_PA17__SPI0_NPCS0>;
3484+ bias-disable;
3485+ };
3486+
3487+ pinctrl_uart1_default: uart1_default {
3488+ pinmux = <PIN_PD2__URXD1>,
3489+ <PIN_PD3__UTXD1>;
3490+ bias-disable;
3491+ };
3492+
3493+ pinctrl_uart3_default: uart3_default {
3494+ pinmux = <PIN_PC12__URXD3>,
3495+ <PIN_PC13__UTXD3>;
3496+ bias-disable;
3497+ };
3498+
3499+ pinctrl_usb_default: usb_default {
3500+ pinmux = <PIN_PA10__GPIO>,
3501+ <PIN_PD19__GPIO>;
3502+ bias-disable;
3503+ };
3504+
3505+ pinctrl_usba_vbus: usba_vbus {
3506+ pinmux = <PIN_PD20__GPIO>;
3507+ bias-disable;
3508+ };
3509+
3510+ pinctrl_mikrobus1_an: mikrobus1_an {
3511+ pinmux = <PIN_PD25__GPIO>;
3512+ bias-disable;
3513+ };
3514+
3515+ pinctrl_mikrobus2_an: mikrobus2_an {
3516+ pinmux = <PIN_PD26__GPIO>;
3517+ bias-disable;
3518+ };
3519+
3520+ pinctrl_mikrobus1_rst: mikrobus1_rst {
3521+ pinmux = <PIN_PB2__GPIO>;
3522+ bias-disable;
3523+ };
3524+
3525+ pinctrl_mikrobus2_rst: mikrobus2_rst {
3526+ pinmux = <PIN_PA26__GPIO>;
3527+ bias-disable;
3528+ };
3529+
3530+ pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs {
3531+ pinmux = <PIN_PD0__FLEXCOM4_IO4>;
3532+ bias-disable;
3533+ };
3534+
3535+ pinctrl_mikrobus2_spi_cs: mikrobus2_spi_cs {
3536+ pinmux = <PIN_PC31__FLEXCOM4_IO3>;
3537+ bias-disable;
3538+ };
3539+
3540+ pinctrl_mikrobus_spi: mikrobus_spi {
3541+ pinmux = <PIN_PC28__FLEXCOM4_IO0>,
3542+ <PIN_PC29__FLEXCOM4_IO1>,
3543+ <PIN_PC30__FLEXCOM4_IO2>;
3544+ bias-disable;
3545+ };
3546+
3547+ pinctrl_mikrobus1_pwm: mikrobus1_pwm {
3548+ pinmux = <PIN_PB1__PWML1>;
3549+ bias-disable;
3550+ };
3551+
3552+ pinctrl_mikrobus2_pwm: mikrobus2_pwm {
3553+ pinmux = <PIN_PA31__PWML0>;
3554+ bias-disable;
3555+ };
3556+
3557+ pinctrl_mikrobus1_int: mikrobus1_int {
3558+ pinmux = <PIN_PB0__GPIO>;
3559+ bias-disable;
3560+ };
3561+
3562+ pinctrl_mikrobus2_int: mikrobus2_int {
3563+ pinmux = <PIN_PA25__GPIO>;
3564+ bias-disable;
3565+ };
3566+
3567+ pinctrl_mikrobus1_uart: mikrobus1_uart {
3568+ pinmux = <PIN_PB3__URXD4>,
3569+ <PIN_PB4__UTXD4>;
3570+ bias-disable;
3571+ };
3572+
3573+ pinctrl_mikrobus2_uart: mikrobus2_uart {
3574+ pinmux = <PIN_PD23__URXD2>,
3575+ <PIN_PD24__UTXD2>;
3576+ bias-disable;
3577+ };
3578+
3579+ pinctrl_mikrobus_i2c: mikrobus1_i2c {
3580+ pinmux = <PIN_PA24__FLEXCOM1_IO0>,
3581+ <PIN_PA23__FLEXCOM1_IO1>;
3582+ bias-disable;
3583+ };
3584+
3585+ pinctrl_flx4_default: flx4_uart_default {
3586+ pinmux = <PIN_PC28__FLEXCOM4_IO0>,
3587+ <PIN_PC29__FLEXCOM4_IO1>,
3588+ <PIN_PC30__FLEXCOM4_IO2>,
3589+ <PIN_PC31__FLEXCOM4_IO3>,
3590+ <PIN_PD0__FLEXCOM4_IO4>;
3591+ bias-disable;
3592+ };
3593+ };
3594+
3595+ can1: can@fc050000 {
3596+ pinctrl-names = "default";
3597+ pinctrl-0 = <&pinctrl_can1_default>;
3598+ status = "okay";
3599+ };
3600+ };
3601+ };
3602+
3603+ gpio_keys {
3604+ compatible = "gpio-keys";
3605+
3606+ pinctrl-names = "default";
3607+ pinctrl-0 = <&pinctrl_key_gpio_default>;
3608+
3609+ pb4 {
3610+ label = "USER";
3611+ gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>;
3612+ linux,code = <0x104>;
3613+ };
3614+ };
3615+
3616+ leds {
3617+ compatible = "gpio-leds";
3618+ pinctrl-names = "default";
3619+ pinctrl-0 = <&pinctrl_led_gpio_default>;
3620+ status = "okay";
3621+
3622+ red {
3623+ label = "red";
3624+ gpios = <&pioA PIN_PA27 GPIO_ACTIVE_LOW>;
3625+ };
3626+
3627+ green {
3628+ label = "green";
3629+ gpios = <&pioA PIN_PB1 GPIO_ACTIVE_LOW>;
3630+ };
3631+
3632+ blue {
3633+ label = "blue";
3634+ gpios = <&pioA PIN_PA31 GPIO_ACTIVE_LOW>;
3635+ linux,default-trigger = "heartbeat";
3636+ };
3637+ };
3638+};
3639diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
3640index 2e2c3d1a1fa2..c7e9ccf2bc87 100644
3641--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
3642+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
3643@@ -68,7 +68,7 @@ main_xtal {
3644
3645 ahb {
3646 usb0: gadget@00300000 {
3647- atmel,vbus-gpio = <&pioA 31 GPIO_ACTIVE_HIGH>;
3648+ atmel,vbus-gpio = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>;
3649 pinctrl-names = "default";
3650 pinctrl-0 = <&pinctrl_usba_vbus>;
3651 status = "okay";
3652@@ -76,8 +76,8 @@ usb0: gadget@00300000 {
3653
3654 usb1: ohci@00400000 {
3655 num-ports = <3>;
3656- atmel,vbus-gpio = <0 /* &pioA 41 GPIO_ACTIVE_HIGH */
3657- &pioA 42 GPIO_ACTIVE_HIGH
3658+ atmel,vbus-gpio = <0 /* &pioA PIN_PB9 GPIO_ACTIVE_HIGH */
3659+ &pioA PIN_PB10 GPIO_ACTIVE_HIGH
3660 0
3661 >;
3662 pinctrl-names = "default";
3663@@ -127,7 +127,7 @@ macb0: ethernet@f8008000 {
3664 ethernet-phy@1 {
3665 reg = <0x1>;
3666 interrupt-parent = <&pioA>;
3667- interrupts = <73 IRQ_TYPE_LEVEL_LOW>;
3668+ interrupts = <PIN_PC9 IRQ_TYPE_LEVEL_LOW>;
3669 };
3670 };
3671
3672@@ -160,9 +160,9 @@ pmic@5b {
3673 compatible = "active-semi,act8945a";
3674 reg = <0x5b>;
3675 active-semi,vsel-high;
3676- active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>;
3677- active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>;
3678- active-semi,irq_gpios = <&pioA 45 GPIO_ACTIVE_LOW>;
3679+ active-semi,chglev-gpios = <&pioA PIN_PA12 GPIO_ACTIVE_HIGH>;
3680+ active-semi,lbo-gpios = <&pioA PIN_PC8 GPIO_ACTIVE_LOW>;
3681+ active-semi,irq_gpios = <&pioA PIN_PB13 GPIO_ACTIVE_LOW>;
3682 active-semi,input-voltage-threshold-microvolt = <6600>;
3683 active-semi,precondition-timeout = <40>;
3684 active-semi,total-timeout = <3>;
3685@@ -355,6 +355,14 @@ pinctrl_charger_lbo: charger_lbo {
3686 bias-pull-up;
3687 };
3688
3689+ pinctrl_classd_default: classd_default {
3690+ pinmux = <PIN_PB1__CLASSD_R0>,
3691+ <PIN_PB2__CLASSD_R1>,
3692+ <PIN_PB3__CLASSD_R2>,
3693+ <PIN_PB4__CLASSD_R3>;
3694+ bias-pull-up;
3695+ };
3696+
3697 pinctrl_flx0_default: flx0_default {
3698 pinmux = <PIN_PB28__FLEXCOM0_IO0>,
3699 <PIN_PB29__FLEXCOM0_IO1>;
3700@@ -488,6 +496,14 @@ pinctrl_usba_vbus: usba_vbus {
3701
3702 };
3703
3704+ classd: classd@fc048000 {
3705+ pinctrl-names = "default";
3706+ pinctrl-0 = <&pinctrl_classd_default>;
3707+ atmel,pwm-type = "diff";
3708+ atmel,non-overlap-time = <10>;
3709+ status = "okay";
3710+ };
3711+
3712 can1: can@fc050000 {
3713 pinctrl-names = "default";
3714 pinctrl-0 = <&pinctrl_can1_default>;
3715@@ -504,7 +520,7 @@ gpio_keys {
3716
3717 bp1 {
3718 label = "PB_USER";
3719- gpios = <&pioA 41 GPIO_ACTIVE_LOW>;
3720+ gpios = <&pioA PIN_PB9 GPIO_ACTIVE_LOW>;
3721 linux,code = <0x104>;
3722 };
3723 };
3724@@ -517,17 +533,18 @@ leds {
3725
3726 red {
3727 label = "red";
3728- gpios = <&pioA 38 GPIO_ACTIVE_LOW>;
3729+ gpios = <&pioA PIN_PB6 GPIO_ACTIVE_LOW>;
3730 };
3731
3732+
3733 green {
3734 label = "green";
3735- gpios = <&pioA 37 GPIO_ACTIVE_LOW>;
3736+ gpios = <&pioA PIN_PB5 GPIO_ACTIVE_LOW>;
3737 };
3738
3739 blue {
3740 label = "blue";
3741- gpios = <&pioA 32 GPIO_ACTIVE_LOW>;
3742+ gpios = <&pioA PIN_PB0 GPIO_ACTIVE_LOW>;
3743 linux,default-trigger = "heartbeat";
3744 };
3745 };
3746diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
3747index a4808c4fbc05..64fa3f9a39d3 100644
3748--- a/arch/arm/boot/dts/at91sam9g45.dtsi
3749+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
3750@@ -455,6 +455,16 @@ pinctrl@fffff200 {
3751 >;
3752
3753 /* shared pinctrl settings */
3754+ ac97 {
3755+ pinctrl_ac97: ac97-0 {
3756+ atmel,pins =
3757+ <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97RX */
3758+ AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97TX */
3759+ AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97FS */
3760+ AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* AC97CK */
3761+ };
3762+ };
3763+
3764 adc0 {
3765 pinctrl_adc0_adtrg: adc0_adtrg {
3766 atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
3767@@ -1043,6 +1053,17 @@ ssc1: ssc@fffa0000 {
3768 status = "disabled";
3769 };
3770
3771+ ac97: sound@fffac000 {
3772+ compatible = "atmel,at91sam9263-ac97c";
3773+ reg = <0xfffac000 0x4000>;
3774+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 4>;
3775+ pinctrl-names = "default";
3776+ pinctrl-0 = <&pinctrl_ac97>;
3777+ clocks = <&ac97_clk>;
3778+ clock-names = "ac97_clk";
3779+ status = "disabled";
3780+ };
3781+
3782 adc0: adc@fffb0000 {
3783 #address-cells = <1>;
3784 #size-cells = <0>;
3785diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
3786index 2522c3308305..94c52c555f83 100644
3787--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
3788+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
3789@@ -166,6 +166,10 @@ usb2: gadget@fff78000 {
3790 status = "okay";
3791 };
3792
3793+ ac97: sound@fffac000 {
3794+ status = "okay";
3795+ };
3796+
3797 adc0: adc@fffb0000 {
3798 pinctrl-names = "default";
3799 pinctrl-0 = <
3800diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
3801index bf8c83815753..7c957ea06c66 100644
3802--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
3803+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
3804@@ -55,6 +55,11 @@ cpu@0 {
3805
3806 /include/ "bcm-cygnus-clock.dtsi"
3807
3808+ pmu {
3809+ compatible = "arm,cortex-a9-pmu";
3810+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
3811+ };
3812+
3813 core {
3814 compatible = "simple-bus";
3815 ranges = <0x00000000 0x19000000 0x1000000>;
3816@@ -119,6 +124,21 @@ pinctrl: pinctrl@0301d0c8 {
3817 compatible = "brcm,cygnus-pinmux";
3818 reg = <0x0301d0c8 0x30>,
3819 <0x0301d24c 0x2c>;
3820+
3821+ spi_0: spi_0 {
3822+ function = "spi0";
3823+ groups = "spi0_grp";
3824+ };
3825+
3826+ spi_1: spi_1 {
3827+ function = "spi1";
3828+ groups = "spi1_grp";
3829+ };
3830+
3831+ spi_2: spi_2 {
3832+ function = "spi2";
3833+ groups = "spi2_grp";
3834+ };
3835 };
3836
3837 mailbox: mailbox@03024024 {
3838@@ -300,6 +320,23 @@ msi1: msi-controller {
3839 };
3840 };
3841
3842+ dma0: dma@18018000 {
3843+ compatible = "arm,pl330", "arm,primecell";
3844+ reg = <0x18018000 0x1000>;
3845+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
3846+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
3847+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
3848+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
3849+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
3850+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
3851+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
3852+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
3853+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
3854+ clocks = <&apb_clk>;
3855+ clock-names = "apb_pclk";
3856+ #dma-cells = <1>;
3857+ };
3858+
3859 uart0: serial@18020000 {
3860 compatible = "snps,dw-apb-uart";
3861 reg = <0x18020000 0x100>;
3862@@ -324,7 +361,7 @@ uart1: serial@18021000 {
3863
3864 uart2: serial@18022000 {
3865 compatible = "snps,dw-apb-uart";
3866- reg = <0x18020000 0x100>;
3867+ reg = <0x18022000 0x100>;
3868 reg-shift = <2>;
3869 reg-io-width = <4>;
3870 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
3871@@ -344,6 +381,52 @@ uart3: serial@18023000 {
3872 status = "disabled";
3873 };
3874
3875+ spi0: spi@18028000 {
3876+ compatible = "arm,pl022", "arm,primecell";
3877+ reg = <0x18028000 0x1000>;
3878+ #address-cells = <1>;
3879+ #size-cells = <0>;
3880+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
3881+ pinctrl-0 = <&spi_0>;
3882+ clocks = <&axi81_clk>;
3883+ clock-names = "apb_pclk";
3884+ status = "disabled";
3885+ };
3886+
3887+ spi1: spi@18029000 {
3888+ compatible = "arm,pl022", "arm,primecell";
3889+ reg = <0x18029000 0x1000>;
3890+ #address-cells = <1>;
3891+ #size-cells = <0>;
3892+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
3893+ pinctrl-0 = <&spi_1>;
3894+ clocks = <&axi81_clk>;
3895+ clock-names = "apb_pclk";
3896+ status = "disabled";
3897+ };
3898+
3899+ spi2: spi@1802a000 {
3900+ compatible = "arm,pl022", "arm,primecell";
3901+ reg = <0x1802a000 0x1000>;
3902+ #address-cells = <1>;
3903+ #size-cells = <0>;
3904+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
3905+ pinctrl-0 = <&spi_2>;
3906+ clocks = <&axi81_clk>;
3907+ clock-names = "apb_pclk";
3908+ status = "disabled";
3909+ };
3910+
3911+ sdhci0: sdhci@18041000 {
3912+ compatible = "brcm,sdhci-iproc-cygnus";
3913+ reg = <0x18041000 0x100>;
3914+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3915+ clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
3916+ bus-width = <4>;
3917+ sdhci,auto-cmd12;
3918+ status = "disabled";
3919+ };
3920+
3921 eth0: ethernet@18042000 {
3922 compatible = "brcm,amac";
3923 reg = <0x18042000 0x1000>,
3924@@ -353,6 +436,16 @@ eth0: ethernet@18042000 {
3925 status = "disabled";
3926 };
3927
3928+ sdhci1: sdhci@18043000 {
3929+ compatible = "brcm,sdhci-iproc-cygnus";
3930+ reg = <0x18043000 0x100>;
3931+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
3932+ clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
3933+ bus-width = <4>;
3934+ sdhci,auto-cmd12;
3935+ status = "disabled";
3936+ };
3937+
3938 nand: nand@18046000 {
3939 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
3940 reg = <0x18046000 0x600>, <0xf8105408 0x600>,
3941@@ -366,6 +459,33 @@ nand: nand@18046000 {
3942 brcm,nand-has-wp;
3943 };
3944
3945+ ehci0: usb@18048000 {
3946+ compatible = "generic-ehci";
3947+ reg = <0x18048000 0x100>;
3948+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
3949+ status = "disabled";
3950+ };
3951+
3952+ ohci0: usb@18048800 {
3953+ compatible = "generic-ohci";
3954+ reg = <0x18048800 0x100>;
3955+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
3956+ status = "disabled";
3957+ };
3958+
3959+ v3d: v3d@180a2000 {
3960+ compatible = "brcm,cygnus-v3d";
3961+ reg = <0x180a2000 0x1000>;
3962+ clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>;
3963+ clock-names = "v3d_clk";
3964+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
3965+ status = "disabled";
3966+ };
3967+
3968+ vc4: gpu {
3969+ compatible = "brcm,cygnus-vc4";
3970+ };
3971+
3972 gpio_asiu: gpio@180a5000 {
3973 compatible = "brcm,cygnus-asiu-gpio";
3974 reg = <0x180a5000 0x668>;
3975@@ -444,19 +564,6 @@ touchscreen: touchscreen@180a6000 {
3976 status = "disabled";
3977 };
3978
3979- v3d: v3d@180a2000 {
3980- compatible = "brcm,cygnus-v3d";
3981- reg = <0x180a2000 0x1000>;
3982- clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>;
3983- clock-names = "v3d_clk";
3984- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
3985- status = "disabled";
3986- };
3987-
3988- vc4: gpu {
3989- compatible = "brcm,cygnus-vc4";
3990- };
3991-
3992 adc: adc@180a6000 {
3993 compatible = "brcm,iproc-static-adc";
3994 #io-channel-cells = <1>;
3995@@ -467,5 +574,19 @@ adc: adc@180a6000 {
3996 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
3997 status = "disabled";
3998 };
3999+
4000+ keypad: keypad@180ac000 {
4001+ compatible = "brcm,bcm-keypad";
4002+ reg = <0x180ac000 0x14c>;
4003+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
4004+ clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>;
4005+ clock-names = "peri_clk";
4006+ clock-frequency = <31250>;
4007+ pull-up-enabled;
4008+ col-debounce-filter-period = <0>;
4009+ status-debounce-filter-period = <0>;
4010+ row-output-enabled;
4011+ status = "disabled";
4012+ };
4013 };
4014 };
4015diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
4016index 7204d1def23d..dff66974feed 100644
4017--- a/arch/arm/boot/dts/bcm-nsp.dtsi
4018+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
4019@@ -215,6 +215,7 @@ sdio: sdhci@21000 {
4020 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
4021 sdhci,auto-cmd12;
4022 clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
4023+ dma-coherent;
4024 status = "disabled";
4025 };
4026
4027@@ -224,6 +225,7 @@ amac0: ethernet@22000 {
4028 <0x110000 0x1000>;
4029 reg-names = "amac_base", "idm_base";
4030 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
4031+ dma-coherent;
4032 status = "disabled";
4033 };
4034
4035@@ -233,6 +235,7 @@ amac1: ethernet@23000 {
4036 <0x111000 0x1000>;
4037 reg-names = "amac_base", "idm_base";
4038 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
4039+ dma-coherent;
4040 status = "disabled";
4041 };
4042
4043@@ -242,6 +245,7 @@ amac2: ethernet@24000 {
4044 <0x112000 0x1000>;
4045 reg-names = "amac_base", "idm_base";
4046 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
4047+ dma-coherent;
4048 status = "disabled";
4049 };
4050
4051@@ -252,6 +256,7 @@ mailbox: mailbox@25000 {
4052 #mbox-cells = <1>;
4053 brcm,rx-status-len = <32>;
4054 brcm,use-bcm-hdr;
4055+ dma-coherent;
4056 };
4057
4058 nand: nand@26000 {
4059@@ -297,6 +302,32 @@ qspi: qspi@27200 {
4060 #size-cells = <0>;
4061 };
4062
4063+ xhci: usb@29000 {
4064+ compatible = "generic-xhci";
4065+ reg = <0x29000 0x1000>;
4066+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
4067+ phys = <&usb3_phy>;
4068+ phy-names = "usb3-phy";
4069+ dma-coherent;
4070+ status = "disabled";
4071+ };
4072+
4073+ ehci0: usb@2a000 {
4074+ compatible = "generic-ehci";
4075+ reg = <0x2a000 0x100>;
4076+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
4077+ dma-coherent;
4078+ status = "disabled";
4079+ };
4080+
4081+ ohci0: usb@2b000 {
4082+ compatible = "generic-ohci";
4083+ reg = <0x2b000 0x100>;
4084+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
4085+ dma-coherent;
4086+ status = "disabled";
4087+ };
4088+
4089 crypto@2f000 {
4090 compatible = "brcm,spum-nsp-crypto";
4091 reg = <0x2f000 0x900>;
4092@@ -321,20 +352,6 @@ pwm: pwm@31000 {
4093 status = "disabled";
4094 };
4095
4096- ehci0: usb@2a000 {
4097- compatible = "generic-ehci";
4098- reg = <0x2a000 0x100>;
4099- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
4100- status = "disabled";
4101- };
4102-
4103- ohci0: usb@2b000 {
4104- compatible = "generic-ohci";
4105- reg = <0x2b000 0x100>;
4106- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
4107- status = "disabled";
4108- };
4109-
4110 rng: rng@33000 {
4111 compatible = "brcm,bcm-nsp-rng";
4112 reg = <0x33000 0x14>;
4113@@ -376,6 +393,7 @@ i2c0: i2c@38000 {
4114 #size-cells = <0>;
4115 interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
4116 clock-frequency = <100000>;
4117+ dma-coherent;
4118 status = "disabled";
4119 };
4120
4121@@ -446,6 +464,7 @@ sata: ahci@41000 {
4122 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
4123 #address-cells = <1>;
4124 #size-cells = <0>;
4125+ dma-coherent;
4126 status = "disabled";
4127
4128 sata0: sata-port@0 {
4129@@ -460,6 +479,15 @@ sata1: sata-port@1 {
4130 phy-names = "sata-phy";
4131 };
4132 };
4133+
4134+ usb3_phy: usb3-phy@104000 {
4135+ compatible = "brcm,ns-bx-usb3-phy";
4136+ reg = <0x104000 0x1000>,
4137+ <0x032000 0x1000>;
4138+ reg-names = "dmp", "ccb-mii";
4139+ #phy-cells = <0>;
4140+ status = "disabled";
4141+ };
4142 };
4143
4144 pcie0: pcie@18012000 {
4145@@ -483,6 +511,7 @@ pcie0: pcie@18012000 {
4146 */
4147 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
4148
4149+ dma-coherent;
4150 status = "disabled";
4151
4152 msi-parent = <&msi0>;
4153@@ -519,6 +548,7 @@ pcie1: pcie@18013000 {
4154 */
4155 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
4156
4157+ dma-coherent;
4158 status = "disabled";
4159
4160 msi-parent = <&msi1>;
4161@@ -555,6 +585,7 @@ pcie2: pcie@18014000 {
4162 */
4163 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
4164
4165+ dma-coherent;
4166 status = "disabled";
4167
4168 msi-parent = <&msi2>;
4169diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
4170index d0704540db6b..9f866491efdf 100644
4171--- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
4172+++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
4173@@ -99,3 +99,9 @@ i2s_alt0: i2s_alt0 {
4174 &hdmi {
4175 hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
4176 };
4177+
4178+&uart0 {
4179+ pinctrl-names = "default";
4180+ pinctrl-0 = <&uart0_gpio14>;
4181+ status = "okay";
4182+};
4183diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts
4184index 46d078e29017..4b1af06c8dc0 100644
4185--- a/arch/arm/boot/dts/bcm2835-rpi-a.dts
4186+++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts
4187@@ -94,3 +94,9 @@ i2s_alt2: i2s_alt2 {
4188 &hdmi {
4189 hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
4190 };
4191+
4192+&uart0 {
4193+ pinctrl-names = "default";
4194+ pinctrl-0 = <&uart0_gpio14>;
4195+ status = "okay";
4196+};
4197diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
4198index 432088ebb0a1..a846f1e781d8 100644
4199--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
4200+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
4201@@ -101,3 +101,9 @@ i2s_alt0: i2s_alt0 {
4202 &hdmi {
4203 hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
4204 };
4205+
4206+&uart0 {
4207+ pinctrl-names = "default";
4208+ pinctrl-0 = <&uart0_gpio14>;
4209+ status = "okay";
4210+};
4211diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
4212index 4133bc2cd9be..e860964e39fa 100644
4213--- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
4214+++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
4215@@ -94,3 +94,9 @@ i2s_alt2: i2s_alt2 {
4216 &hdmi {
4217 hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
4218 };
4219+
4220+&uart0 {
4221+ pinctrl-names = "default";
4222+ pinctrl-0 = <&uart0_gpio14>;
4223+ status = "okay";
4224+};
4225diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
4226index 4d56fe3006b0..5d77f3f8c4c5 100644
4227--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
4228+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
4229@@ -89,3 +89,9 @@ &gpio {
4230 &hdmi {
4231 hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
4232 };
4233+
4234+&uart0 {
4235+ pinctrl-names = "default";
4236+ pinctrl-0 = <&uart0_gpio14>;
4237+ status = "okay";
4238+};
4239diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
4240new file mode 100644
4241index 000000000000..82651c3eb682
4242--- /dev/null
4243+++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
4244@@ -0,0 +1,139 @@
4245+/*
4246+ * Copyright (C) 2017 Stefan Wahren <stefan.wahren@i2se.com>
4247+ *
4248+ * The code contained herein is licensed under the GNU General Public
4249+ * License. You may obtain a copy of the GNU General Public License
4250+ * Version 2 or later at the following locations:
4251+ *
4252+ * http://www.opensource.org/licenses/gpl-license.html
4253+ * http://www.gnu.org/copyleft/gpl.html
4254+ */
4255+
4256+/dts-v1/;
4257+#include "bcm2835.dtsi"
4258+#include "bcm2835-rpi.dtsi"
4259+#include "bcm283x-rpi-usb-host.dtsi"
4260+
4261+/ {
4262+ compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
4263+ model = "Raspberry Pi Zero W";
4264+
4265+ /* Needed by firmware to properly init UARTs */
4266+ aliases {
4267+ uart0 = "/soc/serial@7e201000";
4268+ uart1 = "/soc/serial@7e215040";
4269+ serial0 = "/soc/serial@7e201000";
4270+ serial1 = "/soc/serial@7e215040";
4271+ };
4272+
4273+ leds {
4274+ act {
4275+ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
4276+ };
4277+ };
4278+
4279+ wifi_pwrseq: wifi-pwrseq {
4280+ compatible = "mmc-pwrseq-simple";
4281+ pinctrl-names = "default";
4282+ pinctrl-0 = <&wl_on>;
4283+ reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
4284+ };
4285+};
4286+
4287+&gpio {
4288+ /*
4289+ * This is based on the official GPU firmware DT blob.
4290+ *
4291+ * Legend:
4292+ * "NC" = not connected (no rail from the SoC)
4293+ * "FOO" = GPIO line named "FOO" on the schematic
4294+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
4295+ */
4296+ gpio-line-names = "GPIO0",
4297+ "GPIO1",
4298+ "SDA1",
4299+ "SCL1",
4300+ "GPIO_GCLK",
4301+ "GPIO5",
4302+ "GPIO6",
4303+ "SPI_CE1_N",
4304+ "SPI_CE0_N",
4305+ "SPI_MISO",
4306+ "SPI_MOSI",
4307+ "SPI_SCLK",
4308+ "GPIO12",
4309+ "GPIO13",
4310+ /* Serial port */
4311+ "TXD0",
4312+ "RXD0",
4313+ "GPIO16",
4314+ "GPIO17",
4315+ "GPIO18",
4316+ "GPIO19",
4317+ "GPIO20",
4318+ "GPIO21",
4319+ "GPIO22",
4320+ "GPIO23",
4321+ "GPIO24",
4322+ "GPIO25",
4323+ "GPIO26",
4324+ "GPIO27",
4325+ "SDA0",
4326+ "SCL0",
4327+ "NC", /* GPIO30 */
4328+ "NC", /* GPIO31 */
4329+ "NC", /* GPIO32 */
4330+ "NC", /* GPIO33 */
4331+ "NC", /* GPIO34 */
4332+ "NC", /* GPIO35 */
4333+ "NC", /* GPIO36 */
4334+ "NC", /* GPIO37 */
4335+ "NC", /* GPIO38 */
4336+ "NC", /* GPIO39 */
4337+ "CAM_GPIO1", /* GPIO40 */
4338+ "WL_ON", /* GPIO41 */
4339+ "NC", /* GPIO42 */
4340+ "WIFI_CLK", /* GPIO43 */
4341+ "CAM_GPIO0", /* GPIO44 */
4342+ "BT_ON", /* GPIO45 */
4343+ "HDMI_HPD_N",
4344+ "STATUS_LED_N",
4345+ /* Used by SD Card */
4346+ "SD_CLK_R",
4347+ "SD_CMD_R",
4348+ "SD_DATA0_R",
4349+ "SD_DATA1_R",
4350+ "SD_DATA2_R",
4351+ "SD_DATA3_R";
4352+
4353+ pinctrl-0 = <&gpioout &alt0>;
4354+
4355+ wl_on: wl-on {
4356+ brcm,pins = <41>;
4357+ brcm,function = <BCM2835_FSEL_GPIO_OUT>;
4358+ };
4359+};
4360+
4361+&hdmi {
4362+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
4363+};
4364+
4365+&sdhci {
4366+ #address-cells = <1>;
4367+ #size-cells = <0>;
4368+ pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
4369+ mmc-pwrseq = <&wifi_pwrseq>;
4370+ non-removable;
4371+ status = "okay";
4372+
4373+ brcmf: wifi@1 {
4374+ reg = <1>;
4375+ compatible = "brcm,bcm4329-fmac";
4376+ };
4377+};
4378+
4379+&uart0 {
4380+ pinctrl-names = "default";
4381+ pinctrl-0 = <&uart0_gpio14>;
4382+ status = "okay";
4383+};
4384diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
4385index 79a20d520931..70362405c595 100644
4386--- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts
4387+++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
4388@@ -103,3 +103,9 @@ i2s_alt0: i2s_alt0 {
4389 &hdmi {
4390 hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
4391 };
4392+
4393+&uart0 {
4394+ pinctrl-names = "default";
4395+ pinctrl-0 = <&uart0_gpio14>;
4396+ status = "okay";
4397+};
4398diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
4399index e55b362b9d6e..e36c392a2b8f 100644
4400--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
4401+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
4402@@ -39,7 +39,7 @@ gpioout: gpioout {
4403 };
4404
4405 alt0: alt0 {
4406- brcm,pins = <4 5 7 8 9 10 11 14 15>;
4407+ brcm,pins = <4 5 7 8 9 10 11>;
4408 brcm,function = <BCM2835_FSEL_ALT0>;
4409 };
4410 };
4411diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
4412index bf19e8cfb9e6..e8de41444b68 100644
4413--- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
4414+++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
4415@@ -39,3 +39,9 @@ i2s_alt0: i2s_alt0 {
4416 &hdmi {
4417 hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
4418 };
4419+
4420+&uart0 {
4421+ pinctrl-names = "default";
4422+ pinctrl-0 = <&uart0_gpio14>;
4423+ status = "okay";
4424+};
4425diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi
4426index da3deeb42592..2c26d0be8b03 100644
4427--- a/arch/arm/boot/dts/bcm2836.dtsi
4428+++ b/arch/arm/boot/dts/bcm2836.dtsi
4429@@ -36,6 +36,7 @@ timer {
4430 cpus: cpus {
4431 #address-cells = <1>;
4432 #size-cells = <0>;
4433+ enable-method = "brcm,bcm2836-smp";
4434
4435 v7_cpu0: cpu@0 {
4436 device_type = "cpu";
4437diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
4438index c72a27d908b6..20725ca487f3 100644
4439--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
4440+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
4441@@ -1 +1,51 @@
4442-#include "arm64/broadcom/bcm2837-rpi-3-b.dts"
4443+/dts-v1/;
4444+#include "bcm2837.dtsi"
4445+#include "bcm2835-rpi.dtsi"
4446+#include "bcm283x-rpi-smsc9514.dtsi"
4447+#include "bcm283x-rpi-usb-host.dtsi"
4448+
4449+/ {
4450+ compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
4451+ model = "Raspberry Pi 3 Model B";
4452+
4453+ memory {
4454+ reg = <0 0x40000000>;
4455+ };
4456+
4457+ leds {
4458+ act {
4459+ gpios = <&gpio 47 0>;
4460+ };
4461+ };
4462+};
4463+
4464+/* uart0 communicates with the BT module */
4465+&uart0 {
4466+ pinctrl-names = "default";
4467+ pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>;
4468+ status = "okay";
4469+};
4470+
4471+/* uart1 is mapped to the pin header */
4472+&uart1 {
4473+ pinctrl-names = "default";
4474+ pinctrl-0 = <&uart1_gpio14>;
4475+ status = "okay";
4476+};
4477+
4478+/* SDHCI is used to control the SDIO for wireless */
4479+&sdhci {
4480+ pinctrl-names = "default";
4481+ pinctrl-0 = <&emmc_gpio34>;
4482+ status = "okay";
4483+ bus-width = <4>;
4484+ non-removable;
4485+};
4486+
4487+/* SDHOST is used to drive the SD card */
4488+&sdhost {
4489+ pinctrl-names = "default";
4490+ pinctrl-0 = <&sdhost_gpio48>;
4491+ status = "okay";
4492+ bus-width = <4>;
4493+};
4494diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
4495new file mode 100644
4496index 000000000000..bc1cca5cf43c
4497--- /dev/null
4498+++ b/arch/arm/boot/dts/bcm2837.dtsi
4499@@ -0,0 +1,87 @@
4500+#include "bcm283x.dtsi"
4501+
4502+/ {
4503+ compatible = "brcm,bcm2837";
4504+
4505+ soc {
4506+ ranges = <0x7e000000 0x3f000000 0x1000000>,
4507+ <0x40000000 0x40000000 0x00001000>;
4508+ dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
4509+
4510+ local_intc: local_intc {
4511+ compatible = "brcm,bcm2836-l1-intc";
4512+ reg = <0x40000000 0x100>;
4513+ interrupt-controller;
4514+ #interrupt-cells = <1>;
4515+ interrupt-parent = <&local_intc>;
4516+ };
4517+ };
4518+
4519+ timer {
4520+ compatible = "arm,armv7-timer";
4521+ interrupt-parent = <&local_intc>;
4522+ interrupts = <0>, // PHYS_SECURE_PPI
4523+ <1>, // PHYS_NONSECURE_PPI
4524+ <3>, // VIRT_PPI
4525+ <2>; // HYP_PPI
4526+ always-on;
4527+ };
4528+
4529+ cpus: cpus {
4530+ #address-cells = <1>;
4531+ #size-cells = <0>;
4532+ enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
4533+
4534+ cpu0: cpu@0 {
4535+ device_type = "cpu";
4536+ compatible = "arm,cortex-a53";
4537+ reg = <0>;
4538+ enable-method = "spin-table";
4539+ cpu-release-addr = <0x0 0x000000d8>;
4540+ };
4541+
4542+ cpu1: cpu@1 {
4543+ device_type = "cpu";
4544+ compatible = "arm,cortex-a53";
4545+ reg = <1>;
4546+ enable-method = "spin-table";
4547+ cpu-release-addr = <0x0 0x000000e0>;
4548+ };
4549+
4550+ cpu2: cpu@2 {
4551+ device_type = "cpu";
4552+ compatible = "arm,cortex-a53";
4553+ reg = <2>;
4554+ enable-method = "spin-table";
4555+ cpu-release-addr = <0x0 0x000000e8>;
4556+ };
4557+
4558+ cpu3: cpu@3 {
4559+ device_type = "cpu";
4560+ compatible = "arm,cortex-a53";
4561+ reg = <3>;
4562+ enable-method = "spin-table";
4563+ cpu-release-addr = <0x0 0x000000f0>;
4564+ };
4565+ };
4566+};
4567+
4568+/* Make the BCM2835-style global interrupt controller be a child of the
4569+ * CPU-local interrupt controller.
4570+ */
4571+&intc {
4572+ compatible = "brcm,bcm2836-armctrl-ic";
4573+ reg = <0x7e00b200 0x200>;
4574+ interrupt-parent = <&local_intc>;
4575+ interrupts = <8>;
4576+};
4577+
4578+&cpu_thermal {
4579+ coefficients = <(-538) 412000>;
4580+};
4581+
4582+/* enable thermal sensor with the correct compatible property set */
4583+&thermal {
4584+ compatible = "brcm,bcm2837-thermal";
4585+ status = "okay";
4586+};
4587diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
4588index 62e1427b3f10..8b64caabaad8 100644
4589--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
4590+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
4591@@ -52,6 +52,10 @@ leds {
4592 usb {
4593 label = "bcm53xx:blue:usb";
4594 gpios = <&hc595 0 GPIO_ACTIVE_HIGH>;
4595+ trigger-sources = <&ohci_port1>, <&ehci_port1>,
4596+ <&xhci_port1>, <&ohci_port2>,
4597+ <&ehci_port2>;
4598+ linux,default-trigger = "usbport";
4599 };
4600
4601 power0 {
4602diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
4603index a5647efe4118..d7c34fa72b4b 100644
4604--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
4605+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
4606@@ -48,6 +48,9 @@ power1 {
4607 usb {
4608 label = "bcm53xx:blue:usb";
4609 gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
4610+ trigger-sources = <&ohci_port1>, <&ehci_port1>,
4611+ <&xhci_port1>;
4612+ linux,default-trigger = "usbport";
4613 };
4614
4615 wireless {
4616diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
4617index 19ee924d7d53..83a4c60bb431 100644
4618--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
4619+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
4620@@ -42,16 +42,22 @@ power-amber {
4621 usb2 {
4622 label = "bcm53xx:white:usb2";
4623 gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>;
4624+ trigger-sources = <&ohci_port2>, <&ehci_port2>;
4625+ linux,default-trigger = "usbport";
4626 };
4627
4628 usb3-white {
4629 label = "bcm53xx:white:usb3";
4630 gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
4631+ trigger-sources = <&xhci_port1>;
4632+ linux,default-trigger = "usbport";
4633 };
4634
4635 usb3-green {
4636 label = "bcm53xx:green:usb3";
4637 gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
4638+ trigger-sources = <&ohci_port1>, <&ehci_port1>;
4639+ linux,default-trigger = "usbport";
4640 };
4641
4642 wps {
4643diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
4644index a854a5174b7f..3ed8de42cb48 100644
4645--- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
4646+++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
4647@@ -36,6 +36,8 @@ lan {
4648 usb2-port1 {
4649 label = "bcm53xx:green:usb2-port1";
4650 gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>;
4651+ trigger-sources = <&ohci_port1>, <&ehci_port1>;
4652+ linux,default-trigger = "usbport";
4653 };
4654
4655 power {
4656@@ -67,6 +69,8 @@ wan-amber {
4657 usb2-port2 {
4658 label = "bcm53xx:green:usb2-port2";
4659 gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
4660+ trigger-sources = <&ohci_port2>, <&ehci_port2>;
4661+ linux,default-trigger = "usbport";
4662 };
4663 };
4664
4665diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
4666index 97aa5d59a1d8..ec4a50e440f6 100644
4667--- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
4668+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
4669@@ -46,11 +46,16 @@ wps {
4670 usb3 {
4671 label = "bcm53xx:blue:usb3";
4672 gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
4673+ trigger-sources = <&ohci_port1>, <&ehci_port1>,
4674+ <&xhci_port1>;
4675+ linux,default-trigger = "usbport";
4676 };
4677
4678 usb2 {
4679 label = "bcm53xx:blue:usb2";
4680 gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
4681+ trigger-sources = <&ohci_port2>, <&ehci_port2>;
4682+ linux,default-trigger = "usbport";
4683 };
4684
4685 wan-blue {
4686diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
4687index 51b0641b5f79..7cc7d344fe5b 100644
4688--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
4689+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
4690@@ -71,6 +71,9 @@ wan-amber {
4691 usb3-white {
4692 label = "bcm53xx:white:usb3";
4693 gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
4694+ trigger-sources = <&ohci_port1>, <&ehci_port1>,
4695+ <&xhci_port1>;
4696+ linux,default-trigger = "usbport";
4697 };
4698
4699 2ghz {
4700diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
4701index 5f8621d00c50..bc1d1e10d4ac 100644
4702--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
4703+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
4704@@ -59,6 +59,9 @@ lan2 {
4705 usb3 {
4706 label = "bcm53xx:green:usb3";
4707 gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
4708+ trigger-sources = <&ohci_port1>, <&ehci_port1>,
4709+ <&xhci_port1>;
4710+ linux,default-trigger = "usbport";
4711 };
4712
4713 status {
4714diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
4715index 34417dac1cd0..19e61b5b066c 100644
4716--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
4717+++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
4718@@ -26,6 +26,8 @@ leds {
4719 usb {
4720 label = "bcm53xx:blue:usb";
4721 gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
4722+ trigger-sources = <&ohci_port1>, <&ehci_port1>;
4723+ linux,default-trigger = "usbport";
4724 };
4725
4726 wps {
4727diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
4728index 98647d22b291..045b9bb857f9 100644
4729--- a/arch/arm/boot/dts/bcm5301x.dtsi
4730+++ b/arch/arm/boot/dts/bcm5301x.dtsi
4731@@ -272,6 +272,19 @@ ehci: ehci@21000 {
4732 reg = <0x00021000 0x1000>;
4733 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
4734 phys = <&usb2_phy>;
4735+
4736+ #address-cells = <1>;
4737+ #size-cells = <0>;
4738+
4739+ ehci_port1: port@1 {
4740+ reg = <1>;
4741+ #trigger-source-cells = <0>;
4742+ };
4743+
4744+ ehci_port2: port@2 {
4745+ reg = <2>;
4746+ #trigger-source-cells = <0>;
4747+ };
4748 };
4749
4750 ohci: ohci@22000 {
4751@@ -280,6 +293,19 @@ ohci: ohci@22000 {
4752 compatible = "generic-ohci";
4753 reg = <0x00022000 0x1000>;
4754 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
4755+
4756+ #address-cells = <1>;
4757+ #size-cells = <0>;
4758+
4759+ ohci_port1: port@1 {
4760+ reg = <1>;
4761+ #trigger-source-cells = <0>;
4762+ };
4763+
4764+ ohci_port2: port@2 {
4765+ reg = <2>;
4766+ #trigger-source-cells = <0>;
4767+ };
4768 };
4769 };
4770
4771@@ -300,6 +326,14 @@ xhci: xhci@23000 {
4772 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
4773 phys = <&usb3_phy>;
4774 phy-names = "usb";
4775+
4776+ #address-cells = <1>;
4777+ #size-cells = <0>;
4778+
4779+ xhci_port1: port@1 {
4780+ reg = <1>;
4781+ #trigger-source-cells = <0>;
4782+ };
4783 };
4784 };
4785
4786diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi
4787index eae623f76401..c698a565b8ae 100644
4788--- a/arch/arm/boot/dts/bcm53573.dtsi
4789+++ b/arch/arm/boot/dts/bcm53573.dtsi
4790@@ -138,10 +138,12 @@ ehci: ehci@4000 {
4791
4792 ehci_port1: port@1 {
4793 reg = <1>;
4794+ #trigger-source-cells = <0>;
4795 };
4796
4797 ehci_port2: port@2 {
4798 reg = <2>;
4799+ #trigger-source-cells = <0>;
4800 };
4801 };
4802
4803@@ -158,10 +160,12 @@ ohci: ohci@d000 {
4804
4805 ohci_port1: port@1 {
4806 reg = <1>;
4807+ #trigger-source-cells = <0>;
4808 };
4809
4810 ohci_port2: port@2 {
4811 reg = <2>;
4812+ #trigger-source-cells = <0>;
4813 };
4814 };
4815 };
4816diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
4817index 000f5f19215e..53f990defd6a 100644
4818--- a/arch/arm/boot/dts/bcm911360_entphn.dts
4819+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
4820@@ -39,9 +39,12 @@ / {
4821 model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
4822 compatible = "brcm,bcm11360", "brcm,cygnus";
4823
4824+ aliases {
4825+ serial0 = &uart3;
4826+ };
4827+
4828 chosen {
4829- stdout-path = &uart3;
4830- bootargs = "console=ttyS0,115200";
4831+ stdout-path = "serial0:115200n8";
4832 };
4833
4834 gpio_keys {
4835diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/bcm947189acdbmr.dts
4836new file mode 100644
4837index 000000000000..ef263412fea5
4838--- /dev/null
4839+++ b/arch/arm/boot/dts/bcm947189acdbmr.dts
4840@@ -0,0 +1,97 @@
4841+/*
4842+ * Copyright (C) 2017 Broadcom
4843+ * Author: Florian Fainelli <f.fainelli@gmail.com>
4844+ *
4845+ * Licensed under the ISC license.
4846+ */
4847+
4848+/dts-v1/;
4849+
4850+#include "bcm53573.dtsi"
4851+
4852+/ {
4853+ compatible = "brcm,bcm947189acdbmr", "brcm,bcm47189", "brcm,bcm53573";
4854+ model = "Broadcom BCM947189ACDBMR";
4855+
4856+ chosen {
4857+ bootargs = "console=ttyS0,115200 earlycon";
4858+ };
4859+
4860+ memory {
4861+ reg = <0x00000000 0x08000000>;
4862+ };
4863+
4864+ leds {
4865+ compatible = "gpio-leds";
4866+
4867+ wps {
4868+ label = "bcm53xx:blue:wps";
4869+ gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
4870+ };
4871+
4872+ 5ghz {
4873+ label = "bcm53xx:blue:5ghz";
4874+ gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
4875+ };
4876+
4877+ 2ghz {
4878+ label = "bcm53xx:blue:2ghz";
4879+ gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
4880+ };
4881+ };
4882+
4883+ gpio-keys {
4884+ compatible = "gpio-keys";
4885+ #address-cells = <1>;
4886+ #size-cells = <0>;
4887+
4888+ restart {
4889+ label = "Reset";
4890+ linux,code = <KEY_RESTART>;
4891+ gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
4892+ };
4893+
4894+ wps {
4895+ label = "WPS";
4896+ linux,code = <KEY_WPS_BUTTON>;
4897+ gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
4898+ };
4899+ };
4900+
4901+ spi {
4902+ compatible = "spi-gpio";
4903+ num-chipselects = <1>;
4904+ gpio-sck = <&chipcommon 21 0>;
4905+ gpio-miso = <&chipcommon 22 0>;
4906+ gpio-mosi = <&chipcommon 23 0>;
4907+ cs-gpios = <&chipcommon 24 0>;
4908+ #address-cells = <1>;
4909+ #size-cells = <0>;
4910+
4911+ /* External BCM6802 MoCA chip is connected */
4912+ };
4913+};
4914+
4915+&pcie0 {
4916+ ranges = <0x00000000 0 0 0 0 0x00100000>;
4917+ #address-cells = <3>;
4918+ #size-cells = <2>;
4919+
4920+ bridge@0,0,0 {
4921+ reg = <0x0000 0 0 0 0>;
4922+ ranges = <0x00000000 0 0 0 0 0 0 0x00100000>;
4923+ #address-cells = <3>;
4924+ #size-cells = <2>;
4925+
4926+ wifi@0,1,0 {
4927+ reg = <0x0000 0 0 0 0>;
4928+ ranges = <0x00000000 0 0 0 0x00100000>;
4929+ #address-cells = <1>;
4930+ #size-cells = <1>;
4931+ };
4932+ };
4933+};
4934+
4935+&usb2 {
4936+ vcc-gpio = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
4937+};
4938diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts
4939index f5c42962c201..f9dd342cc2ae 100644
4940--- a/arch/arm/boot/dts/bcm958522er.dts
4941+++ b/arch/arm/boot/dts/bcm958522er.dts
4942@@ -170,3 +170,11 @@ partition@700000 {
4943 &uart0 {
4944 status = "okay";
4945 };
4946+
4947+&usb3_phy {
4948+ status = "okay";
4949+};
4950+
4951+&xhci {
4952+ status = "okay";
4953+};
4954diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts
4955index efcb1f67bdad..374508a9cfbf 100644
4956--- a/arch/arm/boot/dts/bcm958525er.dts
4957+++ b/arch/arm/boot/dts/bcm958525er.dts
4958@@ -182,3 +182,11 @@ &sata {
4959 &uart0 {
4960 status = "okay";
4961 };
4962+
4963+&usb3_phy {
4964+ status = "okay";
4965+};
4966+
4967+&xhci {
4968+ status = "okay";
4969+};
4970diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts
4971index b335ce02e32f..403250c5ad8e 100644
4972--- a/arch/arm/boot/dts/bcm958525xmc.dts
4973+++ b/arch/arm/boot/dts/bcm958525xmc.dts
4974@@ -202,3 +202,11 @@ &sdio {
4975 &uart0 {
4976 status = "okay";
4977 };
4978+
4979+&usb3_phy {
4980+ status = "okay";
4981+};
4982+
4983+&xhci {
4984+ status = "okay";
4985+};
4986diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts
4987index 16ab2d82a14b..fd8b8c689ffe 100644
4988--- a/arch/arm/boot/dts/bcm958622hr.dts
4989+++ b/arch/arm/boot/dts/bcm958622hr.dts
4990@@ -219,3 +219,11 @@ fixed-link {
4991 &uart0 {
4992 status = "okay";
4993 };
4994+
4995+&usb3_phy {
4996+ status = "okay";
4997+};
4998+
4999+&xhci {
5000+ status = "okay";
5001+};
5002diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts
5003index 9b921c6aa8f8..3bc50849d013 100644
5004--- a/arch/arm/boot/dts/bcm958623hr.dts
5005+++ b/arch/arm/boot/dts/bcm958623hr.dts
5006@@ -227,3 +227,11 @@ fixed-link {
5007 &uart0 {
5008 status = "okay";
5009 };
5010+
5011+&usb3_phy {
5012+ status = "okay";
5013+};
5014+
5015+&xhci {
5016+ status = "okay";
5017+};
5018diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
5019index 006b08e41a3b..d94d14b3c745 100644
5020--- a/arch/arm/boot/dts/bcm958625hr.dts
5021+++ b/arch/arm/boot/dts/bcm958625hr.dts
5022@@ -229,3 +229,11 @@ fixed-link {
5023 &uart0 {
5024 status = "okay";
5025 };
5026+
5027+&usb3_phy {
5028+ status = "okay";
5029+};
5030+
5031+&xhci {
5032+ status = "okay";
5033+};
5034diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
5035index 64740f85cf4c..2cf2392483b2 100644
5036--- a/arch/arm/boot/dts/bcm958625k.dts
5037+++ b/arch/arm/boot/dts/bcm958625k.dts
5038@@ -264,3 +264,11 @@ &uart0 {
5039 &uart1 {
5040 status = "okay";
5041 };
5042+
5043+&usb3_phy {
5044+ status = "okay";
5045+};
5046+
5047+&xhci {
5048+ status = "okay";
5049+};
5050diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts
5051index 45983c04a8a7..413dbd5d9f64 100644
5052--- a/arch/arm/boot/dts/da850-lego-ev3.dts
5053+++ b/arch/arm/boot/dts/da850-lego-ev3.dts
5054@@ -249,6 +249,15 @@ battery_pins: pinmux_battery_pins {
5055 0x4c 0x00000080 0x000000f0
5056 >;
5057 };
5058+
5059+ ev3_lcd_pins: pinmux_lcd {
5060+ pinctrl-single,bits = <
5061+ /* SIMO, GP2[11], GP2[12], CLK */
5062+ 0x14 0x00188100 0x00ffff00
5063+ /* GP5[0] */
5064+ 0x30 0x80000000 0xf0000000
5065+ >;
5066+ };
5067 };
5068
5069 &pinconf {
5070@@ -357,6 +366,21 @@ adc: adc@3 {
5071 };
5072 };
5073
5074+&spi1 {
5075+ status = "okay";
5076+ pinctrl-0 = <&ev3_lcd_pins>;
5077+ pinctrl-names = "default";
5078+ cs-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
5079+
5080+ display@0{
5081+ compatible = "lego,ev3-lcd";
5082+ reg = <0>;
5083+ spi-max-frequency = <10000000>;
5084+ a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
5085+ reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>;
5086+ };
5087+};
5088+
5089 &ehrpwm0 {
5090 status = "okay";
5091 };
5092diff --git a/arch/arm/boot/dts/dove-d3plug.dts b/arch/arm/boot/dts/dove-d3plug.dts
5093index f5f59bb5a534..e88ff83f1dec 100644
5094--- a/arch/arm/boot/dts/dove-d3plug.dts
5095+++ b/arch/arm/boot/dts/dove-d3plug.dts
5096@@ -88,7 +88,7 @@ spi-flash@0 {
5097 &pcie {
5098 status = "okay";
5099 /* Fresco Logic USB3.0 xHCI controller */
5100- pcie-port@0 {
5101+ pcie@1 {
5102 status = "okay";
5103 reset-gpios = <&gpio0 26 1>;
5104 reset-delay-us = <20000>;
5105@@ -96,7 +96,7 @@ pcie-port@0 {
5106 pinctrl-names = "default";
5107 };
5108 /* Mini-PCIe slot */
5109- pcie-port@1 {
5110+ pcie@2 {
5111 status = "okay";
5112 reset-gpios = <&gpio0 25 1>;
5113 };
5114diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
5115index 698d58cea20d..1475d3672e56 100644
5116--- a/arch/arm/boot/dts/dove.dtsi
5117+++ b/arch/arm/boot/dts/dove.dtsi
5118@@ -89,7 +89,7 @@ MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
5119 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
5120 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
5121
5122- pcie: pcie-controller {
5123+ pcie: pcie {
5124 compatible = "marvell,dove-pcie";
5125 status = "disabled";
5126 device_type = "pci";
5127@@ -106,7 +106,7 @@ pcie: pcie-controller {
5128 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
5129 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
5130
5131- pcie0: pcie-port@0 {
5132+ pcie0: pcie@1 {
5133 device_type = "pci";
5134 status = "disabled";
5135 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
5136@@ -118,13 +118,14 @@ pcie0: pcie-port@0 {
5137 #size-cells = <2>;
5138 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
5139 0x81000000 0 0 0x81000000 0x1 0 1 0>;
5140+ bus-range = <0x00 0xff>;
5141
5142 #interrupt-cells = <1>;
5143 interrupt-map-mask = <0 0 0 0>;
5144 interrupt-map = <0 0 0 0 &intc 16>;
5145 };
5146
5147- pcie1: pcie-port@1 {
5148+ pcie1: pcie@2 {
5149 device_type = "pci";
5150 status = "disabled";
5151 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
5152@@ -136,6 +137,7 @@ pcie1: pcie-port@1 {
5153 #size-cells = <2>;
5154 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
5155 0x81000000 0 0 0x81000000 0x2 0 1 0>;
5156+ bus-range = <0x00 0xff>;
5157
5158 #interrupt-cells = <1>;
5159 interrupt-map-mask = <0 0 0 0>;
5160diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi
5161new file mode 100644
5162index 000000000000..343e95f9a001
5163--- /dev/null
5164+++ b/arch/arm/boot/dts/dra7-evm-common.dtsi
5165@@ -0,0 +1,258 @@
5166+/*
5167+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
5168+ *
5169+ * This program is free software; you can redistribute it and/or modify
5170+ * it under the terms of the GNU General Public License version 2 as
5171+ * published by the Free Software Foundation.
5172+ */
5173+
5174+#include <dt-bindings/gpio/gpio.h>
5175+#include <dt-bindings/clk/ti-dra7-atl.h>
5176+#include <dt-bindings/input/input.h>
5177+
5178+/ {
5179+ chosen {
5180+ stdout-path = &uart1;
5181+ };
5182+
5183+ extcon_usb1: extcon_usb1 {
5184+ compatible = "linux,extcon-usb-gpio";
5185+ id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
5186+ };
5187+
5188+ sound0: sound0 {
5189+ compatible = "simple-audio-card";
5190+ simple-audio-card,name = "DRA7xx-EVM";
5191+ simple-audio-card,widgets =
5192+ "Headphone", "Headphone Jack",
5193+ "Line", "Line Out",
5194+ "Microphone", "Mic Jack",
5195+ "Line", "Line In";
5196+ simple-audio-card,routing =
5197+ "Headphone Jack", "HPLOUT",
5198+ "Headphone Jack", "HPROUT",
5199+ "Line Out", "LLOUT",
5200+ "Line Out", "RLOUT",
5201+ "MIC3L", "Mic Jack",
5202+ "MIC3R", "Mic Jack",
5203+ "Mic Jack", "Mic Bias",
5204+ "LINE1L", "Line In",
5205+ "LINE1R", "Line In";
5206+ simple-audio-card,format = "dsp_b";
5207+ simple-audio-card,bitclock-master = <&sound0_master>;
5208+ simple-audio-card,frame-master = <&sound0_master>;
5209+ simple-audio-card,bitclock-inversion;
5210+
5211+ sound0_master: simple-audio-card,cpu {
5212+ sound-dai = <&mcasp3>;
5213+ system-clock-frequency = <5644800>;
5214+ };
5215+
5216+ simple-audio-card,codec {
5217+ sound-dai = <&tlv320aic3106>;
5218+ clocks = <&atl_clkin2_ck>;
5219+ };
5220+ };
5221+
5222+ leds {
5223+ compatible = "gpio-leds";
5224+ led0 {
5225+ label = "dra7:usr1";
5226+ gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
5227+ default-state = "off";
5228+ };
5229+
5230+ led1 {
5231+ label = "dra7:usr2";
5232+ gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
5233+ default-state = "off";
5234+ };
5235+
5236+ led2 {
5237+ label = "dra7:usr3";
5238+ gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
5239+ default-state = "off";
5240+ };
5241+
5242+ led3 {
5243+ label = "dra7:usr4";
5244+ gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
5245+ default-state = "off";
5246+ };
5247+ };
5248+
5249+ gpio_keys {
5250+ compatible = "gpio-keys";
5251+ #address-cells = <1>;
5252+ #size-cells = <0>;
5253+ autorepeat;
5254+
5255+ USER1 {
5256+ label = "btnUser1";
5257+ linux,code = <BTN_0>;
5258+ gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
5259+ };
5260+
5261+ USER2 {
5262+ label = "btnUser2";
5263+ linux,code = <BTN_1>;
5264+ gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
5265+ };
5266+ };
5267+};
5268+
5269+&i2c3 {
5270+ status = "okay";
5271+ clock-frequency = <400000>;
5272+};
5273+
5274+&mcspi1 {
5275+ status = "okay";
5276+};
5277+
5278+&mcspi2 {
5279+ status = "okay";
5280+};
5281+
5282+&uart1 {
5283+ status = "okay";
5284+ interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
5285+ <&dra7_pmx_core 0x3e0>;
5286+};
5287+
5288+&uart2 {
5289+ status = "okay";
5290+};
5291+
5292+&uart3 {
5293+ status = "okay";
5294+};
5295+
5296+&qspi {
5297+ status = "okay";
5298+
5299+ spi-max-frequency = <76800000>;
5300+ m25p80@0 {
5301+ compatible = "s25fl256s1";
5302+ spi-max-frequency = <76800000>;
5303+ reg = <0>;
5304+ spi-tx-bus-width = <1>;
5305+ spi-rx-bus-width = <4>;
5306+ #address-cells = <1>;
5307+ #size-cells = <1>;
5308+
5309+ /* MTD partition table.
5310+ * The ROM checks the first four physical blocks
5311+ * for a valid file to boot and the flash here is
5312+ * 64KiB block size.
5313+ */
5314+ partition@0 {
5315+ label = "QSPI.SPL";
5316+ reg = <0x00000000 0x000010000>;
5317+ };
5318+ partition@1 {
5319+ label = "QSPI.SPL.backup1";
5320+ reg = <0x00010000 0x00010000>;
5321+ };
5322+ partition@2 {
5323+ label = "QSPI.SPL.backup2";
5324+ reg = <0x00020000 0x00010000>;
5325+ };
5326+ partition@3 {
5327+ label = "QSPI.SPL.backup3";
5328+ reg = <0x00030000 0x00010000>;
5329+ };
5330+ partition@4 {
5331+ label = "QSPI.u-boot";
5332+ reg = <0x00040000 0x00100000>;
5333+ };
5334+ partition@5 {
5335+ label = "QSPI.u-boot-spl-os";
5336+ reg = <0x00140000 0x00080000>;
5337+ };
5338+ partition@6 {
5339+ label = "QSPI.u-boot-env";
5340+ reg = <0x001c0000 0x00010000>;
5341+ };
5342+ partition@7 {
5343+ label = "QSPI.u-boot-env.backup1";
5344+ reg = <0x001d0000 0x0010000>;
5345+ };
5346+ partition@8 {
5347+ label = "QSPI.kernel";
5348+ reg = <0x001e0000 0x0800000>;
5349+ };
5350+ partition@9 {
5351+ label = "QSPI.file-system";
5352+ reg = <0x009e0000 0x01620000>;
5353+ };
5354+ };
5355+};
5356+
5357+&omap_dwc3_1 {
5358+ extcon = <&extcon_usb1>;
5359+};
5360+
5361+&usb1 {
5362+ dr_mode = "otg";
5363+ extcon = <&extcon_usb1>;
5364+};
5365+
5366+&usb2 {
5367+ dr_mode = "host";
5368+};
5369+
5370+&atl {
5371+ assigned-clocks = <&abe_dpll_sys_clk_mux>,
5372+ <&atl_gfclk_mux>,
5373+ <&dpll_abe_ck>,
5374+ <&dpll_abe_m2x2_ck>,
5375+ <&atl_clkin2_ck>;
5376+ assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
5377+ assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
5378+
5379+ status = "okay";
5380+
5381+ atl2 {
5382+ bws = <DRA7_ATL_WS_MCASP2_FSX>;
5383+ aws = <DRA7_ATL_WS_MCASP3_FSX>;
5384+ };
5385+};
5386+
5387+&mcasp3 {
5388+ #sound-dai-cells = <0>;
5389+
5390+ assigned-clocks = <&mcasp3_ahclkx_mux>;
5391+ assigned-clock-parents = <&atl_clkin2_ck>;
5392+
5393+ status = "okay";
5394+
5395+ op-mode = <0>; /* MCASP_IIS_MODE */
5396+ tdm-slots = <2>;
5397+ /* 4 serializer */
5398+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
5399+ 1 2 0 0
5400+ >;
5401+ tx-num-evt = <32>;
5402+ rx-num-evt = <32>;
5403+};
5404+
5405+&mailbox5 {
5406+ status = "okay";
5407+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
5408+ status = "okay";
5409+ };
5410+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
5411+ status = "okay";
5412+ };
5413+};
5414+
5415+&mailbox6 {
5416+ status = "okay";
5417+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
5418+ status = "okay";
5419+ };
5420+ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
5421+ status = "okay";
5422+ };
5423+};
5424diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
5425index f47fc4daf062..aa426dabb6c3 100644
5426--- a/arch/arm/boot/dts/dra7-evm.dts
5427+++ b/arch/arm/boot/dts/dra7-evm.dts
5428@@ -8,9 +8,8 @@
5429 /dts-v1/;
5430
5431 #include "dra74x.dtsi"
5432-#include <dt-bindings/gpio/gpio.h>
5433-#include <dt-bindings/clk/ti-dra7-atl.h>
5434-#include <dt-bindings/input/input.h>
5435+#include "dra7-evm-common.dtsi"
5436+#include "dra74x-mmc-iodelay.dtsi"
5437
5438 / {
5439 model = "TI DRA742";
5440@@ -21,8 +20,12 @@ memory@0 {
5441 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
5442 };
5443
5444- chosen {
5445- stdout-path = &uart1;
5446+ evm_1v8_sw: fixedregulator-evm_1v8 {
5447+ compatible = "regulator-fixed";
5448+ regulator-name = "evm_1v8";
5449+ vin-supply = <&smps9_reg>;
5450+ regulator-min-microvolt = <1800000>;
5451+ regulator-max-microvolt = <1800000>;
5452 };
5453
5454 evm_3v3_sd: fixedregulator-sd {
5455@@ -51,11 +54,6 @@ aic_dvdd: fixedregulator-aic_dvdd {
5456 regulator-max-microvolt = <1800000>;
5457 };
5458
5459- extcon_usb1: extcon_usb1 {
5460- compatible = "linux,extcon-usb-gpio";
5461- id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
5462- };
5463-
5464 extcon_usb2: extcon_usb2 {
5465 compatible = "linux,extcon-usb-gpio";
5466 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
5467@@ -73,85 +71,6 @@ vtt_fixed: fixedregulator-vtt {
5468 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
5469 };
5470
5471- sound0: sound0 {
5472- compatible = "simple-audio-card";
5473- simple-audio-card,name = "DRA7xx-EVM";
5474- simple-audio-card,widgets =
5475- "Headphone", "Headphone Jack",
5476- "Line", "Line Out",
5477- "Microphone", "Mic Jack",
5478- "Line", "Line In";
5479- simple-audio-card,routing =
5480- "Headphone Jack", "HPLOUT",
5481- "Headphone Jack", "HPROUT",
5482- "Line Out", "LLOUT",
5483- "Line Out", "RLOUT",
5484- "MIC3L", "Mic Jack",
5485- "MIC3R", "Mic Jack",
5486- "Mic Jack", "Mic Bias",
5487- "LINE1L", "Line In",
5488- "LINE1R", "Line In";
5489- simple-audio-card,format = "dsp_b";
5490- simple-audio-card,bitclock-master = <&sound0_master>;
5491- simple-audio-card,frame-master = <&sound0_master>;
5492- simple-audio-card,bitclock-inversion;
5493-
5494- sound0_master: simple-audio-card,cpu {
5495- sound-dai = <&mcasp3>;
5496- system-clock-frequency = <5644800>;
5497- };
5498-
5499- simple-audio-card,codec {
5500- sound-dai = <&tlv320aic3106>;
5501- clocks = <&atl_clkin2_ck>;
5502- };
5503- };
5504-
5505- leds {
5506- compatible = "gpio-leds";
5507- led0 {
5508- label = "dra7:usr1";
5509- gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
5510- default-state = "off";
5511- };
5512-
5513- led1 {
5514- label = "dra7:usr2";
5515- gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
5516- default-state = "off";
5517- };
5518-
5519- led2 {
5520- label = "dra7:usr3";
5521- gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
5522- default-state = "off";
5523- };
5524-
5525- led3 {
5526- label = "dra7:usr4";
5527- gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
5528- default-state = "off";
5529- };
5530- };
5531-
5532- gpio_keys {
5533- compatible = "gpio-keys";
5534- #address-cells = <1>;
5535- #size-cells = <0>;
5536- autorepeat;
5537-
5538- USER1 {
5539- label = "btnUser1";
5540- linux,code = <BTN_0>;
5541- gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
5542- };
5543-
5544- USER2 {
5545- label = "btnUser2";
5546- linux,code = <BTN_1>;
5547- gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
5548- };
5549- };
5550 };
5551
5552 &dra7_pmx_core {
5553@@ -406,137 +325,49 @@ p1 {
5554 };
5555 };
5556
5557-&i2c3 {
5558- status = "okay";
5559- clock-frequency = <400000>;
5560-};
5561-
5562-&mcspi1 {
5563- status = "okay";
5564-};
5565-
5566-&mcspi2 {
5567- status = "okay";
5568-};
5569-
5570-&uart1 {
5571- status = "okay";
5572- interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
5573- <&dra7_pmx_core 0x3e0>;
5574-};
5575-
5576-&uart2 {
5577- status = "okay";
5578-};
5579-
5580-&uart3 {
5581- status = "okay";
5582-};
5583-
5584 &mmc1 {
5585 status = "okay";
5586- pinctrl-names = "default";
5587- pinctrl-0 = <&mmc1_pins_default>;
5588 vmmc-supply = <&evm_3v3_sd>;
5589- vmmc_aux-supply = <&ldo1_reg>;
5590+ vqmmc-supply = <&ldo1_reg>;
5591 bus-width = <4>;
5592 /*
5593 * SDCD signal is not being used here - using the fact that GPIO mode
5594 * is always hardwired.
5595 */
5596 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
5597+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104";
5598+ pinctrl-0 = <&mmc1_pins_default>;
5599+ pinctrl-1 = <&mmc1_pins_hs>;
5600+ pinctrl-2 = <&mmc1_pins_sdr12>;
5601+ pinctrl-3 = <&mmc1_pins_sdr25>;
5602+ pinctrl-4 = <&mmc1_pins_sdr50>;
5603+ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
5604+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
5605+ pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
5606+ pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
5607 };
5608
5609 &mmc2 {
5610 status = "okay";
5611- pinctrl-names = "default";
5612- pinctrl-0 = <&mmc2_pins_default>;
5613- vmmc-supply = <&evm_3v3_sw>;
5614+ vmmc-supply = <&evm_1v8_sw>;
5615 bus-width = <8>;
5616+ pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
5617+ pinctrl-0 = <&mmc2_pins_default>;
5618+ pinctrl-1 = <&mmc2_pins_hs>;
5619+ pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>;
5620+ pinctrl-3 = <&mmc2_pins_ddr_rev20>;
5621+ pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>;
5622+ pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
5623 };
5624
5625 &cpu0 {
5626 cpu0-supply = <&smps123_reg>;
5627 };
5628
5629-&qspi {
5630- status = "okay";
5631-
5632- spi-max-frequency = <76800000>;
5633- m25p80@0 {
5634- compatible = "s25fl256s1";
5635- spi-max-frequency = <76800000>;
5636- reg = <0>;
5637- spi-tx-bus-width = <1>;
5638- spi-rx-bus-width = <4>;
5639- #address-cells = <1>;
5640- #size-cells = <1>;
5641-
5642- /* MTD partition table.
5643- * The ROM checks the first four physical blocks
5644- * for a valid file to boot and the flash here is
5645- * 64KiB block size.
5646- */
5647- partition@0 {
5648- label = "QSPI.SPL";
5649- reg = <0x00000000 0x000010000>;
5650- };
5651- partition@1 {
5652- label = "QSPI.SPL.backup1";
5653- reg = <0x00010000 0x00010000>;
5654- };
5655- partition@2 {
5656- label = "QSPI.SPL.backup2";
5657- reg = <0x00020000 0x00010000>;
5658- };
5659- partition@3 {
5660- label = "QSPI.SPL.backup3";
5661- reg = <0x00030000 0x00010000>;
5662- };
5663- partition@4 {
5664- label = "QSPI.u-boot";
5665- reg = <0x00040000 0x00100000>;
5666- };
5667- partition@5 {
5668- label = "QSPI.u-boot-spl-os";
5669- reg = <0x00140000 0x00080000>;
5670- };
5671- partition@6 {
5672- label = "QSPI.u-boot-env";
5673- reg = <0x001c0000 0x00010000>;
5674- };
5675- partition@7 {
5676- label = "QSPI.u-boot-env.backup1";
5677- reg = <0x001d0000 0x0010000>;
5678- };
5679- partition@8 {
5680- label = "QSPI.kernel";
5681- reg = <0x001e0000 0x0800000>;
5682- };
5683- partition@9 {
5684- label = "QSPI.file-system";
5685- reg = <0x009e0000 0x01620000>;
5686- };
5687- };
5688-};
5689-
5690-&omap_dwc3_1 {
5691- extcon = <&extcon_usb1>;
5692-};
5693-
5694 &omap_dwc3_2 {
5695 extcon = <&extcon_usb2>;
5696 };
5697
5698-&usb1 {
5699- dr_mode = "otg";
5700- extcon = <&extcon_usb1>;
5701-};
5702-
5703-&usb2 {
5704- dr_mode = "host";
5705-};
5706-
5707 &elm {
5708 status = "okay";
5709 };
5710@@ -556,6 +387,7 @@ nand@0,0 {
5711 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
5712 <1 IRQ_TYPE_NONE>; /* termcount */
5713 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
5714+ ti,nand-xfer-type = "prefetch-dma";
5715 ti,nand-ecc-opt = "bch8";
5716 ti,elm-id = <&elm>;
5717 nand-bus-width = <16>;
5718@@ -666,57 +498,6 @@ &dcan1 {
5719 pinctrl-2 = <&dcan1_pins_default>;
5720 };
5721
5722-&atl {
5723- assigned-clocks = <&abe_dpll_sys_clk_mux>,
5724- <&atl_gfclk_mux>,
5725- <&dpll_abe_ck>,
5726- <&dpll_abe_m2x2_ck>,
5727- <&atl_clkin2_ck>;
5728- assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
5729- assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
5730-
5731- status = "okay";
5732-
5733- atl2 {
5734- bws = <DRA7_ATL_WS_MCASP2_FSX>;
5735- aws = <DRA7_ATL_WS_MCASP3_FSX>;
5736- };
5737-};
5738-
5739-&mcasp3 {
5740- #sound-dai-cells = <0>;
5741-
5742- assigned-clocks = <&mcasp3_ahclkx_mux>;
5743- assigned-clock-parents = <&atl_clkin2_ck>;
5744-
5745- status = "okay";
5746-
5747- op-mode = <0>; /* MCASP_IIS_MODE */
5748- tdm-slots = <2>;
5749- /* 4 serializer */
5750- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
5751- 1 2 0 0
5752- >;
5753- tx-num-evt = <32>;
5754- rx-num-evt = <32>;
5755-};
5756-
5757-&mailbox5 {
5758+&pcie1_rc {
5759 status = "okay";
5760- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
5761- status = "okay";
5762- };
5763- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
5764- status = "okay";
5765- };
5766-};
5767-
5768-&mailbox6 {
5769- status = "okay";
5770- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
5771- status = "okay";
5772- };
5773- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
5774- status = "okay";
5775- };
5776 };
5777diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
5778index 0f0f6f58bd18..02a136a4661a 100644
5779--- a/arch/arm/boot/dts/dra7.dtsi
5780+++ b/arch/arm/boot/dts/dra7.dtsi
5781@@ -196,6 +196,7 @@ dra7_pmx_core: pinmux@1400 {
5782 scm_conf1: scm_conf@1c04 {
5783 compatible = "syscon";
5784 reg = <0x1c04 0x0020>;
5785+ #syscon-cells = <2>;
5786 };
5787
5788 scm_conf_pcie: scm_conf@1c24 {
5789@@ -287,7 +288,11 @@ axi@0 {
5790 #address-cells = <1>;
5791 ranges = <0x51000000 0x51000000 0x3000
5792 0x0 0x20000000 0x10000000>;
5793- pcie1: pcie@51000000 {
5794+ /**
5795+ * To enable PCI endpoint mode, disable the pcie1_rc
5796+ * node and enable pcie1_ep mode.
5797+ */
5798+ pcie1_rc: pcie@51000000 {
5799 compatible = "ti,dra7-pcie";
5800 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
5801 reg-names = "rc_dbics", "ti_conf", "config";
5802@@ -309,12 +314,28 @@ pcie1: pcie@51000000 {
5803 <0 0 0 2 &pcie1_intc 2>,
5804 <0 0 0 3 &pcie1_intc 3>,
5805 <0 0 0 4 &pcie1_intc 4>;
5806+ status = "disabled";
5807 pcie1_intc: interrupt-controller {
5808 interrupt-controller;
5809 #address-cells = <0>;
5810 #interrupt-cells = <1>;
5811 };
5812 };
5813+
5814+ pcie1_ep: pcie_ep@51000000 {
5815+ compatible = "ti,dra7-pcie-ep";
5816+ reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
5817+ reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
5818+ interrupts = <0 232 0x4>;
5819+ num-lanes = <1>;
5820+ num-ib-windows = <4>;
5821+ num-ob-windows = <16>;
5822+ ti,hwmods = "pcie1";
5823+ phys = <&pcie1_phy>;
5824+ phy-names = "pcie-phy0";
5825+ ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
5826+ status = "disabled";
5827+ };
5828 };
5829
5830 axi@1 {
5831@@ -418,6 +439,14 @@ dsp1_system: dsp_system@40d00000 {
5832 reg = <0x40d00000 0x100>;
5833 };
5834
5835+ dra7_iodelay_core: padconf@4844a000 {
5836+ compatible = "ti,dra7-iodelay";
5837+ reg = <0x4844a000 0x0d1c>;
5838+ #address-cells = <1>;
5839+ #size-cells = <0>;
5840+ #pinctrl-cells = <2>;
5841+ };
5842+
5843 sdma: dma-controller@4a056000 {
5844 compatible = "ti,omap4430-sdma";
5845 reg = <0x4a056000 0x1000>;
5846@@ -1037,6 +1066,7 @@ mmc1: mmc@4809c000 {
5847 dma-names = "tx", "rx";
5848 status = "disabled";
5849 pbias-supply = <&pbias_mmc_reg>;
5850+ max-frequency = <192000000>;
5851 };
5852
5853 mmc2: mmc@480b4000 {
5854@@ -1048,6 +1078,7 @@ mmc2: mmc@480b4000 {
5855 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
5856 dma-names = "tx", "rx";
5857 status = "disabled";
5858+ max-frequency = <192000000>;
5859 };
5860
5861 mmc3: mmc@480ad000 {
5862@@ -1059,6 +1090,8 @@ mmc3: mmc@480ad000 {
5863 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
5864 dma-names = "tx", "rx";
5865 status = "disabled";
5866+ /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
5867+ max-frequency = <64000000>;
5868 };
5869
5870 mmc4: mmc@480d1000 {
5871@@ -1070,6 +1103,7 @@ mmc4: mmc@480d1000 {
5872 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
5873 dma-names = "tx", "rx";
5874 status = "disabled";
5875+ max-frequency = <192000000>;
5876 };
5877
5878 mmu0_dsp1: mmu@40d01000 {
5879diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts
5880index 9897e8fa6845..41c9132eb550 100644
5881--- a/arch/arm/boot/dts/dra71-evm.dts
5882+++ b/arch/arm/boot/dts/dra71-evm.dts
5883@@ -7,6 +7,7 @@
5884 */
5885
5886 #include "dra72-evm-common.dtsi"
5887+#include "dra72x-mmc-iodelay.dtsi"
5888 #include <dt-bindings/net/ti-dp83867.h>
5889
5890 / {
5891@@ -32,6 +33,16 @@ vpo_sd_1v8_3v3: gpio-regulator-TPS74801 {
5892 3000000 0x1>;
5893 };
5894
5895+ evm_1v8_sw: fixedregulator-evm_1v8 {
5896+ compatible = "regulator-fixed";
5897+ regulator-name = "evm_1v8";
5898+ regulator-min-microvolt = <1800000>;
5899+ regulator-max-microvolt = <1800000>;
5900+ vin-supply = <&lp8732_buck0_reg>;
5901+ regulator-always-on;
5902+ regulator-boot-on;
5903+ };
5904+
5905 poweroff: gpio-poweroff {
5906 compatible = "gpio-poweroff";
5907 gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>;
5908@@ -162,7 +173,24 @@ p0 {
5909 };
5910
5911 &mmc1 {
5912- vmmc_aux-supply = <&vpo_sd_1v8_3v3>;
5913+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
5914+ pinctrl-0 = <&mmc1_pins_default>;
5915+ pinctrl-1 = <&mmc1_pins_hs>;
5916+ pinctrl-2 = <&mmc1_pins_sdr12>;
5917+ pinctrl-3 = <&mmc1_pins_sdr25>;
5918+ pinctrl-4 = <&mmc1_pins_sdr50>;
5919+ pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
5920+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
5921+ vqmmc-supply = <&vpo_sd_1v8_3v3>;
5922+};
5923+
5924+&mmc2 {
5925+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
5926+ pinctrl-0 = <&mmc2_pins_default>;
5927+ pinctrl-1 = <&mmc2_pins_hs>;
5928+ pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
5929+ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
5930+ vmmc-supply = <&evm_1v8_sw>;
5931 };
5932
5933 &mac {
5934diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
5935index 85780549bc26..2e485a13dfd7 100644
5936--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
5937+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
5938@@ -311,6 +311,7 @@ nand@0,0 {
5939 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
5940 <1 IRQ_TYPE_NONE>; /* termcount */
5941 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
5942+ ti,nand-xfer-type = "prefetch-dma";
5943 ti,nand-ecc-opt = "bch8";
5944 ti,elm-id = <&elm>;
5945 nand-bus-width = <16>;
5946@@ -419,8 +420,6 @@ &mmc2 {
5947 status = "okay";
5948 pinctrl-names = "default";
5949 pinctrl-0 = <&mmc2_pins_default>;
5950-
5951- vmmc-supply = <&evm_3v3_sw>;
5952 bus-width = <8>;
5953 ti,non-removable;
5954 max-frequency = <192000000>;
5955@@ -564,3 +563,7 @@ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
5956 status = "okay";
5957 };
5958 };
5959+
5960+&pcie1_rc {
5961+ status = "okay";
5962+};
5963diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts
5964index 6f9b6f31437e..bf588d00728d 100644
5965--- a/arch/arm/boot/dts/dra72-evm-revc.dts
5966+++ b/arch/arm/boot/dts/dra72-evm-revc.dts
5967@@ -6,6 +6,7 @@
5968 * published by the Free Software Foundation.
5969 */
5970 #include "dra72-evm-common.dtsi"
5971+#include "dra72x-mmc-iodelay.dtsi"
5972 #include <dt-bindings/net/ti-dp83867.h>
5973
5974 / {
5975@@ -15,6 +16,16 @@ memory@0 {
5976 device_type = "memory";
5977 reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
5978 };
5979+
5980+ evm_1v8_sw: fixedregulator-evm_1v8 {
5981+ compatible = "regulator-fixed";
5982+ regulator-name = "evm_1v8";
5983+ regulator-min-microvolt = <1800000>;
5984+ regulator-max-microvolt = <1800000>;
5985+ vin-supply = <&smps4_reg>;
5986+ regulator-always-on;
5987+ regulator-boot-on;
5988+ };
5989 };
5990
5991 &i2c1 {
5992@@ -84,3 +95,24 @@ dp83867_1: ethernet-phy@3 {
5993 ti,dp83867-rxctrl-strap-quirk;
5994 };
5995 };
5996+
5997+&mmc1 {
5998+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
5999+ pinctrl-0 = <&mmc1_pins_default>;
6000+ pinctrl-1 = <&mmc1_pins_hs>;
6001+ pinctrl-2 = <&mmc1_pins_sdr12>;
6002+ pinctrl-3 = <&mmc1_pins_sdr25>;
6003+ pinctrl-4 = <&mmc1_pins_sdr50>;
6004+ pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
6005+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
6006+ vqmmc-supply = <&ldo1_reg>;
6007+};
6008+
6009+&mmc2 {
6010+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
6011+ pinctrl-0 = <&mmc2_pins_default>;
6012+ pinctrl-1 = <&mmc2_pins_hs>;
6013+ pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
6014+ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
6015+ vmmc-supply = <&evm_1v8_sw>;
6016+};
6017diff --git a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi
6018index e6df676886c0..57bfe5caf5e4 100644
6019--- a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi
6020+++ b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi
6021@@ -146,5 +146,5 @@ &dss {
6022 };
6023
6024 &mmc1 {
6025- vmmc_aux-supply = <&ldo1_reg>;
6026+ vqmmc-supply = <&ldo1_reg>;
6027 };
6028diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
6029index cd9c4ff12654..c572693b1665 100644
6030--- a/arch/arm/boot/dts/dra72-evm.dts
6031+++ b/arch/arm/boot/dts/dra72-evm.dts
6032@@ -6,6 +6,7 @@
6033 * published by the Free Software Foundation.
6034 */
6035 #include "dra72-evm-common.dtsi"
6036+#include "dra72x-mmc-iodelay.dtsi"
6037 / {
6038 model = "TI DRA722";
6039
6040@@ -13,6 +14,16 @@ memory@0 {
6041 device_type = "memory";
6042 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
6043 };
6044+
6045+ evm_1v8_sw: fixedregulator-evm_1v8 {
6046+ compatible = "regulator-fixed";
6047+ regulator-name = "evm_1v8";
6048+ regulator-min-microvolt = <1800000>;
6049+ regulator-max-microvolt = <1800000>;
6050+ vin-supply = <&smps4_reg>;
6051+ regulator-always-on;
6052+ regulator-boot-on;
6053+ };
6054 };
6055
6056 &i2c1 {
6057@@ -43,3 +54,24 @@ &cpsw_emac0 {
6058 phy_id = <&davinci_mdio>, <3>;
6059 phy-mode = "rgmii";
6060 };
6061+
6062+&mmc1 {
6063+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
6064+ pinctrl-0 = <&mmc1_pins_default>;
6065+ pinctrl-1 = <&mmc1_pins_hs>;
6066+ pinctrl-2 = <&mmc1_pins_sdr12>;
6067+ pinctrl-3 = <&mmc1_pins_sdr25>;
6068+ pinctrl-4 = <&mmc1_pins_sdr50>;
6069+ pinctrl-5 = <&mmc1_pins_ddr50_rev10>;
6070+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>;
6071+ vqmmc-supply = <&ldo1_reg>;
6072+};
6073+
6074+&mmc2 {
6075+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
6076+ pinctrl-0 = <&mmc2_pins_default>;
6077+ pinctrl-1 = <&mmc2_pins_hs>;
6078+ pinctrl-2 = <&mmc2_pins_ddr_rev10>;
6079+ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>;
6080+ vmmc-supply = <&evm_1v8_sw>;
6081+};
6082diff --git a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi
6083new file mode 100644
6084index 000000000000..088013c6dc6e
6085--- /dev/null
6086+++ b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi
6087@@ -0,0 +1,350 @@
6088+/*
6089+ * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs.
6090+ *
6091+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
6092+ *
6093+ * This program is free software; you can redistribute it and/or
6094+ * modify it under the terms of the GNU General Public License as
6095+ * published by the Free Software Foundation version 2.
6096+ *
6097+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
6098+ * kind, whether express or implied; without even the implied warranty
6099+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6100+ * GNU General Public License for more details.
6101+ */
6102+
6103+/*
6104+ * Rules for modifying this file:
6105+ * a) Update of this file should typically correspond to a datamanual revision.
6106+ * Datamanual revision that was used should be updated in comment below.
6107+ * If there is no update to datamanual, do not update the values. If you
6108+ * need to use values different from that recommended by the datamanual
6109+ * for your design, then you should consider adding values to the device-
6110+ * -tree file for your board directly.
6111+ * b) We keep the mode names as close to the datamanual as possible. So
6112+ * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
6113+ * we follow that in code too.
6114+ * c) If the values change between multiple revisions of silicon, we add
6115+ * a revision tag to both the new and old entry. Use 'rev10' for PG 1.0,
6116+ * 'rev20' for PG 2.0 and so on.
6117+ * d) The node name and node label should be the exact same string. This is
6118+ * to curb naming creativity and achieve consistency.
6119+ * e) If in future, DRA71x and DRA72x values differ, then add 'dra71_' and
6120+ * 'dra72_' tag to entries. Both the new and old entries should gain a tag.
6121+ *
6122+ * Datamanual Revisions:
6123+ *
6124+ * AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017
6125+ * AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017
6126+ * DRA71x : SPRS960B, Revised February 2017
6127+ */
6128+
6129+&dra7_pmx_core {
6130+ mmc1_pins_default: mmc1_pins_default {
6131+ pinctrl-single,pins = <
6132+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
6133+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
6134+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
6135+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
6136+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
6137+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
6138+ >;
6139+ };
6140+
6141+ mmc1_pins_sdr12: mmc1_pins_sdr12 {
6142+ pinctrl-single,pins = <
6143+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
6144+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
6145+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
6146+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
6147+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
6148+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
6149+ >;
6150+ };
6151+
6152+ mmc1_pins_hs: mmc1_pins_hs {
6153+ pinctrl-single,pins = <
6154+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
6155+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
6156+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
6157+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
6158+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
6159+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
6160+ >;
6161+ };
6162+
6163+ mmc1_pins_sdr25: mmc1_pins_sdr25 {
6164+ pinctrl-single,pins = <
6165+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
6166+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
6167+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
6168+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
6169+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
6170+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
6171+ >;
6172+ };
6173+
6174+ mmc1_pins_sdr50: mmc1_pins_sdr50 {
6175+ pinctrl-single,pins = <
6176+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */
6177+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */
6178+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.dat0 */
6179+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.dat1 */
6180+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.dat2 */
6181+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.dat3 */
6182+ >;
6183+ };
6184+
6185+ mmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 {
6186+ pinctrl-single,pins = <
6187+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_clk.mmc1_clk */
6188+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
6189+ DRA7XX_CORE_IOPAD(0x375C, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
6190+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
6191+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
6192+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
6193+ >;
6194+ };
6195+
6196+ mmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 {
6197+ pinctrl-single,pins = <
6198+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
6199+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
6200+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
6201+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
6202+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
6203+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
6204+ >;
6205+ };
6206+
6207+ mmc1_pins_sdr104: mmc1_pins_sdr104 {
6208+ pinctrl-single,pins = <
6209+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
6210+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
6211+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
6212+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
6213+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
6214+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
6215+ >;
6216+ };
6217+
6218+ mmc2_pins_default: mmc2_pins_default {
6219+ pinctrl-single,pins = <
6220+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
6221+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
6222+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
6223+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
6224+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
6225+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
6226+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
6227+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
6228+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
6229+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
6230+ >;
6231+ };
6232+
6233+ mmc2_pins_hs: mmc2_pins_hs {
6234+ pinctrl-single,pins = <
6235+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
6236+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
6237+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
6238+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
6239+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
6240+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
6241+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
6242+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
6243+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
6244+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
6245+ >;
6246+ };
6247+
6248+ mmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 {
6249+ pinctrl-single,pins = <
6250+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
6251+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
6252+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
6253+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
6254+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
6255+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
6256+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
6257+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
6258+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
6259+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
6260+ >;
6261+ };
6262+
6263+ mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {
6264+ pinctrl-single,pins = <
6265+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
6266+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
6267+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
6268+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
6269+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
6270+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
6271+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
6272+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
6273+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
6274+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
6275+ >;
6276+ };
6277+
6278+ mmc2_pins_hs200: mmc2_pins_hs200 {
6279+ pinctrl-single,pins = <
6280+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
6281+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
6282+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
6283+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
6284+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
6285+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
6286+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
6287+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
6288+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
6289+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
6290+ >;
6291+ };
6292+};
6293+
6294+&dra7_iodelay_core {
6295+
6296+ /* Corresponds to MMC1_MANUAL1 in datamanual */
6297+ mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
6298+ pinctrl-pin-array = <
6299+ 0x618 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */
6300+ 0x624 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */
6301+ 0x630 A_DELAY_PS(1375) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */
6302+ 0x63C A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */
6303+ 0x648 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */
6304+ 0x654 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
6305+ 0x620 A_DELAY_PS(1230) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
6306+ 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
6307+ 0x638 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
6308+ 0x644 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
6309+ 0x650 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
6310+ 0x65C A_DELAY_PS(99) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
6311+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
6312+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
6313+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
6314+ 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
6315+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
6316+ >;
6317+ };
6318+
6319+ /* Corresponds to MMC1_MANUAL2 in datamanual */
6320+ mmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf {
6321+ pinctrl-pin-array = <
6322+ 0x620 A_DELAY_PS(560) G_DELAY_PS(365) /* CFG_MMC1_CLK_OUT */
6323+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
6324+ 0x638 A_DELAY_PS(29) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
6325+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
6326+ 0x650 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
6327+ 0x65c A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
6328+ 0x628 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
6329+ 0x634 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
6330+ 0x640 A_DELAY_PS(433) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
6331+ 0x64c A_DELAY_PS(287) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
6332+ 0x658 A_DELAY_PS(351) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
6333+ >;
6334+ };
6335+
6336+ /* Corresponds to MMC1_MANUAL2 in datamanual */
6337+ mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
6338+ pinctrl-pin-array = <
6339+ 0x620 A_DELAY_PS(520) G_DELAY_PS(320) /* CFG_MMC1_CLK_OUT */
6340+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
6341+ 0x638 A_DELAY_PS(40) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
6342+ 0x644 A_DELAY_PS(83) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
6343+ 0x650 A_DELAY_PS(98) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
6344+ 0x65c A_DELAY_PS(106) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
6345+ 0x628 A_DELAY_PS(51) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
6346+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
6347+ 0x640 A_DELAY_PS(363) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
6348+ 0x64c A_DELAY_PS(199) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
6349+ 0x658 A_DELAY_PS(273) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
6350+ >;
6351+ };
6352+
6353+ /* Corresponds to MMC2_MANUAL1 in datamanual */
6354+ mmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf {
6355+ pinctrl-pin-array = <
6356+ 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */
6357+ 0x1a4 A_DELAY_PS(119) G_DELAY_PS(0) /* CFG_GPMC_A20_IN */
6358+ 0x1b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_IN */
6359+ 0x1bc A_DELAY_PS(18) G_DELAY_PS(0) /* CFG_GPMC_A22_IN */
6360+ 0x1c8 A_DELAY_PS(894) G_DELAY_PS(0) /* CFG_GPMC_A23_IN */
6361+ 0x1d4 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_IN */
6362+ 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
6363+ 0x1ec A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
6364+ 0x1f8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_IN */
6365+ 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
6366+ 0x194 A_DELAY_PS(152) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
6367+ 0x1ac A_DELAY_PS(206) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
6368+ 0x1b8 A_DELAY_PS(78) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
6369+ 0x1c4 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
6370+ 0x1d0 A_DELAY_PS(266) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */
6371+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
6372+ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
6373+ 0x1f4 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
6374+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
6375+ 0x368 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
6376+ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
6377+ 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
6378+ 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
6379+ 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
6380+ 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
6381+ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
6382+ 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
6383+ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
6384+ 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
6385+ >;
6386+ };
6387+
6388+ /* Corresponds to MMC2_MANUAL3 in datamanual */
6389+ mmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf {
6390+ pinctrl-pin-array = <
6391+ 0x194 A_DELAY_PS(150) G_DELAY_PS(95) /* CFG_GPMC_A19_OUT */
6392+ 0x1ac A_DELAY_PS(250) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
6393+ 0x1b8 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
6394+ 0x1c4 A_DELAY_PS(100) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
6395+ 0x1d0 A_DELAY_PS(870) G_DELAY_PS(415) /* CFG_GPMC_A23_OUT */
6396+ 0x1dc A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
6397+ 0x1e8 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
6398+ 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
6399+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
6400+ 0x368 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
6401+ 0x190 A_DELAY_PS(695) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
6402+ 0x1a8 A_DELAY_PS(924) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
6403+ 0x1b4 A_DELAY_PS(719) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
6404+ 0x1c0 A_DELAY_PS(824) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
6405+ 0x1d8 A_DELAY_PS(877) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
6406+ 0x1e4 A_DELAY_PS(446) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
6407+ 0x1f0 A_DELAY_PS(847) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
6408+ 0x1fc A_DELAY_PS(586) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
6409+ 0x364 A_DELAY_PS(1039) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
6410+ >;
6411+ };
6412+
6413+ /* Corresponds to MMC2_MANUAL3 in datamanual */
6414+ mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
6415+ pinctrl-pin-array = <
6416+ 0x194 A_DELAY_PS(285) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
6417+ 0x1ac A_DELAY_PS(189) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
6418+ 0x1b8 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_OUT */
6419+ 0x1c4 A_DELAY_PS(0) G_DELAY_PS(70) /* CFG_GPMC_A22_OUT */
6420+ 0x1d0 A_DELAY_PS(730) G_DELAY_PS(360) /* CFG_GPMC_A23_OUT */
6421+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
6422+ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
6423+ 0x1f4 A_DELAY_PS(70) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
6424+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
6425+ 0x368 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_CS1_OUT */
6426+ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
6427+ 0x1a8 A_DELAY_PS(231) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
6428+ 0x1b4 A_DELAY_PS(39) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
6429+ 0x1c0 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
6430+ 0x1d8 A_DELAY_PS(176) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
6431+ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
6432+ 0x1f0 A_DELAY_PS(101) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
6433+ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
6434+ 0x364 A_DELAY_PS(360) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
6435+ >;
6436+ };
6437+};
6438diff --git a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
6439new file mode 100644
6440index 000000000000..28ebb4eb884a
6441--- /dev/null
6442+++ b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
6443@@ -0,0 +1,647 @@
6444+/*
6445+ * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs.
6446+ *
6447+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
6448+ *
6449+ * This program is free software; you can redistribute it and/or
6450+ * modify it under the terms of the GNU General Public License as
6451+ * published by the Free Software Foundation version 2.
6452+ *
6453+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
6454+ * kind, whether express or implied; without even the implied warranty
6455+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6456+ * GNU General Public License for more details.
6457+ */
6458+
6459+/*
6460+ * Rules for modifying this file:
6461+ * a) Update of this file should typically correspond to a datamanual revision.
6462+ * Datamanual revision that was used should be updated in comment below.
6463+ * If there is no update to datamanual, do not update the values. If you
6464+ * need to use values different from that recommended by the datamanual
6465+ * for your design, then you should consider adding values to the device-
6466+ * -tree file for your board directly.
6467+ * b) We keep the mode names as close to the datamanual as possible. So
6468+ * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
6469+ * we follow that in code too.
6470+ * c) If the values change between multiple revisions of silicon, we add
6471+ * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
6472+ * 'rev20' for PG 2.0 and so on.
6473+ * d) The node name and node label should be the exact same string. This is
6474+ * to curb naming creativity and achieve consistency.
6475+ *
6476+ * Datamanual Revisions:
6477+ *
6478+ * AM572x Silicon Revision 2.0: SPRS953B, Revised November 2016
6479+ * AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016
6480+ *
6481+ */
6482+
6483+&dra7_pmx_core {
6484+ mmc1_pins_default: mmc1_pins_default {
6485+ pinctrl-single,pins = <
6486+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
6487+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
6488+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
6489+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
6490+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
6491+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
6492+ >;
6493+ };
6494+
6495+ mmc1_pins_sdr12: mmc1_pins_sdr12 {
6496+ pinctrl-single,pins = <
6497+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
6498+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
6499+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
6500+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
6501+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
6502+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
6503+ >;
6504+ };
6505+
6506+ mmc1_pins_hs: mmc1_pins_hs {
6507+ pinctrl-single,pins = <
6508+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
6509+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
6510+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
6511+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
6512+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
6513+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
6514+ >;
6515+ };
6516+
6517+ mmc1_pins_sdr25: mmc1_pins_sdr25 {
6518+ pinctrl-single,pins = <
6519+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
6520+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
6521+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
6522+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
6523+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
6524+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
6525+ >;
6526+ };
6527+
6528+ mmc1_pins_sdr50: mmc1_pins_sdr50 {
6529+ pinctrl-single,pins = <
6530+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */
6531+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */
6532+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */
6533+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */
6534+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */
6535+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */
6536+ >;
6537+ };
6538+
6539+ mmc1_pins_ddr50: mmc1_pins_ddr50 {
6540+ pinctrl-single,pins = <
6541+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
6542+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
6543+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
6544+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
6545+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
6546+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
6547+ >;
6548+ };
6549+
6550+ mmc1_pins_sdr104: mmc1_pins_sdr104 {
6551+ pinctrl-single,pins = <
6552+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
6553+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
6554+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
6555+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
6556+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
6557+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
6558+ >;
6559+ };
6560+
6561+ mmc2_pins_default: mmc2_pins_default {
6562+ pinctrl-single,pins = <
6563+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
6564+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
6565+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
6566+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
6567+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
6568+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
6569+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
6570+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
6571+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
6572+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
6573+ >;
6574+ };
6575+
6576+ mmc2_pins_hs: mmc2_pins_hs {
6577+ pinctrl-single,pins = <
6578+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
6579+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
6580+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
6581+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
6582+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
6583+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
6584+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
6585+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
6586+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
6587+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
6588+ >;
6589+ };
6590+
6591+ mmc2_pins_ddr_3_3v_rev11: mmc2_pins_ddr_3_3v_rev11 {
6592+ pinctrl-single,pins = <
6593+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
6594+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
6595+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
6596+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
6597+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
6598+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
6599+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
6600+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
6601+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
6602+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
6603+ >;
6604+ };
6605+
6606+ mmc2_pins_ddr_1_8v_rev11: mmc2_pins_ddr_1_8v_rev11 {
6607+ pinctrl-single,pins = <
6608+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
6609+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
6610+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
6611+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
6612+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
6613+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
6614+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
6615+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
6616+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
6617+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
6618+ >;
6619+ };
6620+
6621+ mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {
6622+ pinctrl-single,pins = <
6623+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
6624+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
6625+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
6626+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
6627+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
6628+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
6629+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
6630+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
6631+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
6632+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
6633+ >;
6634+ };
6635+
6636+ mmc2_pins_hs200: mmc2_pins_hs200 {
6637+ pinctrl-single,pins = <
6638+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
6639+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
6640+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
6641+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
6642+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
6643+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
6644+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
6645+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
6646+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
6647+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
6648+ >;
6649+ };
6650+
6651+ mmc4_pins_default: mmc4_pins_default {
6652+ pinctrl-single,pins = <
6653+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
6654+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
6655+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
6656+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
6657+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
6658+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
6659+ >;
6660+ };
6661+
6662+ mmc4_pins_hs: mmc4_pins_hs {
6663+ pinctrl-single,pins = <
6664+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
6665+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
6666+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
6667+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
6668+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
6669+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
6670+ >;
6671+ };
6672+
6673+ mmc3_pins_default: mmc3_pins_default {
6674+ pinctrl-single,pins = <
6675+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
6676+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
6677+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
6678+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
6679+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
6680+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
6681+ >;
6682+ };
6683+
6684+ mmc3_pins_hs: mmc3_pins_hs {
6685+ pinctrl-single,pins = <
6686+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
6687+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
6688+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
6689+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
6690+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
6691+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
6692+ >;
6693+ };
6694+
6695+ mmc3_pins_sdr12: mmc3_pins_sdr12 {
6696+ pinctrl-single,pins = <
6697+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
6698+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
6699+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
6700+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
6701+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
6702+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
6703+ >;
6704+ };
6705+
6706+ mmc3_pins_sdr25: mmc3_pins_sdr25 {
6707+ pinctrl-single,pins = <
6708+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
6709+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
6710+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
6711+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
6712+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
6713+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
6714+ >;
6715+ };
6716+
6717+ mmc3_pins_sdr50: mmc3_pins_sdr50 {
6718+ pinctrl-single,pins = <
6719+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
6720+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
6721+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
6722+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
6723+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
6724+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
6725+ >;
6726+ };
6727+
6728+ mmc4_pins_sdr12: mmc4_pins_sdr12 {
6729+ pinctrl-single,pins = <
6730+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
6731+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
6732+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
6733+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
6734+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
6735+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
6736+ >;
6737+ };
6738+
6739+ mmc4_pins_sdr25: mmc4_pins_sdr25 {
6740+ pinctrl-single,pins = <
6741+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
6742+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
6743+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
6744+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
6745+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
6746+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
6747+ >;
6748+ };
6749+};
6750+
6751+&dra7_iodelay_core {
6752+
6753+ /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
6754+ mmc1_iodelay_ddr_rev11_conf: mmc1_iodelay_ddr_rev11_conf {
6755+ pinctrl-pin-array = <
6756+ 0x618 A_DELAY_PS(572) G_DELAY_PS(540) /* CFG_MMC1_CLK_IN */
6757+ 0x620 A_DELAY_PS(1525) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
6758+ 0x624 A_DELAY_PS(0) G_DELAY_PS(600) /* CFG_MMC1_CMD_IN */
6759+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
6760+ 0x62c A_DELAY_PS(55) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
6761+ 0x630 A_DELAY_PS(403) G_DELAY_PS(120) /* CFG_MMC1_DAT0_IN */
6762+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
6763+ 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
6764+ 0x63c A_DELAY_PS(23) G_DELAY_PS(60) /* CFG_MMC1_DAT1_IN */
6765+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
6766+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
6767+ 0x648 A_DELAY_PS(25) G_DELAY_PS(60) /* CFG_MMC1_DAT2_IN */
6768+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
6769+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
6770+ 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
6771+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
6772+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
6773+ >;
6774+ };
6775+
6776+ /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
6777+ mmc1_iodelay_ddr_rev20_conf: mmc1_iodelay_ddr50_rev20_conf {
6778+ pinctrl-pin-array = <
6779+ 0x618 A_DELAY_PS(1076) G_DELAY_PS(330) /* CFG_MMC1_CLK_IN */
6780+ 0x620 A_DELAY_PS(1271) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
6781+ 0x624 A_DELAY_PS(722) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */
6782+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
6783+ 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
6784+ 0x630 A_DELAY_PS(751) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */
6785+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
6786+ 0x638 A_DELAY_PS(20) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
6787+ 0x63C A_DELAY_PS(256) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */
6788+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
6789+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
6790+ 0x648 A_DELAY_PS(263) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */
6791+ 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
6792+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
6793+ 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
6794+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
6795+ 0x65C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
6796+ >;
6797+ };
6798+
6799+ /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
6800+ mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf {
6801+ pinctrl-pin-array = <
6802+ 0x620 A_DELAY_PS(1063) G_DELAY_PS(17) /* CFG_MMC1_CLK_OUT */
6803+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
6804+ 0x62c A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
6805+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
6806+ 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
6807+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
6808+ 0x644 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
6809+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
6810+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
6811+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
6812+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
6813+ >;
6814+ };
6815+
6816+ /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
6817+ mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
6818+ pinctrl-pin-array = <
6819+ 0x620 A_DELAY_PS(600) G_DELAY_PS(400) /* CFG_MMC1_CLK_OUT */
6820+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
6821+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
6822+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
6823+ 0x638 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
6824+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
6825+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
6826+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
6827+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
6828+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
6829+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
6830+ >;
6831+ };
6832+
6833+ /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
6834+ mmc2_iodelay_hs200_rev11_conf: mmc2_iodelay_hs200_rev11_conf {
6835+ pinctrl-pin-array = <
6836+ 0x190 A_DELAY_PS(621) G_DELAY_PS(600) /* CFG_GPMC_A19_OEN */
6837+ 0x194 A_DELAY_PS(300) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
6838+ 0x1a8 A_DELAY_PS(739) G_DELAY_PS(600) /* CFG_GPMC_A20_OEN */
6839+ 0x1ac A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
6840+ 0x1b4 A_DELAY_PS(812) G_DELAY_PS(600) /* CFG_GPMC_A21_OEN */
6841+ 0x1b8 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
6842+ 0x1c0 A_DELAY_PS(954) G_DELAY_PS(600) /* CFG_GPMC_A22_OEN */
6843+ 0x1c4 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
6844+ 0x1d0 A_DELAY_PS(1340) G_DELAY_PS(420) /* CFG_GPMC_A23_OUT */
6845+ 0x1d8 A_DELAY_PS(935) G_DELAY_PS(600) /* CFG_GPMC_A24_OEN */
6846+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
6847+ 0x1e4 A_DELAY_PS(525) G_DELAY_PS(600) /* CFG_GPMC_A25_OEN */
6848+ 0x1e8 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
6849+ 0x1f0 A_DELAY_PS(767) G_DELAY_PS(600) /* CFG_GPMC_A26_OEN */
6850+ 0x1f4 A_DELAY_PS(225) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
6851+ 0x1fc A_DELAY_PS(565) G_DELAY_PS(600) /* CFG_GPMC_A27_OEN */
6852+ 0x200 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
6853+ 0x364 A_DELAY_PS(969) G_DELAY_PS(600) /* CFG_GPMC_CS1_OEN */
6854+ 0x368 A_DELAY_PS(180) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
6855+ >;
6856+ };
6857+
6858+ /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
6859+ mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
6860+ pinctrl-pin-array = <
6861+ 0x190 A_DELAY_PS(274) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
6862+ 0x194 A_DELAY_PS(162) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
6863+ 0x1a8 A_DELAY_PS(401) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
6864+ 0x1ac A_DELAY_PS(73) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
6865+ 0x1b4 A_DELAY_PS(465) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
6866+ 0x1b8 A_DELAY_PS(115) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
6867+ 0x1c0 A_DELAY_PS(633) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
6868+ 0x1c4 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
6869+ 0x1d0 A_DELAY_PS(935) G_DELAY_PS(280) /* CFG_GPMC_A23_OUT */
6870+ 0x1d8 A_DELAY_PS(621) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
6871+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
6872+ 0x1e4 A_DELAY_PS(183) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
6873+ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
6874+ 0x1f0 A_DELAY_PS(467) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
6875+ 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
6876+ 0x1fc A_DELAY_PS(262) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
6877+ 0x200 A_DELAY_PS(46) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
6878+ 0x364 A_DELAY_PS(684) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
6879+ 0x368 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
6880+ >;
6881+ };
6882+
6883+ /* Correspnds to MMC2_DDR_3V3_MANUAL1 in datamanual */
6884+ mmc2_iodelay_ddr_3_3v_rev11_conf: mmc2_iodelay_ddr_3_3v_rev11_conf {
6885+ pinctrl-pin-array = <
6886+ 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
6887+ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
6888+ 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
6889+ 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
6890+ 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
6891+ 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
6892+ 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
6893+ 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
6894+ 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
6895+ 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
6896+ 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
6897+ 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
6898+ 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
6899+ 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */
6900+ 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
6901+ 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
6902+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
6903+ 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
6904+ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
6905+ 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
6906+ 0x1ec A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A26_IN */
6907+ 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
6908+ 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
6909+ 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */
6910+ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
6911+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
6912+ 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
6913+ 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
6914+ 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
6915+ >;
6916+ };
6917+
6918+ /* Corresponds to MMC2_DDR_1V8_MANUAL1 in datamanual */
6919+ mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf {
6920+ pinctrl-pin-array = <
6921+ 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */
6922+ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
6923+ 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
6924+ 0x1a4 A_DELAY_PS(274) G_DELAY_PS(240) /* CFG_GPMC_A20_IN */
6925+ 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
6926+ 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
6927+ 0x1b0 A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A21_IN */
6928+ 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
6929+ 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
6930+ 0x1bc A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A22_IN */
6931+ 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
6932+ 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
6933+ 0x1c8 A_DELAY_PS(514) G_DELAY_PS(360) /* CFG_GPMC_A23_IN */
6934+ 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */
6935+ 0x1d4 A_DELAY_PS(187) G_DELAY_PS(120) /* CFG_GPMC_A24_IN */
6936+ 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
6937+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
6938+ 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
6939+ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
6940+ 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
6941+ 0x1ec A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A26_IN */
6942+ 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
6943+ 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
6944+ 0x1f8 A_DELAY_PS(121) G_DELAY_PS(60) /* CFG_GPMC_A27_IN */
6945+ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
6946+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
6947+ 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
6948+ 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
6949+ 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
6950+ >;
6951+ };
6952+
6953+ /* Corresponds to MMC3_MANUAL1 in datamanual */
6954+ mmc3_iodelay_manual1_rev20_conf: mmc3_iodelay_manual1_conf {
6955+ pinctrl-pin-array = <
6956+ 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */
6957+ 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
6958+ 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
6959+ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
6960+ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
6961+ 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
6962+ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
6963+ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
6964+ 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
6965+ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
6966+ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
6967+ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
6968+ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
6969+ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
6970+ 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
6971+ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
6972+ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
6973+ >;
6974+ };
6975+
6976+ /* Corresponds to MMC3_MANUAL1 in datamanual */
6977+ mmc3_iodelay_manual1_rev11_conf: mmc3_iodelay_manual1_conf {
6978+ pinctrl-pin-array = <
6979+ 0x678 A_DELAY_PS(406) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */
6980+ 0x680 A_DELAY_PS(659) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
6981+ 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
6982+ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
6983+ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
6984+ 0x690 A_DELAY_PS(130) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
6985+ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
6986+ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
6987+ 0x69c A_DELAY_PS(169) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
6988+ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
6989+ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
6990+ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
6991+ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
6992+ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
6993+ 0x6b4 A_DELAY_PS(457) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
6994+ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
6995+ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
6996+ >;
6997+ };
6998+
6999+ /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
7000+ mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf {
7001+ pinctrl-pin-array = <
7002+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
7003+ 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
7004+ 0x84c A_DELAY_PS(96) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
7005+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
7006+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
7007+ 0x870 A_DELAY_PS(582) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
7008+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
7009+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
7010+ 0x87c A_DELAY_PS(391) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
7011+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
7012+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
7013+ 0x888 A_DELAY_PS(561) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
7014+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
7015+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
7016+ 0x894 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
7017+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
7018+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
7019+ >;
7020+ };
7021+
7022+ /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
7023+ mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf {
7024+ pinctrl-pin-array = <
7025+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
7026+ 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
7027+ 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
7028+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
7029+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
7030+ 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
7031+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
7032+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
7033+ 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
7034+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
7035+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
7036+ 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
7037+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
7038+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
7039+ 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
7040+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
7041+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
7042+ >;
7043+ };
7044+
7045+ /* Corresponds to MMC4_MANUAL1 in datamanual */
7046+ mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
7047+ pinctrl-pin-array = <
7048+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
7049+ 0x848 A_DELAY_PS(2651) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
7050+ 0x84c A_DELAY_PS(1572) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
7051+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
7052+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
7053+ 0x870 A_DELAY_PS(1913) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
7054+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
7055+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
7056+ 0x87c A_DELAY_PS(1721) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
7057+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
7058+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
7059+ 0x888 A_DELAY_PS(1891) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
7060+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
7061+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
7062+ 0x894 A_DELAY_PS(1919) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
7063+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
7064+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
7065+ >;
7066+ };
7067+
7068+ /* Corresponds to MMC4_MANUAL1 in datamanual */
7069+ mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
7070+ pinctrl-pin-array = <
7071+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
7072+ 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
7073+ 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
7074+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
7075+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
7076+ 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
7077+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
7078+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
7079+ 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */
7080+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
7081+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
7082+ 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */
7083+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
7084+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
7085+ 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */
7086+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
7087+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
7088+ >;
7089+ };
7090+};
7091diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
7092new file mode 100644
7093index 000000000000..b024a65c6e27
7094--- /dev/null
7095+++ b/arch/arm/boot/dts/dra76-evm.dts
7096@@ -0,0 +1,423 @@
7097+/*
7098+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
7099+ *
7100+ * This program is free software; you can redistribute it and/or modify
7101+ * it under the terms of the GNU General Public License version 2 as
7102+ * published by the Free Software Foundation.
7103+ */
7104+/dts-v1/;
7105+
7106+#include "dra76x.dtsi"
7107+#include "dra7-evm-common.dtsi"
7108+#include <dt-bindings/net/ti-dp83867.h>
7109+
7110+/ {
7111+ model = "TI DRA762 EVM";
7112+ compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
7113+
7114+ memory@0 {
7115+ device_type = "memory";
7116+ reg = <0x0 0x80000000 0x0 0x80000000>;
7117+ };
7118+
7119+ vsys_12v0: fixedregulator-vsys12v0 {
7120+ /* main supply */
7121+ compatible = "regulator-fixed";
7122+ regulator-name = "vsys_12v0";
7123+ regulator-min-microvolt = <12000000>;
7124+ regulator-max-microvolt = <12000000>;
7125+ regulator-always-on;
7126+ regulator-boot-on;
7127+ };
7128+
7129+ vsys_5v0: fixedregulator-vsys5v0 {
7130+ /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */
7131+ compatible = "regulator-fixed";
7132+ regulator-name = "vsys_5v0";
7133+ regulator-min-microvolt = <5000000>;
7134+ regulator-max-microvolt = <5000000>;
7135+ vin-supply = <&vsys_12v0>;
7136+ regulator-always-on;
7137+ regulator-boot-on;
7138+ };
7139+
7140+ vsys_3v3: fixedregulator-vsys3v3 {
7141+ /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */
7142+ compatible = "regulator-fixed";
7143+ regulator-name = "vsys_3v3";
7144+ regulator-min-microvolt = <3300000>;
7145+ regulator-max-microvolt = <3300000>;
7146+ vin-supply = <&vsys_12v0>;
7147+ regulator-always-on;
7148+ regulator-boot-on;
7149+ };
7150+
7151+ vio_3v3: fixedregulator-vio_3v3 {
7152+ compatible = "regulator-fixed";
7153+ regulator-name = "vio_3v3";
7154+ regulator-min-microvolt = <3300000>;
7155+ regulator-max-microvolt = <3300000>;
7156+ vin-supply = <&vsys_3v3>;
7157+ regulator-always-on;
7158+ regulator-boot-on;
7159+ };
7160+
7161+ vio_3v3_sd: fixedregulator-sd {
7162+ compatible = "regulator-fixed";
7163+ regulator-name = "vio_3v3_sd";
7164+ regulator-min-microvolt = <3300000>;
7165+ regulator-max-microvolt = <3300000>;
7166+ vin-supply = <&vio_3v3>;
7167+ enable-active-high;
7168+ gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
7169+ };
7170+
7171+ vio_1v8: fixedregulator-vio_1v8 {
7172+ compatible = "regulator-fixed";
7173+ regulator-name = "vio_1v8";
7174+ regulator-min-microvolt = <1800000>;
7175+ regulator-max-microvolt = <1800000>;
7176+ vin-supply = <&smps5_reg>;
7177+ };
7178+
7179+ vtt_fixed: fixedregulator-vtt {
7180+ compatible = "regulator-fixed";
7181+ regulator-name = "vtt_fixed";
7182+ regulator-min-microvolt = <1350000>;
7183+ regulator-max-microvolt = <1350000>;
7184+ vin-supply = <&vsys_3v3>;
7185+ regulator-always-on;
7186+ regulator-boot-on;
7187+ };
7188+
7189+ aic_dvdd: fixedregulator-aic_dvdd {
7190+ /* TPS77018DBVT */
7191+ compatible = "regulator-fixed";
7192+ regulator-name = "aic_dvdd";
7193+ vin-supply = <&vio_3v3>;
7194+ regulator-min-microvolt = <1800000>;
7195+ regulator-max-microvolt = <1800000>;
7196+ };
7197+};
7198+
7199+&dra7_pmx_core {
7200+ mmc1_pins_default: mmc1_pins_default {
7201+ pinctrl-single,pins = <
7202+ DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
7203+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
7204+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
7205+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
7206+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
7207+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
7208+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
7209+ >;
7210+ };
7211+
7212+ mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
7213+ pinctrl-single,pins = <
7214+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
7215+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
7216+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
7217+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
7218+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
7219+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
7220+ >;
7221+ };
7222+
7223+ mmc2_pins_default: mmc2_pins_default {
7224+ pinctrl-single,pins = <
7225+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
7226+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
7227+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
7228+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
7229+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
7230+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
7231+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
7232+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
7233+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
7234+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
7235+ >;
7236+ };
7237+};
7238+
7239+&i2c1 {
7240+ status = "okay";
7241+ clock-frequency = <400000>;
7242+
7243+ tps65917: tps65917@58 {
7244+ compatible = "ti,tps65917";
7245+ reg = <0x58>;
7246+ ti,system-power-controller;
7247+ interrupt-controller;
7248+ #interrupt-cells = <2>;
7249+
7250+ tps65917_pmic {
7251+ compatible = "ti,tps65917-pmic";
7252+
7253+ smps12-in-supply = <&vsys_3v3>;
7254+ smps3-in-supply = <&vsys_3v3>;
7255+ smps4-in-supply = <&vsys_3v3>;
7256+ smps5-in-supply = <&vsys_3v3>;
7257+ ldo1-in-supply = <&vsys_3v3>;
7258+ ldo2-in-supply = <&vsys_3v3>;
7259+ ldo3-in-supply = <&vsys_5v0>;
7260+ ldo4-in-supply = <&vsys_5v0>;
7261+ ldo5-in-supply = <&vsys_3v3>;
7262+
7263+ tps65917_regulators: regulators {
7264+ smps12_reg: smps12 {
7265+ /* VDD_DSPEVE */
7266+ regulator-name = "smps12";
7267+ regulator-min-microvolt = <850000>;
7268+ regulator-max-microvolt = <1250000>;
7269+ regulator-always-on;
7270+ regulator-boot-on;
7271+ };
7272+
7273+ smps3_reg: smps3 {
7274+ /* VDD_CORE */
7275+ regulator-name = "smps3";
7276+ regulator-min-microvolt = <850000>;
7277+ regulator-max-microvolt = <1250000>;
7278+ regulator-boot-on;
7279+ regulator-always-on;
7280+ };
7281+
7282+ smps4_reg: smps4 {
7283+ /* VDD_IVA */
7284+ regulator-name = "smps4";
7285+ regulator-min-microvolt = <850000>;
7286+ regulator-max-microvolt = <1250000>;
7287+ regulator-always-on;
7288+ regulator-boot-on;
7289+ };
7290+
7291+ smps5_reg: smps5 {
7292+ /* VDDS1V8 */
7293+ regulator-name = "smps5";
7294+ regulator-min-microvolt = <1800000>;
7295+ regulator-max-microvolt = <1800000>;
7296+ regulator-boot-on;
7297+ regulator-always-on;
7298+ };
7299+
7300+ ldo1_reg: ldo1 {
7301+ /* LDO1_OUT --> VDA_PHY1_1V8 */
7302+ regulator-name = "ldo1";
7303+ regulator-min-microvolt = <1800000>;
7304+ regulator-max-microvolt = <1800000>;
7305+ regulator-always-on;
7306+ regulator-boot-on;
7307+ regulator-allow-bypass;
7308+ };
7309+
7310+ ldo2_reg: ldo2 {
7311+ /* LDO2_OUT --> VDA_PHY2_1V8 */
7312+ regulator-name = "ldo2";
7313+ regulator-min-microvolt = <1800000>;
7314+ regulator-max-microvolt = <1800000>;
7315+ regulator-allow-bypass;
7316+ regulator-always-on;
7317+ };
7318+
7319+ ldo3_reg: ldo3 {
7320+ /* VDA_USB_3V3 */
7321+ regulator-name = "ldo3";
7322+ regulator-min-microvolt = <3300000>;
7323+ regulator-max-microvolt = <3300000>;
7324+ regulator-boot-on;
7325+ regulator-always-on;
7326+ };
7327+
7328+ ldo5_reg: ldo5 {
7329+ /* VDDA_1V8_PLL */
7330+ regulator-name = "ldo5";
7331+ regulator-min-microvolt = <1800000>;
7332+ regulator-max-microvolt = <1800000>;
7333+ regulator-always-on;
7334+ regulator-boot-on;
7335+ };
7336+
7337+ ldo4_reg: ldo4 {
7338+ /* VDD_SDIO_DV */
7339+ regulator-name = "ldo4";
7340+ regulator-min-microvolt = <1800000>;
7341+ regulator-max-microvolt = <3300000>;
7342+ regulator-boot-on;
7343+ regulator-always-on;
7344+ };
7345+ };
7346+ };
7347+
7348+ tps65917_power_button {
7349+ compatible = "ti,palmas-pwrbutton";
7350+ interrupt-parent = <&tps65917>;
7351+ interrupts = <1 IRQ_TYPE_NONE>;
7352+ wakeup-source;
7353+ ti,palmas-long-press-seconds = <6>;
7354+ };
7355+ };
7356+
7357+ lp87565: lp87565@60 {
7358+ compatible = "ti,lp87565-q1";
7359+ reg = <0x60>;
7360+
7361+ buck10-in-supply =<&vsys_3v3>;
7362+ buck23-in-supply =<&vsys_3v3>;
7363+
7364+ regulators: regulators {
7365+ buck10_reg: buck10 {
7366+ /*VDD_MPU*/
7367+ regulator-name = "buck10";
7368+ regulator-min-microvolt = <850000>;
7369+ regulator-max-microvolt = <1250000>;
7370+ regulator-always-on;
7371+ regulator-boot-on;
7372+ };
7373+
7374+ buck23_reg: buck23 {
7375+ /* VDD_GPU*/
7376+ regulator-name = "buck23";
7377+ regulator-min-microvolt = <850000>;
7378+ regulator-max-microvolt = <1250000>;
7379+ regulator-boot-on;
7380+ regulator-always-on;
7381+ };
7382+ };
7383+ };
7384+
7385+ pcf_lcd: pcf8757@20 {
7386+ compatible = "ti,pcf8575", "nxp,pcf8575";
7387+ reg = <0x20>;
7388+ gpio-controller;
7389+ #gpio-cells = <2>;
7390+ interrupt-controller;
7391+ #interrupt-cells = <2>;
7392+ interrupt-parent = <&gpio1>;
7393+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
7394+ };
7395+
7396+ pcf_gpio_21: pcf8757@21 {
7397+ compatible = "ti,pcf8575", "nxp,pcf8575";
7398+ reg = <0x21>;
7399+ gpio-controller;
7400+ #gpio-cells = <2>;
7401+ interrupt-parent = <&gpio1>;
7402+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
7403+ interrupt-controller;
7404+ #interrupt-cells = <2>;
7405+ };
7406+
7407+ pcf_hdmi: pcf8575@26 {
7408+ compatible = "ti,pcf8575", "nxp,pcf8575";
7409+ reg = <0x26>;
7410+ gpio-controller;
7411+ #gpio-cells = <2>;
7412+ p1 {
7413+ /* vin6_sel_s0: high: VIN6, low: audio */
7414+ gpio-hog;
7415+ gpios = <1 GPIO_ACTIVE_HIGH>;
7416+ output-low;
7417+ line-name = "vin6_sel_s0";
7418+ };
7419+ };
7420+
7421+ tlv320aic3106: tlv320aic3106@19 {
7422+ #sound-dai-cells = <0>;
7423+ compatible = "ti,tlv320aic3106";
7424+ reg = <0x19>;
7425+ adc-settle-ms = <40>;
7426+ ai3x-micbias-vg = <1>; /* 2.0V */
7427+ status = "okay";
7428+
7429+ /* Regulators */
7430+ AVDD-supply = <&vio_3v3>;
7431+ IOVDD-supply = <&vio_3v3>;
7432+ DRVDD-supply = <&vio_3v3>;
7433+ DVDD-supply = <&aic_dvdd>;
7434+ };
7435+};
7436+
7437+&cpu0 {
7438+ vdd-supply = <&buck10_reg>;
7439+};
7440+
7441+&mmc1 {
7442+ status = "okay";
7443+ vmmc-supply = <&vio_3v3_sd>;
7444+ vmmc_aux-supply = <&ldo4_reg>;
7445+ bus-width = <4>;
7446+ /*
7447+ * SDCD signal is not being used here - using the fact that GPIO mode
7448+ * is always hardwired.
7449+ */
7450+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
7451+ pinctrl-names = "default";
7452+ pinctrl-0 = <&mmc1_pins_default>;
7453+};
7454+
7455+&mmc2 {
7456+ status = "okay";
7457+ vmmc-supply = <&vio_1v8>;
7458+ bus-width = <8>;
7459+ pinctrl-names = "default";
7460+ pinctrl-0 = <&mmc2_pins_default>;
7461+};
7462+
7463+/* No RTC on this device */
7464+&rtc {
7465+ status = "disabled";
7466+};
7467+
7468+&mac {
7469+ status = "okay";
7470+
7471+ dual_emac;
7472+};
7473+
7474+&cpsw_emac0 {
7475+ phy_id = <&davinci_mdio>, <2>;
7476+ phy-mode = "rgmii-id";
7477+ dual_emac_res_vlan = <1>;
7478+};
7479+
7480+&cpsw_emac1 {
7481+ phy_id = <&davinci_mdio>, <3>;
7482+ phy-mode = "rgmii-id";
7483+ dual_emac_res_vlan = <2>;
7484+};
7485+
7486+&davinci_mdio {
7487+ dp83867_0: ethernet-phy@2 {
7488+ reg = <2>;
7489+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
7490+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
7491+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
7492+ ti,min-output-impedance;
7493+ ti,dp83867-rxctrl-strap-quirk;
7494+ };
7495+
7496+ dp83867_1: ethernet-phy@3 {
7497+ reg = <3>;
7498+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
7499+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
7500+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
7501+ ti,min-output-impedance;
7502+ ti,dp83867-rxctrl-strap-quirk;
7503+ };
7504+};
7505+
7506+&usb2_phy1 {
7507+ phy-supply = <&ldo3_reg>;
7508+};
7509+
7510+&usb2_phy2 {
7511+ phy-supply = <&ldo3_reg>;
7512+};
7513+
7514+&qspi {
7515+ spi-max-frequency = <96000000>;
7516+ m25p80@0 {
7517+ spi-max-frequency = <96000000>;
7518+ };
7519+};
7520diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi
7521new file mode 100644
7522index 000000000000..1c88c581ff18
7523--- /dev/null
7524+++ b/arch/arm/boot/dts/dra76x.dtsi
7525@@ -0,0 +1,19 @@
7526+/*
7527+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
7528+ *
7529+ * This program is free software; you can redistribute it and/or modify
7530+ * it under the terms of the GNU General Public License version 2 as
7531+ * published by the Free Software Foundation.
7532+ */
7533+
7534+#include "dra74x.dtsi"
7535+
7536+/ {
7537+ compatible = "ti,dra762", "ti,dra7";
7538+
7539+};
7540+
7541+/* MCAN interrupts are hard-wired to irqs 67, 68 */
7542+&crossbar_mpu {
7543+ ti,irqs-skip = <10 67 68 133 139 140>;
7544+};
7545diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts
7546index 4bd2ee87124e..4cbfa09c6c4e 100644
7547--- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts
7548+++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts
7549@@ -22,7 +22,6 @@ / {
7550 };
7551
7552 &mshc_2 {
7553- num-slots = <1>;
7554 cap-sd-highspeed;
7555 disable-wp;
7556 vqmmc-supply = <&ldo3_reg>;
7557diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
7558index 59c89d7662a8..639c2e605f3c 100644
7559--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
7560+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
7561@@ -304,7 +304,6 @@ buck5_reg: BUCK5 {
7562 };
7563
7564 &mshc_0 {
7565- num-slots = <1>;
7566 non-removable;
7567 cap-mmc-highspeed;
7568 card-detect-delay = <200>;
7569diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
7570index accee81da266..bbdfcbc6e7d2 100644
7571--- a/arch/arm/boot/dts/exynos3250-monk.dts
7572+++ b/arch/arm/boot/dts/exynos3250-monk.dts
7573@@ -426,7 +426,6 @@ &i2s2 {
7574 &mshc_0 {
7575 #address-cells = <1>;
7576 #size-cells = <0>;
7577- num-slots = <1>;
7578 broken-cd;
7579 non-removable;
7580 cap-mmc-highspeed;
7581diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
7582index 443e0c98dc73..0b45467d77a8 100644
7583--- a/arch/arm/boot/dts/exynos3250-rinato.dts
7584+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
7585@@ -220,21 +220,6 @@ &dsi_0 {
7586 samsung,pll-clock-frequency = <24000000>;
7587 status = "okay";
7588
7589- ports {
7590- #address-cells = <1>;
7591- #size-cells = <0>;
7592-
7593- port@1 {
7594- reg = <1>;
7595-
7596- dsi_out: endpoint {
7597- remote-endpoint = <&dsi_in>;
7598- samsung,burst-clock-frequency = <250000000>;
7599- samsung,esc-clock-frequency = <20000000>;
7600- };
7601- };
7602- };
7603-
7604 panel@0 {
7605 compatible = "samsung,s6e63j0x03";
7606 reg = <0>;
7607@@ -264,12 +249,6 @@ timing-0 {
7608 vsync-len = <2>;
7609 };
7610 };
7611-
7612- port {
7613- dsi_in: endpoint {
7614- remote-endpoint = <&dsi_out>;
7615- };
7616- };
7617 };
7618 };
7619
7620@@ -642,7 +621,6 @@ &jpeg {
7621 &mshc_0 {
7622 #address-cells = <1>;
7623 #size-cells = <0>;
7624- num-slots = <1>;
7625 broken-cd;
7626 non-removable;
7627 cap-mmc-highspeed;
7628diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
7629index 645feffb9239..7b6ab7265110 100644
7630--- a/arch/arm/boot/dts/exynos4210-trats.dts
7631+++ b/arch/arm/boot/dts/exynos4210-trats.dts
7632@@ -202,21 +202,6 @@ &dsi_0 {
7633 samsung,pll-clock-frequency = <24000000>;
7634 status = "okay";
7635
7636- ports {
7637- #address-cells = <1>;
7638- #size-cells = <0>;
7639-
7640- port@1 {
7641- reg = <1>;
7642-
7643- dsi_out: endpoint {
7644- remote-endpoint = <&dsi_in>;
7645- samsung,burst-clock-frequency = <500000000>;
7646- samsung,esc-clock-frequency = <20000000>;
7647- };
7648- };
7649- };
7650-
7651 panel@0 {
7652 reg = <0>;
7653 compatible = "samsung,s6e8aa0";
7654@@ -244,12 +229,6 @@ timing-0 {
7655 vsync-len = <2>;
7656 };
7657 };
7658-
7659- port {
7660- dsi_in: endpoint {
7661- remote-endpoint = <&dsi_out>;
7662- };
7663- };
7664 };
7665 };
7666
7667diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
7668index 4cd62487bb16..14ce2c69bc0b 100644
7669--- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
7670+++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
7671@@ -466,7 +466,6 @@ &mshc_0 {
7672 pinctrl-names = "default";
7673 status = "okay";
7674 vmmc-supply = <&buck9_reg>;
7675- num-slots = <1>;
7676 broken-cd;
7677 card-detect-delay = <200>;
7678 samsung,dw-mshc-ciu-div = <3>;
7679diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
7680index 219d587c5a85..102acd78be15 100644
7681--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
7682+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
7683@@ -516,7 +516,6 @@ &mshc_0 {
7684 mmc-pwrseq = <&emmc_pwrseq>;
7685 status = "okay";
7686
7687- num-slots = <1>;
7688 broken-cd;
7689 card-detect-delay = <200>;
7690 samsung,dw-mshc-ciu-div = <3>;
7691diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
7692index 7a83e2df18a6..8a89eb893d64 100644
7693--- a/arch/arm/boot/dts/exynos4412-origen.dts
7694+++ b/arch/arm/boot/dts/exynos4412-origen.dts
7695@@ -488,7 +488,6 @@ &mshc_0 {
7696 pinctrl-names = "default";
7697 status = "okay";
7698
7699- num-slots = <1>;
7700 broken-cd;
7701 card-detect-delay = <200>;
7702 samsung,dw-mshc-ciu-div = <3>;
7703diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
7704index 35e9b94b86b8..bceb919ac637 100644
7705--- a/arch/arm/boot/dts/exynos4412-trats2.dts
7706+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
7707@@ -390,21 +390,6 @@ &dsi_0 {
7708 samsung,pll-clock-frequency = <24000000>;
7709 status = "okay";
7710
7711- ports {
7712- #address-cells = <1>;
7713- #size-cells = <0>;
7714-
7715- port@1 {
7716- reg = <1>;
7717-
7718- dsi_out: endpoint {
7719- remote-endpoint = <&dsi_in>;
7720- samsung,burst-clock-frequency = <500000000>;
7721- samsung,esc-clock-frequency = <20000000>;
7722- };
7723- };
7724- };
7725-
7726 panel@0 {
7727 compatible = "samsung,s6e8aa0";
7728 reg = <0>;
7729@@ -432,12 +417,6 @@ timing-0 {
7730 vsync-len = <2>;
7731 };
7732 };
7733-
7734- port {
7735- dsi_in: endpoint {
7736- remote-endpoint = <&dsi_out>;
7737- };
7738- };
7739 };
7740 };
7741
7742@@ -901,7 +880,6 @@ &i2s0 {
7743 };
7744
7745 &mshc_0 {
7746- num-slots = <1>;
7747 broken-cd;
7748 non-removable;
7749 card-detect-delay = <200>;
7750diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
7751index 6a432460eb77..18a7f396ac5f 100644
7752--- a/arch/arm/boot/dts/exynos5250-arndale.dts
7753+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
7754@@ -518,7 +518,6 @@ &i2s0 {
7755
7756 &mmc_0 {
7757 status = "okay";
7758- num-slots = <1>;
7759 broken-cd;
7760 card-detect-delay = <200>;
7761 samsung,dw-mshc-ciu-div = <3>;
7762@@ -533,7 +532,6 @@ &mmc_0 {
7763
7764 &mmc_2 {
7765 status = "okay";
7766- num-slots = <1>;
7767 card-detect-delay = <200>;
7768 samsung,dw-mshc-ciu-div = <3>;
7769 samsung,dw-mshc-sdr-timing = <2 3>;
7770diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
7771index 6632f657394e..062cba4c2c31 100644
7772--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
7773+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
7774@@ -346,7 +346,6 @@ &i2s0 {
7775
7776 &mmc_0 {
7777 status = "okay";
7778- num-slots = <1>;
7779 broken-cd;
7780 card-detect-delay = <200>;
7781 samsung,dw-mshc-ciu-div = <3>;
7782@@ -360,7 +359,6 @@ &mmc_0 {
7783
7784 &mmc_2 {
7785 status = "okay";
7786- num-slots = <1>;
7787 card-detect-delay = <200>;
7788 samsung,dw-mshc-ciu-div = <3>;
7789 samsung,dw-mshc-sdr-timing = <2 3>;
7790diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
7791index e1d293dbbe5d..8788880e459d 100644
7792--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
7793+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
7794@@ -530,7 +530,6 @@ &i2s0 {
7795 /* eMMC flash */
7796 &mmc_0 {
7797 status = "okay";
7798- num-slots = <1>;
7799 non-removable;
7800 samsung,dw-mshc-ciu-div = <3>;
7801 samsung,dw-mshc-sdr-timing = <2 3>;
7802@@ -544,7 +543,6 @@ &mmc_0 {
7803 /* uSD card */
7804 &mmc_2 {
7805 status = "okay";
7806- num-slots = <1>;
7807 card-detect-delay = <200>;
7808 samsung,dw-mshc-ciu-div = <3>;
7809 samsung,dw-mshc-sdr-timing = <2 3>;
7810@@ -564,7 +562,6 @@ &mmc_2 {
7811 */
7812 &mmc_3 {
7813 status = "okay";
7814- num-slots = <1>;
7815 non-removable;
7816 cap-sdio-irq;
7817 keep-power-in-suspend;
7818diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
7819index 95c3bcace9dc..d53bfcbeb39c 100644
7820--- a/arch/arm/boot/dts/exynos5250-spring.dts
7821+++ b/arch/arm/boot/dts/exynos5250-spring.dts
7822@@ -427,7 +427,6 @@ &i2s0 {
7823
7824 &mmc_0 {
7825 status = "okay";
7826- num-slots = <1>;
7827 broken-cd;
7828 card-detect-delay = <200>;
7829 samsung,dw-mshc-ciu-div = <3>;
7830@@ -445,7 +444,6 @@ &mmc_0 {
7831 */
7832 &mmc_1 {
7833 status = "okay";
7834- num-slots = <1>;
7835 broken-cd;
7836 card-detect-delay = <200>;
7837 samsung,dw-mshc-ciu-div = <3>;
7838diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
7839index d0cc300cfb4b..73b7cdd5f522 100644
7840--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts
7841+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
7842@@ -67,7 +67,6 @@ &uart3 {
7843
7844 &mmc_0 {
7845 status = "okay";
7846- num-slots = <1>;
7847 broken-cd;
7848 bypass-smu;
7849 cap-mmc-highspeed;
7850@@ -83,7 +82,6 @@ &mmc_0 {
7851
7852 &mmc_2 {
7853 status = "okay";
7854- num-slots = <1>;
7855 cap-sd-highspeed;
7856 card-detect-delay = <200>;
7857 samsung,dw-mshc-ciu-div = <3>;
7858diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
7859index 6cc74d97daae..9cb7726ef8d0 100644
7860--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
7861+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
7862@@ -41,7 +41,6 @@ firmware@02037000 {
7863
7864 &mmc_0 {
7865 status = "okay";
7866- num-slots = <1>;
7867 cap-mmc-highspeed;
7868 broken-cd;
7869 card-detect-delay = <200>;
7870@@ -53,7 +52,6 @@ &mmc_0 {
7871
7872 &mmc_2 {
7873 status = "okay";
7874- num-slots = <1>;
7875 cap-sd-highspeed;
7876 card-detect-delay = <200>;
7877 samsung,dw-mshc-ciu-div = <3>;
7878diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
7879index f9a75bfd3f2b..683a4cfb4a23 100644
7880--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
7881+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
7882@@ -699,7 +699,6 @@ &i2s0 {
7883 /* eMMC flash */
7884 &mmc_0 {
7885 status = "okay";
7886- num-slots = <1>;
7887 mmc-hs200-1_8v;
7888 cap-mmc-highspeed;
7889 non-removable;
7890@@ -717,7 +716,6 @@ &mmc_0 {
7891 /* WiFi SDIO module */
7892 &mmc_1 {
7893 status = "okay";
7894- num-slots = <1>;
7895 non-removable;
7896 cap-sdio-irq;
7897 keep-power-in-suspend;
7898@@ -737,7 +735,6 @@ &mmc_1 {
7899 /* uSD card */
7900 &mmc_2 {
7901 status = "okay";
7902- num-slots = <1>;
7903 cap-sd-highspeed;
7904 card-detect-delay = <200>;
7905 clock-frequency = <400000000>;
7906diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
7907index bc4954e69f7b..7a00be7ea6d7 100644
7908--- a/arch/arm/boot/dts/exynos5440.dtsi
7909+++ b/arch/arm/boot/dts/exynos5440.dtsi
7910@@ -317,6 +317,7 @@ pcie_0: pcie@290000 {
7911 phys = <&pcie_phy0>;
7912 ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
7913 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
7914+ bus-range = <0x00 0xff>;
7915 #interrupt-cells = <1>;
7916 interrupt-map-mask = <0 0 0 0>;
7917 interrupt-map = <0x0 0 &gic 53>;
7918@@ -339,6 +340,7 @@ pcie_1: pcie@2a0000 {
7919 phys = <&pcie_phy1>;
7920 ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
7921 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
7922+ bus-range = <0x00 0xff>;
7923 #interrupt-cells = <1>;
7924 interrupt-map-mask = <0 0 0 0>;
7925 interrupt-map = <0x0 0 &gic 56>;
7926diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
7927index 953dc8677dc8..b2b95ff205e8 100644
7928--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
7929+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
7930@@ -667,7 +667,6 @@ &i2s0 {
7931 /* eMMC flash */
7932 &mmc_0 {
7933 status = "okay";
7934- num-slots = <1>;
7935 mmc-hs200-1_8v;
7936 mmc-hs400-1_8v;
7937 cap-mmc-highspeed;
7938@@ -686,7 +685,6 @@ &mmc_0 {
7939 /* WiFi SDIO module */
7940 &mmc_1 {
7941 status = "okay";
7942- num-slots = <1>;
7943 non-removable;
7944 cap-sdio-irq;
7945 keep-power-in-suspend;
7946@@ -706,7 +704,6 @@ &mmc_1 {
7947 /* uSD card */
7948 &mmc_2 {
7949 status = "okay";
7950- num-slots = <1>;
7951 cap-sd-highspeed;
7952 card-detect-delay = <200>;
7953 clock-frequency = <400000000>;
7954diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
7955new file mode 100644
7956index 000000000000..e75e2d44371c
7957--- /dev/null
7958+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
7959@@ -0,0 +1,246 @@
7960+/*
7961+ * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
7962+ */
7963+
7964+/dts-v1/;
7965+
7966+#include "gemini.dtsi"
7967+#include <dt-bindings/input/input.h>
7968+
7969+/ {
7970+ model = "D-Link DIR-685 Xtreme N Storage Router";
7971+ compatible = "dlink,dir-685", "cortina,gemini";
7972+ #address-cells = <1>;
7973+ #size-cells = <1>;
7974+
7975+ memory {
7976+ /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
7977+ device_type = "memory";
7978+ reg = <0x00000000 0x8000000>;
7979+ };
7980+
7981+ chosen {
7982+ stdout-path = "uart0:115200n8";
7983+ };
7984+
7985+ gpio_keys {
7986+ compatible = "gpio-keys";
7987+ #address-cells = <1>;
7988+ #size-cells = <0>;
7989+ button-esc {
7990+ debounce_interval = <50>;
7991+ wakeup-source;
7992+ linux,code = <KEY_ESC>;
7993+ label = "reset";
7994+ /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
7995+ gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
7996+ };
7997+ button-eject {
7998+ debounce_interval = <50>;
7999+ wakeup-source;
8000+ linux,code = <KEY_EJECTCD>;
8001+ label = "unmount";
8002+ /* Collides with LPC LFRAME, UART RTS, SSP TXD */
8003+ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
8004+ };
8005+ };
8006+
8007+ leds {
8008+ compatible = "gpio-leds";
8009+ led-wps {
8010+ label = "dir685:blue:WPS";
8011+ /* Collides with ICE */
8012+ gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
8013+ default-state = "on";
8014+ linux,default-trigger = "heartbeat";
8015+ };
8016+ /*
8017+ * These two LEDs are on the side of the device.
8018+ * For electrical reasons, both LEDs cannot be active
8019+ * at the same time so only blue or orange can on at
8020+ * one time. Enabling both makes the LED go dark.
8021+ * The LEDs both sit inside the unmount button and the
8022+ * label on the case says "unmount".
8023+ */
8024+ led-blue-hd {
8025+ label = "dir685:blue:HD";
8026+ /* Collides with LPC_SERIRQ, UART DTR, SSP FSC pins */
8027+ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
8028+ default-state = "off";
8029+ };
8030+ led-orange-hd {
8031+ label = "dir685:orange:HD";
8032+ /* Collides with LPC_LAD[2], UART DSR, SSP ECLK pins */
8033+ gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
8034+ default-state = "off";
8035+ };
8036+ };
8037+
8038+ /*
8039+ * This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM.
8040+ * Since the platform has no temperature sensor, this is controlled
8041+ * from userspace by using the hard disks S.M.A.R.T. temperature
8042+ * sensor. It is turned on when the temperature exceeds 46 degrees
8043+ * and turned off when the temperatures goes below 41 degrees
8044+ * (celsius).
8045+ */
8046+ gpio-fan {
8047+ compatible = "gpio-fan";
8048+ /* Collides with IDE */
8049+ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
8050+ gpio-fan,speed-map = <0 0>, <10000 1>;
8051+ #cooling-cells = <2>;
8052+ };
8053+
8054+ /*
8055+ * The touchpad input is connected to a GPIO bit-banged
8056+ * I2C bus.
8057+ */
8058+ gpio-i2c {
8059+ compatible = "i2c-gpio";
8060+ /* Collides with ICE */
8061+ gpios = <&gpio0 5 0>, /* SDA */
8062+ <&gpio0 6 0>; /* SCL */
8063+ #address-cells = <1>;
8064+ #size-cells = <0>;
8065+
8066+ touchkeys@26 {
8067+ compatible = "dlink,dir685-touchkeys";
8068+ reg = <0x26>;
8069+ interrupt-parent = <&gpio0>;
8070+ /* Collides with NAND flash */
8071+ interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
8072+ };
8073+ };
8074+
8075+ soc {
8076+ flash@30000000 {
8077+ status = "okay";
8078+ /* 32MB of flash */
8079+ reg = <0x30000000 0x02000000>;
8080+
8081+ /*
8082+ * This "RedBoot" is the Storlink derivative.
8083+ */
8084+ partition@0 {
8085+ label = "RedBoot";
8086+ reg = <0x00000000 0x00040000>;
8087+ read-only;
8088+ };
8089+ /*
8090+ * Between the boot loader and the rootfs is the kernel
8091+ * in a custom Storlink format flashed from the boot
8092+ * menu. The rootfs is in squashfs format.
8093+ */
8094+ partition@1800c0 {
8095+ label = "rootfs";
8096+ reg = <0x001800c0 0x01dbff40>;
8097+ read-only;
8098+ };
8099+ partition@1f40000 {
8100+ label = "upgrade";
8101+ reg = <0x01f40000 0x00040000>;
8102+ read-only;
8103+ };
8104+ partition@1f80000 {
8105+ label = "rgdb";
8106+ reg = <0x01f80000 0x00040000>;
8107+ read-only;
8108+ };
8109+ /*
8110+ * This partition contains MAC addresses for WAN,
8111+ * WLAN and LAN, and the country code (for wireless
8112+ * I guess).
8113+ */
8114+ partition@1fc0000 {
8115+ label = "nvram";
8116+ reg = <0x01fc0000 0x00020000>;
8117+ read-only;
8118+ };
8119+ partition@1fe0000 {
8120+ label = "LangPack";
8121+ reg = <0x01fe0000 0x00020000>;
8122+ read-only;
8123+ };
8124+ };
8125+
8126+ syscon: syscon@40000000 {
8127+ pinctrl {
8128+ /*
8129+ * gpio0bgrp cover line 5, 6 used by TK I2C
8130+ * gpio0bgrp cover line 7 used by WPS LED
8131+ * gpio0cgrp cover line 8, 13 used by keys
8132+ * and 11, 12 used by the HD LEDs
8133+ * gpio0egrp cover line 16 used by VDISP
8134+ * gpio0fgrp cover line 17 used by TK IRQ
8135+ * gpio0ggrp cover line 20 used by panel CS
8136+ * gpio0hgrp cover line 21,22 used by RTL8366RB
8137+ */
8138+ gpio0_default_pins: pinctrl-gpio0 {
8139+ mux {
8140+ function = "gpio0";
8141+ groups = "gpio0bgrp",
8142+ "gpio0cgrp",
8143+ "gpio0egrp",
8144+ "gpio0fgrp",
8145+ "gpio0ggrp",
8146+ "gpio0hgrp";
8147+ };
8148+ };
8149+ /*
8150+ * gpio1bgrp cover line 5,8,7 used by panel SPI
8151+ * also line 6 used by the fan
8152+ *
8153+ */
8154+ gpio1_default_pins: pinctrl-gpio1 {
8155+ mux {
8156+ function = "gpio1";
8157+ groups = "gpio1bgrp";
8158+ };
8159+ };
8160+ };
8161+ };
8162+
8163+ sata: sata@46000000 {
8164+ cortina,gemini-ata-muxmode = <0>;
8165+ cortina,gemini-enable-sata-bridge;
8166+ status = "okay";
8167+ };
8168+
8169+ gpio0: gpio@4d000000 {
8170+ pinctrl-names = "default";
8171+ pinctrl-0 = <&gpio0_default_pins>;
8172+ };
8173+
8174+ gpio1: gpio@4e000000 {
8175+ pinctrl-names = "default";
8176+ pinctrl-0 = <&gpio1_default_pins>;
8177+ };
8178+
8179+ pci@50000000 {
8180+ status = "okay";
8181+ interrupt-map-mask = <0xf800 0 0 7>;
8182+ interrupt-map =
8183+ <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
8184+ <0x4800 0 0 2 &pci_intc 1>,
8185+ <0x4800 0 0 3 &pci_intc 2>,
8186+ <0x4800 0 0 4 &pci_intc 3>,
8187+ <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
8188+ <0x5000 0 0 2 &pci_intc 2>,
8189+ <0x5000 0 0 3 &pci_intc 3>,
8190+ <0x5000 0 0 4 &pci_intc 0>,
8191+ <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
8192+ <0x5800 0 0 2 &pci_intc 3>,
8193+ <0x5800 0 0 3 &pci_intc 0>,
8194+ <0x5800 0 0 4 &pci_intc 1>,
8195+ <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
8196+ <0x6000 0 0 2 &pci_intc 0>,
8197+ <0x6000 0 0 3 &pci_intc 1>,
8198+ <0x6000 0 0 4 &pci_intc 2>;
8199+ };
8200+
8201+ ata@63000000 {
8202+ status = "okay";
8203+ };
8204+ };
8205+};
8206diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts
8207index 55f6a4f1f801..b4fc58c8cf8d 100644
8208--- a/arch/arm/boot/dts/gemini-nas4220b.dts
8209+++ b/arch/arm/boot/dts/gemini-nas4220b.dts
8210@@ -33,6 +33,7 @@ button@29 {
8211 wakeup-source;
8212 linux,code = <KEY_SETUP>;
8213 label = "Backup button";
8214+ /* Conflict with TVC */
8215 gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
8216 };
8217 button@31 {
8218@@ -40,6 +41,7 @@ button@31 {
8219 wakeup-source;
8220 linux,code = <KEY_RESTART>;
8221 label = "Softreset button";
8222+ /* Conflict with TVC */
8223 gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
8224 };
8225 };
8226@@ -48,11 +50,13 @@ leds {
8227 compatible = "gpio-leds";
8228 led@28 {
8229 label = "nas4220b:orange:hdd";
8230+ /* Conflict with TVC */
8231 gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
8232 default-state = "on";
8233 };
8234 led@30 {
8235 label = "nas4220b:green:os";
8236+ /* Conflict with TVC */
8237 gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
8238 default-state = "on";
8239 linux,default-trigger = "heartbeat";
8240@@ -99,12 +103,32 @@ partition@fe0000 {
8241 };
8242 };
8243
8244+ syscon: syscon@40000000 {
8245+ pinctrl {
8246+ /*
8247+ * gpio1dgrp cover line 28-31 otherwise used
8248+ * by TVC.
8249+ */
8250+ gpio1_default_pins: pinctrl-gpio1 {
8251+ mux {
8252+ function = "gpio1";
8253+ groups = "gpio1dgrp";
8254+ };
8255+ };
8256+ };
8257+ };
8258+
8259 sata: sata@46000000 {
8260 cortina,gemini-ata-muxmode = <0>;
8261 cortina,gemini-enable-sata-bridge;
8262 status = "okay";
8263 };
8264
8265+ gpio1: gpio@4e000000 {
8266+ pinctrl-names = "default";
8267+ pinctrl-0 = <&gpio1_default_pins>;
8268+ };
8269+
8270 ata@63000000 {
8271 status = "okay";
8272 };
8273diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini-rut1xx.dts
8274index 7b920bfbda32..3613b264f45f 100644
8275--- a/arch/arm/boot/dts/gemini-rut1xx.dts
8276+++ b/arch/arm/boot/dts/gemini-rut1xx.dts
8277@@ -33,6 +33,7 @@ button@28 {
8278 wakeup-source;
8279 linux,code = <KEY_SETUP>;
8280 label = "Reset to defaults";
8281+ /* Conflict with TVC */
8282 gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
8283 };
8284 };
8285@@ -42,12 +43,14 @@ leds {
8286 led@7 {
8287 /* FIXME: add the LED color */
8288 label = "rut1xx::gsm";
8289+ /* Conflict with ICE */
8290 gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
8291 default-state = "on";
8292 };
8293 led@31 {
8294 /* FIXME: add the LED color */
8295 label = "rut1xx::power";
8296+ /* Conflict with NAND CE0 */
8297 gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
8298 default-state = "off";
8299 linux,default-trigger = "heartbeat";
8300@@ -61,5 +64,41 @@ flash@30000000 {
8301 reg = <0x30000000 0x00800000>;
8302 /* TODO: add flash partitions here */
8303 };
8304+
8305+ syscon: syscon@40000000 {
8306+ pinctrl {
8307+ /*
8308+ * gpio0bgrp cover line 7 used by GSM LED
8309+ * gpio0fgrp cover line 17 used by power LED
8310+ */
8311+ gpio0_default_pins: pinctrl-gpio0 {
8312+ mux {
8313+ function = "gpio0";
8314+ groups = "gpio0bgrp",
8315+ "gpio0fgrp";
8316+ };
8317+ };
8318+ /*
8319+ * gpio1dgrp cover line 28-31 otherwise used
8320+ * by TVC.
8321+ */
8322+ gpio1_default_pins: pinctrl-gpio1 {
8323+ mux {
8324+ function = "gpio1";
8325+ groups = "gpio1dgrp";
8326+ };
8327+ };
8328+ };
8329+ };
8330+
8331+ gpio0: gpio@4d000000 {
8332+ pinctrl-names = "default";
8333+ pinctrl-0 = <&gpio0_default_pins>;
8334+ };
8335+
8336+ gpio1: gpio@4e000000 {
8337+ pinctrl-names = "default";
8338+ pinctrl-0 = <&gpio1_default_pins>;
8339+ };
8340 };
8341 };
8342diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts
8343index 4d200f0bcd45..7cfa9caf47d4 100644
8344--- a/arch/arm/boot/dts/gemini-sq201.dts
8345+++ b/arch/arm/boot/dts/gemini-sq201.dts
8346@@ -33,6 +33,7 @@ button@18 {
8347 wakeup-source;
8348 linux,code = <KEY_SETUP>;
8349 label = "factory reset";
8350+ /* Conflict with NAND flash */
8351 gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
8352 };
8353 };
8354@@ -41,12 +42,14 @@ leds {
8355 compatible = "gpio-leds";
8356 led@20 {
8357 label = "sq201:green:info";
8358+ /* Conflict with parallel flash */
8359 gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
8360 default-state = "on";
8361 linux,default-trigger = "heartbeat";
8362 };
8363 led@31 {
8364 label = "sq201:green:usb";
8365+ /* Conflict with parallel and NAND flash */
8366 gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
8367 default-state = "off";
8368 linux,default-trigger = "usb-host";
8369@@ -55,7 +58,15 @@ led@31 {
8370
8371 soc {
8372 flash@30000000 {
8373- status = "okay";
8374+ /*
8375+ * Flash access can be enabled, with the side effect
8376+ * of disabling access to GPIO LED on GPIO0[20] which
8377+ * reuse one of the parallel flash chip select lines.
8378+ * Also the default firmware on the machine has the
8379+ * problem that since it uses the flash, the two LEDS
8380+ * on the right become numb.
8381+ */
8382+ /* status = "okay"; */
8383 /* 16MB of flash */
8384 reg = <0x30000000 0x01000000>;
8385
8386@@ -93,12 +104,35 @@ partition@fe0000 {
8387 };
8388 };
8389
8390+ syscon: syscon@40000000 {
8391+ pinctrl {
8392+ /*
8393+ * gpio0fgrp cover line 18 used by reset button
8394+ * gpio0ggrp cover line 20 used by info LED
8395+ * gpio0kgrp cover line 31 used by USB LED
8396+ */
8397+ gpio0_default_pins: pinctrl-gpio0 {
8398+ mux {
8399+ function = "gpio0";
8400+ groups = "gpio0fgrp",
8401+ "gpio0ggrp",
8402+ "gpio0kgrp";
8403+ };
8404+ };
8405+ };
8406+ };
8407+
8408 sata: sata@46000000 {
8409 cortina,gemini-ata-muxmode = <0>;
8410 cortina,gemini-enable-sata-bridge;
8411 status = "okay";
8412 };
8413
8414+ gpio0: gpio@4d000000 {
8415+ pinctrl-names = "default";
8416+ pinctrl-0 = <&gpio0_default_pins>;
8417+ };
8418+
8419 pci@50000000 {
8420 status = "okay";
8421 interrupt-map-mask = <0xf800 0 0 7>;
8422diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts
8423index 63b756e3bf5a..38a49e750478 100644
8424--- a/arch/arm/boot/dts/gemini-wbd111.dts
8425+++ b/arch/arm/boot/dts/gemini-wbd111.dts
8426@@ -33,6 +33,7 @@ button@5 {
8427 wakeup-source;
8428 linux,code = <KEY_SETUP>;
8429 label = "reset";
8430+ /* Conflict with ICE */
8431 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
8432 };
8433 };
8434@@ -42,21 +43,25 @@ leds {
8435
8436 led@1 {
8437 label = "wbd111:red:L3";
8438+ /* Conflict with TVC and extended parallel flash */
8439 gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
8440 default-state = "off";
8441 };
8442 led@2 {
8443 label = "wbd111:green:L4";
8444+ /* Conflict with TVC and extended parallel flash */
8445 gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
8446 default-state = "off";
8447 };
8448 led@3 {
8449 label = "wbd111:red:L4";
8450+ /* Conflict with TVC and extended parallel flash */
8451 gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
8452 default-state = "off";
8453 };
8454 led@5 {
8455 label = "wbd111:green:L3";
8456+ /* Conflict with TVC and extended parallel flash */
8457 gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
8458 default-state = "on";
8459 linux,default-trigger = "heartbeat";
8460@@ -98,5 +103,26 @@ partition@7e0000 {
8461 read-only;
8462 };
8463 };
8464+
8465+ syscon: syscon@40000000 {
8466+ pinctrl {
8467+ /*
8468+ * gpio0agrp cover line 0-4
8469+ * gpio0bgrp cover line 5
8470+ */
8471+ gpio0_default_pins: pinctrl-gpio0 {
8472+ mux {
8473+ function = "gpio0";
8474+ groups = "gpio0agrp",
8475+ "gpio0bgrp";
8476+ };
8477+ };
8478+ };
8479+ };
8480+
8481+ gpio0: gpio@4d000000 {
8482+ pinctrl-names = "default";
8483+ pinctrl-0 = <&gpio0_default_pins>;
8484+ };
8485 };
8486 };
8487diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts
8488index 9747f5a47807..f77e34e0df0b 100644
8489--- a/arch/arm/boot/dts/gemini-wbd222.dts
8490+++ b/arch/arm/boot/dts/gemini-wbd222.dts
8491@@ -33,6 +33,7 @@ button@5 {
8492 wakeup-source;
8493 linux,code = <KEY_SETUP>;
8494 label = "reset";
8495+ /* Conflict with ICE */
8496 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
8497 };
8498 };
8499@@ -42,21 +43,25 @@ leds {
8500
8501 led@1 {
8502 label = "wbd111:red:L3";
8503+ /* Conflict with TVC and extended parallel flash */
8504 gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
8505 default-state = "off";
8506 };
8507 led@2 {
8508 label = "wbd111:green:L4";
8509+ /* Conflict with TVC and extended parallel flash */
8510 gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
8511 default-state = "off";
8512 };
8513 led@3 {
8514 label = "wbd111:red:L4";
8515+ /* Conflict with TVC and extended parallel flash */
8516 gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
8517 default-state = "off";
8518 };
8519 led@5 {
8520 label = "wbd111:green:L3";
8521+ /* Conflict with TVC and extended parallel flash */
8522 gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
8523 default-state = "on";
8524 linux,default-trigger = "heartbeat";
8525@@ -98,5 +103,26 @@ partition@7e0000 {
8526 read-only;
8527 };
8528 };
8529+
8530+ syscon: syscon@40000000 {
8531+ pinctrl {
8532+ /*
8533+ * gpio0agrp cover line 0-4
8534+ * gpio0bgrp cover line 5
8535+ */
8536+ gpio0_default_pins: pinctrl-gpio0 {
8537+ mux {
8538+ function = "gpio0";
8539+ groups = "gpio0agrp",
8540+ "gpio0bgrp";
8541+ };
8542+ };
8543+ };
8544+ };
8545+
8546+ gpio0: gpio@4d000000 {
8547+ pinctrl-names = "default";
8548+ pinctrl-0 = <&gpio0_default_pins>;
8549+ };
8550 };
8551 };
8552diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi
8553index 141d8d3a1d07..c68e8d430234 100644
8554--- a/arch/arm/boot/dts/gemini.dtsi
8555+++ b/arch/arm/boot/dts/gemini.dtsi
8556@@ -5,6 +5,8 @@
8557 /include/ "skeleton.dtsi"
8558
8559 #include <dt-bindings/interrupt-controller/irq.h>
8560+#include <dt-bindings/clock/cortina,gemini-clock.h>
8561+#include <dt-bindings/reset/cortina,gemini-reset.h>
8562 #include <dt-bindings/gpio/gpio.h>
8563
8564 / {
8565@@ -18,6 +20,8 @@ soc {
8566 flash@30000000 {
8567 compatible = "cortina,gemini-flash", "cfi-flash";
8568 syscon = <&syscon>;
8569+ pinctrl-names = "default";
8570+ pinctrl-0 = <&pflash_default_pins>;
8571 bank-width = <2>;
8572 #address-cells = <1>;
8573 #size-cells = <1>;
8574@@ -39,22 +43,123 @@ syscon-reboot {
8575 /* RESET_GLOBAL | RESET_CPU1 */
8576 mask = <0xC0000000>;
8577 };
8578+
8579+ pinctrl {
8580+ compatible = "cortina,gemini-pinctrl";
8581+ regmap = <&syscon>;
8582+ /* Hog the DRAM pins */
8583+ pinctrl-names = "default";
8584+ pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
8585+ <&vcontrol_default_pins>;
8586+
8587+ dram_default_pins: pinctrl-dram {
8588+ mux {
8589+ function = "dram";
8590+ groups = "dramgrp";
8591+ };
8592+ };
8593+ rtc_default_pins: pinctrl-rtc {
8594+ mux {
8595+ function = "rtc";
8596+ groups = "rtcgrp";
8597+ };
8598+ };
8599+ power_default_pins: pinctrl-power {
8600+ mux {
8601+ function = "power";
8602+ groups = "powergrp";
8603+ };
8604+ };
8605+ cir_default_pins: pinctrl-cir {
8606+ mux {
8607+ function = "cir";
8608+ groups = "cirgrp";
8609+ };
8610+ };
8611+ system_default_pins: pinctrl-system {
8612+ mux {
8613+ function = "system";
8614+ groups = "systemgrp";
8615+ };
8616+ };
8617+ vcontrol_default_pins: pinctrl-vcontrol {
8618+ mux {
8619+ function = "vcontrol";
8620+ groups = "vcontrolgrp";
8621+ };
8622+ };
8623+ ice_default_pins: pinctrl-ice {
8624+ mux {
8625+ function = "ice";
8626+ groups = "icegrp";
8627+ };
8628+ };
8629+ uart_default_pins: pinctrl-uart {
8630+ mux {
8631+ function = "uart";
8632+ groups = "uartrxtxgrp";
8633+ };
8634+ };
8635+ pflash_default_pins: pinctrl-pflash {
8636+ mux {
8637+ function = "pflash";
8638+ groups = "pflashgrp";
8639+ };
8640+ };
8641+ usb_default_pins: pinctrl-usb {
8642+ mux {
8643+ function = "usb";
8644+ groups = "usbgrp";
8645+ };
8646+ };
8647+ gmii_default_pins: pinctrl-gmii {
8648+ mux {
8649+ function = "gmii";
8650+ groups = "gmiigrp";
8651+ };
8652+ };
8653+ pci_default_pins: pinctrl-pci {
8654+ mux {
8655+ function = "pci";
8656+ groups = "pcigrp";
8657+ };
8658+ };
8659+ sata_default_pins: pinctrl-sata {
8660+ mux {
8661+ function = "sata";
8662+ groups = "satagrp";
8663+ };
8664+ };
8665+ /* Activate both groups of pins for this state */
8666+ sata_and_ide_pins: pinctrl-sata-ide {
8667+ mux0 {
8668+ function = "sata";
8669+ groups = "satagrp";
8670+ };
8671+ mux1 {
8672+ function = "ide";
8673+ groups = "idegrp";
8674+ };
8675+ };
8676+ };
8677 };
8678
8679 watchdog@41000000 {
8680 compatible = "cortina,gemini-watchdog";
8681 reg = <0x41000000 0x1000>;
8682 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
8683- resets = <&syscon 23>;
8684- clocks = <&syscon 2>;
8685+ resets = <&syscon GEMINI_RESET_WDOG>;
8686+ clocks = <&syscon GEMINI_CLK_APB>;
8687 };
8688
8689 uart0: serial@42000000 {
8690 compatible = "ns16550a";
8691 reg = <0x42000000 0x100>;
8692- resets = <&syscon 18>;
8693- clocks = <&syscon 6>;
8694+ resets = <&syscon GEMINI_RESET_UART>;
8695+ clocks = <&syscon GEMINI_CLK_UART>;
8696 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
8697+ pinctrl-names = "default";
8698+ pinctrl-0 = <&uart_default_pins>;
8699 reg-shift = <2>;
8700 };
8701
8702@@ -65,9 +170,9 @@ timer@43000000 {
8703 interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
8704 <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
8705 <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
8706- resets = <&syscon 17>;
8707+ resets = <&syscon GEMINI_RESET_TIMER>;
8708 /* APB clock or RTC clock */
8709- clocks = <&syscon 2>, <&syscon 0>;
8710+ clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
8711 clock-names = "PCLK", "EXTCLK";
8712 syscon = <&syscon>;
8713 };
8714@@ -76,20 +181,30 @@ rtc@45000000 {
8715 compatible = "cortina,gemini-rtc";
8716 reg = <0x45000000 0x100>;
8717 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
8718- resets = <&syscon 16>;
8719- clocks = <&syscon 2>, <&syscon 0>;
8720+ resets = <&syscon GEMINI_RESET_RTC>;
8721+ clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
8722 clock-names = "PCLK", "EXTCLK";
8723+ pinctrl-names = "default";
8724+ pinctrl-0 = <&rtc_default_pins>;
8725 };
8726
8727 sata: sata@46000000 {
8728 compatible = "cortina,gemini-sata-bridge";
8729 reg = <0x46000000 0x100>;
8730- resets = <&syscon 26>,
8731- <&syscon 27>;
8732+ resets = <&syscon GEMINI_RESET_SATA0>,
8733+ <&syscon GEMINI_RESET_SATA1>;
8734 reset-names = "sata0", "sata1";
8735- clocks = <&syscon 10>,
8736- <&syscon 11>;
8737+ clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
8738+ <&syscon GEMINI_CLK_GATE_SATA1>;
8739 clock-names = "SATA0_PCLK", "SATA1_PCLK";
8740+ /*
8741+ * This defines the special "ide" state that needs
8742+ * to be explicitly enabled to enable the IDE pins,
8743+ * as these pins are normally used for other things.
8744+ */
8745+ pinctrl-names = "default", "ide";
8746+ pinctrl-0 = <&sata_default_pins>;
8747+ pinctrl-1 = <&sata_and_ide_pins>;
8748 syscon = <&syscon>;
8749 status = "disabled";
8750 };
8751@@ -97,7 +212,7 @@ sata: sata@46000000 {
8752 intcon: interrupt-controller@48000000 {
8753 compatible = "faraday,ftintc010";
8754 reg = <0x48000000 0x1000>;
8755- resets = <&syscon 14>;
8756+ resets = <&syscon GEMINI_RESET_INTCON0>;
8757 interrupt-controller;
8758 #interrupt-cells = <2>;
8759 };
8760@@ -106,14 +221,16 @@ power-controller@4b000000 {
8761 compatible = "cortina,gemini-power-controller";
8762 reg = <0x4b000000 0x100>;
8763 interrupts = <26 IRQ_TYPE_EDGE_RISING>;
8764+ pinctrl-names = "default";
8765+ pinctrl-0 = <&power_default_pins>;
8766 };
8767
8768 gpio0: gpio@4d000000 {
8769 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
8770 reg = <0x4d000000 0x100>;
8771 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
8772- resets = <&syscon 20>;
8773- clocks = <&syscon 2>;
8774+ resets = <&syscon GEMINI_RESET_GPIO0>;
8775+ clocks = <&syscon GEMINI_CLK_APB>;
8776 gpio-controller;
8777 #gpio-cells = <2>;
8778 interrupt-controller;
8779@@ -124,8 +241,8 @@ gpio1: gpio@4e000000 {
8780 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
8781 reg = <0x4e000000 0x100>;
8782 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
8783- resets = <&syscon 21>;
8784- clocks = <&syscon 2>;
8785+ resets = <&syscon GEMINI_RESET_GPIO1>;
8786+ clocks = <&syscon GEMINI_CLK_APB>;
8787 gpio-controller;
8788 #gpio-cells = <2>;
8789 interrupt-controller;
8790@@ -136,8 +253,8 @@ gpio2: gpio@4f000000 {
8791 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
8792 reg = <0x4f000000 0x100>;
8793 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
8794- resets = <&syscon 22>;
8795- clocks = <&syscon 2>;
8796+ resets = <&syscon GEMINI_RESET_GPIO2>;
8797+ clocks = <&syscon GEMINI_CLK_APB>;
8798 gpio-controller;
8799 #gpio-cells = <2>;
8800 interrupt-controller;
8801@@ -151,9 +268,11 @@ pci@50000000 {
8802 * to configure the host bridge.
8803 */
8804 reg = <0x50000000 0x100>;
8805- resets = <&syscon 7>;
8806- clocks = <&syscon 15>, <&syscon 4>;
8807+ resets = <&syscon GEMINI_RESET_PCI>;
8808+ clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
8809 clock-names = "PCLK", "PCICLK";
8810+ pinctrl-names = "default";
8811+ pinctrl-0 = <&pci_default_pins>;
8812 #address-cells = <3>;
8813 #size-cells = <2>;
8814 #interrupt-cells = <1>;
8815@@ -193,8 +312,8 @@ ata@63000000 {
8816 compatible = "cortina,gemini-pata", "faraday,ftide010";
8817 reg = <0x63000000 0x1000>;
8818 interrupts = <4 IRQ_TYPE_EDGE_RISING>;
8819- resets = <&syscon 2>;
8820- clocks = <&syscon 14>;
8821+ resets = <&syscon GEMINI_RESET_IDE>;
8822+ clocks = <&syscon GEMINI_CLK_GATE_IDE>;
8823 clock-names = "PCLK";
8824 sata = <&sata>;
8825 status = "disabled";
8826@@ -204,8 +323,8 @@ ata@63400000 {
8827 compatible = "cortina,gemini-pata", "faraday,ftide010";
8828 reg = <0x63400000 0x1000>;
8829 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
8830- resets = <&syscon 2>;
8831- clocks = <&syscon 14>;
8832+ resets = <&syscon GEMINI_RESET_IDE>;
8833+ clocks = <&syscon GEMINI_CLK_GATE_IDE>;
8834 clock-names = "PCLK";
8835 sata = <&sata>;
8836 status = "disabled";
8837@@ -217,8 +336,8 @@ dma-controller@67000000 {
8838 arm,primecell-periphid = <0x0003b080>;
8839 reg = <0x67000000 0x1000>;
8840 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
8841- resets = <&syscon 10>;
8842- clocks = <&syscon 1>;
8843+ resets = <&syscon GEMINI_RESET_DMAC>;
8844+ clocks = <&syscon GEMINI_CLK_AHB>;
8845 clock-names = "apb_pclk";
8846 /* Bus interface AHB1 (AHB0) is totally tilted */
8847 lli-bus-interface-ahb2;
8848diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
8849index 0ade3619f3c3..09ce8b81fafa 100644
8850--- a/arch/arm/boot/dts/imx25.dtsi
8851+++ b/arch/arm/boot/dts/imx25.dtsi
8852@@ -452,6 +452,13 @@ scc: crypto@53fac000 {
8853 interrupt-names = "scm", "smn";
8854 };
8855
8856+ rngb: rngb@53fb0000 {
8857+ compatible = "fsl,imx25-rngb";
8858+ reg = <0x53fb0000 0x4000>;
8859+ clocks = <&clks 109>;
8860+ interrupts = <22>;
8861+ };
8862+
8863 esdhc1: esdhc@53fb4000 {
8864 compatible = "fsl,imx25-esdhc";
8865 reg = <0x53fb4000 0x4000>;
8866diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/imx53-cx9020.dts
8867new file mode 100644
8868index 000000000000..4f54fd4418a3
8869--- /dev/null
8870+++ b/arch/arm/boot/dts/imx53-cx9020.dts
8871@@ -0,0 +1,297 @@
8872+/*
8873+ * Copyright 2017 Beckhoff Automation GmbH & Co. KG
8874+ * based on imx53-qsb.dts
8875+ *
8876+ * The code contained herein is licensed under the GNU General Public
8877+ * License. You may obtain a copy of the GNU General Public License
8878+ * Version 2 or later at the following locations:
8879+ *
8880+ * http://www.opensource.org/licenses/gpl-license.html
8881+ * http://www.gnu.org/copyleft/gpl.html
8882+ */
8883+
8884+/dts-v1/;
8885+#include "imx53.dtsi"
8886+
8887+/ {
8888+ model = "Beckhoff CX9020 Embedded PC";
8889+ compatible = "bhf,cx9020", "fsl,imx53";
8890+
8891+ chosen {
8892+ stdout-path = &uart2;
8893+ };
8894+
8895+ memory {
8896+ reg = <0x70000000 0x20000000>,
8897+ <0xb0000000 0x20000000>;
8898+ };
8899+
8900+ display-0 {
8901+ #address-cells =<1>;
8902+ #size-cells = <0>;
8903+ compatible = "fsl,imx-parallel-display";
8904+ interface-pix-fmt = "rgb24";
8905+ pinctrl-names = "default";
8906+ pinctrl-0 = <&pinctrl_ipu_disp0>;
8907+
8908+ port@0 {
8909+ reg = <0>;
8910+
8911+ display0_in: endpoint {
8912+ remote-endpoint = <&ipu_di0_disp0>;
8913+ };
8914+ };
8915+
8916+ port@1 {
8917+ reg = <1>;
8918+
8919+ display0_out: endpoint {
8920+ remote-endpoint = <&tfp410_in>;
8921+ };
8922+ };
8923+ };
8924+
8925+ dvi-connector {
8926+ compatible = "dvi-connector";
8927+ ddc-i2c-bus = <&i2c2>;
8928+ digital;
8929+
8930+ port {
8931+ dvi_connector_in: endpoint {
8932+ remote-endpoint = <&tfp410_out>;
8933+ };
8934+ };
8935+ };
8936+
8937+ dvi-converter {
8938+ #address-cells = <1>;
8939+ #size-cells = <0>;
8940+ compatible = "ti,tfp410";
8941+
8942+ port@0 {
8943+ reg = <0>;
8944+
8945+ tfp410_in: endpoint {
8946+ remote-endpoint = <&display0_out>;
8947+ };
8948+ };
8949+
8950+ port@1 {
8951+ reg = <1>;
8952+
8953+ tfp410_out: endpoint {
8954+ remote-endpoint = <&dvi_connector_in>;
8955+ };
8956+ };
8957+ };
8958+
8959+ leds {
8960+ compatible = "gpio-leds";
8961+
8962+ pwr-r {
8963+ gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
8964+ default-state = "off";
8965+ };
8966+
8967+ pwr-g {
8968+ gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
8969+ default-state = "on";
8970+ };
8971+
8972+ pwr-b {
8973+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
8974+ default-state = "off";
8975+ };
8976+
8977+ sd1-b {
8978+ linux,default-trigger = "mmc0";
8979+ gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
8980+ };
8981+
8982+ sd2-b {
8983+ linux,default-trigger = "mmc1";
8984+ gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
8985+ };
8986+ };
8987+
8988+ regulator-3p2v {
8989+ compatible = "regulator-fixed";
8990+ regulator-name = "3P2V";
8991+ regulator-min-microvolt = <3200000>;
8992+ regulator-max-microvolt = <3200000>;
8993+ regulator-always-on;
8994+ };
8995+
8996+ reg_usb_vbus: regulator-vbus {
8997+ compatible = "regulator-fixed";
8998+ regulator-name = "usb_vbus";
8999+ regulator-min-microvolt = <5000000>;
9000+ regulator-max-microvolt = <5000000>;
9001+ gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
9002+ enable-active-high;
9003+ };
9004+};
9005+
9006+&esdhc1 {
9007+ pinctrl-names = "default";
9008+ pinctrl-0 = <&pinctrl_esdhc1>;
9009+ cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
9010+ bus-width = <4>;
9011+ status = "okay";
9012+};
9013+
9014+&esdhc2 {
9015+ pinctrl-names = "default";
9016+ pinctrl-0 = <&pinctrl_esdhc2>;
9017+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
9018+ bus-width = <4>;
9019+ status = "okay";
9020+};
9021+
9022+&fec {
9023+ pinctrl-names = "default";
9024+ pinctrl-0 = <&pinctrl_fec>;
9025+ phy-mode = "rmii";
9026+ phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
9027+ status = "okay";
9028+};
9029+
9030+&i2c2 {
9031+ pinctrl-names = "default";
9032+ pinctrl-0 = <&pinctrl_i2c2>;
9033+ status = "okay";
9034+};
9035+
9036+&ipu_di0_disp0 {
9037+ remote-endpoint = <&display0_in>;
9038+};
9039+
9040+&uart2 {
9041+ pinctrl-names = "default";
9042+ pinctrl-0 = <&pinctrl_uart2>;
9043+ fsl,dte-mode;
9044+ status = "okay";
9045+};
9046+
9047+&usbh1 {
9048+ vbus-supply = <&reg_usb_vbus>;
9049+ phy_type = "utmi";
9050+ status = "okay";
9051+};
9052+
9053+&usbotg {
9054+ dr_mode = "peripheral";
9055+ status = "okay";
9056+};
9057+
9058+&vpu {
9059+ status = "okay";
9060+};
9061+
9062+&iomuxc {
9063+ pinctrl-names = "default";
9064+ pinctrl-0 = <&pinctrl_hog>;
9065+
9066+ pinctrl_hog: hoggrp {
9067+ fsl,pins = <
9068+ MX53_PAD_GPIO_0__CCM_CLKO 0x1c4
9069+ MX53_PAD_GPIO_16__I2C3_SDA 0x1c4
9070+ MX53_PAD_EIM_D22__GPIO3_22 0x1c4
9071+ MX53_PAD_EIM_D23__GPIO3_23 0x1e4
9072+ MX53_PAD_EIM_D24__GPIO3_24 0x1e4
9073+ >;
9074+ };
9075+
9076+ pinctrl_esdhc1: esdhc1grp {
9077+ fsl,pins = <
9078+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
9079+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
9080+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
9081+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
9082+ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
9083+ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
9084+ MX53_PAD_GPIO_1__ESDHC1_CD 0x1c4
9085+ MX53_PAD_EIM_D17__GPIO3_17 0x1e4
9086+ MX53_PAD_GPIO_3__GPIO1_3 0x1c4
9087+ >;
9088+ };
9089+
9090+ pinctrl_esdhc2: esdhc2grp {
9091+ fsl,pins = <
9092+ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
9093+ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
9094+ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
9095+ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
9096+ MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
9097+ MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
9098+ MX53_PAD_GPIO_4__ESDHC2_CD 0x1e4
9099+ MX53_PAD_EIM_D20__GPIO3_20 0x1e4
9100+ MX53_PAD_GPIO_8__GPIO1_8 0x1c4
9101+ >;
9102+ };
9103+
9104+ pinctrl_fec: fecgrp {
9105+ fsl,pins = <
9106+ MX53_PAD_FEC_MDC__FEC_MDC 0x4
9107+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
9108+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
9109+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
9110+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
9111+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
9112+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
9113+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
9114+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
9115+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
9116+ >;
9117+ };
9118+
9119+ pinctrl_i2c2: i2c2grp {
9120+ fsl,pins = <
9121+ MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
9122+ MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
9123+ >;
9124+ };
9125+
9126+ pinctrl_ipu_disp0: ipudisp0grp {
9127+ fsl,pins = <
9128+ MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
9129+ MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
9130+ MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
9131+ MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
9132+ MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5
9133+ MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
9134+ MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
9135+ MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
9136+ MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
9137+ MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
9138+ MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
9139+ MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
9140+ MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
9141+ MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
9142+ MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
9143+ MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
9144+ MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
9145+ MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
9146+ MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
9147+ MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
9148+ MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
9149+ MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
9150+ MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
9151+ MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
9152+ MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
9153+ MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
9154+ MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
9155+ MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
9156+ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
9157+ >;
9158+ };
9159+
9160+ pinctrl_uart2: uart2grp {
9161+ fsl,pins = <
9162+ MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4
9163+ MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4
9164+ MX53_PAD_EIM_D28__UART2_RTS 0x1e4
9165+ MX53_PAD_EIM_D29__UART2_CTS 0x1e4
9166+ >;
9167+ };
9168+};
9169diff --git a/arch/arm/boot/dts/imx53-pinfunc.h b/arch/arm/boot/dts/imx53-pinfunc.h
9170index aec406bc65eb..59f9c29e3fe2 100644
9171--- a/arch/arm/boot/dts/imx53-pinfunc.h
9172+++ b/arch/arm/boot/dts/imx53-pinfunc.h
9173@@ -524,6 +524,7 @@
9174 #define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0
9175 #define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0
9176 #define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0
9177+#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0
9178 #define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0
9179 #define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0
9180 #define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0
9181@@ -533,6 +534,7 @@
9182 #define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0
9183 #define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0
9184 #define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1
9185+#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0
9186 #define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0
9187 #define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0
9188 #define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0
9189@@ -541,6 +543,7 @@
9190 #define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0
9191 #define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0
9192 #define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0
9193+#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0
9194 #define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1
9195 #define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1
9196 #define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1
9197@@ -548,6 +551,7 @@
9198 #define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0
9199 #define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0
9200 #define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0
9201+#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0
9202 #define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1
9203 #define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0
9204 #define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2
9205diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
9206index 2e516f4985e4..8bf0d89cdd35 100644
9207--- a/arch/arm/boot/dts/imx53.dtsi
9208+++ b/arch/arm/boot/dts/imx53.dtsi
9209@@ -433,6 +433,15 @@ gpt: timer@53fa0000 {
9210 clock-names = "ipg", "per";
9211 };
9212
9213+ srtc: srtc@53fa4000 {
9214+ compatible = "fsl,imx53-rtc", "fsl,imx25-rtc";
9215+ reg = <0x53fa4000 0x4000>;
9216+ interrupts = <24>;
9217+ interrupt-parent = <&tzic>;
9218+ clocks = <&clks IMX5_CLK_SRTC_GATE>;
9219+ clock-names = "ipg";
9220+ };
9221+
9222 iomuxc: iomuxc@53fa8000 {
9223 compatible = "fsl,imx53-iomuxc";
9224 reg = <0x53fa8000 0x4000>;
9225diff --git a/arch/arm/boot/dts/imx6dl-gw52xx.dts b/arch/arm/boot/dts/imx6dl-gw52xx.dts
9226index a2e0b73fdd4a..5f9f8948100d 100644
9227--- a/arch/arm/boot/dts/imx6dl-gw52xx.dts
9228+++ b/arch/arm/boot/dts/imx6dl-gw52xx.dts
9229@@ -17,3 +17,61 @@ / {
9230 model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX";
9231 compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl";
9232 };
9233+
9234+&i2c3 {
9235+ adv7180: camera@20 {
9236+ compatible = "adi,adv7180";
9237+ pinctrl-names = "default";
9238+ pinctrl-0 = <&pinctrl_adv7180>;
9239+ reg = <0x20>;
9240+ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
9241+ interrupt-parent = <&gpio3>;
9242+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
9243+
9244+ port {
9245+ adv7180_to_ipu1_csi1_mux: endpoint {
9246+ remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>;
9247+ bus-width = <8>;
9248+ };
9249+ };
9250+ };
9251+};
9252+
9253+&ipu1_csi1_from_ipu1_csi1_mux {
9254+ bus-width = <8>;
9255+};
9256+
9257+&ipu1_csi1_mux_from_parallel_sensor {
9258+ remote-endpoint = <&adv7180_to_ipu1_csi1_mux>;
9259+ bus-width = <8>;
9260+};
9261+
9262+&ipu1_csi1 {
9263+ pinctrl-names = "default";
9264+ pinctrl-0 = <&pinctrl_ipu1_csi1>;
9265+};
9266+
9267+&iomuxc {
9268+ pinctrl_adv7180: adv7180grp {
9269+ fsl,pins = <
9270+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
9271+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
9272+ >;
9273+ };
9274+
9275+ pinctrl_ipu1_csi1: ipu1_csi1grp {
9276+ fsl,pins = <
9277+ MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0
9278+ MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0
9279+ MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0
9280+ MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0
9281+ MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0
9282+ MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0
9283+ MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0
9284+ MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0
9285+ MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0
9286+ MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0
9287+ MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0
9288+ >;
9289+ };
9290+};
9291diff --git a/arch/arm/boot/dts/imx6dl-gw53xx.dts b/arch/arm/boot/dts/imx6dl-gw53xx.dts
9292index 6844b708d2f8..9bfc620d37bd 100644
9293--- a/arch/arm/boot/dts/imx6dl-gw53xx.dts
9294+++ b/arch/arm/boot/dts/imx6dl-gw53xx.dts
9295@@ -17,3 +17,61 @@ / {
9296 model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX";
9297 compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl";
9298 };
9299+
9300+&i2c3 {
9301+ adv7180: camera@20 {
9302+ compatible = "adi,adv7180";
9303+ pinctrl-names = "default";
9304+ pinctrl-0 = <&pinctrl_adv7180>;
9305+ reg = <0x20>;
9306+ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
9307+ interrupt-parent = <&gpio3>;
9308+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
9309+
9310+ port {
9311+ adv7180_to_ipu1_csi1_mux: endpoint {
9312+ remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>;
9313+ bus-width = <8>;
9314+ };
9315+ };
9316+ };
9317+};
9318+
9319+&ipu1_csi1_from_ipu1_csi1_mux {
9320+ bus-width = <8>;
9321+};
9322+
9323+&ipu1_csi1_mux_from_parallel_sensor {
9324+ remote-endpoint = <&adv7180_to_ipu1_csi1_mux>;
9325+ bus-width = <8>;
9326+};
9327+
9328+&ipu1_csi1 {
9329+ pinctrl-names = "default";
9330+ pinctrl-0 = <&pinctrl_ipu1_csi1>;
9331+};
9332+
9333+&iomuxc {
9334+ pinctrl_adv7180: adv7180grp {
9335+ fsl,pins = <
9336+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
9337+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
9338+ >;
9339+ };
9340+
9341+ pinctrl_ipu1_csi1: ipu1_csi1grp {
9342+ fsl,pins = <
9343+ MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0
9344+ MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0
9345+ MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0
9346+ MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0
9347+ MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0
9348+ MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0
9349+ MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0
9350+ MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0
9351+ MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0
9352+ MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0
9353+ MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0
9354+ >;
9355+ };
9356+};
9357diff --git a/arch/arm/boot/dts/imx6dl-gw54xx.dts b/arch/arm/boot/dts/imx6dl-gw54xx.dts
9358index be915412f852..b909bdf9a2ef 100644
9359--- a/arch/arm/boot/dts/imx6dl-gw54xx.dts
9360+++ b/arch/arm/boot/dts/imx6dl-gw54xx.dts
9361@@ -17,3 +17,61 @@ / {
9362 model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX";
9363 compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl";
9364 };
9365+
9366+&i2c3 {
9367+ adv7180: camera@20 {
9368+ compatible = "adi,adv7180";
9369+ pinctrl-names = "default";
9370+ pinctrl-0 = <&pinctrl_adv7180>;
9371+ reg = <0x20>;
9372+ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
9373+ interrupt-parent = <&gpio3>;
9374+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
9375+
9376+ port {
9377+ adv7180_to_ipu1_csi1_mux: endpoint {
9378+ remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>;
9379+ bus-width = <8>;
9380+ };
9381+ };
9382+ };
9383+};
9384+
9385+&ipu1_csi1_from_ipu1_csi1_mux {
9386+ bus-width = <8>;
9387+};
9388+
9389+&ipu1_csi1_mux_from_parallel_sensor {
9390+ remote-endpoint = <&adv7180_to_ipu1_csi1_mux>;
9391+ bus-width = <8>;
9392+};
9393+
9394+&ipu1_csi1 {
9395+ pinctrl-names = "default";
9396+ pinctrl-0 = <&pinctrl_ipu1_csi1>;
9397+};
9398+
9399+&iomuxc {
9400+ pinctrl_adv7180: adv7180grp {
9401+ fsl,pins = <
9402+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
9403+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
9404+ >;
9405+ };
9406+
9407+ pinctrl_ipu1_csi1: ipu1_csi1grp {
9408+ fsl,pins = <
9409+ MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0
9410+ MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0
9411+ MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0
9412+ MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0
9413+ MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0
9414+ MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0
9415+ MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0
9416+ MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0
9417+ MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0
9418+ MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0
9419+ MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0
9420+ >;
9421+ };
9422+};
9423diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
9424index 29b45f2e64e0..275c6c05219d 100644
9425--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
9426+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
9427@@ -101,6 +101,51 @@ &fec {
9428 status = "okay";
9429 };
9430
9431+&gpio1 {
9432+ gpio-line-names =
9433+ "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL",
9434+ "I2C3_SDA", "I2C4_SCL",
9435+ "I2C4_SDA", "", "", "", "", "", "", "",
9436+ "", "PWM3", "", "", "", "", "", "",
9437+ "", "", "", "", "", "", "", "";
9438+};
9439+
9440+&gpio3 {
9441+ gpio-line-names =
9442+ "", "", "", "", "", "", "", "",
9443+ "", "", "", "", "", "", "", "",
9444+ "", "", "", "", "", "", "USB_OTG_VBUS", "",
9445+ "UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", "";
9446+};
9447+
9448+&gpio4 {
9449+ gpio-line-names =
9450+ "", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
9451+ "UART5_TXD", "UART5_RXD", "", "", "", "", "", "",
9452+ "GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "",
9453+ "CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO",
9454+ "CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27",
9455+ "CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31";
9456+};
9457+
9458+&gpio5 {
9459+ gpio-line-names =
9460+ "", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06",
9461+ "GPIO5_07",
9462+ "GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO",
9463+ "CSPI2_CS0", "CSPI2_CLK", "", "",
9464+ "", "", "", "", "", "", "", "",
9465+ "", "", "", "", "", "", "", "";
9466+};
9467+
9468+&gpio7 {
9469+ gpio-line-names =
9470+ "SD3_CD", "SD3_WP", "", "", "", "", "", "",
9471+ "", "", "", "", "", "", "", "",
9472+ "", "", "", "", "", "", "", "",
9473+ "", "", "", "", "", "", "", "";
9474+};
9475+
9476 &hdmi {
9477 ddc-i2c-bus = <&i2c2>;
9478 status = "okay";
9479diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts
9480new file mode 100644
9481index 000000000000..4bbfe3d61027
9482--- /dev/null
9483+++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts
9484@@ -0,0 +1,278 @@
9485+/*
9486+ * Copyright 2014-2017 Toradex AG
9487+ * Copyright 2012 Freescale Semiconductor, Inc.
9488+ * Copyright 2011 Linaro Ltd.
9489+ *
9490+ * This file is dual-licensed: you can use it either under the terms
9491+ * of the GPL or the X11 license, at your option. Note that this dual
9492+ * licensing only applies to this file, and not this project as a
9493+ * whole.
9494+ *
9495+ * a) This file is free software; you can redistribute it and/or
9496+ * modify it under the terms of the GNU General Public License
9497+ * version 2 as published by the Free Software Foundation.
9498+ *
9499+ * This file is distributed in the hope that it will be useful,
9500+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
9501+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9502+ * GNU General Public License for more details.
9503+ *
9504+ * Or, alternatively,
9505+ *
9506+ * b) Permission is hereby granted, free of charge, to any person
9507+ * obtaining a copy of this software and associated documentation
9508+ * files (the "Software"), to deal in the Software without
9509+ * restriction, including without limitation the rights to use,
9510+ * copy, modify, merge, publish, distribute, sublicense, and/or
9511+ * sell copies of the Software, and to permit persons to whom the
9512+ * Software is furnished to do so, subject to the following
9513+ * conditions:
9514+ *
9515+ * The above copyright notice and this permission notice shall be
9516+ * included in all copies or substantial portions of the Software.
9517+ *
9518+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
9519+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
9520+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
9521+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
9522+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
9523+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
9524+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
9525+ * OTHER DEALINGS IN THE SOFTWARE.
9526+ */
9527+
9528+/dts-v1/;
9529+
9530+#include <dt-bindings/gpio/gpio.h>
9531+#include <dt-bindings/input/input.h>
9532+#include <dt-bindings/interrupt-controller/irq.h>
9533+#include "imx6q.dtsi"
9534+#include "imx6qdl-apalis.dtsi"
9535+
9536+/ {
9537+ model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board";
9538+ compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q",
9539+ "fsl,imx6q";
9540+
9541+ aliases {
9542+ i2c0 = &i2c1;
9543+ i2c1 = &i2c3;
9544+ i2c2 = &i2c2;
9545+ rtc0 = &rtc_i2c;
9546+ rtc1 = &snvs_rtc;
9547+ };
9548+
9549+ gpio-keys {
9550+ compatible = "gpio-keys";
9551+ pinctrl-names = "default";
9552+ pinctrl-0 = <&pinctrl_gpio_keys>;
9553+
9554+ wakeup {
9555+ label = "Wake-Up";
9556+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
9557+ linux,code = <KEY_WAKEUP>;
9558+ debounce-interval = <10>;
9559+ wakeup-source;
9560+ };
9561+ };
9562+
9563+ lcd_display: display@di0 {
9564+ compatible = "fsl,imx-parallel-display";
9565+ #address-cells = <1>;
9566+ #size-cells = <0>;
9567+ interface-pix-fmt = "rgb24";
9568+ pinctrl-names = "default";
9569+ pinctrl-0 = <&pinctrl_ipu1_lcdif>;
9570+ status = "okay";
9571+
9572+ port@0 {
9573+ reg = <0>;
9574+
9575+ lcd_display_in: endpoint {
9576+ remote-endpoint = <&ipu1_di1_disp1>;
9577+ };
9578+ };
9579+
9580+ port@1 {
9581+ reg = <1>;
9582+
9583+ lcd_display_out: endpoint {
9584+ remote-endpoint = <&lcd_panel_in>;
9585+ };
9586+ };
9587+ };
9588+
9589+ panel: panel {
9590+ /*
9591+ * edt,et057090dhu: EDT 5.7" LCD TFT
9592+ * edt,et070080dh6: EDT 7.0" LCD TFT
9593+ */
9594+ compatible = "edt,et057090dhu";
9595+ backlight = <&backlight>;
9596+
9597+ port {
9598+ lcd_panel_in: endpoint {
9599+ remote-endpoint = <&lcd_display_out>;
9600+ };
9601+ };
9602+ };
9603+
9604+ reg_pcie_switch: regulator-pcie-switch {
9605+ compatible = "regulator-fixed";
9606+ regulator-name = "pcie_switch";
9607+ regulator-min-microvolt = <1800000>;
9608+ regulator-max-microvolt = <1800000>;
9609+ gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
9610+ startup-delay-us = <100000>;
9611+ enable-active-high;
9612+ status = "okay";
9613+ };
9614+};
9615+
9616+&backlight {
9617+ brightness-levels = <0 127 191 223 239 247 251 255>;
9618+ default-brightness-level = <1>;
9619+ status = "okay";
9620+};
9621+
9622+&can1 {
9623+ status = "okay";
9624+};
9625+
9626+&can2 {
9627+ status = "okay";
9628+};
9629+
9630+&hdmi {
9631+ status = "okay";
9632+};
9633+
9634+/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
9635+&i2c1 {
9636+ status = "okay";
9637+
9638+ pcie-switch@58 {
9639+ compatible = "plx,pex8605";
9640+ reg = <0x58>;
9641+ };
9642+
9643+ /* M41T0M6 real time clock on carrier board */
9644+ rtc_i2c: rtc@68 {
9645+ compatible = "st,m41t00";
9646+ reg = <0x68>;
9647+ };
9648+};
9649+
9650+/*
9651+ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
9652+ * board)
9653+ */
9654+&i2c3 {
9655+ status = "okay";
9656+};
9657+
9658+&ipu1_di1_disp1 {
9659+ remote-endpoint = <&lcd_display_in>;
9660+};
9661+
9662+&ldb {
9663+ status = "okay";
9664+};
9665+
9666+&pcie {
9667+ /* active-high meaning opposite of regular PERST# active-low polarity */
9668+ reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
9669+ reset-gpio-active-high;
9670+ vpcie-supply = <&reg_pcie_switch>;
9671+ status = "okay";
9672+};
9673+
9674+&pwm1 {
9675+ status = "okay";
9676+};
9677+
9678+&pwm2 {
9679+ status = "okay";
9680+};
9681+
9682+&pwm3 {
9683+ status = "okay";
9684+};
9685+
9686+&pwm4 {
9687+ status = "okay";
9688+};
9689+
9690+&reg_usb_otg_vbus {
9691+ status = "okay";
9692+};
9693+
9694+&reg_usb_host_vbus {
9695+ status = "okay";
9696+};
9697+
9698+&sata {
9699+ status = "okay";
9700+};
9701+
9702+&sound_spdif {
9703+ status = "okay";
9704+};
9705+
9706+&spdif {
9707+ status = "okay";
9708+};
9709+
9710+&uart1 {
9711+ status = "okay";
9712+};
9713+
9714+&uart2 {
9715+ status = "okay";
9716+};
9717+
9718+&uart4 {
9719+ status = "okay";
9720+};
9721+
9722+&uart5 {
9723+ status = "okay";
9724+};
9725+
9726+&usbh1 {
9727+ vbus-supply = <&reg_usb_host_vbus>;
9728+ status = "okay";
9729+};
9730+
9731+&usbotg {
9732+ vbus-supply = <&reg_usb_otg_vbus>;
9733+ status = "okay";
9734+};
9735+
9736+/* MMC1 */
9737+&usdhc1 {
9738+ pinctrl-names = "default";
9739+ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
9740+ cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
9741+ status = "okay";
9742+};
9743+
9744+/* SD1 */
9745+&usdhc2 {
9746+ pinctrl-names = "default";
9747+ pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
9748+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
9749+ status = "okay";
9750+};
9751+
9752+&iomuxc {
9753+ /*
9754+ * Mux the Apalis GPIOs
9755+ */
9756+ pinctrl-names = "default";
9757+ pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
9758+ &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
9759+ &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
9760+ &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
9761+ >;
9762+};
9763diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
9764new file mode 100644
9765index 000000000000..a35c7a54ad3b
9766--- /dev/null
9767+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
9768@@ -0,0 +1,291 @@
9769+/*
9770+ * Copyright 2014-2017 Toradex AG
9771+ * Copyright 2012 Freescale Semiconductor, Inc.
9772+ * Copyright 2011 Linaro Ltd.
9773+ *
9774+ * This file is dual-licensed: you can use it either under the terms
9775+ * of the GPL or the X11 license, at your option. Note that this dual
9776+ * licensing only applies to this file, and not this project as a
9777+ * whole.
9778+ *
9779+ * a) This file is free software; you can redistribute it and/or
9780+ * modify it under the terms of the GNU General Public License
9781+ * version 2 as published by the Free Software Foundation.
9782+ *
9783+ * This file is distributed in the hope that it will be useful,
9784+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
9785+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9786+ * GNU General Public License for more details.
9787+ *
9788+ * Or, alternatively,
9789+ *
9790+ * b) Permission is hereby granted, free of charge, to any person
9791+ * obtaining a copy of this software and associated documentation
9792+ * files (the "Software"), to deal in the Software without
9793+ * restriction, including without limitation the rights to use,
9794+ * copy, modify, merge, publish, distribute, sublicense, and/or
9795+ * sell copies of the Software, and to permit persons to whom the
9796+ * Software is furnished to do so, subject to the following
9797+ * conditions:
9798+ *
9799+ * The above copyright notice and this permission notice shall be
9800+ * included in all copies or substantial portions of the Software.
9801+ *
9802+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
9803+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
9804+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
9805+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
9806+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
9807+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
9808+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
9809+ * OTHER DEALINGS IN THE SOFTWARE.
9810+ */
9811+
9812+/dts-v1/;
9813+
9814+#include <dt-bindings/gpio/gpio.h>
9815+#include <dt-bindings/input/input.h>
9816+#include <dt-bindings/interrupt-controller/irq.h>
9817+#include "imx6q.dtsi"
9818+#include "imx6qdl-apalis.dtsi"
9819+
9820+/ {
9821+ model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1";
9822+ compatible = "toradex,apalis_imx6q-ixora-v1.1",
9823+ "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q",
9824+ "fsl,imx6q";
9825+
9826+ aliases {
9827+ i2c0 = &i2c1;
9828+ i2c1 = &i2c3;
9829+ i2c2 = &i2c2;
9830+ rtc0 = &rtc_i2c;
9831+ rtc1 = &snvs_rtc;
9832+ };
9833+
9834+ gpio-keys {
9835+ compatible = "gpio-keys";
9836+ pinctrl-names = "default";
9837+ pinctrl-0 = <&pinctrl_gpio_keys>;
9838+
9839+ wakeup {
9840+ label = "Wake-Up";
9841+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
9842+ linux,code = <KEY_WAKEUP>;
9843+ debounce-interval = <10>;
9844+ wakeup-source;
9845+ };
9846+ };
9847+
9848+ lcd_display: display@di0 {
9849+ compatible = "fsl,imx-parallel-display";
9850+ #address-cells = <1>;
9851+ #size-cells = <0>;
9852+ interface-pix-fmt = "rgb24";
9853+ pinctrl-names = "default";
9854+ pinctrl-0 = <&pinctrl_ipu1_lcdif>;
9855+ status = "okay";
9856+
9857+ port@0 {
9858+ reg = <0>;
9859+
9860+ lcd_display_in: endpoint {
9861+ remote-endpoint = <&ipu1_di1_disp1>;
9862+ };
9863+ };
9864+
9865+ port@1 {
9866+ reg = <1>;
9867+
9868+ lcd_display_out: endpoint {
9869+ remote-endpoint = <&lcd_panel_in>;
9870+ };
9871+ };
9872+ };
9873+
9874+ panel: panel {
9875+ /*
9876+ * edt,et057090dhu: EDT 5.7" LCD TFT
9877+ * edt,et070080dh6: EDT 7.0" LCD TFT
9878+ */
9879+ compatible = "edt,et057090dhu";
9880+ backlight = <&backlight>;
9881+
9882+ port {
9883+ lcd_panel_in: endpoint {
9884+ remote-endpoint = <&lcd_display_out>;
9885+ };
9886+ };
9887+ };
9888+
9889+ leds {
9890+ compatible = "gpio-leds";
9891+
9892+ pinctrl-names = "default";
9893+ pinctrl-0 = <&pinctrl_leds_ixora>;
9894+
9895+ led4-green {
9896+ label = "LED_4_GREEN";
9897+ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
9898+ };
9899+
9900+ led4-red {
9901+ label = "LED_4_RED";
9902+ gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
9903+ };
9904+
9905+ led5-green {
9906+ label = "LED_5_GREEN";
9907+ gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
9908+ };
9909+
9910+ led5-red {
9911+ label = "LED_5_RED";
9912+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
9913+ };
9914+ };
9915+};
9916+
9917+&backlight {
9918+ brightness-levels = <0 127 191 223 239 247 251 255>;
9919+ default-brightness-level = <1>;
9920+ status = "okay";
9921+};
9922+
9923+&can1 {
9924+ status = "okay";
9925+};
9926+
9927+&can2 {
9928+ status = "okay";
9929+};
9930+
9931+&hdmi {
9932+ status = "okay";
9933+};
9934+
9935+/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
9936+&i2c1 {
9937+ status = "okay";
9938+
9939+ /* M41T0M6 real time clock on carrier board */
9940+ rtc_i2c: rtc@68 {
9941+ compatible = "st,m41t00";
9942+ reg = <0x68>;
9943+ };
9944+};
9945+
9946+/*
9947+ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
9948+ * board)
9949+ */
9950+&i2c3 {
9951+ status = "okay";
9952+};
9953+
9954+&ipu1_di1_disp1 {
9955+ remote-endpoint = <&lcd_display_in>;
9956+};
9957+
9958+&ldb {
9959+ status = "okay";
9960+};
9961+
9962+&pcie {
9963+ /* active-high meaning opposite of regular PERST# active-low polarity */
9964+ reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
9965+ reset-gpio-active-high;
9966+ status = "okay";
9967+};
9968+
9969+&pwm1 {
9970+ status = "okay";
9971+};
9972+
9973+&pwm2 {
9974+ status = "okay";
9975+};
9976+
9977+&pwm3 {
9978+ status = "okay";
9979+};
9980+
9981+&pwm4 {
9982+ status = "okay";
9983+};
9984+
9985+&reg_usb_otg_vbus {
9986+ status = "okay";
9987+};
9988+
9989+&reg_usb_host_vbus {
9990+ status = "okay";
9991+};
9992+
9993+&sata {
9994+ status = "okay";
9995+};
9996+
9997+&sound_spdif {
9998+ status = "okay";
9999+};
10000+
10001+&spdif {
10002+ status = "okay";
10003+};
10004+
10005+&uart1 {
10006+ status = "okay";
10007+};
10008+
10009+&uart2 {
10010+ status = "okay";
10011+};
10012+
10013+&uart4 {
10014+ status = "okay";
10015+};
10016+
10017+&uart5 {
10018+ status = "okay";
10019+};
10020+
10021+&usbh1 {
10022+ vbus-supply = <&reg_usb_host_vbus>;
10023+ status = "okay";
10024+};
10025+
10026+&usbotg {
10027+ vbus-supply = <&reg_usb_otg_vbus>;
10028+ status = "okay";
10029+};
10030+
10031+/* MMC1 */
10032+&usdhc1 {
10033+ pinctrl-names = "default";
10034+ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>;
10035+ cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
10036+ bus-width = <4>;
10037+ status = "okay";
10038+};
10039+
10040+&iomuxc {
10041+ /*
10042+ * Mux the Apalis GPIOs
10043+ */
10044+ pinctrl-names = "default";
10045+ pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
10046+ &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
10047+ &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
10048+ &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
10049+ >;
10050+
10051+ pinctrl_leds_ixora: ledsixoragrp {
10052+ fsl,pins = <
10053+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
10054+ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
10055+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
10056+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
10057+ >;
10058+ };
10059+};
10060diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
10061index 88cc7f51a4e9..60d33e99de76 100644
10062--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
10063+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
10064@@ -1,5 +1,5 @@
10065 /*
10066- * Copyright 2014-2016 Toradex AG
10067+ * Copyright 2014-2017 Toradex AG
10068 * Copyright 2012 Freescale Semiconductor, Inc.
10069 * Copyright 2011 Linaro Ltd.
10070 *
10071@@ -55,13 +55,9 @@ / {
10072 "fsl,imx6q";
10073
10074 aliases {
10075- i2c0 = &i2cddc;
10076- i2c1 = &i2c1;
10077+ i2c0 = &i2c1;
10078+ i2c1 = &i2c3;
10079 i2c2 = &i2c2;
10080- i2c3 = &i2c3;
10081- };
10082-
10083- aliases {
10084 rtc0 = &rtc_i2c;
10085 rtc1 = &snvs_rtc;
10086 };
10087@@ -164,15 +160,10 @@ &can2 {
10088 };
10089
10090 &hdmi {
10091- ddc-i2c-bus = <&i2cddc>;
10092- status = "okay";
10093-};
10094-
10095-&i2cddc {
10096 status = "okay";
10097 };
10098
10099-/* GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
10100+/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
10101 &i2c1 {
10102 status = "okay";
10103
10104@@ -188,6 +179,14 @@ rtc_i2c: rtc@68 {
10105 };
10106 };
10107
10108+/*
10109+ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
10110+ * board)
10111+ */
10112+&i2c3 {
10113+ status = "okay";
10114+};
10115+
10116 &ipu1_di1_disp1 {
10117 remote-endpoint = <&lcd_display_in>;
10118 };
10119@@ -268,16 +267,13 @@ &usbotg {
10120 /* SD1 */
10121 &usdhc2 {
10122 pinctrl-names = "default";
10123- pinctrl-0 = <&pinctrl_sd_cd>;
10124+ pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
10125 cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
10126 status = "okay";
10127 };
10128
10129 &iomuxc {
10130- /*
10131- * Mux the Apalis GPIOs
10132- * GPIO5, 6 used by optional fusion_F0710A kernel module
10133- */
10134+ /* Mux the Apalis GPIOs */
10135 pinctrl-names = "default";
10136 pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
10137 &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
10138diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts
10139index 2c1e98e0cf7b..46bdc6722715 100644
10140--- a/arch/arm/boot/dts/imx6q-b850v3.dts
10141+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
10142@@ -57,7 +57,7 @@ &clks {
10143 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
10144 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
10145 <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
10146- <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>;
10147+ <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
10148 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
10149 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
10150 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
10151diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
10152index c90b26f00e24..1015e55ca8f7 100644
10153--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
10154+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
10155@@ -111,6 +111,11 @@ m25_eeprom: m25p80@0 {
10156 };
10157
10158 &i2c1 {
10159+ pinctrl-names = "default", "gpio";
10160+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
10161+ sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
10162+ scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
10163+
10164 pca9547: mux@70 {
10165 compatible = "nxp,pca9547";
10166 reg = <0x70>;
10167@@ -261,6 +266,43 @@ mux1_i2c8: i2c@7 {
10168 };
10169 };
10170
10171+&i2c2 {
10172+ pinctrl-names = "default", "gpio";
10173+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
10174+ sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
10175+ scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
10176+};
10177+
10178+&i2c3 {
10179+ pinctrl-names = "default", "gpio";
10180+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
10181+ sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
10182+ scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
10183+};
10184+
10185+&iomuxc {
10186+ pinctrl_i2c1_gpio: i2c1gpiogrp {
10187+ fsl,pins = <
10188+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0
10189+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0
10190+ >;
10191+ };
10192+
10193+ pinctrl_i2c2_gpio: i2c2gpiogrp {
10194+ fsl,pins = <
10195+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
10196+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0
10197+ >;
10198+ };
10199+
10200+ pinctrl_i2c3_gpio: i2c3gpiogrp {
10201+ fsl,pins = <
10202+ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0
10203+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
10204+ >;
10205+ };
10206+};
10207+
10208 &usdhc4 {
10209 pinctrl-names = "default";
10210 pinctrl-0 = <&pinctrl_usdhc4>;
10211diff --git a/arch/arm/boot/dts/imx6q-gw52xx.dts b/arch/arm/boot/dts/imx6q-gw52xx.dts
10212index a12c47e5ee05..0b8ae007ad73 100644
10213--- a/arch/arm/boot/dts/imx6q-gw52xx.dts
10214+++ b/arch/arm/boot/dts/imx6q-gw52xx.dts
10215@@ -18,6 +18,64 @@ / {
10216 compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q";
10217 };
10218
10219+&i2c3 {
10220+ adv7180: camera@20 {
10221+ compatible = "adi,adv7180";
10222+ pinctrl-names = "default";
10223+ pinctrl-0 = <&pinctrl_adv7180>;
10224+ reg = <0x20>;
10225+ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
10226+ interrupt-parent = <&gpio3>;
10227+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
10228+
10229+ port {
10230+ adv7180_to_ipu2_csi1_mux: endpoint {
10231+ remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
10232+ bus-width = <8>;
10233+ };
10234+ };
10235+ };
10236+};
10237+
10238+&ipu2_csi1_from_ipu2_csi1_mux {
10239+ bus-width = <8>;
10240+};
10241+
10242+&ipu2_csi1_mux_from_parallel_sensor {
10243+ remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
10244+ bus-width = <8>;
10245+};
10246+
10247+&ipu2_csi1 {
10248+ pinctrl-names = "default";
10249+ pinctrl-0 = <&pinctrl_ipu2_csi1>;
10250+};
10251+
10252+&iomuxc {
10253+ pinctrl_adv7180: adv7180grp {
10254+ fsl,pins = <
10255+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
10256+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
10257+ >;
10258+ };
10259+
10260+ pinctrl_ipu2_csi1: ipu2_csi1grp {
10261+ fsl,pins = <
10262+ MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
10263+ MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0
10264+ MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0
10265+ MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0
10266+ MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0
10267+ MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0
10268+ MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0
10269+ MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0
10270+ MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0
10271+ MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
10272+ MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
10273+ >;
10274+ };
10275+};
10276+
10277 &sata {
10278 status = "okay";
10279 };
10280diff --git a/arch/arm/boot/dts/imx6q-gw53xx.dts b/arch/arm/boot/dts/imx6q-gw53xx.dts
10281index d76aaa83dad0..a56ef77eff3f 100644
10282--- a/arch/arm/boot/dts/imx6q-gw53xx.dts
10283+++ b/arch/arm/boot/dts/imx6q-gw53xx.dts
10284@@ -18,6 +18,64 @@ / {
10285 compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q";
10286 };
10287
10288+&i2c3 {
10289+ adv7180: camera@20 {
10290+ compatible = "adi,adv7180";
10291+ pinctrl-names = "default";
10292+ pinctrl-0 = <&pinctrl_adv7180>;
10293+ reg = <0x20>;
10294+ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
10295+ interrupt-parent = <&gpio3>;
10296+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
10297+
10298+ port {
10299+ adv7180_to_ipu2_csi1_mux: endpoint {
10300+ remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
10301+ bus-width = <8>;
10302+ };
10303+ };
10304+ };
10305+};
10306+
10307+&ipu2_csi1_from_ipu2_csi1_mux {
10308+ bus-width = <8>;
10309+};
10310+
10311+&ipu2_csi1_mux_from_parallel_sensor {
10312+ remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
10313+ bus-width = <8>;
10314+};
10315+
10316+&ipu2_csi1 {
10317+ pinctrl-names = "default";
10318+ pinctrl-0 = <&pinctrl_ipu2_csi1>;
10319+};
10320+
10321 &sata {
10322 status = "okay";
10323 };
10324+
10325+&iomuxc {
10326+ pinctrl_adv7180: adv7180grp {
10327+ fsl,pins = <
10328+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
10329+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
10330+ >;
10331+ };
10332+
10333+ pinctrl_ipu2_csi1: ipu2_csi1grp {
10334+ fsl,pins = <
10335+ MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
10336+ MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0
10337+ MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0
10338+ MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0
10339+ MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0
10340+ MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0
10341+ MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0
10342+ MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0
10343+ MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0
10344+ MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
10345+ MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
10346+ >;
10347+ };
10348+};
10349diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/imx6q-gw54xx.dts
10350index 6e8f53e92a2d..56e5b5050fcf 100644
10351--- a/arch/arm/boot/dts/imx6q-gw54xx.dts
10352+++ b/arch/arm/boot/dts/imx6q-gw54xx.dts
10353@@ -18,6 +18,64 @@ / {
10354 compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
10355 };
10356
10357+&i2c3 {
10358+ adv7180: camera@20 {
10359+ compatible = "adi,adv7180";
10360+ pinctrl-names = "default";
10361+ pinctrl-0 = <&pinctrl_adv7180>;
10362+ reg = <0x20>;
10363+ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
10364+ interrupt-parent = <&gpio3>;
10365+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
10366+
10367+ port {
10368+ adv7180_to_ipu2_csi1_mux: endpoint {
10369+ remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
10370+ bus-width = <8>;
10371+ };
10372+ };
10373+ };
10374+};
10375+
10376+&ipu2_csi1_from_ipu2_csi1_mux {
10377+ bus-width = <8>;
10378+};
10379+
10380+&ipu2_csi1_mux_from_parallel_sensor {
10381+ remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
10382+ bus-width = <8>;
10383+};
10384+
10385+&ipu2_csi1 {
10386+ pinctrl-names = "default";
10387+ pinctrl-0 = <&pinctrl_ipu2_csi1>;
10388+};
10389+
10390 &sata {
10391 status = "okay";
10392 };
10393+
10394+&iomuxc {
10395+ pinctrl_adv7180: adv7180grp {
10396+ fsl,pins = <
10397+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
10398+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
10399+ >;
10400+ };
10401+
10402+ pinctrl_ipu2_csi1: ipu2_csi1grp {
10403+ fsl,pins = <
10404+ MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
10405+ MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0
10406+ MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0
10407+ MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0
10408+ MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0
10409+ MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0
10410+ MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0
10411+ MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0
10412+ MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0
10413+ MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
10414+ MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
10415+ >;
10416+ };
10417+};
10418diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
10419index ba01dd76d887..ea339fa58f4a 100644
10420--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
10421+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
10422@@ -1,5 +1,5 @@
10423 /*
10424- * Copyright 2014-2016 Toradex AG
10425+ * Copyright 2014-2017 Toradex AG
10426 * Copyright 2012 Freescale Semiconductor, Inc.
10427 * Copyright 2011 Linaro Ltd.
10428 *
10429@@ -56,18 +56,6 @@ backlight: backlight {
10430 status = "disabled";
10431 };
10432
10433- /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */
10434- i2cddc: i2c@0 {
10435- compatible = "i2c-gpio";
10436- pinctrl-names = "default";
10437- pinctrl-0 = <&pinctrl_i2c_ddc>;
10438- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */
10439- &gpio2 30 GPIO_ACTIVE_HIGH /* scl */
10440- >;
10441- i2c-gpio,delay-us = <2>; /* ~100 kHz */
10442- status = "disabled";
10443- };
10444-
10445 reg_1p8v: regulator-1p8v {
10446 compatible = "regulator-fixed";
10447 regulator-name = "1P8V";
10448@@ -210,10 +198,13 @@ ethphy: ethernet-phy@7 {
10449 };
10450 };
10451
10452-/*
10453- * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
10454- * board)
10455- */
10456+&hdmi {
10457+ pinctrl-names = "default";
10458+ pinctrl-0 = <&pinctrl_hdmi_ddc>;
10459+ status = "disabled";
10460+};
10461+
10462+/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
10463 &i2c1 {
10464 clock-frequency = <100000>;
10465 pinctrl-names = "default";
10466@@ -374,7 +365,8 @@ stmpe_touchscreen {
10467 };
10468
10469 /*
10470- * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused)
10471+ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
10472+ * board)
10473 */
10474 &i2c3 {
10475 clock-frequency = <100000>;
10476@@ -460,7 +452,7 @@ &usbotg {
10477 /* MMC1 */
10478 &usdhc1 {
10479 pinctrl-names = "default";
10480- pinctrl-0 = <&pinctrl_usdhc1>;
10481+ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>;
10482 vqmmc-supply = <&reg_3p3v>;
10483 bus-width = <8>;
10484 voltage-ranges = <3300 3300>;
10485@@ -640,11 +632,10 @@ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
10486 >;
10487 };
10488
10489- pinctrl_i2c_ddc: gpioi2cddcgrp {
10490+ pinctrl_hdmi_ddc: hdmiddcgrp {
10491 fsl,pins = <
10492- /* DDC bitbang */
10493- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
10494- MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0
10495+ MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
10496+ MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
10497 >;
10498 };
10499
10500@@ -912,7 +903,7 @@ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
10501 >;
10502 };
10503
10504- pinctrl_usdhc1: usdhc1grp {
10505+ pinctrl_usdhc1_4bit: usdhc1grp_4bit {
10506 fsl,pins = <
10507 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
10508 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
10509@@ -920,6 +911,11 @@ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
10510 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
10511 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
10512 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
10513+ >;
10514+ };
10515+
10516+ pinctrl_usdhc1_8bit: usdhc1grp_8bit {
10517+ fsl,pins = <
10518 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
10519 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
10520 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
10521diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
10522index e8c1edc82e6e..885556260bd0 100644
10523--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
10524+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
10525@@ -231,6 +231,37 @@ &i2c3 {
10526 pinctrl-names = "default";
10527 pinctrl-0 = <&pinctrl_i2c3>;
10528 status = "okay";
10529+
10530+ adv7180: camera@20 {
10531+ compatible = "adi,adv7180";
10532+ pinctrl-names = "default";
10533+ pinctrl-0 = <&pinctrl_adv7180>;
10534+ reg = <0x20>;
10535+ powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
10536+ interrupt-parent = <&gpio5>;
10537+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
10538+
10539+ port {
10540+ adv7180_to_ipu1_csi0_mux: endpoint {
10541+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
10542+ bus-width = <8>;
10543+ };
10544+ };
10545+ };
10546+};
10547+
10548+&ipu1_csi0_from_ipu1_csi0_mux {
10549+ bus-width = <8>;
10550+};
10551+
10552+&ipu1_csi0_mux_from_parallel_sensor {
10553+ remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
10554+ bus-width = <8>;
10555+};
10556+
10557+&ipu1_csi0 {
10558+ pinctrl-names = "default";
10559+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
10560 };
10561
10562 &pcie {
10563@@ -302,6 +333,13 @@ &wdog1 {
10564
10565 &iomuxc {
10566 imx6qdl-gw51xx {
10567+ pinctrl_adv7180: adv7180grp {
10568+ fsl,pins = <
10569+ MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
10570+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
10571+ >;
10572+ };
10573+
10574 pinctrl_enet: enetgrp {
10575 fsl,pins = <
10576 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
10577@@ -372,6 +410,22 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
10578 >;
10579 };
10580
10581+ pinctrl_ipu1_csi0: ipu1csi0grp {
10582+ fsl,pins = <
10583+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
10584+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
10585+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
10586+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
10587+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
10588+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
10589+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
10590+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
10591+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
10592+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
10593+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
10594+ >;
10595+ };
10596+
10597 pinctrl_pcie: pciegrp {
10598 fsl,pins = <
10599 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
10600diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
10601index 91991d63a69c..115d706228ef 100644
10602--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
10603+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
10604@@ -377,7 +377,6 @@ &ssi1 {
10605 &uart1 {
10606 pinctrl-names = "default";
10607 pinctrl-0 = <&pinctrl_uart1>;
10608- uart-has-rtscts;
10609 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
10610 status = "okay";
10611 };
10612diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
10613index 5bc6ed1a5b35..24be7965056c 100644
10614--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
10615+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
10616@@ -368,7 +368,6 @@ &ssi1 {
10617 &uart1 {
10618 pinctrl-names = "default";
10619 pinctrl-0 = <&pinctrl_uart1>;
10620- uart-has-rtscts;
10621 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
10622 status = "okay";
10623 };
10624diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
10625index 66fcf838e964..4594b2279169 100644
10626--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
10627+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
10628@@ -416,7 +416,6 @@ &ssi2 {
10629 &uart1 {
10630 pinctrl-names = "default";
10631 pinctrl-0 = <&pinctrl_uart1>;
10632- uart-has-rtscts;
10633 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
10634 status = "okay";
10635 };
10636diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
10637index 57374dddf98d..1a0faa1a14c8 100644
10638--- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
10639+++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
10640@@ -261,6 +261,37 @@ &i2c3 {
10641 pinctrl-names = "default";
10642 pinctrl-0 = <&pinctrl_i2c3>;
10643 status = "okay";
10644+
10645+ adv7180: camera@20 {
10646+ compatible = "adi,adv7180";
10647+ pinctrl-names = "default";
10648+ pinctrl-0 = <&pinctrl_adv7180>;
10649+ reg = <0x20>;
10650+ powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
10651+ interrupt-parent = <&gpio5>;
10652+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
10653+
10654+ port {
10655+ adv7180_to_ipu1_csi0_mux: endpoint {
10656+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
10657+ bus-width = <8>;
10658+ };
10659+ };
10660+ };
10661+};
10662+
10663+&ipu1_csi0_from_ipu1_csi0_mux {
10664+ bus-width = <8>;
10665+};
10666+
10667+&ipu1_csi0_mux_from_parallel_sensor {
10668+ remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
10669+ bus-width = <8>;
10670+};
10671+
10672+&ipu1_csi0 {
10673+ pinctrl-names = "default";
10674+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
10675 };
10676
10677 &pcie {
10678@@ -340,6 +371,13 @@ &wdog1 {
10679 };
10680
10681 &iomuxc {
10682+ pinctrl_adv7180: adv7180grp {
10683+ fsl,pins = <
10684+ MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
10685+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
10686+ >;
10687+ };
10688+
10689 pinctrl_gpmi_nand: gpminandgrp {
10690 fsl,pins = <
10691 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
10692@@ -387,6 +425,22 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
10693 >;
10694 };
10695
10696+ pinctrl_ipu1_csi0: ipu1csi0grp {
10697+ fsl,pins = <
10698+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
10699+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
10700+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
10701+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
10702+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
10703+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
10704+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
10705+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
10706+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
10707+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
10708+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
10709+ >;
10710+ };
10711+
10712 pinctrl_gpio_leds: gpioledsgrp {
10713 fsl,pins = <
10714 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
10715diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
10716index 5fab5be414fe..7ca291e9dbdb 100644
10717--- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
10718+++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
10719@@ -184,7 +184,6 @@ &pcie {
10720 };
10721
10722 &ssi1 {
10723- fsl,mode = "i2s-slave";
10724 status = "okay";
10725 };
10726
10727diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
10728index f22e5879340b..d309a4d0eb08 100644
10729--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
10730+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
10731@@ -108,6 +108,18 @@ reg_wlan_vmmc: regulator@4 {
10732 startup-delay-us = <70000>;
10733 enable-active-high;
10734 };
10735+
10736+ reg_usb_h1_vbus: regulator@5 {
10737+ compatible = "regulator-fixed";
10738+ reg = <5>;
10739+ pinctrl-names = "default";
10740+ pinctrl-0 = <&pinctrl_usbh1>;
10741+ regulator-name = "usb_h1_vbus";
10742+ regulator-min-microvolt = <3300000>;
10743+ regulator-max-microvolt = <3300000>;
10744+ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
10745+ enable-active-high;
10746+ };
10747 };
10748
10749 gpio-keys {
10750@@ -515,6 +527,12 @@ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
10751 >;
10752 };
10753
10754+ pinctrl_usbh1: usbh1grp {
10755+ fsl,pins = <
10756+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0
10757+ >;
10758+ };
10759+
10760 pinctrl_usbotg: usbotggrp {
10761 fsl,pins = <
10762 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
10763@@ -629,6 +647,7 @@ &uart2 {
10764 };
10765
10766 &usbh1 {
10767+ vbus-supply = <&reg_usb_h1_vbus>;
10768 status = "okay";
10769 };
10770
10771diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
10772index afe7449c47da..756c5054f047 100644
10773--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
10774+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
10775@@ -123,6 +123,18 @@ reg_2p8v: regulator@6 {
10776 regulator-max-microvolt = <2800000>;
10777 regulator-always-on;
10778 };
10779+
10780+ reg_usb_h1_vbus: regulator@7 {
10781+ compatible = "regulator-fixed";
10782+ reg = <7>;
10783+ pinctrl-names = "default";
10784+ pinctrl-0 = <&pinctrl_usbh1>;
10785+ regulator-name = "usb_h1_vbus";
10786+ regulator-min-microvolt = <3300000>;
10787+ regulator-max-microvolt = <3300000>;
10788+ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
10789+ enable-active-high;
10790+ };
10791 };
10792
10793 mipi_xclk: mipi_xclk {
10794@@ -610,6 +622,12 @@ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
10795 >;
10796 };
10797
10798+ pinctrl_usbh1: usbh1grp {
10799+ fsl,pins = <
10800+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0
10801+ >;
10802+ };
10803+
10804 pinctrl_usbotg: usbotggrp {
10805 fsl,pins = <
10806 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
10807@@ -705,6 +723,7 @@ &uart2 {
10808 };
10809
10810 &usbh1 {
10811+ vbus-supply = <&reg_usb_h1_vbus>;
10812 status = "okay";
10813 };
10814
10815diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
10816index 5d94b5ee6aa0..eeb7679fd348 100644
10817--- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
10818+++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
10819@@ -59,6 +59,14 @@ mdio1: mdio {
10820 pinctrl-0 = <&pinctrl_mdio1>;
10821 gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
10822 &gpio6 4 GPIO_ACTIVE_HIGH>;
10823+
10824+ phy: ethernet-phy@0 {
10825+ pinctrl-0 = <&pinctrl_rmii_phy_irq>;
10826+ pinctrl-names = "default";
10827+ reg = <0>;
10828+ interrupt-parent = <&gpio3>;
10829+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
10830+ };
10831 };
10832
10833 reg_28p0v: regulator-28p0v {
10834@@ -615,14 +623,106 @@ &fec {
10835 pinctrl-names = "default";
10836 pinctrl-0 = <&pinctrl_enet>;
10837 phy-mode = "rmii";
10838+ phy-handle = <&phy>;
10839 phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
10840 phy-reset-duration = <100>;
10841 phy-supply = <&reg_3p3v>;
10842 status = "okay";
10843
10844- fixed-link {
10845- speed = <100>;
10846- full-duplex;
10847+ mdio {
10848+ #address-cells = <1>;
10849+ #size-cells = <0>;
10850+ status = "okay";
10851+
10852+ switch: switch@0 {
10853+ compatible = "marvell,mv88e6085";
10854+ pinctrl-0 = <&pinctrl_switch_irq>;
10855+ pinctrl-names = "default";
10856+ #address-cells = <1>;
10857+ #size-cells = <0>;
10858+ reg = <0>;
10859+ dsa,member = <0 0>;
10860+ eeprom-length = <512>;
10861+ interrupt-parent = <&gpio6>;
10862+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
10863+ interrupt-controller;
10864+ #interrupt-cells = <2>;
10865+
10866+ ports {
10867+ #address-cells = <1>;
10868+ #size-cells = <0>;
10869+
10870+ port@0 {
10871+ reg = <0>;
10872+ label = "gigabit_proc";
10873+ phy-handle = <&switchphy0>;
10874+ };
10875+
10876+ port@1 {
10877+ reg = <1>;
10878+ label = "netaux";
10879+ phy-handle = <&switchphy1>;
10880+ };
10881+
10882+ port@2 {
10883+ reg = <2>;
10884+ label = "cpu";
10885+ ethernet = <&fec>;
10886+
10887+ fixed-link {
10888+ speed = <100>;
10889+ full-duplex;
10890+ };
10891+ };
10892+
10893+ port@3 {
10894+ reg = <3>;
10895+ label = "netright";
10896+ phy-handle = <&switchphy3>;
10897+ };
10898+
10899+ port@4 {
10900+ reg = <4>;
10901+ label = "netleft";
10902+ phy-handle = <&switchphy4>;
10903+ };
10904+ };
10905+
10906+ mdio {
10907+ #address-cells = <1>;
10908+ #size-cells = <0>;
10909+
10910+ switchphy0: switchphy@0 {
10911+ reg = <0>;
10912+ interrupt-parent = <&switch>;
10913+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
10914+ };
10915+
10916+ switchphy1: switchphy@1 {
10917+ reg = <1>;
10918+ interrupt-parent = <&switch>;
10919+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
10920+ };
10921+
10922+ switchphy2: switchphy@2 {
10923+ reg = <2>;
10924+ interrupt-parent = <&switch>;
10925+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
10926+ };
10927+
10928+ switchphy3: switchphy@3 {
10929+ reg = <3>;
10930+ interrupt-parent = <&switch>;
10931+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
10932+ };
10933+
10934+ switchphy4: switchphy@4 {
10935+ reg = <4>;
10936+ interrupt-parent = <&switch>;
10937+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
10938+ };
10939+ };
10940+ };
10941 };
10942 };
10943
10944@@ -840,6 +940,12 @@ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x40010000
10945 >;
10946 };
10947
10948+ pinctrl_switch_irq: switchgrp {
10949+ fsl,pins = <
10950+ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x4001b000
10951+ >;
10952+ };
10953+
10954 pinctrl_tc358767: tc358767grp {
10955 fsl,pins = <
10956 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x10
10957diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
10958index a9723b94bafa..8884b4a3cafb 100644
10959--- a/arch/arm/boot/dts/imx6qdl.dtsi
10960+++ b/arch/arm/boot/dts/imx6qdl.dtsi
10961@@ -769,6 +769,7 @@ snvs_poweroff: snvs-poweroff {
10962 compatible = "syscon-poweroff";
10963 regmap = <&snvs>;
10964 offset = <0x38>;
10965+ value = <0x60>;
10966 mask = <0x60>;
10967 status = "disabled";
10968 };
10969diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
10970index 3243af4a9984..3f76f980947e 100644
10971--- a/arch/arm/boot/dts/imx6sl.dtsi
10972+++ b/arch/arm/boot/dts/imx6sl.dtsi
10973@@ -655,6 +655,7 @@ snvs_poweroff: snvs-poweroff {
10974 compatible = "syscon-poweroff";
10975 regmap = <&snvs>;
10976 offset = <0x38>;
10977+ value = <0x60>;
10978 mask = <0x60>;
10979 status = "disabled";
10980 };
10981diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
10982index f16b9df9d0c6..6c7eb54be9e2 100644
10983--- a/arch/arm/boot/dts/imx6sx.dtsi
10984+++ b/arch/arm/boot/dts/imx6sx.dtsi
10985@@ -710,6 +710,7 @@ snvs_poweroff: snvs-poweroff {
10986 compatible = "syscon-poweroff";
10987 regmap = <&snvs>;
10988 offset = <0x38>;
10989+ value = <0x60>;
10990 mask = <0x60>;
10991 status = "disabled";
10992 };
10993diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
10994index d2be8aa3370b..9c23e017d86a 100644
10995--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts
10996+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
10997@@ -22,7 +22,7 @@ memory {
10998 reg = <0x80000000 0x20000000>;
10999 };
11000
11001- backlight {
11002+ backlight_display: backlight-display {
11003 compatible = "pwm-backlight";
11004 pwms = <&pwm1 0 5000000>;
11005 brightness-levels = <0 4 8 16 32 64 128 255>;
11006@@ -78,6 +78,17 @@ dailink_master: simple-audio-card,codec {
11007 clocks = <&clks IMX6UL_CLK_SAI2>;
11008 };
11009 };
11010+
11011+ panel {
11012+ compatible = "innolux,at043tn24";
11013+ backlight = <&backlight_display>;
11014+
11015+ port {
11016+ panel_in: endpoint {
11017+ remote-endpoint = <&display_out>;
11018+ };
11019+ };
11020+ };
11021 };
11022
11023 &clks {
11024@@ -139,31 +150,11 @@ &lcdif {
11025 pinctrl-names = "default";
11026 pinctrl-0 = <&pinctrl_lcdif_dat
11027 &pinctrl_lcdif_ctrl>;
11028- display = <&display0>;
11029 status = "okay";
11030
11031- display0: display {
11032- bits-per-pixel = <16>;
11033- bus-width = <24>;
11034-
11035- display-timings {
11036- native-mode = <&timing0>;
11037-
11038- timing0: timing0 {
11039- clock-frequency = <9200000>;
11040- hactive = <480>;
11041- vactive = <272>;
11042- hfront-porch = <8>;
11043- hback-porch = <4>;
11044- hsync-len = <41>;
11045- vback-porch = <2>;
11046- vfront-porch = <4>;
11047- vsync-len = <10>;
11048- hsync-active = <0>;
11049- vsync-active = <0>;
11050- de-active = <1>;
11051- pixelclk-active = <0>;
11052- };
11053+ port {
11054+ display_out: endpoint {
11055+ remote-endpoint = <&panel_in>;
11056 };
11057 };
11058 };
11059@@ -316,7 +307,6 @@ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
11060 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
11061 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
11062 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
11063- MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
11064 >;
11065 };
11066
11067diff --git a/arch/arm/boot/dts/imx6ul-geam-kit.dts b/arch/arm/boot/dts/imx6ul-geam-kit.dts
11068deleted file mode 100644
11069index 142e60cab65f..000000000000
11070--- a/arch/arm/boot/dts/imx6ul-geam-kit.dts
11071+++ /dev/null
11072@@ -1,101 +0,0 @@
11073-/*
11074- * Copyright (C) 2016 Amarula Solutions B.V.
11075- * Copyright (C) 2016 Engicam S.r.l.
11076- *
11077- * This file is dual-licensed: you can use it either under the terms
11078- * of the GPL or the X11 license, at your option. Note that this dual
11079- * licensing only applies to this file, and not this project as a
11080- * whole.
11081- *
11082- * a) This file is free software; you can redistribute it and/or
11083- * modify it under the terms of the GNU General Public License
11084- * version 2 as published by the Free Software Foundation.
11085- *
11086- * This file is distributed in the hope that it will be useful,
11087- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11088- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11089- * GNU General Public License for more details.
11090- *
11091- * Or, alternatively,
11092- *
11093- * b) Permission is hereby granted, free of charge, to any person
11094- * obtaining a copy of this software and associated documentation
11095- * files (the "Software"), to deal in the Software without
11096- * restriction, including without limitation the rights to use,
11097- * copy, modify, merge, publish, distribute, sublicense, and/or
11098- * sell copies of the Software, and to permit persons to whom the
11099- * Software is furnished to do so, subject to the following
11100- * conditions:
11101- *
11102- * The above copyright notice and this permission notice shall be
11103- * included in all copies or substantial portions of the Software.
11104- *
11105- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11106- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
11107- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
11108- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
11109- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
11110- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
11111- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
11112- * OTHER DEALINGS IN THE SOFTWARE.
11113- */
11114-
11115-/dts-v1/;
11116-
11117-#include <dt-bindings/gpio/gpio.h>
11118-#include "imx6ul-geam.dtsi"
11119-
11120-/ {
11121- model = "Engicam GEAM6UL";
11122- compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
11123-};
11124-
11125-&can1 {
11126- status = "okay";
11127-};
11128-
11129-&can2 {
11130- status = "okay";
11131-};
11132-
11133-&lcdif {
11134- display = <&display0>;
11135- status = "okay";
11136-
11137- display0: display {
11138- bits-per-pixel = <16>;
11139- bus-width = <18>;
11140- status = "okay";
11141-
11142- display-timings {
11143- native-mode = <&timing0>;
11144- timing0: timing0 {
11145- clock-frequency = <28000000>;
11146- hactive = <800>;
11147- vactive = <480>;
11148- hfront-porch = <30>;
11149- hback-porch = <30>;
11150- hsync-len = <64>;
11151- vback-porch = <5>;
11152- vfront-porch = <5>;
11153- vsync-len = <20>;
11154- hsync-active = <0>;
11155- vsync-active = <0>;
11156- de-active = <1>;
11157- pixelclk-active = <0>;
11158- };
11159- };
11160- };
11161-};
11162-
11163-&usdhc1 {
11164- pinctrl-names = "default";
11165- pinctrl-0 = <&pinctrl_usdhc1>;
11166- status = "okay";
11167-};
11168-
11169-&tsc {
11170- measure-delay-time = <0x1ffff>;
11171- pre-charge-time = <0x1fff>;
11172- status = "okay";
11173-};
11174diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/imx6ul-geam.dts
11175new file mode 100644
11176index 000000000000..571eea7f1c6b
11177--- /dev/null
11178+++ b/arch/arm/boot/dts/imx6ul-geam.dts
11179@@ -0,0 +1,480 @@
11180+/*
11181+ * Copyright (C) 2016 Amarula Solutions B.V.
11182+ * Copyright (C) 2016 Engicam S.r.l.
11183+ *
11184+ * This file is dual-licensed: you can use it either under the terms
11185+ * of the GPL or the X11 license, at your option. Note that this dual
11186+ * licensing only applies to this file, and not this project as a
11187+ * whole.
11188+ *
11189+ * a) This file is free software; you can redistribute it and/or
11190+ * modify it under the terms of the GNU General Public License
11191+ * version 2 as published by the Free Software Foundation.
11192+ *
11193+ * This file is distributed in the hope that it will be useful,
11194+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
11195+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11196+ * GNU General Public License for more details.
11197+ *
11198+ * Or, alternatively,
11199+ *
11200+ * b) Permission is hereby granted, free of charge, to any person
11201+ * obtaining a copy of this software and associated documentation
11202+ * files (the "Software"), to deal in the Software without
11203+ * restriction, including without limitation the rights to use,
11204+ * copy, modify, merge, publish, distribute, sublicense, and/or
11205+ * sell copies of the Software, and to permit persons to whom the
11206+ * Software is furnished to do so, subject to the following
11207+ * conditions:
11208+ *
11209+ * The above copyright notice and this permission notice shall be
11210+ * included in all copies or substantial portions of the Software.
11211+ *
11212+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11213+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
11214+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
11215+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
11216+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
11217+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
11218+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
11219+ * OTHER DEALINGS IN THE SOFTWARE.
11220+ */
11221+
11222+/dts-v1/;
11223+
11224+#include <dt-bindings/gpio/gpio.h>
11225+#include <dt-bindings/input/input.h>
11226+#include "imx6ul.dtsi"
11227+
11228+/ {
11229+ model = "Engicam GEAM6UL Starter Kit";
11230+ compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
11231+
11232+ memory {
11233+ reg = <0x80000000 0x08000000>;
11234+ };
11235+
11236+ backlight {
11237+ compatible = "pwm-backlight";
11238+ pwms = <&pwm8 0 100000>;
11239+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
11240+ 10 11 12 13 14 15 16 17 18 19
11241+ 20 21 22 23 24 25 26 27 28 29
11242+ 30 31 32 33 34 35 36 37 38 39
11243+ 40 41 42 43 44 45 46 47 48 49
11244+ 50 51 52 53 54 55 56 57 58 59
11245+ 60 61 62 63 64 65 66 67 68 69
11246+ 70 71 72 73 74 75 76 77 78 79
11247+ 80 81 82 83 84 85 86 87 88 89
11248+ 90 91 92 93 94 95 96 97 98 99
11249+ 100>;
11250+ default-brightness-level = <100>;
11251+ };
11252+
11253+ chosen {
11254+ stdout-path = &uart1;
11255+ };
11256+
11257+ reg_1p8v: regulator-1p8v {
11258+ compatible = "regulator-fixed";
11259+ regulator-name = "1P8V";
11260+ regulator-min-microvolt = <1800000>;
11261+ regulator-max-microvolt = <1800000>;
11262+ regulator-always-on;
11263+ regulator-boot-on;
11264+ };
11265+
11266+ reg_3p3v: regulator-3p3v {
11267+ compatible = "regulator-fixed";
11268+ regulator-name = "3P3V";
11269+ regulator-min-microvolt = <3300000>;
11270+ regulator-max-microvolt = <3300000>;
11271+ regulator-always-on;
11272+ regulator-boot-on;
11273+ };
11274+
11275+ sound {
11276+ compatible = "simple-audio-card";
11277+ simple-audio-card,name = "imx6ul-geam-sgtl5000";
11278+ simple-audio-card,format = "i2s";
11279+ simple-audio-card,bitclock-master = <&dailink_master>;
11280+ simple-audio-card,frame-master = <&dailink_master>;
11281+ simple-audio-card,widgets =
11282+ "Microphone", "Mic Jack",
11283+ "Line", "Line In",
11284+ "Line", "Line Out",
11285+ "Headphone", "Headphone Jack";
11286+ simple-audio-card,routing =
11287+ "MIC_IN", "Mic Jack",
11288+ "Mic Jack", "Mic Bias",
11289+ "Headphone Jack", "HP_OUT";
11290+
11291+ simple-audio-card,cpu {
11292+ sound-dai = <&sai2>;
11293+ };
11294+
11295+ dailink_master: simple-audio-card,codec {
11296+ sound-dai = <&sgtl5000>;
11297+ clocks = <&clks IMX6UL_CLK_SAI2>;
11298+ };
11299+ };
11300+};
11301+
11302+&can1 {
11303+ pinctrl-names = "default";
11304+ pinctrl-0 = <&pinctrl_flexcan1>;
11305+ xceiver-supply = <&reg_3p3v>;
11306+ status = "okay";
11307+};
11308+
11309+&can2 {
11310+ pinctrl-names = "default";
11311+ pinctrl-0 = <&pinctrl_flexcan2>;
11312+ xceiver-supply = <&reg_3p3v>;
11313+ status = "okay";
11314+};
11315+
11316+&fec1 {
11317+ pinctrl-names = "default";
11318+ pinctrl-0 = <&pinctrl_enet1>;
11319+ phy-mode = "rmii";
11320+ phy-handle = <&ethphy0>;
11321+ status = "okay";
11322+};
11323+
11324+&fec2 {
11325+ pinctrl-names = "default";
11326+ pinctrl-0 = <&pinctrl_enet2>;
11327+ phy-mode = "rmii";
11328+ phy-handle = <&ethphy1>;
11329+ status = "okay";
11330+
11331+ mdio {
11332+ #address-cells = <1>;
11333+ #size-cells = <0>;
11334+
11335+ ethphy0: ethernet-phy@0 {
11336+ compatible = "ethernet-phy-ieee802.3-c22";
11337+ reg = <0>;
11338+ };
11339+
11340+ ethphy1: ethernet-phy@1 {
11341+ compatible = "ethernet-phy-ieee802.3-c22";
11342+ reg = <1>;
11343+ };
11344+ };
11345+};
11346+
11347+&gpmi {
11348+ pinctrl-names = "default";
11349+ pinctrl-0 = <&pinctrl_gpmi_nand>;
11350+ nand-on-flash-bbt;
11351+ status = "okay";
11352+};
11353+
11354+&i2c1 {
11355+ clock-frequency = <100000>;
11356+ pinctrl-names = "default";
11357+ pinctrl-0 = <&pinctrl_i2c1>;
11358+ status = "okay";
11359+
11360+ sgtl5000: codec@a {
11361+ compatible = "fsl,sgtl5000";
11362+ reg = <0x0a>;
11363+ clocks = <&clks IMX6UL_CLK_OSC>;
11364+ clock-names = "mclk";
11365+ VDDA-supply = <&reg_3p3v>;
11366+ VDDIO-supply = <&reg_3p3v>;
11367+ VDDD-supply = <&reg_1p8v>;
11368+ };
11369+};
11370+
11371+&i2c2 {
11372+ clock_frequency = <100000>;
11373+ pinctrl-names = "default";
11374+ pinctrl-0 = <&pinctrl_i2c2>;
11375+ status = "okay";
11376+};
11377+
11378+&lcdif {
11379+ pinctrl-names = "default";
11380+ pinctrl-0 = <&pinctrl_lcdif_dat
11381+ &pinctrl_lcdif_ctrl>;
11382+ display = <&display0>;
11383+ status = "okay";
11384+
11385+ display0: display {
11386+ bits-per-pixel = <16>;
11387+ bus-width = <18>;
11388+
11389+ display-timings {
11390+ native-mode = <&timing0>;
11391+ timing0: timing0 {
11392+ clock-frequency = <28000000>;
11393+ hactive = <800>;
11394+ vactive = <480>;
11395+ hfront-porch = <30>;
11396+ hback-porch = <30>;
11397+ hsync-len = <64>;
11398+ vback-porch = <5>;
11399+ vfront-porch = <5>;
11400+ vsync-len = <20>;
11401+ hsync-active = <0>;
11402+ vsync-active = <0>;
11403+ de-active = <1>;
11404+ pixelclk-active = <0>;
11405+ };
11406+ };
11407+ };
11408+};
11409+
11410+&pwm8 {
11411+ pinctrl-names = "default";
11412+ pinctrl-0 = <&pinctrl_pwm8>;
11413+ status = "okay";
11414+};
11415+
11416+&tsc {
11417+ pinctrl-names = "default";
11418+ pinctrl-0 = <&pinctrl_tsc>;
11419+ xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
11420+};
11421+
11422+&sai2 {
11423+ pinctrl-names = "default";
11424+ pinctrl-0 = <&pinctrl_sai2>;
11425+ status = "okay";
11426+};
11427+
11428+&tsc {
11429+ measure-delay-time = <0x1ffff>;
11430+ pre-charge-time = <0x1fff>;
11431+ status = "okay";
11432+};
11433+
11434+&uart1 {
11435+ pinctrl-names = "default";
11436+ pinctrl-0 = <&pinctrl_uart1>;
11437+ status = "okay";
11438+};
11439+
11440+&uart2 {
11441+ pinctrl-names = "default";
11442+ pinctrl-0 = <&pinctrl_uart2>;
11443+ status = "okay";
11444+};
11445+
11446+&usbotg1 {
11447+ dr_mode = "peripheral";
11448+ status = "okay";
11449+};
11450+
11451+&usbotg2 {
11452+ dr_mode = "host";
11453+ status = "okay";
11454+};
11455+
11456+&usdhc1 {
11457+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
11458+ pinctrl-0 = <&pinctrl_usdhc1>;
11459+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
11460+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
11461+ bus-width = <4>;
11462+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
11463+ no-1-8-v;
11464+ status = "okay";
11465+};
11466+
11467+&iomuxc {
11468+ pinctrl_enet1: enet1grp {
11469+ fsl,pins = <
11470+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
11471+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
11472+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
11473+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
11474+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
11475+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
11476+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
11477+ >;
11478+ };
11479+
11480+ pinctrl_enet2: enet2grp {
11481+ fsl,pins = <
11482+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
11483+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
11484+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
11485+ MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */
11486+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
11487+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
11488+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
11489+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
11490+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
11491+ MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031
11492+ >;
11493+ };
11494+
11495+ pinctrl_flexcan1: flexcan1grp {
11496+ fsl,pins = <
11497+ MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
11498+ MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
11499+ >;
11500+ };
11501+
11502+ pinctrl_flexcan2: flexcan2grp {
11503+ fsl,pins = <
11504+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
11505+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
11506+ >;
11507+ };
11508+
11509+ pinctrl_gpmi_nand: gpmi-nand {
11510+ fsl,pins = <
11511+ MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
11512+ MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
11513+ MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
11514+ MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
11515+ MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
11516+ MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
11517+ MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
11518+ MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
11519+ MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
11520+ MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
11521+ MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
11522+ MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
11523+ MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
11524+ MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
11525+ MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
11526+ >;
11527+ };
11528+
11529+ pinctrl_i2c1: i2c1grp {
11530+ fsl,pins = <
11531+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
11532+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
11533+ >;
11534+ };
11535+
11536+ pinctrl_i2c2: i2c2grp {
11537+ fsl,pins = <
11538+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
11539+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
11540+ >;
11541+ };
11542+
11543+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
11544+ fsl,pins = <
11545+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
11546+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
11547+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
11548+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
11549+ >;
11550+ };
11551+
11552+ pinctrl_lcdif_dat: lcdifdatgrp {
11553+ fsl,pins = <
11554+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
11555+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
11556+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
11557+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
11558+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
11559+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
11560+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
11561+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
11562+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
11563+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
11564+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
11565+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
11566+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
11567+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
11568+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
11569+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
11570+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
11571+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
11572+ >;
11573+ };
11574+
11575+ pinctrl_pwm8: pwm8grp {
11576+ fsl,pins = <
11577+ MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
11578+ >;
11579+ };
11580+
11581+ pinctrl_tsc: tscgrp {
11582+ fsl,pin = <
11583+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
11584+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
11585+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
11586+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
11587+ >;
11588+ };
11589+
11590+ pinctrl_sai2: sai2grp {
11591+ fsl,pins = <
11592+ MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
11593+ MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
11594+ MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
11595+ MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
11596+ MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
11597+ >;
11598+ };
11599+
11600+ pinctrl_uart1: uart1grp {
11601+ fsl,pins = <
11602+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
11603+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
11604+ >;
11605+ };
11606+
11607+ pinctrl_uart2: uart2grp {
11608+ fsl,pins = <
11609+ MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
11610+ MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
11611+ MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
11612+ MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
11613+ >;
11614+ };
11615+
11616+ pinctrl_usdhc1: usdhc1grp {
11617+ fsl,pins = <
11618+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
11619+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
11620+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
11621+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
11622+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
11623+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
11624+ >;
11625+ };
11626+
11627+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
11628+ fsl,pins = <
11629+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
11630+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
11631+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
11632+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
11633+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
11634+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
11635+ >;
11636+ };
11637+
11638+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
11639+ fsl,pins = <
11640+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
11641+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
11642+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
11643+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
11644+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
11645+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
11646+ >;
11647+ };
11648+
11649+ pinctrl_usdhc2: usdhc2grp {
11650+ fsl,pins = <
11651+ MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070
11652+ MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070
11653+ MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070
11654+ MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070
11655+ MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070
11656+ MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070
11657+ >;
11658+ };
11659+};
11660diff --git a/arch/arm/boot/dts/imx6ul-geam.dtsi b/arch/arm/boot/dts/imx6ul-geam.dtsi
11661deleted file mode 100644
11662index eb94d956808b..000000000000
11663--- a/arch/arm/boot/dts/imx6ul-geam.dtsi
11664+++ /dev/null
11665@@ -1,406 +0,0 @@
11666-/*
11667- * Copyright (C) 2016 Amarula Solutions B.V.
11668- * Copyright (C) 2016 Engicam S.r.l.
11669- *
11670- * This file is dual-licensed: you can use it either under the terms
11671- * of the GPL or the X11 license, at your option. Note that this dual
11672- * licensing only applies to this file, and not this project as a
11673- * whole.
11674- *
11675- * a) This file is free software; you can redistribute it and/or
11676- * modify it under the terms of the GNU General Public License
11677- * version 2 as published by the Free Software Foundation.
11678- *
11679- * This file is distributed in the hope that it will be useful,
11680- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11681- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11682- * GNU General Public License for more details.
11683- *
11684- * Or, alternatively,
11685- *
11686- * b) Permission is hereby granted, free of charge, to any person
11687- * obtaining a copy of this software and associated documentation
11688- * files (the "Software"), to deal in the Software without
11689- * restriction, including without limitation the rights to use,
11690- * copy, modify, merge, publish, distribute, sublicense, and/or
11691- * sell copies of the Software, and to permit persons to whom the
11692- * Software is furnished to do so, subject to the following
11693- * conditions:
11694- *
11695- * The above copyright notice and this permission notice shall be
11696- * included in all copies or substantial portions of the Software.
11697- *
11698- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11699- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
11700- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
11701- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
11702- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
11703- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
11704- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
11705- * OTHER DEALINGS IN THE SOFTWARE.
11706- */
11707-
11708-#include <dt-bindings/gpio/gpio.h>
11709-#include <dt-bindings/input/input.h>
11710-#include "imx6ul.dtsi"
11711-
11712-/ {
11713- memory {
11714- reg = <0x80000000 0x08000000>;
11715- };
11716-
11717- backlight {
11718- compatible = "pwm-backlight";
11719- pwms = <&pwm8 0 100000>;
11720- brightness-levels = < 0 1 2 3 4 5 6 7 8 9
11721- 10 11 12 13 14 15 16 17 18 19
11722- 20 21 22 23 24 25 26 27 28 29
11723- 30 31 32 33 34 35 36 37 38 39
11724- 40 41 42 43 44 45 46 47 48 49
11725- 50 51 52 53 54 55 56 57 58 59
11726- 60 61 62 63 64 65 66 67 68 69
11727- 70 71 72 73 74 75 76 77 78 79
11728- 80 81 82 83 84 85 86 87 88 89
11729- 90 91 92 93 94 95 96 97 98 99
11730- 100>;
11731- default-brightness-level = <100>;
11732- };
11733-
11734- chosen {
11735- stdout-path = &uart1;
11736- };
11737-
11738- reg_1p8v: regulator-1p8v {
11739- compatible = "regulator-fixed";
11740- regulator-name = "1P8V";
11741- regulator-min-microvolt = <1800000>;
11742- regulator-max-microvolt = <1800000>;
11743- regulator-always-on;
11744- regulator-boot-on;
11745- };
11746-
11747- reg_3p3v: regulator-3p3v {
11748- compatible = "regulator-fixed";
11749- regulator-name = "3P3V";
11750- regulator-min-microvolt = <3300000>;
11751- regulator-max-microvolt = <3300000>;
11752- regulator-always-on;
11753- regulator-boot-on;
11754- };
11755-};
11756-
11757-&can1 {
11758- pinctrl-names = "default";
11759- pinctrl-0 = <&pinctrl_flexcan1>;
11760- xceiver-supply = <&reg_3p3v>;
11761-};
11762-
11763-&can2 {
11764- pinctrl-names = "default";
11765- pinctrl-0 = <&pinctrl_flexcan2>;
11766- xceiver-supply = <&reg_3p3v>;
11767-};
11768-
11769-&fec1 {
11770- pinctrl-names = "default";
11771- pinctrl-0 = <&pinctrl_enet1>;
11772- phy-mode = "rmii";
11773- phy-handle = <&ethphy0>;
11774- status = "okay";
11775-};
11776-
11777-&fec2 {
11778- pinctrl-names = "default";
11779- pinctrl-0 = <&pinctrl_enet2>;
11780- phy-mode = "rmii";
11781- phy-handle = <&ethphy1>;
11782- status = "okay";
11783-
11784- mdio {
11785- #address-cells = <1>;
11786- #size-cells = <0>;
11787-
11788- ethphy0: ethernet-phy@0 {
11789- compatible = "ethernet-phy-ieee802.3-c22";
11790- reg = <0>;
11791- };
11792-
11793- ethphy1: ethernet-phy@1 {
11794- compatible = "ethernet-phy-ieee802.3-c22";
11795- reg = <1>;
11796- };
11797- };
11798-};
11799-
11800-&gpmi {
11801- pinctrl-names = "default";
11802- pinctrl-0 = <&pinctrl_gpmi_nand>;
11803- nand-on-flash-bbt;
11804- status = "okay";
11805-};
11806-
11807-&i2c1 {
11808- clock-frequency = <100000>;
11809- pinctrl-names = "default";
11810- pinctrl-0 = <&pinctrl_i2c1>;
11811- status = "okay";
11812-};
11813-
11814-&i2c2 {
11815- clock_frequency = <100000>;
11816- pinctrl-names = "default";
11817- pinctrl-0 = <&pinctrl_i2c2>;
11818- status = "okay";
11819-};
11820-
11821-&lcdif {
11822- pinctrl-names = "default";
11823- pinctrl-0 = <&pinctrl_lcdif_dat
11824- &pinctrl_lcdif_ctrl>;
11825- display = <&display0>;
11826-};
11827-
11828-&pwm8 {
11829- pinctrl-names = "default";
11830- pinctrl-0 = <&pinctrl_pwm8>;
11831- status = "okay";
11832-};
11833-
11834-&tsc {
11835- pinctrl-names = "default";
11836- pinctrl-0 = <&pinctrl_tsc>;
11837- xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
11838-};
11839-
11840-&sai2 {
11841- pinctrl-names = "default";
11842- pinctrl-0 = <&pinctrl_sai2>;
11843- status = "okay";
11844-};
11845-
11846-&uart1 {
11847- pinctrl-names = "default";
11848- pinctrl-0 = <&pinctrl_uart1>;
11849- status = "okay";
11850-};
11851-
11852-&uart2 {
11853- pinctrl-names = "default";
11854- pinctrl-0 = <&pinctrl_uart2>;
11855- status = "okay";
11856-};
11857-
11858-&usbotg1 {
11859- dr_mode = "peripheral";
11860- status = "okay";
11861-};
11862-
11863-&usbotg2 {
11864- dr_mode = "host";
11865- status = "okay";
11866-};
11867-
11868-&usdhc1 {
11869- pinctrl-names = "default", "state_100mhz", "state_200mhz";
11870- pinctrl-0 = <&pinctrl_usdhc1>;
11871- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
11872- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
11873- bus-width = <4>;
11874- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
11875- no-1-8-v;
11876- status = "okay";
11877-};
11878-
11879-&iomuxc {
11880- pinctrl_enet1: enet1grp {
11881- fsl,pins = <
11882- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
11883- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
11884- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
11885- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
11886- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
11887- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
11888- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
11889- >;
11890- };
11891-
11892- pinctrl_enet2: enet2grp {
11893- fsl,pins = <
11894- MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
11895- MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
11896- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
11897- MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */
11898- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
11899- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
11900- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
11901- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
11902- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
11903- MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031
11904- >;
11905- };
11906-
11907- pinctrl_flexcan1: flexcan1grp {
11908- fsl,pins = <
11909- MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
11910- MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
11911- >;
11912- };
11913-
11914- pinctrl_flexcan2: flexcan2grp {
11915- fsl,pins = <
11916- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
11917- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
11918- >;
11919- };
11920-
11921- pinctrl_gpmi_nand: gpmi-nand {
11922- fsl,pins = <
11923- MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
11924- MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
11925- MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
11926- MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
11927- MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
11928- MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
11929- MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
11930- MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
11931- MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
11932- MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
11933- MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
11934- MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
11935- MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
11936- MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
11937- MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
11938- >;
11939- };
11940-
11941- pinctrl_i2c1: i2c1grp {
11942- fsl,pins = <
11943- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
11944- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
11945- >;
11946- };
11947-
11948- pinctrl_i2c2: i2c2grp {
11949- fsl,pins = <
11950- MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
11951- MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
11952- >;
11953- };
11954-
11955- pinctrl_lcdif_ctrl: lcdifctrlgrp {
11956- fsl,pins = <
11957- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
11958- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
11959- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
11960- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
11961- >;
11962- };
11963-
11964- pinctrl_lcdif_dat: lcdifdatgrp {
11965- fsl,pins = <
11966- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
11967- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
11968- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
11969- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
11970- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
11971- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
11972- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
11973- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
11974- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
11975- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
11976- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
11977- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
11978- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
11979- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
11980- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
11981- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
11982- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
11983- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
11984- >;
11985- };
11986-
11987- pinctrl_pwm8: pwm8grp {
11988- fsl,pins = <
11989- MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
11990- >;
11991- };
11992-
11993- pinctrl_tsc: tscgrp {
11994- fsl,pin = <
11995- MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
11996- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
11997- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
11998- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
11999- >;
12000- };
12001-
12002- pinctrl_sai2: sai2grp {
12003- fsl,pins = <
12004- MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
12005- MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
12006- MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
12007- MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
12008- MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
12009- >;
12010- };
12011-
12012- pinctrl_uart1: uart1grp {
12013- fsl,pins = <
12014- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
12015- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
12016- >;
12017- };
12018-
12019- pinctrl_uart2: uart2grp {
12020- fsl,pins = <
12021- MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
12022- MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
12023- MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
12024- MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
12025- >;
12026- };
12027-
12028- pinctrl_usdhc1: usdhc1grp {
12029- fsl,pins = <
12030- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
12031- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
12032- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
12033- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
12034- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
12035- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
12036- >;
12037- };
12038-
12039- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
12040- fsl,pins = <
12041- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
12042- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
12043- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
12044- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
12045- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
12046- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
12047- >;
12048- };
12049-
12050- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
12051- fsl,pins = <
12052- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
12053- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
12054- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
12055- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
12056- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
12057- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
12058- >;
12059- };
12060-
12061- pinctrl_usdhc2: usdhc2grp {
12062- fsl,pins = <
12063- MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070
12064- MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070
12065- MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070
12066- MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070
12067- MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070
12068- MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070
12069- >;
12070- };
12071-};
12072diff --git a/arch/arm/boot/dts/imx6ul-isiot-common.dtsi b/arch/arm/boot/dts/imx6ul-isiot-common.dtsi
12073deleted file mode 100644
12074index 2beaab6e272e..000000000000
12075--- a/arch/arm/boot/dts/imx6ul-isiot-common.dtsi
12076+++ /dev/null
12077@@ -1,141 +0,0 @@
12078-/*
12079- * Copyright (C) 2016 Amarula Solutions B.V.
12080- * Copyright (C) 2016 Engicam S.r.l.
12081- *
12082- * This file is dual-licensed: you can use it either under the terms
12083- * of the GPL or the X11 license, at your option. Note that this dual
12084- * licensing only applies to this file, and not this project as a
12085- * whole.
12086- *
12087- * a) This file is free software; you can redistribute it and/or
12088- * modify it under the terms of the GNU General Public License
12089- * version 2 as published by the Free Software Foundation.
12090- *
12091- * This file is distributed in the hope that it will be useful,
12092- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12093- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12094- * GNU General Public License for more details.
12095- *
12096- * Or, alternatively,
12097- *
12098- * b) Permission is hereby granted, free of charge, to any person
12099- * obtaining a copy of this software and associated documentation
12100- * files (the "Software"), to deal in the Software without
12101- * restriction, including without limitation the rights to use,
12102- * copy, modify, merge, publish, distribute, sublicense, and/or
12103- * sell copies of the Software, and to permit persons to whom the
12104- * Software is furnished to do so, subject to the following
12105- * conditions:
12106- *
12107- * The above copyright notice and this permission notice shall be
12108- * included in all copies or substantial portions of the Software.
12109- *
12110- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
12111- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
12112- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12113- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
12114- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
12115- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
12116- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
12117- * OTHER DEALINGS IN THE SOFTWARE.
12118- */
12119-
12120-&i2c1 {
12121- stmpe811: gpio-expander@44 {
12122- compatible = "st,stmpe811";
12123- reg = <0x44>;
12124- #address-cells = <1>;
12125- #size-cells = <0>;
12126- pinctrl-names = "default";
12127- pinctrl-0 = <&pinctrl_stmpe>;
12128- interrupt-parent = <&gpio1>;
12129- interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
12130- interrupt-controller;
12131- #interrupt-cells = <2>;
12132-
12133- stmpe: touchscreen {
12134- compatible = "st,stmpe-ts";
12135- st,sample-time = <4>;
12136- st,mod-12b = <1>;
12137- st,ref-sel = <0>;
12138- st,adc-freq = <1>;
12139- st,ave-ctrl = <1>;
12140- st,touch-det-delay = <2>;
12141- st,settling = <2>;
12142- st,fraction-z = <7>;
12143- st,i-drive = <1>;
12144- };
12145- };
12146-};
12147-
12148-&lcdif {
12149- pinctrl-names = "default";
12150- pinctrl-0 = <&pinctrl_lcdif_dat
12151- &pinctrl_lcdif_ctrl>;
12152- display = <&display0>;
12153- status = "okay";
12154-
12155- display0: display {
12156- bits-per-pixel = <16>;
12157- bus-width = <18>;
12158-
12159- display-timings {
12160- native-mode = <&timing0>;
12161- timing0: timing0 {
12162- clock-frequency = <28000000>;
12163- hactive = <800>;
12164- vactive = <480>;
12165- hfront-porch = <30>;
12166- hback-porch = <30>;
12167- hsync-len = <64>;
12168- vback-porch = <5>;
12169- vfront-porch = <5>;
12170- vsync-len = <20>;
12171- hsync-active = <0>;
12172- vsync-active = <0>;
12173- de-active = <1>;
12174- pixelclk-active = <0>;
12175- };
12176- };
12177- };
12178-};
12179-
12180-&iomuxc {
12181- pinctrl_lcdif_ctrl: lcdifctrlgrp {
12182- fsl,pins = <
12183- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
12184- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
12185- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
12186- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
12187- >;
12188- };
12189-
12190- pinctrl_lcdif_dat: lcdifdatgrp {
12191- fsl,pins = <
12192- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
12193- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
12194- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
12195- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
12196- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
12197- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
12198- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
12199- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
12200- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
12201- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
12202- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
12203- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
12204- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
12205- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
12206- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
12207- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
12208- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
12209- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
12210- >;
12211- };
12212-
12213- pinctrl_stmpe: stmpegrp {
12214- fsl,pins = <
12215- MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
12216- >;
12217- };
12218-};
12219diff --git a/arch/arm/boot/dts/imx6ul-isiot-emmc.dts b/arch/arm/boot/dts/imx6ul-isiot-emmc.dts
12220index 73a1d0f0b9d5..f5b422898e61 100644
12221--- a/arch/arm/boot/dts/imx6ul-isiot-emmc.dts
12222+++ b/arch/arm/boot/dts/imx6ul-isiot-emmc.dts
12223@@ -43,7 +43,6 @@
12224 /dts-v1/;
12225
12226 #include "imx6ul-isiot.dtsi"
12227-#include "imx6ul-isiot-common.dtsi"
12228
12229 / {
12230 model = "Engicam Is.IoT MX6UL eMMC Starter kit";
12231diff --git a/arch/arm/boot/dts/imx6ul-isiot-nand.dts b/arch/arm/boot/dts/imx6ul-isiot-nand.dts
12232index da29a86eb6a8..de15e1c75dd1 100644
12233--- a/arch/arm/boot/dts/imx6ul-isiot-nand.dts
12234+++ b/arch/arm/boot/dts/imx6ul-isiot-nand.dts
12235@@ -43,7 +43,6 @@
12236 /dts-v1/;
12237
12238 #include "imx6ul-isiot.dtsi"
12239-#include "imx6ul-isiot-common.dtsi"
12240
12241 / {
12242 model = "Engicam Is.IoT MX6UL NAND Starter kit";
12243diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi
12244index ea30380ad7a4..950fb28b630a 100644
12245--- a/arch/arm/boot/dts/imx6ul-isiot.dtsi
12246+++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi
12247@@ -69,6 +69,68 @@ backlight {
12248 100>;
12249 default-brightness-level = <100>;
12250 };
12251+
12252+ reg_1p8v: regulator-1p8v {
12253+ compatible = "regulator-fixed";
12254+ regulator-name = "1P8V";
12255+ regulator-min-microvolt = <1800000>;
12256+ regulator-max-microvolt = <1800000>;
12257+ regulator-always-on;
12258+ regulator-boot-on;
12259+ };
12260+
12261+ reg_3p3v: regulator-3p3v {
12262+ compatible = "regulator-fixed";
12263+ regulator-name = "3P3V";
12264+ regulator-min-microvolt = <3300000>;
12265+ regulator-max-microvolt = <3300000>;
12266+ regulator-always-on;
12267+ regulator-boot-on;
12268+ };
12269+
12270+ sound {
12271+ compatible = "simple-audio-card";
12272+ simple-audio-card,name = "imx6ul-isiot-sgtl5000";
12273+ simple-audio-card,format = "i2s";
12274+ simple-audio-card,bitclock-master = <&dailink_master>;
12275+ simple-audio-card,frame-master = <&dailink_master>;
12276+ simple-audio-card,widgets =
12277+ "Microphone", "Mic Jack",
12278+ "Line", "Line In",
12279+ "Line", "Line Out",
12280+ "Headphone", "Headphone Jack";
12281+ simple-audio-card,routing =
12282+ "MIC_IN", "Mic Jack",
12283+ "Mic Jack", "Mic Bias",
12284+ "Headphone Jack", "HP_OUT";
12285+
12286+ simple-audio-card,cpu {
12287+ sound-dai = <&sai2>;
12288+ };
12289+
12290+ dailink_master: simple-audio-card,codec {
12291+ sound-dai = <&sgtl5000>;
12292+ clocks = <&clks IMX6UL_CLK_SAI2>;
12293+ };
12294+ };
12295+};
12296+
12297+&fec1 {
12298+ pinctrl-names = "default";
12299+ pinctrl-0 = <&pinctrl_enet1>;
12300+ phy-mode = "rmii";
12301+ phy-handle = <&ethphy0>;
12302+ status = "okay";
12303+
12304+ mdio {
12305+ #address-cells = <1>;
12306+ #size-cells = <0>;
12307+
12308+ ethphy0: ethernet-phy@0 {
12309+ compatible = "ethernet-phy-ieee802.3-c22";
12310+ reg = <0>;
12311+ };
12312+ };
12313 };
12314
12315 &i2c1 {
12316@@ -76,6 +138,42 @@ &i2c1 {
12317 pinctrl-names = "default";
12318 pinctrl-0 = <&pinctrl_i2c1>;
12319 status = "okay";
12320+
12321+ sgtl5000: codec@a {
12322+ compatible = "fsl,sgtl5000";
12323+ reg = <0x0a>;
12324+ clocks = <&clks IMX6UL_CLK_OSC>;
12325+ clock-names = "mclk";
12326+ VDDA-supply = <&reg_3p3v>;
12327+ VDDIO-supply = <&reg_3p3v>;
12328+ VDDD-supply = <&reg_1p8v>;
12329+ };
12330+
12331+ stmpe811: gpio-expander@44 {
12332+ compatible = "st,stmpe811";
12333+ reg = <0x44>;
12334+ #address-cells = <1>;
12335+ #size-cells = <0>;
12336+ pinctrl-names = "default";
12337+ pinctrl-0 = <&pinctrl_stmpe>;
12338+ interrupt-parent = <&gpio1>;
12339+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
12340+ interrupt-controller;
12341+ #interrupt-cells = <2>;
12342+
12343+ stmpe: touchscreen {
12344+ compatible = "st,stmpe-ts";
12345+ st,sample-time = <4>;
12346+ st,mod-12b = <1>;
12347+ st,ref-sel = <0>;
12348+ st,adc-freq = <1>;
12349+ st,ave-ctrl = <1>;
12350+ st,touch-det-delay = <2>;
12351+ st,settling = <2>;
12352+ st,fraction-z = <7>;
12353+ st,i-drive = <1>;
12354+ };
12355+ };
12356 };
12357
12358 &i2c2 {
12359@@ -85,6 +183,38 @@ &i2c2 {
12360 status = "okay";
12361 };
12362
12363+&lcdif {
12364+ pinctrl-names = "default";
12365+ pinctrl-0 = <&pinctrl_lcdif_dat
12366+ &pinctrl_lcdif_ctrl>;
12367+ display = <&display0>;
12368+ status = "okay";
12369+
12370+ display0: display {
12371+ bits-per-pixel = <16>;
12372+ bus-width = <18>;
12373+
12374+ display-timings {
12375+ native-mode = <&timing0>;
12376+ timing0: timing0 {
12377+ clock-frequency = <28000000>;
12378+ hactive = <800>;
12379+ vactive = <480>;
12380+ hfront-porch = <30>;
12381+ hback-porch = <30>;
12382+ hsync-len = <64>;
12383+ vback-porch = <5>;
12384+ vfront-porch = <5>;
12385+ vsync-len = <20>;
12386+ hsync-active = <0>;
12387+ vsync-active = <0>;
12388+ de-active = <1>;
12389+ pixelclk-active = <0>;
12390+ };
12391+ };
12392+ };
12393+};
12394+
12395 &pwm8 {
12396 pinctrl-names = "default";
12397 pinctrl-0 = <&pinctrl_pwm8>;
12398@@ -115,6 +245,21 @@ &usdhc1 {
12399 };
12400
12401 &iomuxc {
12402+ pinctrl_enet1: enet1grp {
12403+ fsl,pins = <
12404+ MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0
12405+ MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0
12406+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
12407+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
12408+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
12409+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
12410+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
12411+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
12412+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
12413+ MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
12414+ >;
12415+ };
12416+
12417 pinctrl_i2c1: i2c1grp {
12418 fsl,pins = <
12419 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
12420@@ -129,6 +274,38 @@ MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
12421 >;
12422 };
12423
12424+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
12425+ fsl,pins = <
12426+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
12427+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
12428+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
12429+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
12430+ >;
12431+ };
12432+
12433+ pinctrl_lcdif_dat: lcdifdatgrp {
12434+ fsl,pins = <
12435+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
12436+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
12437+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
12438+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
12439+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
12440+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
12441+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
12442+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
12443+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
12444+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
12445+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
12446+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
12447+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
12448+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
12449+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
12450+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
12451+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
12452+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
12453+ >;
12454+ };
12455+
12456 pinctrl_pwm8: pwm8grp {
12457 fsl,pins = <
12458 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
12459@@ -145,6 +322,12 @@ MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
12460 >;
12461 };
12462
12463+ pinctrl_stmpe: stmpegrp {
12464+ fsl,pins = <
12465+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
12466+ >;
12467+ };
12468+
12469 pinctrl_uart1: uart1grp {
12470 fsl,pins = <
12471 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
12472diff --git a/arch/arm/boot/dts/imx6ul-liteboard.dts b/arch/arm/boot/dts/imx6ul-liteboard.dts
12473index ed1d891d6a89..1d863a16bcf0 100644
12474--- a/arch/arm/boot/dts/imx6ul-liteboard.dts
12475+++ b/arch/arm/boot/dts/imx6ul-liteboard.dts
12476@@ -124,6 +124,10 @@ ethphy0: ethernet-phy@0 {
12477 };
12478 };
12479
12480+&snvs_poweroff {
12481+ status = "okay";
12482+};
12483+
12484 &uart1 {
12485 pinctrl-names = "default";
12486 pinctrl-0 = <&pinctrl_uart1>;
12487diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
12488index 6da2b77edd46..f11a241a340d 100644
12489--- a/arch/arm/boot/dts/imx6ul.dtsi
12490+++ b/arch/arm/boot/dts/imx6ul.dtsi
12491@@ -614,6 +614,7 @@ snvs_poweroff: snvs-poweroff {
12492 compatible = "syscon-poweroff";
12493 regmap = <&snvs>;
12494 offset = <0x38>;
12495+ value = <0x60>;
12496 mask = <0x60>;
12497 status = "disabled";
12498 };
12499diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
12500index d7753f79937a..0a3915868aa3 100644
12501--- a/arch/arm/boot/dts/imx7-colibri.dtsi
12502+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
12503@@ -106,6 +106,15 @@ &fec1 {
12504 fsl,magic-packet;
12505 };
12506
12507+&gpmi {
12508+ pinctrl-names = "default";
12509+ pinctrl-0 = <&pinctrl_gpmi_nand>;
12510+ fsl,use-minimum-ecc;
12511+ nand-on-flash-bbt;
12512+ nand-ecc-mode = "hw";
12513+ status = "okay";
12514+};
12515+
12516 &i2c1 {
12517 clock-frequency = <100000>;
12518 pinctrl-names = "default";
12519diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
12520index 0a24d1bf3c39..44637cabcc56 100644
12521--- a/arch/arm/boot/dts/imx7d-sdb.dts
12522+++ b/arch/arm/boot/dts/imx7d-sdb.dts
12523@@ -117,6 +117,37 @@ reg_brcm: regulator-brcm {
12524 regulator-max-microvolt = <3300000>;
12525 startup-delay-us = <200000>;
12526 };
12527+
12528+ reg_lcd_3v3: regulator-lcd-3v3 {
12529+ compatible = "regulator-fixed";
12530+ regulator-name = "lcd-3v3";
12531+ regulator-min-microvolt = <3300000>;
12532+ regulator-max-microvolt = <3300000>;
12533+ gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
12534+ };
12535+
12536+ reg_can2_3v3: regulator-can2-3v3 {
12537+ compatible = "regulator-fixed";
12538+ regulator-name = "can2-3v3";
12539+ pinctrl-names = "default";
12540+ pinctrl-0 = <&pinctrl_flexcan2_reg>;
12541+ regulator-min-microvolt = <3300000>;
12542+ regulator-max-microvolt = <3300000>;
12543+ gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
12544+ };
12545+
12546+ panel {
12547+ compatible = "innolux,at043tn24";
12548+ pinctrl-0 = <&pinctrl_backlight>;
12549+ enable-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
12550+ power-supply = <&reg_lcd_3v3>;
12551+
12552+ port {
12553+ panel_in: endpoint {
12554+ remote-endpoint = <&display_out>;
12555+ };
12556+ };
12557+ };
12558 };
12559
12560 &adc1 {
12561@@ -168,6 +199,7 @@ &fec1 {
12562 phy-mode = "rgmii";
12563 phy-handle = <&ethphy0>;
12564 fsl,magic-packet;
12565+ phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
12566 status = "okay";
12567
12568 mdio {
12569@@ -197,6 +229,13 @@ &fec2 {
12570 status = "okay";
12571 };
12572
12573+&flexcan2 {
12574+ pinctrl-names = "default";
12575+ pinctrl-0 = <&pinctrl_flexcan2>;
12576+ xceiver-supply = <&reg_can2_3v3>;
12577+ status = "okay";
12578+};
12579+
12580 &i2c1 {
12581 pinctrl-names = "default";
12582 pinctrl-0 = <&pinctrl_i2c1>;
12583@@ -285,8 +324,8 @@ vgen5_reg: vldo3 {
12584 };
12585
12586 vgen6_reg: vldo4 {
12587- regulator-min-microvolt = <1800000>;
12588- regulator-max-microvolt = <3300000>;
12589+ regulator-min-microvolt = <2800000>;
12590+ regulator-max-microvolt = <2800000>;
12591 regulator-always-on;
12592 };
12593 };
12594@@ -322,31 +361,11 @@ codec: wm8960@1a {
12595 &lcdif {
12596 pinctrl-names = "default";
12597 pinctrl-0 = <&pinctrl_lcdif>;
12598- display = <&display0>;
12599 status = "okay";
12600
12601- display0: display {
12602- bits-per-pixel = <16>;
12603- bus-width = <24>;
12604-
12605- display-timings {
12606- native-mode = <&timing0>;
12607-
12608- timing0: timing0 {
12609- clock-frequency = <9200000>;
12610- hactive = <480>;
12611- vactive = <272>;
12612- hfront-porch = <8>;
12613- hback-porch = <4>;
12614- hsync-len = <41>;
12615- vback-porch = <2>;
12616- vfront-porch = <4>;
12617- vsync-len = <10>;
12618- hsync-active = <0>;
12619- vsync-active = <0>;
12620- de-active = <1>;
12621- pixelclk-active = <0>;
12622- };
12623+ port {
12624+ display_out: endpoint {
12625+ remote-endpoint = <&panel_in>;
12626 };
12627 };
12628 };
12629@@ -356,12 +375,6 @@ &pcie {
12630 status = "okay";
12631 };
12632
12633-&pwm1 {
12634- pinctrl-names = "default";
12635- pinctrl-0 = <&pinctrl_pwm1>;
12636- status = "okay";
12637-};
12638-
12639 &uart1 {
12640 pinctrl-names = "default";
12641 pinctrl-0 = <&pinctrl_uart1>;
12642@@ -488,6 +501,20 @@ MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
12643 >;
12644 };
12645
12646+ pinctrl_flexcan2: flexcan2grp {
12647+ fsl,pins = <
12648+ MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
12649+ MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
12650+ >;
12651+ };
12652+
12653+ pinctrl_flexcan2_reg: flexcan2reggrp {
12654+ fsl,pins = <
12655+ MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */
12656+ >;
12657+ };
12658+
12659+
12660 pinctrl_hog: hoggrp {
12661 fsl,pins = <
12662 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
12663@@ -701,9 +728,9 @@ MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
12664 >;
12665 };
12666
12667- pinctrl_pwm1: pwm1grp {
12668+ pinctrl_backlight: backlightgrp {
12669 fsl,pins = <
12670- MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0
12671+ MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x110b0
12672 >;
12673 };
12674 };
12675diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
12676index 4cf6c458b583..82ad26e766eb 100644
12677--- a/arch/arm/boot/dts/imx7s.dtsi
12678+++ b/arch/arm/boot/dts/imx7s.dtsi
12679@@ -540,6 +540,7 @@ snvs_poweroff: snvs-poweroff {
12680 compatible = "syscon-poweroff";
12681 regmap = <&snvs>;
12682 offset = <0x38>;
12683+ value = <0x60>;
12684 mask = <0x60>;
12685 };
12686
12687@@ -1021,5 +1022,36 @@ fec1: ethernet@30be0000 {
12688 status = "disabled";
12689 };
12690 };
12691+
12692+ dma_apbh: dma-apbh@33000000 {
12693+ compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
12694+ reg = <0x33000000 0x2000>;
12695+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
12696+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
12697+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
12698+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
12699+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
12700+ #dma-cells = <1>;
12701+ dma-channels = <4>;
12702+ clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
12703+ };
12704+
12705+ gpmi: gpmi-nand@33002000{
12706+ compatible = "fsl,imx7d-gpmi-nand";
12707+ #address-cells = <1>;
12708+ #size-cells = <1>;
12709+ reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
12710+ reg-names = "gpmi-nand", "bch";
12711+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
12712+ interrupt-names = "bch";
12713+ clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
12714+ <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
12715+ clock-names = "gpmi_io", "gpmi_bch_apb";
12716+ dmas = <&dma_apbh 0>;
12717+ dma-names = "rx-tx";
12718+ status = "disabled";
12719+ assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
12720+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
12721+ };
12722 };
12723 };
12724diff --git a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/keystone-k2e-evm.dts
12725index ae1ebe7ee021..f1f32c54e72f 100644
12726--- a/arch/arm/boot/dts/keystone-k2e-evm.dts
12727+++ b/arch/arm/boot/dts/keystone-k2e-evm.dts
12728@@ -16,6 +16,19 @@ / {
12729 compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
12730 model = "Texas Instruments Keystone 2 Edison EVM";
12731
12732+ reserved-memory {
12733+ #address-cells = <2>;
12734+ #size-cells = <2>;
12735+ ranges;
12736+
12737+ dsp_common_memory: dsp-common-memory@81f800000 {
12738+ compatible = "shared-dma-pool";
12739+ reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
12740+ reusable;
12741+ status = "okay";
12742+ };
12743+ };
12744+
12745 soc {
12746
12747 clocks {
12748@@ -160,3 +173,8 @@ ethphy1: ethernet-phy@1 {
12749 reg = <1>;
12750 };
12751 };
12752+
12753+&dsp0 {
12754+ memory-region = <&dsp_common_memory>;
12755+ status = "okay";
12756+};
12757diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi
12758index 0dd4cdd6d40c..819ab8345916 100644
12759--- a/arch/arm/boot/dts/keystone-k2e.dtsi
12760+++ b/arch/arm/boot/dts/keystone-k2e.dtsi
12761@@ -45,6 +45,10 @@ cpu@3 {
12762 };
12763 };
12764
12765+ aliases {
12766+ rproc0 = &dsp0;
12767+ };
12768+
12769 soc {
12770 /include/ "keystone-k2e-clocks.dtsi"
12771
12772@@ -114,6 +118,22 @@ dspgpio0: keystone_dsp_gpio@02620240 {
12773 gpio,syscon-dev = <&devctrl 0x240>;
12774 };
12775
12776+ dsp0: dsp@10800000 {
12777+ compatible = "ti,k2e-dsp";
12778+ reg = <0x10800000 0x00080000>,
12779+ <0x10e00000 0x00008000>,
12780+ <0x10f00000 0x00008000>;
12781+ reg-names = "l2sram", "l1pram", "l1dram";
12782+ clocks = <&clkgem0>;
12783+ ti,syscon-dev = <&devctrl 0x844>;
12784+ resets = <&pscrst 0>;
12785+ interrupt-parent = <&kirq0>;
12786+ interrupts = <0 8>;
12787+ interrupt-names = "vring", "exception";
12788+ kick-gpios = <&dspgpio0 27 0>;
12789+ status = "disabled";
12790+ };
12791+
12792 pcie1: pcie@21020000 {
12793 compatible = "ti,keystone-pcie","snps,dw-pcie";
12794 clocks = <&clkpcie1>;
12795diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts
12796index 61883cb969d2..f462f1043531 100644
12797--- a/arch/arm/boot/dts/keystone-k2g-evm.dts
12798+++ b/arch/arm/boot/dts/keystone-k2g-evm.dts
12799@@ -25,6 +25,26 @@ memory@800000000 {
12800 reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
12801 };
12802
12803+ reserved-memory {
12804+ #address-cells = <2>;
12805+ #size-cells = <2>;
12806+ ranges;
12807+
12808+ dsp_common_memory: dsp-common-memory@81f800000 {
12809+ compatible = "shared-dma-pool";
12810+ reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
12811+ reusable;
12812+ status = "okay";
12813+ };
12814+ };
12815+
12816+ vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin {
12817+ compatible = "regulator-fixed";
12818+ regulator-name = "mmc0_fixed";
12819+ regulator-min-microvolt = <3300000>;
12820+ regulator-max-microvolt = <3300000>;
12821+ regulator-always-on;
12822+ };
12823 };
12824
12825 &k2g_pinctrl {
12826@@ -34,6 +54,33 @@ K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.
12827 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
12828 >;
12829 };
12830+
12831+ mmc0_pins: pinmux_mmc0_pins {
12832+ pinctrl-single,pins = <
12833+ K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */
12834+ K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */
12835+ K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */
12836+ K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */
12837+ K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */
12838+ K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */
12839+ K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc0_sdcd.gpio1_12 */
12840+ >;
12841+ };
12842+
12843+ mmc1_pins: pinmux_mmc1_pins {
12844+ pinctrl-single,pins = <
12845+ K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */
12846+ K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */
12847+ K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat5.mmc1_dat5 */
12848+ K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat4.mmc1_dat4 */
12849+ K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
12850+ K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
12851+ K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
12852+ K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
12853+ K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
12854+ K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
12855+ >;
12856+ };
12857 };
12858
12859 &uart0 {
12860@@ -41,3 +88,27 @@ &uart0 {
12861 pinctrl-0 = <&uart0_pins>;
12862 status = "okay";
12863 };
12864+
12865+&gpio1 {
12866+ status = "okay";
12867+};
12868+
12869+&mmc0 {
12870+ pinctrl-names = "default";
12871+ pinctrl-0 = <&mmc0_pins>;
12872+ vmmc-supply = <&vcc3v3_dcin_reg>;
12873+ cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
12874+ status = "okay";
12875+};
12876+
12877+&mmc1 {
12878+ pinctrl-names = "default";
12879+ pinctrl-0 = <&mmc1_pins>;
12880+ vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */
12881+ status = "okay";
12882+};
12883+
12884+&dsp0 {
12885+ memory-region = <&dsp_common_memory>;
12886+ status = "okay";
12887+};
12888diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts
12889index d820d37b5148..78692745e0af 100644
12890--- a/arch/arm/boot/dts/keystone-k2g-ice.dts
12891+++ b/arch/arm/boot/dts/keystone-k2g-ice.dts
12892@@ -17,6 +17,19 @@ memory@800000000 {
12893 device_type = "memory";
12894 reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
12895 };
12896+
12897+ reserved-memory {
12898+ #address-cells = <2>;
12899+ #size-cells = <2>;
12900+ ranges;
12901+
12902+ dsp_common_memory: dsp-common-memory@81f800000 {
12903+ compatible = "shared-dma-pool";
12904+ reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
12905+ reusable;
12906+ status = "okay";
12907+ };
12908+ };
12909 };
12910
12911 &k2g_pinctrl {
12912@@ -33,3 +46,8 @@ &uart0 {
12913 pinctrl-0 = <&uart0_pins>;
12914 status = "okay";
12915 };
12916+
12917+&dsp0 {
12918+ memory-region = <&dsp_common_memory>;
12919+ status = "okay";
12920+};
12921diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
12922index a789f75a1ed5..826b286665e6 100644
12923--- a/arch/arm/boot/dts/keystone-k2g.dtsi
12924+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
12925@@ -15,6 +15,7 @@
12926
12927 #include <dt-bindings/interrupt-controller/arm-gic.h>
12928 #include <dt-bindings/pinctrl/keystone.h>
12929+#include <dt-bindings/gpio/gpio.h>
12930
12931 / {
12932 compatible = "ti,k2g","ti,keystone";
12933@@ -27,6 +28,7 @@ / {
12934
12935 aliases {
12936 serial0 = &uart0;
12937+ rproc0 = &dsp0;
12938 };
12939
12940 cpus {
12941@@ -113,6 +115,24 @@ uart0: serial@02530c00 {
12942 status = "disabled";
12943 };
12944
12945+ dcan0: can@0260B200 {
12946+ compatible = "ti,am4372-d_can", "ti,am3352-d_can";
12947+ reg = <0x0260B200 0x200>;
12948+ interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
12949+ status = "disabled";
12950+ power-domains = <&k2g_pds 0x0008>;
12951+ clocks = <&k2g_clks 0x0008 1>;
12952+ };
12953+
12954+ dcan1: can@0260B400 {
12955+ compatible = "ti,am4372-d_can", "ti,am3352-d_can";
12956+ reg = <0x0260B400 0x200>;
12957+ interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
12958+ status = "disabled";
12959+ power-domains = <&k2g_pds 0x0009>;
12960+ clocks = <&k2g_clks 0x0009 1>;
12961+ };
12962+
12963 kirq0: keystone_irq@026202a0 {
12964 compatible = "ti,keystone-irq";
12965 interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>;
12966@@ -128,6 +148,22 @@ dspgpio0: keystone_dsp_gpio@02620240 {
12967 gpio,syscon-dev = <&devctrl 0x240>;
12968 };
12969
12970+ dsp0: dsp@10800000 {
12971+ compatible = "ti,k2g-dsp";
12972+ reg = <0x10800000 0x00100000>,
12973+ <0x10e00000 0x00008000>,
12974+ <0x10f00000 0x00008000>;
12975+ reg-names = "l2sram", "l1pram", "l1dram";
12976+ power-domains = <&k2g_pds 0x0046>;
12977+ ti,syscon-dev = <&devctrl 0x844>;
12978+ resets = <&k2g_reset 0x0046 0x1>;
12979+ interrupt-parent = <&kirq0>;
12980+ interrupts = <0 8>;
12981+ interrupt-names = "vring", "exception";
12982+ kick-gpios = <&dspgpio0 27 0>;
12983+ status = "disabled";
12984+ };
12985+
12986 msgmgr: msgmgr@02a00000 {
12987 compatible = "ti,k2g-message-manager";
12988 #mbox-cells = <2>;
12989@@ -139,5 +175,173 @@ msgmgr: msgmgr@02a00000 {
12990 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
12991 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
12992 };
12993+
12994+ pmmc: pmmc@02921c00 {
12995+ compatible = "ti,k2g-sci";
12996+ /*
12997+ * In case of rare platforms that does not use k2g as
12998+ * system master, use /delete-property/
12999+ */
13000+ ti,system-reboot-controller;
13001+ mbox-names = "rx", "tx";
13002+ mboxes= <&msgmgr 5 2>,
13003+ <&msgmgr 0 0>;
13004+ reg-names = "debug_messages";
13005+ reg = <0x02921c00 0x400>;
13006+
13007+ k2g_pds: power-controller {
13008+ compatible = "ti,sci-pm-domain";
13009+ #power-domain-cells = <1>;
13010+ };
13011+
13012+ k2g_clks: clocks {
13013+ compatible = "ti,k2g-sci-clk";
13014+ #clock-cells = <2>;
13015+ };
13016+
13017+ k2g_reset: reset-controller {
13018+ compatible = "ti,sci-reset";
13019+ #reset-cells = <2>;
13020+ };
13021+ };
13022+
13023+ gpio0: gpio@2603000 {
13024+ compatible = "ti,k2g-gpio", "ti,keystone-gpio";
13025+ reg = <0x02603000 0x100>;
13026+ gpio-controller;
13027+ #gpio-cells = <2>;
13028+
13029+ interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
13030+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
13031+ <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
13032+ <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
13033+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
13034+ <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
13035+ <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
13036+ <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
13037+ <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;
13038+ interrupt-controller;
13039+ #interrupt-cells = <2>;
13040+ ti,ngpio = <144>;
13041+ ti,davinci-gpio-unbanked = <0>;
13042+ clocks = <&k2g_clks 0x001b 0x0>;
13043+ clock-names = "gpio";
13044+ };
13045+
13046+ gpio1: gpio@260a000 {
13047+ compatible = "ti,k2g-gpio", "ti,keystone-gpio";
13048+ reg = <0x0260a000 0x100>;
13049+ gpio-controller;
13050+ #gpio-cells = <2>;
13051+ interrupts = <GIC_SPI 442 IRQ_TYPE_EDGE_RISING>,
13052+ <GIC_SPI 443 IRQ_TYPE_EDGE_RISING>,
13053+ <GIC_SPI 444 IRQ_TYPE_EDGE_RISING>,
13054+ <GIC_SPI 445 IRQ_TYPE_EDGE_RISING>,
13055+ <GIC_SPI 446 IRQ_TYPE_EDGE_RISING>;
13056+ interrupt-controller;
13057+ #interrupt-cells = <2>;
13058+ ti,ngpio = <68>;
13059+ ti,davinci-gpio-unbanked = <0>;
13060+ clocks = <&k2g_clks 0x001c 0x0>;
13061+ clock-names = "gpio";
13062+ };
13063+
13064+ edma0: edma@02700000 {
13065+ compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
13066+ reg = <0x02700000 0x8000>;
13067+ reg-names = "edma3_cc";
13068+ interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
13069+ <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>,
13070+ <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
13071+ interrupt-names = "edma3_ccint", "emda3_mperr",
13072+ "edma3_ccerrint";
13073+ dma-requests = <64>;
13074+ #dma-cells = <2>;
13075+
13076+ ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
13077+
13078+ ti,edma-memcpy-channels = <32 33 34 35>;
13079+
13080+ power-domains = <&k2g_pds 0x3f>;
13081+ };
13082+
13083+ edma0_tptc0: tptc@02760000 {
13084+ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
13085+ reg = <0x02760000 0x400>;
13086+ power-domains = <&k2g_pds 0x3f>;
13087+ };
13088+
13089+ edma0_tptc1: tptc@02768000 {
13090+ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
13091+ reg = <0x02768000 0x400>;
13092+ power-domains = <&k2g_pds 0x3f>;
13093+ };
13094+
13095+ edma1: edma@02728000 {
13096+ compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
13097+ reg = <0x02728000 0x8000>;
13098+ reg-names = "edma3_cc";
13099+ interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
13100+ <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
13101+ <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
13102+ interrupt-names = "edma3_ccint", "emda3_mperr",
13103+ "edma3_ccerrint";
13104+ dma-requests = <64>;
13105+ #dma-cells = <2>;
13106+
13107+ ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;
13108+
13109+ /*
13110+ * memcpy is disabled, can be enabled with:
13111+ * ti,edma-memcpy-channels = <12 13 14 15>;
13112+ * for example.
13113+ */
13114+
13115+ power-domains = <&k2g_pds 0x4f>;
13116+ };
13117+
13118+ edma1_tptc0: tptc@027b0000 {
13119+ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
13120+ reg = <0x027b0000 0x400>;
13121+ power-domains = <&k2g_pds 0x4f>;
13122+ };
13123+
13124+ edma1_tptc1: tptc@027b8000 {
13125+ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
13126+ reg = <0x027b8000 0x400>;
13127+ power-domains = <&k2g_pds 0x4f>;
13128+ };
13129+
13130+ mmc0: mmc@23000000 {
13131+ compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
13132+ reg = <0x23000000 0x400>;
13133+ interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
13134+ dmas = <&edma1 24 0>, <&edma1 25 0>;
13135+ dma-names = "tx", "rx";
13136+ bus-width = <4>;
13137+ ti,needs-special-reset;
13138+ no-1-8-v;
13139+ max-frequency = <96000000>;
13140+ power-domains = <&k2g_pds 0xb>;
13141+ clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
13142+ clock-names = "fck", "mmchsdb_fck";
13143+ status = "disabled";
13144+ };
13145+
13146+ mmc1: mmc@23100000 {
13147+ compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
13148+ reg = <0x23100000 0x400>;
13149+ interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
13150+ dmas = <&edma1 26 0>, <&edma1 27 0>;
13151+ dma-names = "tx", "rx";
13152+ bus-width = <8>;
13153+ ti,needs-special-reset;
13154+ ti,non-removable;
13155+ max-frequency = <96000000>;
13156+ power-domains = <&k2g_pds 0xc>;
13157+ clocks = <&k2g_clks 0xc 1>, <&k2g_clks 0xc 2>;
13158+ clock-names = "fck", "mmchsdb_fck";
13159+ status = "disabled";
13160+ };
13161 };
13162 };
13163diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts
13164index 2156ff92d08f..6dd13b98aaba 100644
13165--- a/arch/arm/boot/dts/keystone-k2hk-evm.dts
13166+++ b/arch/arm/boot/dts/keystone-k2hk-evm.dts
13167@@ -16,6 +16,19 @@ / {
13168 compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
13169 model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
13170
13171+ reserved-memory {
13172+ #address-cells = <2>;
13173+ #size-cells = <2>;
13174+ ranges;
13175+
13176+ dsp_common_memory: dsp-common-memory@81f800000 {
13177+ compatible = "shared-dma-pool";
13178+ reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
13179+ reusable;
13180+ status = "okay";
13181+ };
13182+ };
13183+
13184 soc {
13185 clocks {
13186 refclksys: refclksys {
13187@@ -184,3 +197,43 @@ ethphy1: ethernet-phy@1 {
13188 reg = <1>;
13189 };
13190 };
13191+
13192+&dsp0 {
13193+ memory-region = <&dsp_common_memory>;
13194+ status = "okay";
13195+};
13196+
13197+&dsp1 {
13198+ memory-region = <&dsp_common_memory>;
13199+ status = "okay";
13200+};
13201+
13202+&dsp2 {
13203+ memory-region = <&dsp_common_memory>;
13204+ status = "okay";
13205+};
13206+
13207+&dsp3 {
13208+ memory-region = <&dsp_common_memory>;
13209+ status = "okay";
13210+};
13211+
13212+&dsp4 {
13213+ memory-region = <&dsp_common_memory>;
13214+ status = "okay";
13215+};
13216+
13217+&dsp5 {
13218+ memory-region = <&dsp_common_memory>;
13219+ status = "okay";
13220+};
13221+
13222+&dsp6 {
13223+ memory-region = <&dsp_common_memory>;
13224+ status = "okay";
13225+};
13226+
13227+&dsp7 {
13228+ memory-region = <&dsp_common_memory>;
13229+ status = "okay";
13230+};
13231diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi
13232index 69d449430511..31dc00e4e5fd 100644
13233--- a/arch/arm/boot/dts/keystone-k2hk.dtsi
13234+++ b/arch/arm/boot/dts/keystone-k2hk.dtsi
13235@@ -45,6 +45,17 @@ cpu@3 {
13236 };
13237 };
13238
13239+ aliases {
13240+ rproc0 = &dsp0;
13241+ rproc1 = &dsp1;
13242+ rproc2 = &dsp2;
13243+ rproc3 = &dsp3;
13244+ rproc4 = &dsp4;
13245+ rproc5 = &dsp5;
13246+ rproc6 = &dsp6;
13247+ rproc7 = &dsp7;
13248+ };
13249+
13250 soc {
13251 /include/ "keystone-k2hk-clocks.dtsi"
13252
13253@@ -134,6 +145,134 @@ dspgpio7: keystone_dsp_gpio@262025c {
13254 gpio,syscon-dev = <&devctrl 0x25c>;
13255 };
13256
13257+ dsp0: dsp@10800000 {
13258+ compatible = "ti,k2hk-dsp";
13259+ reg = <0x10800000 0x00100000>,
13260+ <0x10e00000 0x00008000>,
13261+ <0x10f00000 0x00008000>;
13262+ reg-names = "l2sram", "l1pram", "l1dram";
13263+ clocks = <&clkgem0>;
13264+ ti,syscon-dev = <&devctrl 0x40>;
13265+ resets = <&pscrst 0>;
13266+ interrupt-parent = <&kirq0>;
13267+ interrupts = <0 8>;
13268+ interrupt-names = "vring", "exception";
13269+ kick-gpios = <&dspgpio0 27 0>;
13270+ status = "disabled";
13271+ };
13272+
13273+ dsp1: dsp@11800000 {
13274+ compatible = "ti,k2hk-dsp";
13275+ reg = <0x11800000 0x00100000>,
13276+ <0x11e00000 0x00008000>,
13277+ <0x11f00000 0x00008000>;
13278+ reg-names = "l2sram", "l1pram", "l1dram";
13279+ clocks = <&clkgem1>;
13280+ ti,syscon-dev = <&devctrl 0x44>;
13281+ resets = <&pscrst 1>;
13282+ interrupt-parent = <&kirq0>;
13283+ interrupts = <1 9>;
13284+ interrupt-names = "vring", "exception";
13285+ kick-gpios = <&dspgpio1 27 0>;
13286+ status = "disabled";
13287+ };
13288+
13289+ dsp2: dsp@12800000 {
13290+ compatible = "ti,k2hk-dsp";
13291+ reg = <0x12800000 0x00100000>,
13292+ <0x12e00000 0x00008000>,
13293+ <0x12f00000 0x00008000>;
13294+ reg-names = "l2sram", "l1pram", "l1dram";
13295+ clocks = <&clkgem2>;
13296+ ti,syscon-dev = <&devctrl 0x48>;
13297+ resets = <&pscrst 2>;
13298+ interrupt-parent = <&kirq0>;
13299+ interrupts = <2 10>;
13300+ interrupt-names = "vring", "exception";
13301+ kick-gpios = <&dspgpio2 27 0>;
13302+ status = "disabled";
13303+ };
13304+
13305+ dsp3: dsp@13800000 {
13306+ compatible = "ti,k2hk-dsp";
13307+ reg = <0x13800000 0x00100000>,
13308+ <0x13e00000 0x00008000>,
13309+ <0x13f00000 0x00008000>;
13310+ reg-names = "l2sram", "l1pram", "l1dram";
13311+ clocks = <&clkgem3>;
13312+ ti,syscon-dev = <&devctrl 0x4c>;
13313+ resets = <&pscrst 3>;
13314+ interrupt-parent = <&kirq0>;
13315+ interrupts = <3 11>;
13316+ interrupt-names = "vring", "exception";
13317+ kick-gpios = <&dspgpio3 27 0>;
13318+ status = "disabled";
13319+ };
13320+
13321+ dsp4: dsp@14800000 {
13322+ compatible = "ti,k2hk-dsp";
13323+ reg = <0x14800000 0x00100000>,
13324+ <0x14e00000 0x00008000>,
13325+ <0x14f00000 0x00008000>;
13326+ reg-names = "l2sram", "l1pram", "l1dram";
13327+ clocks = <&clkgem4>;
13328+ ti,syscon-dev = <&devctrl 0x50>;
13329+ resets = <&pscrst 4>;
13330+ interrupt-parent = <&kirq0>;
13331+ interrupts = <4 12>;
13332+ interrupt-names = "vring", "exception";
13333+ kick-gpios = <&dspgpio4 27 0>;
13334+ status = "disabled";
13335+ };
13336+
13337+ dsp5: dsp@15800000 {
13338+ compatible = "ti,k2hk-dsp";
13339+ reg = <0x15800000 0x00100000>,
13340+ <0x15e00000 0x00008000>,
13341+ <0x15f00000 0x00008000>;
13342+ reg-names = "l2sram", "l1pram", "l1dram";
13343+ clocks = <&clkgem5>;
13344+ ti,syscon-dev = <&devctrl 0x54>;
13345+ resets = <&pscrst 5>;
13346+ interrupt-parent = <&kirq0>;
13347+ interrupts = <5 13>;
13348+ interrupt-names = "vring", "exception";
13349+ kick-gpios = <&dspgpio5 27 0>;
13350+ status = "disabled";
13351+ };
13352+
13353+ dsp6: dsp@16800000 {
13354+ compatible = "ti,k2hk-dsp";
13355+ reg = <0x16800000 0x00100000>,
13356+ <0x16e00000 0x00008000>,
13357+ <0x16f00000 0x00008000>;
13358+ reg-names = "l2sram", "l1pram", "l1dram";
13359+ clocks = <&clkgem6>;
13360+ ti,syscon-dev = <&devctrl 0x58>;
13361+ resets = <&pscrst 6>;
13362+ interrupt-parent = <&kirq0>;
13363+ interrupts = <6 14>;
13364+ interrupt-names = "vring", "exception";
13365+ kick-gpios = <&dspgpio6 27 0>;
13366+ status = "disabled";
13367+ };
13368+
13369+ dsp7: dsp@17800000 {
13370+ compatible = "ti,k2hk-dsp";
13371+ reg = <0x17800000 0x00100000>,
13372+ <0x17e00000 0x00008000>,
13373+ <0x17f00000 0x00008000>;
13374+ reg-names = "l2sram", "l1pram", "l1dram";
13375+ clocks = <&clkgem7>;
13376+ ti,syscon-dev = <&devctrl 0x5c>;
13377+ resets = <&pscrst 7>;
13378+ interrupt-parent = <&kirq0>;
13379+ interrupts = <7 15>;
13380+ interrupt-names = "vring", "exception";
13381+ kick-gpios = <&dspgpio7 27 0>;
13382+ status = "disabled";
13383+ };
13384+
13385 mdio: mdio@02090300 {
13386 compatible = "ti,keystone_mdio", "ti,davinci_mdio";
13387 #address-cells = <1>;
13388diff --git a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/keystone-k2l-evm.dts
13389index 056b42f99d7a..528667618db4 100644
13390--- a/arch/arm/boot/dts/keystone-k2l-evm.dts
13391+++ b/arch/arm/boot/dts/keystone-k2l-evm.dts
13392@@ -16,6 +16,19 @@ / {
13393 compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone";
13394 model = "Texas Instruments Keystone 2 Lamarr EVM";
13395
13396+ reserved-memory {
13397+ #address-cells = <2>;
13398+ #size-cells = <2>;
13399+ ranges;
13400+
13401+ dsp_common_memory: dsp-common-memory@81f800000 {
13402+ compatible = "shared-dma-pool";
13403+ reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
13404+ reusable;
13405+ status = "okay";
13406+ };
13407+ };
13408+
13409 soc {
13410 clocks {
13411 refclksys: refclksys {
13412@@ -133,3 +146,23 @@ ethphy1: ethernet-phy@1 {
13413 reg = <1>;
13414 };
13415 };
13416+
13417+&dsp0 {
13418+ memory-region = <&dsp_common_memory>;
13419+ status = "okay";
13420+};
13421+
13422+&dsp1 {
13423+ memory-region = <&dsp_common_memory>;
13424+ status = "okay";
13425+};
13426+
13427+&dsp2 {
13428+ memory-region = <&dsp_common_memory>;
13429+ status = "okay";
13430+};
13431+
13432+&dsp3 {
13433+ memory-region = <&dsp_common_memory>;
13434+ status = "okay";
13435+};
13436diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi
13437index 148650406cf7..4431310bc922 100644
13438--- a/arch/arm/boot/dts/keystone-k2l.dtsi
13439+++ b/arch/arm/boot/dts/keystone-k2l.dtsi
13440@@ -33,6 +33,13 @@ cpu@1 {
13441 };
13442 };
13443
13444+ aliases {
13445+ rproc0 = &dsp0;
13446+ rproc1 = &dsp1;
13447+ rproc2 = &dsp2;
13448+ rproc3 = &dsp3;
13449+ };
13450+
13451 soc {
13452 /include/ "keystone-k2l-clocks.dtsi"
13453
13454@@ -268,6 +275,70 @@ dspgpio3: keystone_dsp_gpio@262024c {
13455 gpio,syscon-dev = <&devctrl 0x24c>;
13456 };
13457
13458+ dsp0: dsp@10800000 {
13459+ compatible = "ti,k2l-dsp";
13460+ reg = <0x10800000 0x00100000>,
13461+ <0x10e00000 0x00008000>,
13462+ <0x10f00000 0x00008000>;
13463+ reg-names = "l2sram", "l1pram", "l1dram";
13464+ clocks = <&clkgem0>;
13465+ ti,syscon-dev = <&devctrl 0x844>;
13466+ resets = <&pscrst 0>;
13467+ interrupt-parent = <&kirq0>;
13468+ interrupts = <0 8>;
13469+ interrupt-names = "vring", "exception";
13470+ kick-gpios = <&dspgpio0 27 0>;
13471+ status = "disabled";
13472+ };
13473+
13474+ dsp1: dsp@11800000 {
13475+ compatible = "ti,k2l-dsp";
13476+ reg = <0x11800000 0x00100000>,
13477+ <0x11e00000 0x00008000>,
13478+ <0x11f00000 0x00008000>;
13479+ reg-names = "l2sram", "l1pram", "l1dram";
13480+ clocks = <&clkgem1>;
13481+ ti,syscon-dev = <&devctrl 0x848>;
13482+ resets = <&pscrst 1>;
13483+ interrupt-parent = <&kirq0>;
13484+ interrupts = <1 9>;
13485+ interrupt-names = "vring", "exception";
13486+ kick-gpios = <&dspgpio1 27 0>;
13487+ status = "disabled";
13488+ };
13489+
13490+ dsp2: dsp@12800000 {
13491+ compatible = "ti,k2l-dsp";
13492+ reg = <0x12800000 0x00100000>,
13493+ <0x12e00000 0x00008000>,
13494+ <0x12f00000 0x00008000>;
13495+ reg-names = "l2sram", "l1pram", "l1dram";
13496+ clocks = <&clkgem2>;
13497+ ti,syscon-dev = <&devctrl 0x84c>;
13498+ resets = <&pscrst 2>;
13499+ interrupt-parent = <&kirq0>;
13500+ interrupts = <2 10>;
13501+ interrupt-names = "vring", "exception";
13502+ kick-gpios = <&dspgpio2 27 0>;
13503+ status = "disabled";
13504+ };
13505+
13506+ dsp3: dsp@13800000 {
13507+ compatible = "ti,k2l-dsp";
13508+ reg = <0x13800000 0x00100000>,
13509+ <0x13e00000 0x00008000>,
13510+ <0x13f00000 0x00008000>;
13511+ reg-names = "l2sram", "l1pram", "l1dram";
13512+ clocks = <&clkgem3>;
13513+ ti,syscon-dev = <&devctrl 0x850>;
13514+ resets = <&pscrst 3>;
13515+ interrupt-parent = <&kirq0>;
13516+ interrupts = <3 11>;
13517+ interrupt-names = "vring", "exception";
13518+ kick-gpios = <&dspgpio3 27 0>;
13519+ status = "disabled";
13520+ };
13521+
13522 mdio: mdio@26200f00 {
13523 compatible = "ti,keystone_mdio", "ti,davinci_mdio";
13524 #address-cells = <1>;
13525diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi
13526index d573e03f3134..f003f3f1bd65 100644
13527--- a/arch/arm/boot/dts/kirkwood-6192.dtsi
13528+++ b/arch/arm/boot/dts/kirkwood-6192.dtsi
13529@@ -1,6 +1,6 @@
13530 / {
13531 mbus@f1000000 {
13532- pciec: pcie-controller@82000000 {
13533+ pciec: pcie@82000000 {
13534 compatible = "marvell,kirkwood-pcie";
13535 status = "disabled";
13536 device_type = "pci";
13537@@ -24,6 +24,7 @@ pcie0: pcie@1,0 {
13538 #interrupt-cells = <1>;
13539 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
13540 0x81000000 0 0 0x81000000 0x1 0 1 0>;
13541+ bus-range = <0x00 0xff>;
13542 interrupt-map-mask = <0 0 0 0>;
13543 interrupt-map = <0 0 0 0 &intc 9>;
13544 marvell,pcie-port = <0>;
13545diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
13546index 748d0b62f233..47d4b3d3d9e9 100644
13547--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
13548+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
13549@@ -1,6 +1,6 @@
13550 / {
13551 mbus@f1000000 {
13552- pciec: pcie-controller@82000000 {
13553+ pciec: pcie@82000000 {
13554 compatible = "marvell,kirkwood-pcie";
13555 status = "disabled";
13556 device_type = "pci";
13557@@ -24,6 +24,7 @@ pcie0: pcie@1,0 {
13558 #interrupt-cells = <1>;
13559 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
13560 0x81000000 0 0 0x81000000 0x1 0 1 0>;
13561+ bus-range = <0x00 0xff>;
13562 interrupt-map-mask = <0 0 0 0>;
13563 interrupt-map = <0 0 0 0 &intc 9>;
13564 marvell,pcie-port = <0>;
13565diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
13566index bb63d2d50fc5..a13dad0a7c08 100644
13567--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
13568+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
13569@@ -1,6 +1,6 @@
13570 / {
13571 mbus@f1000000 {
13572- pciec: pcie-controller@82000000 {
13573+ pciec: pcie@82000000 {
13574 compatible = "marvell,kirkwood-pcie";
13575 status = "disabled";
13576 device_type = "pci";
13577@@ -28,6 +28,7 @@ pcie0: pcie@1,0 {
13578 #interrupt-cells = <1>;
13579 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
13580 0x81000000 0 0 0x81000000 0x1 0 1 0>;
13581+ bus-range = <0x00 0xff>;
13582 interrupt-map-mask = <0 0 0 0>;
13583 interrupt-map = <0 0 0 0 &intc 9>;
13584 marvell,pcie-port = <0>;
13585@@ -45,6 +46,7 @@ pcie1: pcie@2,0 {
13586 #interrupt-cells = <1>;
13587 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
13588 0x81000000 0 0 0x81000000 0x2 0 1 0>;
13589+ bus-range = <0x00 0xff>;
13590 interrupt-map-mask = <0 0 0 0>;
13591 interrupt-map = <0 0 0 0 &intc 10>;
13592 marvell,pcie-port = <1>;
13593diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
13594index 720c210d491d..90d4d71b6683 100644
13595--- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
13596+++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
13597@@ -1,6 +1,6 @@
13598 / {
13599 mbus@f1000000 {
13600- pciec: pcie-controller@82000000 {
13601+ pciec: pcie@82000000 {
13602 compatible = "marvell,kirkwood-pcie";
13603 status = "disabled";
13604 device_type = "pci";
13605@@ -24,6 +24,7 @@ pcie0: pcie@1,0 {
13606 #interrupt-cells = <1>;
13607 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
13608 0x81000000 0 0 0x81000000 0x1 0 1 0>;
13609+ bus-range = <0x00 0xff>;
13610 interrupt-map-mask = <0 0 0 0>;
13611 interrupt-map = <0 0 0 0 &intc 9>;
13612 marvell,pcie-port = <0>;
13613diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
13614index 43e9364083de..b4575bbaf085 100644
13615--- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
13616+++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
13617@@ -192,7 +192,7 @@ &mmc1 {
13618 interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
13619 pinctrl-names = "default";
13620 pinctrl-0 = <&mmc1_pins &mmc1_cd>;
13621- cd-gpios = <&gpio4 31 IRQ_TYPE_LEVEL_LOW>; /* gpio127 */
13622+ cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio127 */
13623 vmmc-supply = <&vmmc1>;
13624 bus-width = <4>;
13625 cap-power-off-card;
13626diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
13627index 15204e44161d..cd6ad072e72c 100644
13628--- a/arch/arm/boot/dts/meson.dtsi
13629+++ b/arch/arm/boot/dts/meson.dtsi
13630@@ -86,14 +86,14 @@ hwrng: rng@8100 {
13631 };
13632
13633 uart_A: serial@84c0 {
13634- compatible = "amlogic,meson-uart";
13635+ compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
13636 reg = <0x84c0 0x18>;
13637 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
13638 status = "disabled";
13639 };
13640
13641 uart_B: serial@84dc {
13642- compatible = "amlogic,meson-uart";
13643+ compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
13644 reg = <0x84dc 0x18>;
13645 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
13646 status = "disabled";
13647@@ -108,6 +108,20 @@ i2c_A: i2c@8500 {
13648 status = "disabled";
13649 };
13650
13651+ pwm_ab: pwm@8550 {
13652+ compatible = "amlogic,meson-pwm";
13653+ reg = <0x8550 0x10>;
13654+ #pwm-cells = <3>;
13655+ status = "disabled";
13656+ };
13657+
13658+ pwm_cd: pwm@8650 {
13659+ compatible = "amlogic,meson-pwm";
13660+ reg = <0x8650 0x10>;
13661+ #pwm-cells = <3>;
13662+ status = "disabled";
13663+ };
13664+
13665 saradc: adc@8680 {
13666 compatible = "amlogic,meson-saradc";
13667 reg = <0x8680 0x34>;
13668@@ -117,7 +131,7 @@ saradc: adc@8680 {
13669 };
13670
13671 uart_C: serial@8700 {
13672- compatible = "amlogic,meson-uart";
13673+ compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
13674 reg = <0x8700 0x18>;
13675 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
13676 status = "disabled";
13677@@ -182,7 +196,7 @@ ir_receiver: ir-receiver@480 {
13678 };
13679
13680 uart_AO: serial@4c0 {
13681- compatible = "amlogic,meson-uart";
13682+ compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart";
13683 reg = <0x4c0 0x18>;
13684 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
13685 status = "disabled";
13686@@ -230,5 +244,13 @@ ethmac: ethernet@c9410000 {
13687 interrupt-names = "macirq";
13688 status = "disabled";
13689 };
13690+
13691+ ahb_sram: sram@d9000000 {
13692+ compatible = "mmio-sram";
13693+ reg = <0xd9000000 0x20000>;
13694+ #address-cells = <1>;
13695+ #size-cells = <1>;
13696+ ranges = <0 0xd9000000 0x20000>;
13697+ };
13698 };
13699 }; /* end of / */
13700diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
13701index 8557b6117a4b..ef281d290052 100644
13702--- a/arch/arm/boot/dts/meson6.dtsi
13703+++ b/arch/arm/boot/dts/meson6.dtsi
13704@@ -70,9 +70,37 @@ cpu@201 {
13705 };
13706 };
13707
13708+ xtal: xtal-clk {
13709+ compatible = "fixed-clock";
13710+ clock-frequency = <24000000>;
13711+ clock-output-names = "xtal";
13712+ #clock-cells = <0>;
13713+ };
13714+
13715 clk81: clk@0 {
13716 #clock-cells = <0>;
13717 compatible = "fixed-clock";
13718 clock-frequency = <200000000>;
13719 };
13720 }; /* end of / */
13721+
13722+
13723+&uart_AO {
13724+ clocks = <&xtal>, <&clk81>, <&clk81>;
13725+ clock-names = "xtal", "pclk", "baud";
13726+};
13727+
13728+&uart_A {
13729+ clocks = <&xtal>, <&clk81>, <&clk81>;
13730+ clock-names = "xtal", "pclk", "baud";
13731+};
13732+
13733+&uart_B {
13734+ clocks = <&xtal>, <&clk81>, <&clk81>;
13735+ clock-names = "xtal", "pclk", "baud";
13736+};
13737+
13738+&uart_C {
13739+ clocks = <&xtal>, <&clk81>, <&clk81>;
13740+ clock-names = "xtal", "pclk", "baud";
13741+};
13742diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
13743index cada35828931..b98d44fde6b6 100644
13744--- a/arch/arm/boot/dts/meson8.dtsi
13745+++ b/arch/arm/boot/dts/meson8.dtsi
13746@@ -168,10 +168,18 @@ mux {
13747 &cbus {
13748 clkc: clock-controller@4000 {
13749 #clock-cells = <1>;
13750+ #reset-cells = <1>;
13751 compatible = "amlogic,meson8-clkc";
13752 reg = <0x8000 0x4>, <0x4000 0x460>;
13753 };
13754
13755+ pwm_ef: pwm@86c0 {
13756+ compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
13757+ reg = <0x86c0 0x10>;
13758+ #pwm-cells = <3>;
13759+ status = "disabled";
13760+ };
13761+
13762 pinctrl_cbus: pinctrl@9880 {
13763 compatible = "amlogic,meson8-cbus-pinctrl";
13764 reg = <0x9880 0x10>;
13765@@ -270,6 +278,14 @@ &L2 {
13766 arm,filter-ranges = <0x100000 0xc0000000>;
13767 };
13768
13769+&pwm_ab {
13770+ compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
13771+};
13772+
13773+&pwm_cd {
13774+ compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
13775+};
13776+
13777 &saradc {
13778 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
13779 clocks = <&clkc CLKID_XTAL>,
13780diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
13781index 72e4f425f190..bc278da7df0d 100644
13782--- a/arch/arm/boot/dts/meson8b.dtsi
13783+++ b/arch/arm/boot/dts/meson8b.dtsi
13784@@ -119,6 +119,7 @@ mux {
13785 &cbus {
13786 clkc: clock-controller@4000 {
13787 #clock-cells = <1>;
13788+ #reset-cells = <1>;
13789 compatible = "amlogic,meson8b-clkc";
13790 reg = <0x8000 0x4>, <0x4000 0x460>;
13791 };
13792@@ -129,20 +130,6 @@ reset: reset-controller@4404 {
13793 #reset-cells = <1>;
13794 };
13795
13796- pwm_ab: pwm@8550 {
13797- compatible = "amlogic,meson8b-pwm";
13798- reg = <0x8550 0x10>;
13799- #pwm-cells = <3>;
13800- status = "disabled";
13801- };
13802-
13803- pwm_cd: pwm@8650 {
13804- compatible = "amlogic,meson8b-pwm";
13805- reg = <0x8650 0x10>;
13806- #pwm-cells = <3>;
13807- status = "disabled";
13808- };
13809-
13810 pwm_ef: pwm@86c0 {
13811 compatible = "amlogic,meson8b-pwm";
13812 reg = <0x86c0 0x10>;
13813@@ -150,12 +137,6 @@ pwm_ef: pwm@86c0 {
13814 status = "disabled";
13815 };
13816
13817- wdt: watchdog@9900 {
13818- compatible = "amlogic,meson8b-wdt";
13819- reg = <0x9900 0x8>;
13820- interrupts = <0 0 1>;
13821- };
13822-
13823 pinctrl_cbus: pinctrl@9880 {
13824 compatible = "amlogic,meson8b-cbus-pinctrl";
13825 reg = <0x9880 0x10>;
13826@@ -193,6 +174,14 @@ &L2 {
13827 arm,filter-ranges = <0x100000 0xc0000000>;
13828 };
13829
13830+&pwm_ab {
13831+ compatible = "amlogic,meson8b-pwm";
13832+};
13833+
13834+&pwm_cd {
13835+ compatible = "amlogic,meson8b-pwm";
13836+};
13837+
13838 &saradc {
13839 compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
13840 clocks = <&clkc CLKID_XTAL>,
13841@@ -242,3 +231,7 @@ &usb1_phy {
13842 clock-names = "usb_general", "usb";
13843 resets = <&reset RESET_USB_OTG>;
13844 };
13845+
13846+&wdt {
13847+ compatible = "amlogic,meson8b-wdt";
13848+};
13849diff --git a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
13850index 1eb5da1dc8f0..4d61e5b1334a 100644
13851--- a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
13852+++ b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
13853@@ -255,5 +255,6 @@ vaudio: VAUDIO {
13854 regulator-min-microvolt = <2775000>;
13855 regulator-max-microvolt = <2775000>;
13856 regulator-enable-ramp-delay = <1000>;
13857+ regulator-initial-mode = <0x00>; /* NORMAL */
13858 };
13859 };
13860diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
13861index f1efdc63656a..afe12e5b51f9 100644
13862--- a/arch/arm/boot/dts/mt2701.dtsi
13863+++ b/arch/arm/boot/dts/mt2701.dtsi
13864@@ -13,6 +13,7 @@
13865 */
13866
13867 #include <dt-bindings/clock/mt2701-clk.h>
13868+#include <dt-bindings/phy/phy.h>
13869 #include <dt-bindings/power/mt2701-power.h>
13870 #include <dt-bindings/interrupt-controller/irq.h>
13871 #include <dt-bindings/interrupt-controller/arm-gic.h>
13872@@ -533,6 +534,7 @@ larb0: larb@14010000 {
13873 compatible = "mediatek,mt2701-smi-larb";
13874 reg = <0 0x14010000 0 0x1000>;
13875 mediatek,smi = <&smi_common>;
13876+ mediatek,larb-id = <0>;
13877 clocks = <&mmsys CLK_MM_SMI_LARB0>,
13878 <&mmsys CLK_MM_SMI_LARB0>;
13879 clock-names = "apb", "smi";
13880@@ -549,6 +551,7 @@ larb2: larb@15001000 {
13881 compatible = "mediatek,mt2701-smi-larb";
13882 reg = <0 0x15001000 0 0x1000>;
13883 mediatek,smi = <&smi_common>;
13884+ mediatek,larb-id = <2>;
13885 clocks = <&imgsys CLK_IMG_SMI_COMM>,
13886 <&imgsys CLK_IMG_SMI_COMM>;
13887 clock-names = "apb", "smi";
13888@@ -579,6 +582,7 @@ larb1: larb@16010000 {
13889 compatible = "mediatek,mt2701-smi-larb";
13890 reg = <0 0x16010000 0 0x1000>;
13891 mediatek,smi = <&smi_common>;
13892+ mediatek,larb-id = <1>;
13893 clocks = <&vdecsys CLK_VDEC_CKGEN>,
13894 <&vdecsys CLK_VDEC_LARB>;
13895 clock-names = "apb", "smi";
13896@@ -591,12 +595,114 @@ hifsys: syscon@1a000000 {
13897 #clock-cells = <1>;
13898 };
13899
13900+ usb0: usb@1a1c0000 {
13901+ compatible = "mediatek,mt8173-xhci";
13902+ reg = <0 0x1a1c0000 0 0x1000>,
13903+ <0 0x1a1c4700 0 0x0100>;
13904+ reg-names = "mac", "ippc";
13905+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
13906+ clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
13907+ <&topckgen CLK_TOP_ETHIF_SEL>;
13908+ clock-names = "sys_ck", "ref_ck";
13909+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
13910+ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
13911+ status = "disabled";
13912+ };
13913+
13914+ u3phy0: usb-phy@1a1c4000 {
13915+ compatible = "mediatek,mt2701-u3phy";
13916+ reg = <0 0x1a1c4000 0 0x0700>;
13917+ #address-cells = <2>;
13918+ #size-cells = <2>;
13919+ ranges;
13920+ status = "disabled";
13921+
13922+ u2port0: usb-phy@1a1c4800 {
13923+ reg = <0 0x1a1c4800 0 0x0100>;
13924+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
13925+ clock-names = "ref";
13926+ #phy-cells = <1>;
13927+ status = "okay";
13928+ };
13929+
13930+ u3port0: usb-phy@1a1c4900 {
13931+ reg = <0 0x1a1c4900 0 0x0700>;
13932+ clocks = <&clk26m>;
13933+ clock-names = "ref";
13934+ #phy-cells = <1>;
13935+ status = "okay";
13936+ };
13937+ };
13938+
13939+ usb1: usb@1a240000 {
13940+ compatible = "mediatek,mt8173-xhci";
13941+ reg = <0 0x1a240000 0 0x1000>,
13942+ <0 0x1a244700 0 0x0100>;
13943+ reg-names = "mac", "ippc";
13944+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
13945+ clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
13946+ <&topckgen CLK_TOP_ETHIF_SEL>;
13947+ clock-names = "sys_ck", "ref_ck";
13948+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
13949+ phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
13950+ status = "disabled";
13951+ };
13952+
13953+ u3phy1: usb-phy@1a244000 {
13954+ compatible = "mediatek,mt2701-u3phy";
13955+ reg = <0 0x1a244000 0 0x0700>;
13956+ #address-cells = <2>;
13957+ #size-cells = <2>;
13958+ ranges;
13959+ status = "disabled";
13960+
13961+ u2port1: usb-phy@1a244800 {
13962+ reg = <0 0x1a244800 0 0x0100>;
13963+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
13964+ clock-names = "ref";
13965+ #phy-cells = <1>;
13966+ status = "okay";
13967+ };
13968+
13969+ u3port1: usb-phy@1a244900 {
13970+ reg = <0 0x1a244900 0 0x0700>;
13971+ clocks = <&clk26m>;
13972+ clock-names = "ref";
13973+ #phy-cells = <1>;
13974+ status = "okay";
13975+ };
13976+ };
13977+
13978 ethsys: syscon@1b000000 {
13979 compatible = "mediatek,mt2701-ethsys", "syscon";
13980 reg = <0 0x1b000000 0 0x1000>;
13981 #clock-cells = <1>;
13982 };
13983
13984+ eth: ethernet@1b100000 {
13985+ compatible = "mediatek,mt2701-eth", "syscon";
13986+ reg = <0 0x1b100000 0 0x20000>;
13987+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
13988+ <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
13989+ <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
13990+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
13991+ <&ethsys CLK_ETHSYS_ESW>,
13992+ <&ethsys CLK_ETHSYS_GP1>,
13993+ <&ethsys CLK_ETHSYS_GP2>,
13994+ <&apmixedsys CLK_APMIXED_TRGPLL>;
13995+ clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
13996+ resets = <&ethsys MT2701_ETHSYS_FE_RST>,
13997+ <&ethsys MT2701_ETHSYS_GMAC_RST>,
13998+ <&ethsys MT2701_ETHSYS_PPE_RST>;
13999+ reset-names = "fe", "gmac", "ppe";
14000+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
14001+ mediatek,ethsys = <&ethsys>;
14002+ mediatek,pctl = <&syscfg_pctl_a>;
14003+ #address-cells = <1>;
14004+ #size-cells = <0>;
14005+ status = "disabled";
14006+ };
14007+
14008 bdpsys: syscon@1c000000 {
14009 compatible = "mediatek,mt2701-bdpsys", "syscon";
14010 reg = <0 0x1c000000 0 0x1000>;
14011diff --git a/arch/arm/boot/dts/mt6323.dtsi b/arch/arm/boot/dts/mt6323.dtsi
14012new file mode 100644
14013index 000000000000..7c783d6c750e
14014--- /dev/null
14015+++ b/arch/arm/boot/dts/mt6323.dtsi
14016@@ -0,0 +1,241 @@
14017+/*
14018+ * Copyright (c) 2017 MediaTek Inc.
14019+ * Author: John Crispin <john@phrozen.org>
14020+ * Sean Wang <sean.wang@mediatek.com>
14021+ * This program is free software; you can redistribute it and/or modify
14022+ * it under the terms of the GNU General Public License version 2 as
14023+ * published by the Free Software Foundation.
14024+ *
14025+ * This program is distributed in the hope that it will be useful,
14026+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
14027+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14028+ * GNU General Public License for more details.
14029+ */
14030+
14031+&pwrap {
14032+ pmic: mt6323 {
14033+ compatible = "mediatek,mt6323";
14034+ interrupt-parent = <&pio>;
14035+ interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
14036+ interrupt-controller;
14037+ #interrupt-cells = <2>;
14038+
14039+ mt6323regulator: mt6323regulator{
14040+ compatible = "mediatek,mt6323-regulator";
14041+
14042+ mt6323_vproc_reg: buck_vproc{
14043+ regulator-name = "vproc";
14044+ regulator-min-microvolt = < 700000>;
14045+ regulator-max-microvolt = <1350000>;
14046+ regulator-ramp-delay = <12500>;
14047+ regulator-always-on;
14048+ regulator-boot-on;
14049+ };
14050+
14051+ mt6323_vsys_reg: buck_vsys{
14052+ regulator-name = "vsys";
14053+ regulator-min-microvolt = <1400000>;
14054+ regulator-max-microvolt = <2987500>;
14055+ regulator-ramp-delay = <25000>;
14056+ regulator-always-on;
14057+ regulator-boot-on;
14058+ };
14059+
14060+ mt6323_vpa_reg: buck_vpa{
14061+ regulator-name = "vpa";
14062+ regulator-min-microvolt = < 500000>;
14063+ regulator-max-microvolt = <3650000>;
14064+ };
14065+
14066+ mt6323_vtcxo_reg: ldo_vtcxo{
14067+ regulator-name = "vtcxo";
14068+ regulator-min-microvolt = <2800000>;
14069+ regulator-max-microvolt = <2800000>;
14070+ regulator-enable-ramp-delay = <90>;
14071+ regulator-always-on;
14072+ regulator-boot-on;
14073+ };
14074+
14075+ mt6323_vcn28_reg: ldo_vcn28{
14076+ regulator-name = "vcn28";
14077+ regulator-min-microvolt = <2800000>;
14078+ regulator-max-microvolt = <2800000>;
14079+ regulator-enable-ramp-delay = <185>;
14080+ };
14081+
14082+ mt6323_vcn33_bt_reg: ldo_vcn33_bt{
14083+ regulator-name = "vcn33_bt";
14084+ regulator-min-microvolt = <3300000>;
14085+ regulator-max-microvolt = <3600000>;
14086+ regulator-enable-ramp-delay = <185>;
14087+ };
14088+
14089+ mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
14090+ regulator-name = "vcn33_wifi";
14091+ regulator-min-microvolt = <3300000>;
14092+ regulator-max-microvolt = <3600000>;
14093+ regulator-enable-ramp-delay = <185>;
14094+ };
14095+
14096+ mt6323_va_reg: ldo_va{
14097+ regulator-name = "va";
14098+ regulator-min-microvolt = <2800000>;
14099+ regulator-max-microvolt = <2800000>;
14100+ regulator-enable-ramp-delay = <216>;
14101+ regulator-always-on;
14102+ regulator-boot-on;
14103+ };
14104+
14105+ mt6323_vcama_reg: ldo_vcama{
14106+ regulator-name = "vcama";
14107+ regulator-min-microvolt = <1500000>;
14108+ regulator-max-microvolt = <2800000>;
14109+ regulator-enable-ramp-delay = <216>;
14110+ };
14111+
14112+ mt6323_vio28_reg: ldo_vio28{
14113+ regulator-name = "vio28";
14114+ regulator-min-microvolt = <2800000>;
14115+ regulator-max-microvolt = <2800000>;
14116+ regulator-enable-ramp-delay = <216>;
14117+ regulator-always-on;
14118+ regulator-boot-on;
14119+ };
14120+
14121+ mt6323_vusb_reg: ldo_vusb{
14122+ regulator-name = "vusb";
14123+ regulator-min-microvolt = <3300000>;
14124+ regulator-max-microvolt = <3300000>;
14125+ regulator-enable-ramp-delay = <216>;
14126+ regulator-boot-on;
14127+ };
14128+
14129+ mt6323_vmc_reg: ldo_vmc{
14130+ regulator-name = "vmc";
14131+ regulator-min-microvolt = <1800000>;
14132+ regulator-max-microvolt = <3300000>;
14133+ regulator-enable-ramp-delay = <36>;
14134+ regulator-boot-on;
14135+ };
14136+
14137+ mt6323_vmch_reg: ldo_vmch{
14138+ regulator-name = "vmch";
14139+ regulator-min-microvolt = <3000000>;
14140+ regulator-max-microvolt = <3300000>;
14141+ regulator-enable-ramp-delay = <36>;
14142+ regulator-boot-on;
14143+ };
14144+
14145+ mt6323_vemc3v3_reg: ldo_vemc3v3{
14146+ regulator-name = "vemc3v3";
14147+ regulator-min-microvolt = <3000000>;
14148+ regulator-max-microvolt = <3300000>;
14149+ regulator-enable-ramp-delay = <36>;
14150+ regulator-boot-on;
14151+ };
14152+
14153+ mt6323_vgp1_reg: ldo_vgp1{
14154+ regulator-name = "vgp1";
14155+ regulator-min-microvolt = <1200000>;
14156+ regulator-max-microvolt = <3300000>;
14157+ regulator-enable-ramp-delay = <216>;
14158+ };
14159+
14160+ mt6323_vgp2_reg: ldo_vgp2{
14161+ regulator-name = "vgp2";
14162+ regulator-min-microvolt = <1200000>;
14163+ regulator-max-microvolt = <3000000>;
14164+ regulator-enable-ramp-delay = <216>;
14165+ };
14166+
14167+ mt6323_vgp3_reg: ldo_vgp3{
14168+ regulator-name = "vgp3";
14169+ regulator-min-microvolt = <1200000>;
14170+ regulator-max-microvolt = <1800000>;
14171+ regulator-enable-ramp-delay = <216>;
14172+ };
14173+
14174+ mt6323_vcn18_reg: ldo_vcn18{
14175+ regulator-name = "vcn18";
14176+ regulator-min-microvolt = <1800000>;
14177+ regulator-max-microvolt = <1800000>;
14178+ regulator-enable-ramp-delay = <216>;
14179+ };
14180+
14181+ mt6323_vsim1_reg: ldo_vsim1{
14182+ regulator-name = "vsim1";
14183+ regulator-min-microvolt = <1800000>;
14184+ regulator-max-microvolt = <3000000>;
14185+ regulator-enable-ramp-delay = <216>;
14186+ };
14187+
14188+ mt6323_vsim2_reg: ldo_vsim2{
14189+ regulator-name = "vsim2";
14190+ regulator-min-microvolt = <1800000>;
14191+ regulator-max-microvolt = <3000000>;
14192+ regulator-enable-ramp-delay = <216>;
14193+ };
14194+
14195+ mt6323_vrtc_reg: ldo_vrtc{
14196+ regulator-name = "vrtc";
14197+ regulator-min-microvolt = <2800000>;
14198+ regulator-max-microvolt = <2800000>;
14199+ regulator-always-on;
14200+ regulator-boot-on;
14201+ };
14202+
14203+ mt6323_vcamaf_reg: ldo_vcamaf{
14204+ regulator-name = "vcamaf";
14205+ regulator-min-microvolt = <1200000>;
14206+ regulator-max-microvolt = <3300000>;
14207+ regulator-enable-ramp-delay = <216>;
14208+ };
14209+
14210+ mt6323_vibr_reg: ldo_vibr{
14211+ regulator-name = "vibr";
14212+ regulator-min-microvolt = <1200000>;
14213+ regulator-max-microvolt = <3300000>;
14214+ regulator-enable-ramp-delay = <36>;
14215+ };
14216+
14217+ mt6323_vrf18_reg: ldo_vrf18{
14218+ regulator-name = "vrf18";
14219+ regulator-min-microvolt = <1825000>;
14220+ regulator-max-microvolt = <1825000>;
14221+ regulator-enable-ramp-delay = <187>;
14222+ };
14223+
14224+ mt6323_vm_reg: ldo_vm{
14225+ regulator-name = "vm";
14226+ regulator-min-microvolt = <1200000>;
14227+ regulator-max-microvolt = <1800000>;
14228+ regulator-enable-ramp-delay = <216>;
14229+ regulator-always-on;
14230+ regulator-boot-on;
14231+ };
14232+
14233+ mt6323_vio18_reg: ldo_vio18{
14234+ regulator-name = "vio18";
14235+ regulator-min-microvolt = <1800000>;
14236+ regulator-max-microvolt = <1800000>;
14237+ regulator-enable-ramp-delay = <216>;
14238+ regulator-always-on;
14239+ regulator-boot-on;
14240+ };
14241+
14242+ mt6323_vcamd_reg: ldo_vcamd{
14243+ regulator-name = "vcamd";
14244+ regulator-min-microvolt = <1200000>;
14245+ regulator-max-microvolt = <1800000>;
14246+ regulator-enable-ramp-delay = <216>;
14247+ };
14248+
14249+ mt6323_vcamio_reg: ldo_vcamio{
14250+ regulator-name = "vcamio";
14251+ regulator-min-microvolt = <1800000>;
14252+ regulator-max-microvolt = <1800000>;
14253+ regulator-enable-ramp-delay = <216>;
14254+ };
14255+ };
14256+ };
14257+};
14258diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
14259deleted file mode 100644
14260index b60b41cad592..000000000000
14261--- a/arch/arm/boot/dts/mt7623-evb.dts
14262+++ /dev/null
14263@@ -1,33 +0,0 @@
14264-/*
14265- * Copyright (c) 2016 MediaTek Inc.
14266- * Author: John Crispin <john@phrozen.org>
14267- *
14268- * This program is free software; you can redistribute it and/or modify
14269- * it under the terms of the GNU General Public License version 2 as
14270- * published by the Free Software Foundation.
14271- *
14272- * This program is distributed in the hope that it will be useful,
14273- * but WITHOUT ANY WARRANTY; without even the implied warranty of
14274- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14275- * GNU General Public License for more details.
14276- */
14277-
14278-/dts-v1/;
14279-#include "mt7623.dtsi"
14280-
14281-/ {
14282- model = "MediaTek MT7623 evaluation board";
14283- compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
14284-
14285- chosen {
14286- stdout-path = &uart2;
14287- };
14288-
14289- memory {
14290- reg = <0 0x80000000 0 0x40000000>;
14291- };
14292-};
14293-
14294-&uart2 {
14295- status = "okay";
14296-};
14297diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
14298index d81158b2b02f..ec8a07415cb3 100644
14299--- a/arch/arm/boot/dts/mt7623.dtsi
14300+++ b/arch/arm/boot/dts/mt7623.dtsi
14301@@ -21,36 +21,99 @@
14302 #include <dt-bindings/gpio/gpio.h>
14303 #include <dt-bindings/phy/phy.h>
14304 #include <dt-bindings/reset/mt2701-resets.h>
14305+#include <dt-bindings/thermal/thermal.h>
14306 #include "skeleton64.dtsi"
14307
14308 / {
14309 compatible = "mediatek,mt7623";
14310 interrupt-parent = <&sysirq>;
14311
14312+ cpu_opp_table: opp_table {
14313+ compatible = "operating-points-v2";
14314+ opp-shared;
14315+
14316+ opp-98000000 {
14317+ opp-hz = /bits/ 64 <98000000>;
14318+ opp-microvolt = <1050000>;
14319+ };
14320+
14321+ opp-198000000 {
14322+ opp-hz = /bits/ 64 <198000000>;
14323+ opp-microvolt = <1050000>;
14324+ };
14325+
14326+ opp-398000000 {
14327+ opp-hz = /bits/ 64 <398000000>;
14328+ opp-microvolt = <1050000>;
14329+ };
14330+
14331+ opp-598000000 {
14332+ opp-hz = /bits/ 64 <598000000>;
14333+ opp-microvolt = <1050000>;
14334+ };
14335+
14336+ opp-747500000 {
14337+ opp-hz = /bits/ 64 <747500000>;
14338+ opp-microvolt = <1050000>;
14339+ };
14340+
14341+ opp-1040000000 {
14342+ opp-hz = /bits/ 64 <1040000000>;
14343+ opp-microvolt = <1150000>;
14344+ };
14345+
14346+ opp-1196000000 {
14347+ opp-hz = /bits/ 64 <1196000000>;
14348+ opp-microvolt = <1200000>;
14349+ };
14350+
14351+ opp-1300000000 {
14352+ opp-hz = /bits/ 64 <1300000000>;
14353+ opp-microvolt = <1300000>;
14354+ };
14355+ };
14356+
14357 cpus {
14358 #address-cells = <1>;
14359 #size-cells = <0>;
14360 enable-method = "mediatek,mt6589-smp";
14361
14362- cpu@0 {
14363+ cpu0: cpu@0 {
14364 device_type = "cpu";
14365 compatible = "arm,cortex-a7";
14366 reg = <0x0>;
14367+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
14368+ <&apmixedsys CLK_APMIXED_MAINPLL>;
14369+ clock-names = "cpu", "intermediate";
14370+ operating-points-v2 = <&cpu_opp_table>;
14371+ #cooling-cells = <2>;
14372+ cooling-min-level = <0>;
14373+ cooling-max-level = <7>;
14374+ clock-frequency = <1300000000>;
14375 };
14376- cpu@1 {
14377+
14378+ cpu1: cpu@1 {
14379 device_type = "cpu";
14380 compatible = "arm,cortex-a7";
14381 reg = <0x1>;
14382+ operating-points-v2 = <&cpu_opp_table>;
14383+ clock-frequency = <1300000000>;
14384 };
14385- cpu@2 {
14386+
14387+ cpu2: cpu@2 {
14388 device_type = "cpu";
14389 compatible = "arm,cortex-a7";
14390 reg = <0x2>;
14391+ operating-points-v2 = <&cpu_opp_table>;
14392+ clock-frequency = <1300000000>;
14393 };
14394- cpu@3 {
14395+
14396+ cpu3: cpu@3 {
14397 device_type = "cpu";
14398 compatible = "arm,cortex-a7";
14399 reg = <0x3>;
14400+ operating-points-v2 = <&cpu_opp_table>;
14401+ clock-frequency = <1300000000>;
14402 };
14403 };
14404
14405@@ -74,6 +137,58 @@ clk26m: oscillator@0 {
14406 clock-output-names = "clk26m";
14407 };
14408
14409+ thermal-zones {
14410+ cpu_thermal: cpu_thermal {
14411+ polling-delay-passive = <1000>;
14412+ polling-delay = <1000>;
14413+
14414+ thermal-sensors = <&thermal 0>;
14415+
14416+ trips {
14417+ cpu_passive: cpu_passive {
14418+ temperature = <47000>;
14419+ hysteresis = <2000>;
14420+ type = "passive";
14421+ };
14422+
14423+ cpu_active: cpu_active {
14424+ temperature = <67000>;
14425+ hysteresis = <2000>;
14426+ type = "active";
14427+ };
14428+
14429+ cpu_hot: cpu_hot {
14430+ temperature = <87000>;
14431+ hysteresis = <2000>;
14432+ type = "hot";
14433+ };
14434+
14435+ cpu_crit {
14436+ temperature = <107000>;
14437+ hysteresis = <2000>;
14438+ type = "critical";
14439+ };
14440+ };
14441+
14442+ cooling-maps {
14443+ map0 {
14444+ trip = <&cpu_passive>;
14445+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
14446+ };
14447+
14448+ map1 {
14449+ trip = <&cpu_active>;
14450+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
14451+ };
14452+
14453+ map2 {
14454+ trip = <&cpu_hot>;
14455+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
14456+ };
14457+ };
14458+ };
14459+ };
14460+
14461 timer {
14462 compatible = "arm,armv7-timer";
14463 interrupt-parent = <&gic>;
14464@@ -172,7 +287,7 @@ pwrap: pwrap@1000d000 {
14465 clock-names = "spi", "wrap";
14466 };
14467
14468- cir: cir@0x10013000 {
14469+ cir: cir@10013000 {
14470 compatible = "mediatek,mt7623-cir";
14471 reg = <0 0x10013000 0 0x1000>;
14472 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
14473@@ -193,7 +308,7 @@ sysirq: interrupt-controller@10200100 {
14474 efuse: efuse@10206000 {
14475 compatible = "mediatek,mt7623-efuse",
14476 "mediatek,mt8173-efuse";
14477- reg = <0 0x10206000 0 0x1000>;
14478+ reg = <0 0x10206000 0 0x1000>;
14479 #address-cells = <1>;
14480 #size-cells = <1>;
14481 thermal_calibration_data: calib@424 {
14482@@ -371,6 +486,31 @@ thermal: thermal@1100b000 {
14483 nvmem-cell-names = "calibration-data";
14484 };
14485
14486+ nandc: nfi@1100d000 {
14487+ compatible = "mediatek,mt7623-nfc",
14488+ "mediatek,mt2701-nfc";
14489+ reg = <0 0x1100d000 0 0x1000>;
14490+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
14491+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
14492+ clocks = <&pericfg CLK_PERI_NFI>,
14493+ <&pericfg CLK_PERI_NFI_PAD>;
14494+ clock-names = "nfi_clk", "pad_clk";
14495+ status = "disabled";
14496+ ecc-engine = <&bch>;
14497+ #address-cells = <1>;
14498+ #size-cells = <0>;
14499+ };
14500+
14501+ bch: ecc@1100e000 {
14502+ compatible = "mediatek,mt7623-ecc",
14503+ "mediatek,mt2701-ecc";
14504+ reg = <0 0x1100e000 0 0x1000>;
14505+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
14506+ clocks = <&pericfg CLK_PERI_NFI_ECC>;
14507+ clock-names = "nfiecc_clk";
14508+ status = "disabled";
14509+ };
14510+
14511 spi1: spi@11016000 {
14512 compatible = "mediatek,mt7623-spi",
14513 "mediatek,mt2701-spi";
14514@@ -399,31 +539,6 @@ spi2: spi@11017000 {
14515 status = "disabled";
14516 };
14517
14518- nandc: nfi@1100d000 {
14519- compatible = "mediatek,mt7623-nfc",
14520- "mediatek,mt2701-nfc";
14521- reg = <0 0x1100d000 0 0x1000>;
14522- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
14523- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
14524- clocks = <&pericfg CLK_PERI_NFI>,
14525- <&pericfg CLK_PERI_NFI_PAD>;
14526- clock-names = "nfi_clk", "pad_clk";
14527- status = "disabled";
14528- ecc-engine = <&bch>;
14529- #address-cells = <1>;
14530- #size-cells = <0>;
14531- };
14532-
14533- bch: ecc@1100e000 {
14534- compatible = "mediatek,mt7623-ecc",
14535- "mediatek,mt2701-ecc";
14536- reg = <0 0x1100e000 0 0x1000>;
14537- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
14538- clocks = <&pericfg CLK_PERI_NFI_ECC>;
14539- clock-names = "nfiecc_clk";
14540- status = "disabled";
14541- };
14542-
14543 afe: audio-controller@11220000 {
14544 compatible = "mediatek,mt7623-audio",
14545 "mediatek,mt2701-audio";
14546@@ -538,13 +653,22 @@ mmc1: mmc@11240000 {
14547 compatible = "mediatek,mt7623-mmc",
14548 "mediatek,mt8135-mmc";
14549 reg = <0 0x11240000 0 0x1000>;
14550- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
14551+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
14552 clocks = <&pericfg CLK_PERI_MSDC30_1>,
14553 <&topckgen CLK_TOP_MSDC30_1_SEL>;
14554 clock-names = "source", "hclk";
14555 status = "disabled";
14556 };
14557
14558+ hifsys: syscon@1a000000 {
14559+ compatible = "mediatek,mt7623-hifsys",
14560+ "mediatek,mt2701-hifsys",
14561+ "syscon";
14562+ reg = <0 0x1a000000 0 0x1000>;
14563+ #clock-cells = <1>;
14564+ #reset-cells = <1>;
14565+ };
14566+
14567 usb1: usb@1a1c0000 {
14568 compatible = "mediatek,mt7623-xhci",
14569 "mediatek,mt8173-xhci";
14570@@ -561,7 +685,8 @@ usb1: usb@1a1c0000 {
14571 };
14572
14573 u3phy1: usb-phy@1a1c4000 {
14574- compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";
14575+ compatible = "mediatek,mt7623-u3phy",
14576+ "mediatek,mt2701-u3phy";
14577 reg = <0 0x1a1c4000 0 0x0700>;
14578 clocks = <&clk26m>;
14579 clock-names = "u3phya_ref";
14580@@ -599,7 +724,8 @@ usb2: usb@1a240000 {
14581 };
14582
14583 u3phy2: usb-phy@1a244000 {
14584- compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";
14585+ compatible = "mediatek,mt7623-u3phy",
14586+ "mediatek,mt2701-u3phy";
14587 reg = <0 0x1a244000 0 0x0700>;
14588 clocks = <&clk26m>;
14589 clock-names = "u3phya_ref";
14590@@ -621,15 +747,6 @@ u3port1: usb-phy@1a244900 {
14591 };
14592 };
14593
14594- hifsys: syscon@1a000000 {
14595- compatible = "mediatek,mt7623-hifsys",
14596- "mediatek,mt2701-hifsys",
14597- "syscon";
14598- reg = <0 0x1a000000 0 0x1000>;
14599- #clock-cells = <1>;
14600- #reset-cells = <1>;
14601- };
14602-
14603 ethsys: syscon@1b000000 {
14604 compatible = "mediatek,mt7623-ethsys",
14605 "mediatek,mt2701-ethsys",
14606@@ -639,7 +756,9 @@ ethsys: syscon@1b000000 {
14607 };
14608
14609 eth: ethernet@1b100000 {
14610- compatible = "mediatek,mt2701-eth", "syscon";
14611+ compatible = "mediatek,mt7623-eth",
14612+ "mediatek,mt2701-eth",
14613+ "syscon";
14614 reg = <0 0x1b100000 0 0x20000>;
14615 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
14616 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
14617@@ -650,6 +769,10 @@ eth: ethernet@1b100000 {
14618 <&ethsys CLK_ETHSYS_GP2>,
14619 <&apmixedsys CLK_APMIXED_TRGPLL>;
14620 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
14621+ resets = <&ethsys MT2701_ETHSYS_FE_RST>,
14622+ <&ethsys MT2701_ETHSYS_GMAC_RST>,
14623+ <&ethsys MT2701_ETHSYS_PPE_RST>;
14624+ reset-names = "fe", "gmac", "ppe";
14625 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
14626 mediatek,ethsys = <&ethsys>;
14627 mediatek,pctl = <&syscfg_pctl_a>;
14628diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
14629new file mode 100644
14630index 000000000000..688a86378cee
14631--- /dev/null
14632+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
14633@@ -0,0 +1,487 @@
14634+/*
14635+ * Copyright 2017 Sean Wang <sean.wang@mediatek.com>
14636+ *
14637+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14638+ */
14639+
14640+/dts-v1/;
14641+#include <dt-bindings/input/input.h>
14642+#include "mt7623.dtsi"
14643+#include "mt6323.dtsi"
14644+
14645+/ {
14646+ model = "Bananapi BPI-R2";
14647+ compatible = "bananapi,bpi-r2", "mediatek,mt7623";
14648+
14649+ aliases {
14650+ serial2 = &uart2;
14651+ };
14652+
14653+ chosen {
14654+ stdout-path = "serial2:115200n8";
14655+ };
14656+
14657+ cpus {
14658+ cpu@0 {
14659+ proc-supply = <&mt6323_vproc_reg>;
14660+ };
14661+
14662+ cpu@1 {
14663+ proc-supply = <&mt6323_vproc_reg>;
14664+ };
14665+
14666+ cpu@2 {
14667+ proc-supply = <&mt6323_vproc_reg>;
14668+ };
14669+
14670+ cpu@3 {
14671+ proc-supply = <&mt6323_vproc_reg>;
14672+ };
14673+ };
14674+
14675+ gpio_keys {
14676+ compatible = "gpio-keys";
14677+ pinctrl-names = "default";
14678+ pinctrl-0 = <&key_pins_a>;
14679+
14680+ factory {
14681+ label = "factory";
14682+ linux,code = <BTN_0>;
14683+ gpios = <&pio 256 GPIO_ACTIVE_LOW>;
14684+ };
14685+
14686+ wps {
14687+ label = "wps";
14688+ linux,code = <KEY_WPS_BUTTON>;
14689+ gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
14690+ };
14691+ };
14692+
14693+ leds {
14694+ compatible = "gpio-leds";
14695+ pinctrl-names = "default";
14696+ pinctrl-0 = <&led_pins_a>;
14697+
14698+ blue {
14699+ label = "bpi-r2:pio:blue";
14700+ gpios = <&pio 241 GPIO_ACTIVE_HIGH>;
14701+ default-state = "off";
14702+ };
14703+
14704+ green {
14705+ label = "bpi-r2:pio:green";
14706+ gpios = <&pio 240 GPIO_ACTIVE_HIGH>;
14707+ default-state = "off";
14708+ };
14709+
14710+ red {
14711+ label = "bpi-r2:pio:red";
14712+ gpios = <&pio 239 GPIO_ACTIVE_HIGH>;
14713+ default-state = "off";
14714+ };
14715+ };
14716+
14717+ memory@80000000 {
14718+ reg = <0 0x80000000 0 0x40000000>;
14719+ };
14720+};
14721+
14722+&cir {
14723+ pinctrl-names = "default";
14724+ pinctrl-0 = <&cir_pins_a>;
14725+ status = "okay";
14726+};
14727+
14728+&crypto {
14729+ status = "okay";
14730+};
14731+
14732+&eth {
14733+ status = "okay";
14734+
14735+ gmac0: mac@0 {
14736+ compatible = "mediatek,eth-mac";
14737+ reg = <0>;
14738+ phy-mode = "trgmii";
14739+
14740+ fixed-link {
14741+ speed = <1000>;
14742+ full-duplex;
14743+ pause;
14744+ };
14745+ };
14746+
14747+ mdio: mdio-bus {
14748+ #address-cells = <1>;
14749+ #size-cells = <0>;
14750+
14751+ switch@0 {
14752+ compatible = "mediatek,mt7530";
14753+ #address-cells = <1>;
14754+ #size-cells = <0>;
14755+ reg = <0>;
14756+ pinctrl-names = "default";
14757+ reset-gpios = <&pio 33 0>;
14758+ core-supply = <&mt6323_vpa_reg>;
14759+ io-supply = <&mt6323_vemc3v3_reg>;
14760+
14761+ ports {
14762+ #address-cells = <1>;
14763+ #size-cells = <0>;
14764+ reg = <0>;
14765+
14766+ port@0 {
14767+ reg = <0>;
14768+ label = "wan";
14769+ };
14770+
14771+ port@1 {
14772+ reg = <1>;
14773+ label = "lan0";
14774+ };
14775+
14776+ port@2 {
14777+ reg = <2>;
14778+ label = "lan1";
14779+ };
14780+
14781+ port@3 {
14782+ reg = <3>;
14783+ label = "lan2";
14784+ };
14785+
14786+ port@4 {
14787+ reg = <4>;
14788+ label = "lan3";
14789+ };
14790+
14791+ port@6 {
14792+ reg = <6>;
14793+ label = "cpu";
14794+ ethernet = <&gmac0>;
14795+ phy-mode = "trgmii";
14796+
14797+ fixed-link {
14798+ speed = <1000>;
14799+ full-duplex;
14800+ };
14801+ };
14802+ };
14803+ };
14804+ };
14805+};
14806+
14807+&i2c0 {
14808+ pinctrl-names = "default";
14809+ pinctrl-0 = <&i2c0_pins_a>;
14810+ status = "okay";
14811+};
14812+
14813+&i2c1 {
14814+ pinctrl-names = "default";
14815+ pinctrl-0 = <&i2c1_pins_a>;
14816+ status = "okay";
14817+};
14818+
14819+&mmc0 {
14820+ pinctrl-names = "default", "state_uhs";
14821+ pinctrl-0 = <&mmc0_pins_default>;
14822+ pinctrl-1 = <&mmc0_pins_uhs>;
14823+ status = "okay";
14824+ bus-width = <8>;
14825+ max-frequency = <50000000>;
14826+ cap-mmc-highspeed;
14827+ vmmc-supply = <&mt6323_vemc3v3_reg>;
14828+ vqmmc-supply = <&mt6323_vio18_reg>;
14829+ non-removable;
14830+};
14831+
14832+&mmc1 {
14833+ pinctrl-names = "default", "state_uhs";
14834+ pinctrl-0 = <&mmc1_pins_default>;
14835+ pinctrl-1 = <&mmc1_pins_uhs>;
14836+ status = "okay";
14837+ bus-width = <4>;
14838+ max-frequency = <50000000>;
14839+ cap-sd-highspeed;
14840+ cd-gpios = <&pio 261 0>;
14841+ vmmc-supply = <&mt6323_vmch_reg>;
14842+ vqmmc-supply = <&mt6323_vio18_reg>;
14843+};
14844+
14845+&pio {
14846+ cir_pins_a:cir@0 {
14847+ pins_cir {
14848+ pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
14849+ bias-disable;
14850+ };
14851+ };
14852+
14853+ i2c0_pins_a: i2c@0 {
14854+ pins_i2c0 {
14855+ pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
14856+ <MT7623_PIN_76_SCL0_FUNC_SCL0>;
14857+ bias-disable;
14858+ };
14859+ };
14860+
14861+ i2c1_pins_a: i2c@1 {
14862+ pin_i2c1 {
14863+ pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
14864+ <MT7623_PIN_58_SCL1_FUNC_SCL1>;
14865+ bias-disable;
14866+ };
14867+ };
14868+
14869+ i2s0_pins_a: i2s@0 {
14870+ pin_i2s0 {
14871+ pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
14872+ <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
14873+ <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
14874+ <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
14875+ <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
14876+ drive-strength = <MTK_DRIVE_12mA>;
14877+ bias-pull-down;
14878+ };
14879+ };
14880+
14881+ i2s1_pins_a: i2s@1 {
14882+ pin_i2s1 {
14883+ pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
14884+ <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
14885+ <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
14886+ <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
14887+ <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
14888+ drive-strength = <MTK_DRIVE_12mA>;
14889+ bias-pull-down;
14890+ };
14891+ };
14892+
14893+ key_pins_a: keys@0 {
14894+ pins_keys {
14895+ pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
14896+ <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
14897+ input-enable;
14898+ };
14899+ };
14900+
14901+ led_pins_a: leds@0 {
14902+ pins_leds {
14903+ pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
14904+ <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
14905+ <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
14906+ };
14907+ };
14908+
14909+ mmc0_pins_default: mmc0default {
14910+ pins_cmd_dat {
14911+ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
14912+ <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
14913+ <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
14914+ <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
14915+ <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
14916+ <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
14917+ <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
14918+ <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
14919+ <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
14920+ input-enable;
14921+ bias-pull-up;
14922+ };
14923+
14924+ pins_clk {
14925+ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
14926+ bias-pull-down;
14927+ };
14928+
14929+ pins_rst {
14930+ pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
14931+ bias-pull-up;
14932+ };
14933+ };
14934+
14935+ mmc0_pins_uhs: mmc0 {
14936+ pins_cmd_dat {
14937+ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
14938+ <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
14939+ <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
14940+ <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
14941+ <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
14942+ <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
14943+ <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
14944+ <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
14945+ <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
14946+ input-enable;
14947+ drive-strength = <MTK_DRIVE_2mA>;
14948+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
14949+ };
14950+
14951+ pins_clk {
14952+ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
14953+ drive-strength = <MTK_DRIVE_2mA>;
14954+ bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
14955+ };
14956+
14957+ pins_rst {
14958+ pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
14959+ bias-pull-up;
14960+ };
14961+ };
14962+
14963+ mmc1_pins_default: mmc1default {
14964+ pins_cmd_dat {
14965+ pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
14966+ <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
14967+ <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
14968+ <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
14969+ <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
14970+ input-enable;
14971+ drive-strength = <MTK_DRIVE_4mA>;
14972+ bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
14973+ };
14974+
14975+ pins_clk {
14976+ pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
14977+ bias-pull-down;
14978+ drive-strength = <MTK_DRIVE_4mA>;
14979+ };
14980+
14981+ pins_wp {
14982+ pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
14983+ input-enable;
14984+ bias-pull-up;
14985+ };
14986+
14987+ pins_insert {
14988+ pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
14989+ bias-pull-up;
14990+ };
14991+ };
14992+
14993+ mmc1_pins_uhs: mmc1 {
14994+ pins_cmd_dat {
14995+ pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
14996+ <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
14997+ <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
14998+ <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
14999+ <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
15000+ input-enable;
15001+ drive-strength = <MTK_DRIVE_4mA>;
15002+ bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
15003+ };
15004+
15005+ pins_clk {
15006+ pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
15007+ drive-strength = <MTK_DRIVE_4mA>;
15008+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
15009+ };
15010+ };
15011+
15012+ pwm_pins_a: pwm@0 {
15013+ pins_pwm {
15014+ pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
15015+ <MT7623_PIN_204_PWM1_FUNC_PWM1>,
15016+ <MT7623_PIN_205_PWM2_FUNC_PWM2>,
15017+ <MT7623_PIN_206_PWM3_FUNC_PWM3>,
15018+ <MT7623_PIN_207_PWM4_FUNC_PWM4>;
15019+ };
15020+ };
15021+
15022+ spi0_pins_a: spi@0 {
15023+ pins_spi {
15024+ pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
15025+ <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
15026+ <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
15027+ <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
15028+ bias-disable;
15029+ };
15030+ };
15031+
15032+ uart0_pins_a: uart@0 {
15033+ pins_dat {
15034+ pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
15035+ <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
15036+ };
15037+ };
15038+
15039+ uart1_pins_a: uart@1 {
15040+ pins_dat {
15041+ pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
15042+ <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
15043+ };
15044+ };
15045+};
15046+
15047+&pwm {
15048+ pinctrl-names = "default";
15049+ pinctrl-0 = <&pwm_pins_a>;
15050+ status = "okay";
15051+};
15052+
15053+&pwrap {
15054+ mt6323 {
15055+ mt6323led: led {
15056+ compatible = "mediatek,mt6323-led";
15057+ #address-cells = <1>;
15058+ #size-cells = <0>;
15059+
15060+ led@0 {
15061+ reg = <0>;
15062+ label = "bpi-r2:isink:green";
15063+ default-state = "off";
15064+ };
15065+
15066+ led@1 {
15067+ reg = <1>;
15068+ label = "bpi-r2:isink:red";
15069+ default-state = "off";
15070+ };
15071+
15072+ led@2 {
15073+ reg = <2>;
15074+ label = "bpi-r2:isink:blue";
15075+ default-state = "off";
15076+ };
15077+ };
15078+ };
15079+};
15080+
15081+&spi0 {
15082+ pinctrl-names = "default";
15083+ pinctrl-0 = <&spi0_pins_a>;
15084+ status = "okay";
15085+};
15086+
15087+&uart0 {
15088+ pinctrl-names = "default";
15089+ pinctrl-0 = <&uart0_pins_a>;
15090+ status = "disabled";
15091+};
15092+
15093+&uart1 {
15094+ pinctrl-names = "default";
15095+ pinctrl-0 = <&uart1_pins_a>;
15096+ status = "disabled";
15097+};
15098+
15099+&uart2 {
15100+ status = "okay";
15101+};
15102+
15103+&usb1 {
15104+ vusb33-supply = <&mt6323_vusb_reg>;
15105+ status = "okay";
15106+};
15107+
15108+&usb2 {
15109+ vusb33-supply = <&mt6323_vusb_reg>;
15110+ status = "okay";
15111+};
15112+
15113+&u3phy1 {
15114+ status = "okay";
15115+};
15116+
15117+&u3phy2 {
15118+ status = "okay";
15119+};
15120+
15121diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
15122new file mode 100644
15123index 000000000000..17c578f0d261
15124--- /dev/null
15125+++ b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
15126@@ -0,0 +1,111 @@
15127+/*
15128+ * Copyright (c) 2017 MediaTek Inc.
15129+ * Author: John Crispin <john@phrozen.org>
15130+ *
15131+ * This program is free software; you can redistribute it and/or modify
15132+ * it under the terms of the GNU General Public License version 2 as
15133+ * published by the Free Software Foundation.
15134+ *
15135+ * This program is distributed in the hope that it will be useful,
15136+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
15137+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15138+ * GNU General Public License for more details.
15139+ */
15140+
15141+/dts-v1/;
15142+#include "mt7623n-rfb.dtsi"
15143+
15144+/ {
15145+ model = "MediaTek MT7623N NAND reference board";
15146+ compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
15147+};
15148+
15149+&bch {
15150+ status = "okay";
15151+};
15152+
15153+&nandc {
15154+ status = "okay";
15155+ pinctrl-names = "default";
15156+ pinctrl-0 = <&nand_pins_default>;
15157+
15158+ nand@0 {
15159+ reg = <0>;
15160+ spare_per_sector = <64>;
15161+ nand-ecc-mode = "hw";
15162+ nand-ecc-strength = <12>;
15163+ nand-ecc-step-size = <1024>;
15164+
15165+ partitions {
15166+ compatible = "fixed-partitions";
15167+ #address-cells = <1>;
15168+ #size-cells = <1>;
15169+
15170+ partition@0 {
15171+ label = "preloader";
15172+ reg = <0x0 0x40000>;
15173+ };
15174+
15175+ partition@40000 {
15176+ label = "uboot";
15177+ reg = <0x40000 0x80000>;
15178+ };
15179+
15180+ partition@C0000 {
15181+ label = "uboot-env";
15182+ reg = <0xC0000 0x40000>;
15183+ };
15184+
15185+ partition@140000 {
15186+ label = "bootimg";
15187+ reg = <0x140000 0x2000000>;
15188+ };
15189+
15190+ partition@2140000 {
15191+ label = "recovery";
15192+ reg = <0x2140000 0x2000000>;
15193+ };
15194+
15195+ partition@4140000 {
15196+ label = "rootfs";
15197+ reg = <0x4140000 0x1000000>;
15198+ };
15199+
15200+ partition@5140000 {
15201+ label = "usrdata";
15202+ reg = <0x5140000 0x1000000>;
15203+ };
15204+ };
15205+ };
15206+};
15207+
15208+&pio {
15209+ nand_pins_default: nanddefault {
15210+ pins_ale {
15211+ pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
15212+ drive-strength = <MTK_DRIVE_8mA>;
15213+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
15214+ };
15215+
15216+ pins_dat {
15217+ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
15218+ <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
15219+ <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
15220+ <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
15221+ <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
15222+ <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
15223+ <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
15224+ <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
15225+ <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
15226+ input-enable;
15227+ drive-strength = <MTK_DRIVE_8mA>;
15228+ bias-pull-up;
15229+ };
15230+
15231+ pins_we {
15232+ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
15233+ drive-strength = <MTK_DRIVE_8mA>;
15234+ bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
15235+ };
15236+ };
15237+};
15238diff --git a/arch/arm/boot/dts/mt7623n-rfb.dtsi b/arch/arm/boot/dts/mt7623n-rfb.dtsi
15239new file mode 100644
15240index 000000000000..256c5fd947bf
15241--- /dev/null
15242+++ b/arch/arm/boot/dts/mt7623n-rfb.dtsi
15243@@ -0,0 +1,92 @@
15244+/*
15245+ * Copyright (c) 2017 MediaTek Inc.
15246+ * Author: John Crispin <john@phrozen.org>
15247+ * Sean Wang <sean.wang@mediatek.com>
15248+ *
15249+ * This program is free software; you can redistribute it and/or modify
15250+ * it under the terms of the GNU General Public License version 2 as
15251+ * published by the Free Software Foundation.
15252+ *
15253+ * This program is distributed in the hope that it will be useful,
15254+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
15255+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15256+ * GNU General Public License for more details.
15257+ */
15258+
15259+/dts-v1/;
15260+#include "mt7623.dtsi"
15261+#include "mt6323.dtsi"
15262+
15263+/ {
15264+ aliases {
15265+ serial0 = &uart0;
15266+ serial1 = &uart1;
15267+ serial2 = &uart2;
15268+ };
15269+
15270+ chosen {
15271+ stdout-path = "serial2:115200n8";
15272+ };
15273+
15274+ cpus {
15275+ cpu0 {
15276+ proc-supply = <&mt6323_vproc_reg>;
15277+ };
15278+
15279+ cpu1 {
15280+ proc-supply = <&mt6323_vproc_reg>;
15281+ };
15282+
15283+ cpu2 {
15284+ proc-supply = <&mt6323_vproc_reg>;
15285+ };
15286+
15287+ cpu3 {
15288+ proc-supply = <&mt6323_vproc_reg>;
15289+ };
15290+ };
15291+
15292+ memory@80000000 {
15293+ reg = <0 0x80000000 0 0x40000000>;
15294+ };
15295+
15296+ usb_p1_vbus: regulator@0 {
15297+ compatible = "regulator-fixed";
15298+ regulator-name = "usb_vbus";
15299+ regulator-min-microvolt = <5000000>;
15300+ regulator-max-microvolt = <5000000>;
15301+ gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
15302+ enable-active-high;
15303+ };
15304+};
15305+
15306+&mmc0 {
15307+ vmmc-supply = <&mt6323_vemc3v3_reg>;
15308+ vqmmc-supply = <&mt6323_vio18_reg>;
15309+};
15310+
15311+&mmc1 {
15312+ vmmc-supply = <&mt6323_vmch_reg>;
15313+ vqmmc-supply = <&mt6323_vmc_reg>;
15314+};
15315+
15316+&uart0 {
15317+ status = "okay";
15318+};
15319+
15320+&uart1 {
15321+ status = "okay";
15322+};
15323+
15324+&uart2 {
15325+ status = "okay";
15326+};
15327+
15328+&usb1 {
15329+ vbus-supply = <&usb_p1_vbus>;
15330+ status = "okay";
15331+};
15332+
15333+&u3phy1 {
15334+ status = "okay";
15335+};
15336diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
15337index 673cee2234b2..683b96a8f73e 100644
15338--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
15339+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
15340@@ -299,7 +299,7 @@ &i2c3 {
15341
15342 &mmc1 {
15343 vmmc-supply = <&vmmc1>;
15344- vmmc_aux-supply = <&vsim>;
15345+ vqmmc-supply = <&vsim>;
15346 bus-width = <8>;
15347 };
15348
15349diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
15350index 4be85ce59dd1..4d2eaf843fa9 100644
15351--- a/arch/arm/boot/dts/omap3-beagle.dts
15352+++ b/arch/arm/boot/dts/omap3-beagle.dts
15353@@ -283,7 +283,7 @@ &i2c3 {
15354
15355 &mmc1 {
15356 vmmc-supply = <&vmmc1>;
15357- vmmc_aux-supply = <&vsim>;
15358+ vqmmc-supply = <&vsim>;
15359 bus-width = <8>;
15360 };
15361
15362diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts
15363index 53ae04f9104d..3d293b345e99 100644
15364--- a/arch/arm/boot/dts/omap3-cm-t3517.dts
15365+++ b/arch/arm/boot/dts/omap3-cm-t3517.dts
15366@@ -129,7 +129,7 @@ &mmc2 {
15367 pinctrl-names = "default";
15368 pinctrl-0 = <&mmc2_pins>;
15369 vmmc-supply = <&wl12xx_vmmc2>;
15370- vmmc_aux-supply = <&wl12xx_vaux2>;
15371+ vqmmc-supply = <&wl12xx_vaux2>;
15372 non-removable;
15373 bus-width = <4>;
15374 cap-power-off-card;
15375diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts
15376index 2294f5b0aa10..bdf4b7fdda39 100644
15377--- a/arch/arm/boot/dts/omap3-cm-t3730.dts
15378+++ b/arch/arm/boot/dts/omap3-cm-t3730.dts
15379@@ -69,7 +69,7 @@ &mmc2 {
15380 pinctrl-names = "default";
15381 pinctrl-0 = <&mmc2_pins>;
15382 vmmc-supply = <&wl12xx_vmmc2>;
15383- vmmc_aux-supply = <&wl12xx_vaux2>;
15384+ vqmmc-supply = <&wl12xx_vaux2>;
15385 non-removable;
15386 bus-width = <4>;
15387 cap-power-off-card;
15388diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
15389index 82aa9c4a0f1c..0c0bb1b01b0b 100644
15390--- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
15391+++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
15392@@ -149,7 +149,7 @@ &i2c3 {
15393
15394 &mmc1 {
15395 vmmc-supply = <&vmmc1>;
15396- vmmc_aux-supply = <&vsim>;
15397+ vqmmc-supply = <&vsim>;
15398 bus-width = <8>;
15399 };
15400
15401diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi
15402index 2b1d6977a535..ff35803088e3 100644
15403--- a/arch/arm/boot/dts/omap3-evm-common.dtsi
15404+++ b/arch/arm/boot/dts/omap3-evm-common.dtsi
15405@@ -115,7 +115,7 @@ tsc2046@0 {
15406 &mmc1 {
15407 interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
15408 vmmc-supply = <&vmmc1>;
15409- vmmc_aux-supply = <&vsim>;
15410+ vqmmc-supply = <&vsim>;
15411 bus-width = <8>;
15412 };
15413
15414diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
15415index 49f37084e435..26c20e1167b9 100644
15416--- a/arch/arm/boot/dts/omap3-n900.dts
15417+++ b/arch/arm/boot/dts/omap3-n900.dts
15418@@ -144,6 +144,15 @@ battery: n900-battery {
15419 io-channel-names = "temp", "bsi", "vbat";
15420 };
15421
15422+ rear_camera: camera@0 {
15423+ compatible = "linux,camera";
15424+
15425+ module {
15426+ model = "TCM8341MD";
15427+ sensor = <&cam1>;
15428+ };
15429+ };
15430+
15431 pwm9: dmtimer-pwm {
15432 compatible = "ti,omap-dmtimer-pwm";
15433 #pwm-cells = <3>;
15434@@ -164,6 +173,31 @@ vctcxo: vctcxo {
15435 };
15436 };
15437
15438+&isp {
15439+ vdds_csib-supply = <&vaux2>;
15440+
15441+ pinctrl-names = "default";
15442+ pinctrl-0 = <&camera_pins>;
15443+
15444+ ports {
15445+ port@1 {
15446+ reg = <1>;
15447+
15448+ csi_isp: endpoint {
15449+ remote-endpoint = <&csi_cam1>;
15450+ bus-type = <3>; /* CCP2 */
15451+ clock-lanes = <1>;
15452+ data-lanes = <0>;
15453+ lane-polarity = <0 0>;
15454+ clock-inv = <0>;
15455+ /* Select strobe = <1> for back camera, <0> for front camera */
15456+ strobe = <1>;
15457+ crc = <0>;
15458+ };
15459+ };
15460+ };
15461+};
15462+
15463 &omap3_pmx_core {
15464 pinctrl-names = "default";
15465
15466@@ -328,6 +362,22 @@ modem_pins: pinmux_modem {
15467 OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */
15468 >;
15469 };
15470+
15471+ camera_pins: pinmux_camera {
15472+ pinctrl-single,pins = <
15473+ OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */
15474+ OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */
15475+ OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */
15476+ OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE7) /* cam_d4 */
15477+ OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6 */
15478+ OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7 */
15479+ OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE0) /* cam_d8 */
15480+ OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE0) /* cam_d9 */
15481+ OMAP3_CORE1_IOPAD(0x212a, PIN_OUTPUT | MUX_MODE7) /* cam_d10 */
15482+ OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE7) /* cam_xclkb */
15483+ OMAP3_CORE1_IOPAD(0x2132, PIN_OUTPUT | MUX_MODE0) /* cam_strobe */
15484+ >;
15485+ };
15486 };
15487
15488 &i2c1 {
15489@@ -726,6 +776,40 @@ lis302dl: lis3lv02d@1d {
15490 st,max-limit-y = <32>;
15491 st,max-limit-z = <32>;
15492 };
15493+
15494+ cam1: camera@3e {
15495+ compatible = "toshiba,et8ek8";
15496+ reg = <0x3e>;
15497+
15498+ vana-supply = <&vaux4>;
15499+
15500+ clocks = <&isp 0>;
15501+ clock-names = "extclk";
15502+ clock-frequency = <9600000>;
15503+
15504+ reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
15505+
15506+ port {
15507+ csi_cam1: endpoint {
15508+ bus-type = <3>; /* CCP2 */
15509+ strobe = <1>;
15510+ clock-inv = <0>;
15511+ crc = <1>;
15512+
15513+ remote-endpoint = <&csi_isp>;
15514+ };
15515+ };
15516+ };
15517+
15518+ /* D/A converter for auto-focus */
15519+ ad5820: dac@0c {
15520+ compatible = "adi,ad5820";
15521+ reg = <0x0c>;
15522+
15523+ VANA-supply = <&vaux4>;
15524+
15525+ #io-channel-cells = <0>;
15526+ };
15527 };
15528
15529 &mmc1 {
15530@@ -733,6 +817,9 @@ &mmc1 {
15531 pinctrl-0 = <&mmc1_pins>;
15532 vmmc-supply = <&vmmc1>;
15533 bus-width = <4>;
15534+ /* For debugging, it is often good idea to remove this GPIO.
15535+ It means you can remove back cover (to reboot by removing
15536+ battery) and still use the MMC card. */
15537 cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */
15538 };
15539
15540@@ -741,7 +828,7 @@ &mmc2 {
15541 pinctrl-names = "default";
15542 pinctrl-0 = <&mmc2_pins>;
15543 vmmc-supply = <&vaux3>;
15544- vmmc_aux-supply = <&vsim>;
15545+ vqmmc-supply = <&vsim>;
15546 bus-width = <8>;
15547 non-removable;
15548 no-sdio;
15549diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi
15550index cd220342a805..f25e158e7163 100644
15551--- a/arch/arm/boot/dts/omap3-overo-base.dtsi
15552+++ b/arch/arm/boot/dts/omap3-overo-base.dtsi
15553@@ -181,7 +181,7 @@ &mmc2 {
15554 pinctrl-names = "default";
15555 pinctrl-0 = <&mmc2_pins>;
15556 vmmc-supply = <&w3cbw003c_npoweron>;
15557- vmmc_aux-supply = <&w3cbw003c_wifi_nreset>;
15558+ vqmmc-supply = <&w3cbw003c_wifi_nreset>;
15559 bus-width = <4>;
15560 cap-sdio-irq;
15561 non-removable;
15562diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
15563index 06ac0f80bcf0..9a601d15247b 100644
15564--- a/arch/arm/boot/dts/omap3-tao3530.dtsi
15565+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
15566@@ -223,7 +223,7 @@ &mmc1 {
15567 pinctrl-names = "default";
15568 pinctrl-0 = <&mmc1_pins>;
15569 vmmc-supply = <&vmmc1>;
15570- vmmc_aux-supply = <&vsim>;
15571+ vqmmc-supply = <&vsim>;
15572 cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
15573 bus-width = <8>;
15574 };
15575diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts
15576index 45e2ce0803de..96d0301a336a 100644
15577--- a/arch/arm/boot/dts/omap3-zoom3.dts
15578+++ b/arch/arm/boot/dts/omap3-zoom3.dts
15579@@ -174,7 +174,7 @@ &twl_gpio {
15580
15581 &mmc1 {
15582 vmmc-supply = <&vmmc1>;
15583- vmmc_aux-supply = <&vsim>;
15584+ vqmmc-supply = <&vsim>;
15585 bus-width = <4>;
15586 pinctrl-names = "default";
15587 pinctrl-0 = <&mmc1_pins>;
15588diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
15589index a3ff4933dbc1..bdaf30c8c405 100644
15590--- a/arch/arm/boot/dts/omap3.dtsi
15591+++ b/arch/arm/boot/dts/omap3.dtsi
15592@@ -713,14 +713,12 @@ usbhshost: usbhshost@48064000 {
15593 usbhsohci: ohci@48064400 {
15594 compatible = "ti,ohci-omap3";
15595 reg = <0x48064400 0x400>;
15596- interrupt-parent = <&intc>;
15597 interrupts = <76>;
15598 };
15599
15600 usbhsehci: ehci@48064800 {
15601 compatible = "ti,ehci-omap";
15602 reg = <0x48064800 0x400>;
15603- interrupt-parent = <&intc>;
15604 interrupts = <77>;
15605 };
15606 };
15607@@ -831,7 +829,6 @@ ssi_port1: ssi-port@4805a000 {
15608 reg-names = "tx",
15609 "rx";
15610
15611- interrupt-parent = <&intc>;
15612 interrupts = <67>,
15613 <68>;
15614 };
15615@@ -844,7 +841,6 @@ ssi_port2: ssi-port@4805b000 {
15616 reg-names = "tx",
15617 "rx";
15618
15619- interrupt-parent = <&intc>;
15620 interrupts = <69>,
15621 <70>;
15622 };
15623diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
15624index abd6921143be..908951eb5943 100644
15625--- a/arch/arm/boot/dts/omap3430-sdp.dts
15626+++ b/arch/arm/boot/dts/omap3430-sdp.dts
15627@@ -33,7 +33,7 @@ twl: twl@48 {
15628
15629 &mmc1 {
15630 vmmc-supply = <&vmmc1>;
15631- vmmc_aux-supply = <&vsim>;
15632+ vqmmc-supply = <&vsim>;
15633 /*
15634 * S6-3 must be in ON position for 8 bit mode to function
15635 * Else, use 4 bit mode
15636diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
15637index 10ca1c174995..8b93d37310f2 100644
15638--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts
15639+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
15640@@ -129,6 +129,34 @@ touchscreen_reset {
15641 output-high;
15642 line-name = "touchscreen-reset";
15643 };
15644+
15645+ pwm8: dmtimer-pwm-8 {
15646+ pinctrl-names = "default";
15647+ pinctrl-0 = <&vibrator_direction_pin>;
15648+
15649+ compatible = "ti,omap-dmtimer-pwm";
15650+ #pwm-cells = <3>;
15651+ ti,timers = <&timer8>;
15652+ ti,clock-source = <0x01>;
15653+ };
15654+
15655+ pwm9: dmtimer-pwm-9 {
15656+ pinctrl-names = "default";
15657+ pinctrl-0 = <&vibrator_enable_pin>;
15658+
15659+ compatible = "ti,omap-dmtimer-pwm";
15660+ #pwm-cells = <3>;
15661+ ti,timers = <&timer9>;
15662+ ti,clock-source = <0x01>;
15663+ };
15664+
15665+ vibrator {
15666+ compatible = "pwm-vibrator";
15667+ pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>;
15668+ pwm-names = "enable", "direction";
15669+ direction-duty-cycle-ns = <10000000>;
15670+ };
15671+
15672 };
15673
15674 &dsi1 {
15675@@ -373,7 +401,7 @@ OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3)
15676 /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */
15677 dss_hdmi_pins: pinmux_dss_hdmi_pins {
15678 pinctrl-single,pins = <
15679- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0)
15680+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0)
15681 OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0)
15682 OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0)
15683 >;
15684@@ -488,6 +516,18 @@ usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins {
15685 OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
15686 >;
15687 };
15688+
15689+ vibrator_direction_pin: pinmux_vibrator_direction_pin {
15690+ pinctrl-single,pins = <
15691+ OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */
15692+ >;
15693+ };
15694+
15695+ vibrator_enable_pin: pinmux_vibrator_enable_pin {
15696+ pinctrl-single,pins = <
15697+ OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */
15698+ >;
15699+ };
15700 };
15701
15702 &uart3 {
15703diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts
15704index 1b825128a7b9..a9a584b5b955 100644
15705--- a/arch/arm/boot/dts/omap4-duovero-parlor.dts
15706+++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts
15707@@ -100,7 +100,7 @@ OMAP4_IOPAD(0x070, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enab
15708 dss_hdmi_pins: pinmux_dss_hdmi_pins {
15709 pinctrl-single,pins = <
15710 OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) /* hdmi_hpd.gpio_63 */
15711- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */
15712+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
15713 OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */
15714 OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */
15715 >;
15716diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
15717index edbc4090297d..2b48e51c372a 100644
15718--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
15719+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
15720@@ -267,7 +267,7 @@ OMAP4_IOPAD(0x184, PIN_OUTPUT | MUX_MODE3) /* gpio_0 */
15721
15722 dss_hdmi_pins: pinmux_dss_hdmi_pins {
15723 pinctrl-single,pins = <
15724- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */
15725+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
15726 OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */
15727 OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */
15728 >;
15729diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
15730index b4d19a7ae393..3d3140fd9659 100644
15731--- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts
15732+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
15733@@ -10,7 +10,7 @@
15734 /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
15735 &dss_hdmi_pins {
15736 pinctrl-single,pins = <
15737- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */
15738+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
15739 OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */
15740 OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */
15741 >;
15742diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
15743index d728ec963111..280d92d42bf1 100644
15744--- a/arch/arm/boot/dts/omap4-sdp.dts
15745+++ b/arch/arm/boot/dts/omap4-sdp.dts
15746@@ -290,7 +290,7 @@ OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
15747
15748 dss_hdmi_pins: pinmux_dss_hdmi_pins {
15749 pinctrl-single,pins = <
15750- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */
15751+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
15752 OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */
15753 OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */
15754 >;
15755diff --git a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi
15756index 74940b6d7719..676d8dd0624a 100644
15757--- a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi
15758+++ b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi
15759@@ -122,7 +122,7 @@ OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */
15760
15761 dss_hdmi_pins: pinmux_dss_hdmi_pins {
15762 pinctrl-single,pins = <
15763- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */
15764+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
15765 OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */
15766 OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */
15767 >;
15768diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi
15769index 4caadb253249..7824b2631cb6 100644
15770--- a/arch/arm/boot/dts/omap5-board-common.dtsi
15771+++ b/arch/arm/boot/dts/omap5-board-common.dtsi
15772@@ -290,7 +290,7 @@ OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */
15773
15774 dss_hdmi_pins: pinmux_dss_hdmi_pins {
15775 pinctrl-single,pins = <
15776- OMAP5_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */
15777+ OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
15778 OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */
15779 OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */
15780 >;
15781diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
15782index 78397f66d0b2..552a5c4c5942 100644
15783--- a/arch/arm/boot/dts/omap5-cm-t54.dts
15784+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
15785@@ -266,7 +266,7 @@ OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */
15786
15787 dss_hdmi_pins: pinmux_dss_hdmi_pins {
15788 pinctrl-single,pins = <
15789- OMAP5_IOPAD(0x013c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec */
15790+ OMAP5_IOPAD(0x013c, PIN_INPUT | MUX_MODE0) /* hdmi_cec */
15791 OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */
15792 OMAP5_IOPAD(0x0142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda */
15793 >;
15794diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
15795index b9457dd21a69..e413b21ee331 100644
15796--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
15797+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
15798@@ -20,27 +20,12 @@ / {
15799 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
15800 compatible = "qcom,ipq4019";
15801
15802- clocks {
15803- xo: xo {
15804- compatible = "fixed-clock";
15805- clock-frequency = <48000000>;
15806- #clock-cells = <0>;
15807- };
15808- };
15809-
15810 soc {
15811-
15812-
15813- timer {
15814- compatible = "arm,armv7-timer";
15815- interrupts = <1 2 0xf08>,
15816- <1 3 0xf08>,
15817- <1 4 0xf08>,
15818- <1 1 0xf08>;
15819- clock-frequency = <48000000>;
15820+ rng@22000 {
15821+ status = "ok";
15822 };
15823
15824- pinctrl@0x01000000 {
15825+ pinctrl@1000000 {
15826 serial_pins: serial_pinmux {
15827 mux {
15828 pins = "gpio60", "gpio61";
15829@@ -108,5 +93,13 @@ crypto@8e3a000 {
15830 watchdog@b017000 {
15831 status = "ok";
15832 };
15833+
15834+ wifi@a000000 {
15835+ status = "ok";
15836+ };
15837+
15838+ wifi@a800000 {
15839+ status = "ok";
15840+ };
15841 };
15842 };
15843diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
15844index 4b7d97275c62..10d112a4078e 100644
15845--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
15846+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
15847@@ -96,6 +96,21 @@ sleep_clk: sleep_clk {
15848 clock-frequency = <32768>;
15849 #clock-cells = <0>;
15850 };
15851+
15852+ xo: xo {
15853+ compatible = "fixed-clock";
15854+ clock-frequency = <48000000>;
15855+ #clock-cells = <0>;
15856+ };
15857+ };
15858+
15859+ timer {
15860+ compatible = "arm,armv7-timer";
15861+ interrupts = <1 2 0xf08>,
15862+ <1 3 0xf08>,
15863+ <1 4 0xf08>,
15864+ <1 1 0xf08>;
15865+ clock-frequency = <48000000>;
15866 };
15867
15868 soc {
15869@@ -119,7 +134,15 @@ gcc: clock-controller@1800000 {
15870 reg = <0x1800000 0x60000>;
15871 };
15872
15873- tlmm: pinctrl@0x01000000 {
15874+ rng@22000 {
15875+ compatible = "qcom,prng";
15876+ reg = <0x22000 0x140>;
15877+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
15878+ clock-names = "core";
15879+ status = "disabled";
15880+ };
15881+
15882+ tlmm: pinctrl@1000000 {
15883 compatible = "qcom,ipq4019-pinctrl";
15884 reg = <0x01000000 0x300000>;
15885 gpio-controller;
15886@@ -269,5 +292,89 @@ restart@4ab000 {
15887 compatible = "qcom,pshold";
15888 reg = <0x4ab000 0x4>;
15889 };
15890+
15891+ wifi0: wifi@a000000 {
15892+ compatible = "qcom,ipq4019-wifi";
15893+ reg = <0xa000000 0x200000>;
15894+ resets = <&gcc WIFI0_CPU_INIT_RESET>,
15895+ <&gcc WIFI0_RADIO_SRIF_RESET>,
15896+ <&gcc WIFI0_RADIO_WARM_RESET>,
15897+ <&gcc WIFI0_RADIO_COLD_RESET>,
15898+ <&gcc WIFI0_CORE_WARM_RESET>,
15899+ <&gcc WIFI0_CORE_COLD_RESET>;
15900+ reset-names = "wifi_cpu_init", "wifi_radio_srif",
15901+ "wifi_radio_warm", "wifi_radio_cold",
15902+ "wifi_core_warm", "wifi_core_cold";
15903+ clocks = <&gcc GCC_WCSS2G_CLK>,
15904+ <&gcc GCC_WCSS2G_REF_CLK>,
15905+ <&gcc GCC_WCSS2G_RTC_CLK>;
15906+ clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
15907+ "wifi_wcss_rtc";
15908+ interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
15909+ <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
15910+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
15911+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
15912+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
15913+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
15914+ <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
15915+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
15916+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
15917+ <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
15918+ <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
15919+ <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
15920+ <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
15921+ <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
15922+ <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
15923+ <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
15924+ <GIC_SPI 168 IRQ_TYPE_NONE>;
15925+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
15926+ "msi4", "msi5", "msi6", "msi7",
15927+ "msi8", "msi9", "msi10", "msi11",
15928+ "msi12", "msi13", "msi14", "msi15",
15929+ "legacy";
15930+ status = "disabled";
15931+ };
15932+
15933+ wifi1: wifi@a800000 {
15934+ compatible = "qcom,ipq4019-wifi";
15935+ reg = <0xa800000 0x200000>;
15936+ resets = <&gcc WIFI1_CPU_INIT_RESET>,
15937+ <&gcc WIFI1_RADIO_SRIF_RESET>,
15938+ <&gcc WIFI1_RADIO_WARM_RESET>,
15939+ <&gcc WIFI1_RADIO_COLD_RESET>,
15940+ <&gcc WIFI1_CORE_WARM_RESET>,
15941+ <&gcc WIFI1_CORE_COLD_RESET>;
15942+ reset-names = "wifi_cpu_init", "wifi_radio_srif",
15943+ "wifi_radio_warm", "wifi_radio_cold",
15944+ "wifi_core_warm", "wifi_core_cold";
15945+ clocks = <&gcc GCC_WCSS5G_CLK>,
15946+ <&gcc GCC_WCSS5G_REF_CLK>,
15947+ <&gcc GCC_WCSS5G_RTC_CLK>;
15948+ clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
15949+ "wifi_wcss_rtc";
15950+ interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
15951+ <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
15952+ <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
15953+ <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
15954+ <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
15955+ <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
15956+ <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
15957+ <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
15958+ <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
15959+ <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
15960+ <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
15961+ <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
15962+ <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
15963+ <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
15964+ <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
15965+ <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
15966+ <GIC_SPI 169 IRQ_TYPE_NONE>;
15967+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
15968+ "msi4", "msi5", "msi6", "msi7",
15969+ "msi8", "msi9", "msi10", "msi11",
15970+ "msi12", "msi13", "msi14", "msi15",
15971+ "legacy";
15972+ status = "disabled";
15973+ };
15974 };
15975 };
15976diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
15977index c5ee68a3f7f5..a39207625354 100644
15978--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
15979+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
15980@@ -779,7 +779,7 @@ tpiu_in: endpoint {
15981 };
15982
15983 replicator@fc31c000 {
15984- compatible = "qcom,coresight-replicator1x", "arm,primecell";
15985+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
15986 reg = <0xfc31c000 0x1000>;
15987
15988 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
15989diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
15990index 52a7b586bac7..cd4d5ff7749e 100644
15991--- a/arch/arm/boot/dts/r7s72100-genmai.dts
15992+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
15993@@ -11,6 +11,8 @@
15994
15995 /dts-v1/;
15996 #include "r7s72100.dtsi"
15997+#include <dt-bindings/gpio/gpio.h>
15998+#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
15999
16000 / {
16001 model = "Genmai";
16002@@ -34,6 +36,54 @@ lbsc {
16003 #address-cells = <1>;
16004 #size-cells = <1>;
16005 };
16006+
16007+ leds {
16008+ status = "okay";
16009+ compatible = "gpio-leds";
16010+
16011+ led1 {
16012+ gpios = <&port4 10 GPIO_ACTIVE_LOW>;
16013+ };
16014+
16015+ led2 {
16016+ gpios = <&port4 11 GPIO_ACTIVE_LOW>;
16017+ };
16018+ };
16019+};
16020+
16021+&pinctrl {
16022+
16023+ scif2_pins: serial2 {
16024+ /* P3_0 as TxD2; P3_2 as RxD2 */
16025+ pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
16026+ };
16027+
16028+ i2c2_pins: i2c2 {
16029+ /* RIIC2: P1_4 as SCL, P1_5 as SDA */
16030+ pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
16031+ };
16032+
16033+ ether_pins: ether {
16034+ /* Ethernet on Ports 1,2,3,5 */
16035+ pinmux = <RZA1_PINMUX(1, 14, 4)>,/* P1_14 = ET_COL */
16036+ <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
16037+ <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
16038+ <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
16039+ <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
16040+ <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
16041+ <RZA1_PINMUX(2, 0, 2)>, /* P2_0 = ET_TXCLK */
16042+ <RZA1_PINMUX(2, 1, 2)>, /* P2_1 = ET_TXER */
16043+ <RZA1_PINMUX(2, 2, 2)>, /* P2_2 = ET_TXEN */
16044+ <RZA1_PINMUX(2, 3, 2)>, /* P2_3 = ET_CRS */
16045+ <RZA1_PINMUX(2, 4, 2)>, /* P2_4 = ET_TXD0 */
16046+ <RZA1_PINMUX(2, 5, 2)>, /* P2_5 = ET_TXD1 */
16047+ <RZA1_PINMUX(2, 6, 2)>, /* P2_6 = ET_TXD2 */
16048+ <RZA1_PINMUX(2, 7, 2)>, /* P2_7 = ET_TXD3 */
16049+ <RZA1_PINMUX(2, 8, 2)>, /* P2_8 = ET_RXD0 */
16050+ <RZA1_PINMUX(2, 9, 2)>, /* P2_9 = ET_RXD1 */
16051+ <RZA1_PINMUX(2, 10, 2)>,/* P2_10 = ET_RXD2 */
16052+ <RZA1_PINMUX(2, 11, 2)>;/* P2_11 = ET_RXD3 */
16053+ };
16054 };
16055
16056 &extal_clk {
16057@@ -52,12 +102,28 @@ &mtu2 {
16058 status = "okay";
16059 };
16060
16061+&ether {
16062+ pinctrl-names = "default";
16063+ pinctrl-0 = <&ether_pins>;
16064+
16065+ status = "okay";
16066+
16067+ renesas,no-ether-link;
16068+ phy-handle = <&phy0>;
16069+ phy0: ethernet-phy@0 {
16070+ reg = <0>;
16071+ };
16072+};
16073+
16074 &i2c2 {
16075 status = "okay";
16076 clock-frequency = <400000>;
16077
16078+ pinctrl-names = "default";
16079+ pinctrl-0 = <&i2c2_pins>;
16080+
16081 eeprom@50 {
16082- compatible = "renesas,24c128";
16083+ compatible = "renesas,24c128", "atmel,24c128";
16084 reg = <0x50>;
16085 pagesize = <64>;
16086 };
16087@@ -68,6 +134,9 @@ &rtc {
16088 };
16089
16090 &scif2 {
16091+ pinctrl-names = "default";
16092+ pinctrl-0 = <&scif2_pins>;
16093+
16094 status = "okay";
16095 };
16096
16097diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts
16098index 72df20a04320..5dcaaf131d27 100644
16099--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts
16100+++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts
16101@@ -10,6 +10,8 @@
16102
16103 /dts-v1/;
16104 #include "r7s72100.dtsi"
16105+#include <dt-bindings/gpio/gpio.h>
16106+#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
16107
16108 / {
16109 model = "RSKRZA1";
16110@@ -33,6 +35,15 @@ lbsc {
16111 #address-cells = <1>;
16112 #size-cells = <1>;
16113 };
16114+
16115+ leds {
16116+ status = "okay";
16117+ compatible = "gpio-leds";
16118+
16119+ led0 {
16120+ gpios = <&port7 1 GPIO_ACTIVE_LOW>;
16121+ };
16122+ };
16123 };
16124
16125 &extal_clk {
16126@@ -47,11 +58,57 @@ &rtc_x1_clk {
16127 clock-frequency = <32768>;
16128 };
16129
16130+&pinctrl {
16131+
16132+ /* Serial Console */
16133+ scif2_pins: serial2 {
16134+ pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
16135+ <RZA1_PINMUX(3, 2, 4)>; /* RxD2 */
16136+ };
16137+
16138+ /* Ethernet */
16139+ ether_pins: ether {
16140+ /* Ethernet on Ports 1,2,3,5 */
16141+ pinmux = <RZA1_PINMUX(1, 14, 4)>, /* ET_COL */
16142+ <RZA1_PINMUX(5, 9, 2)>, /* ET_MDC */
16143+ <RZA1_PINMUX(3, 3, 2)>, /* ET_MDIO */
16144+ <RZA1_PINMUX(3, 4, 2)>, /* ET_RXCLK */
16145+ <RZA1_PINMUX(3, 5, 2)>, /* ET_RXER */
16146+ <RZA1_PINMUX(3, 6, 2)>, /* ET_RXDV */
16147+ <RZA1_PINMUX(2, 0, 2)>, /* ET_TXCLK */
16148+ <RZA1_PINMUX(2, 1, 2)>, /* ET_TXER */
16149+ <RZA1_PINMUX(2, 2, 2)>, /* ET_TXEN */
16150+ <RZA1_PINMUX(2, 3, 2)>, /* ET_CRS */
16151+ <RZA1_PINMUX(2, 4, 2)>, /* ET_TXD0 */
16152+ <RZA1_PINMUX(2, 5, 2)>, /* ET_TXD1 */
16153+ <RZA1_PINMUX(2, 6, 2)>, /* ET_TXD2 */
16154+ <RZA1_PINMUX(2, 7, 2)>, /* ET_TXD3 */
16155+ <RZA1_PINMUX(2, 8, 2)>, /* ET_RXD0 */
16156+ <RZA1_PINMUX(2, 9, 2)>, /* ET_RXD1 */
16157+ <RZA1_PINMUX(2, 10, 2)>, /* ET_RXD2 */
16158+ <RZA1_PINMUX(2, 11, 2)>; /* ET_RXD3 */
16159+ };
16160+
16161+ /* SDHI ch1 on CN1 */
16162+ sdhi1_pins: sdhi1 {
16163+ pinmux = <RZA1_PINMUX(3, 8, 7)>, /* SD_CD_1 */
16164+ <RZA1_PINMUX(3, 9, 7)>, /* SD_WP_1 */
16165+ <RZA1_PINMUX(3, 10, 7)>, /* SD_D1_1 */
16166+ <RZA1_PINMUX(3, 11, 7)>, /* SD_D0_1 */
16167+ <RZA1_PINMUX(3, 12, 7)>, /* SD_CLK_1 */
16168+ <RZA1_PINMUX(3, 13, 7)>, /* SD_CMD_1 */
16169+ <RZA1_PINMUX(3, 14, 7)>, /* SD_D3_1 */
16170+ <RZA1_PINMUX(3, 15, 7)>; /* SD_D2_1 */
16171+ };
16172+};
16173+
16174 &mtu2 {
16175 status = "okay";
16176 };
16177
16178 &ether {
16179+ pinctrl-names = "default";
16180+ pinctrl-0 = <&ether_pins>;
16181 status = "okay";
16182 renesas,no-ether-link;
16183 phy-handle = <&phy0>;
16184@@ -61,6 +118,8 @@ phy0: ethernet-phy@0 {
16185 };
16186
16187 &sdhi1 {
16188+ pinctrl-names = "default";
16189+ pinctrl-0 = <&sdhi1_pins>;
16190 bus-width = <4>;
16191 status = "okay";
16192 };
16193@@ -78,5 +137,7 @@ &rtc {
16194 };
16195
16196 &scif2 {
16197+ pinctrl-names = "default";
16198+ pinctrl-0 = <&scif2_pins>;
16199 status = "okay";
16200 };
16201diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
16202index 5cf53e9943af..4ed12a4d9d51 100644
16203--- a/arch/arm/boot/dts/r7s72100.dtsi
16204+++ b/arch/arm/boot/dts/r7s72100.dtsi
16205@@ -207,6 +207,84 @@ cpu@0 {
16206 };
16207 };
16208
16209+ pinctrl: pin-controller@fcfe3000 {
16210+ compatible = "renesas,r7s72100-ports";
16211+
16212+ reg = <0xfcfe3000 0x4230>;
16213+
16214+ port0: gpio-0 {
16215+ gpio-controller;
16216+ #gpio-cells = <2>;
16217+ gpio-ranges = <&pinctrl 0 0 6>;
16218+ };
16219+
16220+ port1: gpio-1 {
16221+ gpio-controller;
16222+ #gpio-cells = <2>;
16223+ gpio-ranges = <&pinctrl 0 16 16>;
16224+ };
16225+
16226+ port2: gpio-2 {
16227+ gpio-controller;
16228+ #gpio-cells = <2>;
16229+ gpio-ranges = <&pinctrl 0 32 16>;
16230+ };
16231+
16232+ port3: gpio-3 {
16233+ gpio-controller;
16234+ #gpio-cells = <2>;
16235+ gpio-ranges = <&pinctrl 0 48 16>;
16236+ };
16237+
16238+ port4: gpio-4 {
16239+ gpio-controller;
16240+ #gpio-cells = <2>;
16241+ gpio-ranges = <&pinctrl 0 64 16>;
16242+ };
16243+
16244+ port5: gpio-5 {
16245+ gpio-controller;
16246+ #gpio-cells = <2>;
16247+ gpio-ranges = <&pinctrl 0 80 11>;
16248+ };
16249+
16250+ port6: gpio-6 {
16251+ gpio-controller;
16252+ #gpio-cells = <2>;
16253+ gpio-ranges = <&pinctrl 0 96 16>;
16254+ };
16255+
16256+ port7: gpio-7 {
16257+ gpio-controller;
16258+ #gpio-cells = <2>;
16259+ gpio-ranges = <&pinctrl 0 112 16>;
16260+ };
16261+
16262+ port8: gpio-8 {
16263+ gpio-controller;
16264+ #gpio-cells = <2>;
16265+ gpio-ranges = <&pinctrl 0 128 16>;
16266+ };
16267+
16268+ port9: gpio-9 {
16269+ gpio-controller;
16270+ #gpio-cells = <2>;
16271+ gpio-ranges = <&pinctrl 0 144 8>;
16272+ };
16273+
16274+ port10: gpio-10 {
16275+ gpio-controller;
16276+ #gpio-cells = <2>;
16277+ gpio-ranges = <&pinctrl 0 160 16>;
16278+ };
16279+
16280+ port11: gpio-11 {
16281+ gpio-controller;
16282+ #gpio-cells = <2>;
16283+ gpio-ranges = <&pinctrl 0 176 16>;
16284+ };
16285+ };
16286+
16287 scif0: serial@e8007000 {
16288 compatible = "renesas,scif-r7s72100", "renesas,scif";
16289 reg = <0xe8007000 64>;
16290diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
16291index 9b54783cc2a5..081af0192851 100644
16292--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
16293+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
16294@@ -17,9 +17,40 @@ / {
16295
16296 aliases {
16297 serial0 = &scif0;
16298+ ethernet0 = &avb;
16299+ };
16300+};
16301+
16302+&pfc {
16303+ scif0_pins: scif0 {
16304+ groups = "scif0_data_d";
16305+ function = "scif0";
16306+ };
16307+
16308+ avb_pins: avb {
16309+ groups = "avb_mdio", "avb_gmii";
16310+ function = "avb";
16311 };
16312 };
16313
16314 &scif0 {
16315+ pinctrl-0 = <&scif0_pins>;
16316+ pinctrl-names = "default";
16317+
16318 status = "okay";
16319 };
16320+
16321+&avb {
16322+ pinctrl-0 = <&avb_pins>;
16323+ pinctrl-names = "default";
16324+
16325+ phy-handle = <&phy3>;
16326+ phy-mode = "gmii";
16327+ renesas,no-ether-link;
16328+ status = "okay";
16329+
16330+ phy3: ethernet-phy@3 {
16331+ reg = <3>;
16332+ micrel,led-mode = <1>;
16333+ };
16334+};
16335diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
16336index 001ca9144f4b..ff7993818637 100644
16337--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
16338+++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
16339@@ -22,8 +22,34 @@ memory@200000000 {
16340 device_type = "memory";
16341 reg = <2 0x00000000 0 0x20000000>;
16342 };
16343+
16344+ reg_3p3v: 3p3v {
16345+ compatible = "regulator-fixed";
16346+ regulator-name = "3P3V";
16347+ regulator-min-microvolt = <3300000>;
16348+ regulator-max-microvolt = <3300000>;
16349+ regulator-always-on;
16350+ regulator-boot-on;
16351+ };
16352 };
16353
16354 &extal_clk {
16355 clock-frequency = <20000000>;
16356 };
16357+
16358+&pfc {
16359+ mmcif0_pins: mmc {
16360+ groups = "mmc_data8_b", "mmc_ctrl";
16361+ function = "mmc";
16362+ };
16363+};
16364+
16365+&mmcif0 {
16366+ pinctrl-0 = <&mmcif0_pins>;
16367+ pinctrl-names = "default";
16368+
16369+ vmmc-supply = <&reg_3p3v>;
16370+ bus-width = <8>;
16371+ non-removable;
16372+ status = "okay";
16373+};
16374diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
16375index 3a22538208f2..3d918d106593 100644
16376--- a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
16377+++ b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
16378@@ -1,7 +1,7 @@
16379 /*
16380 * Device Tree Source for the SK-RZG1M board
16381 *
16382- * Copyright (C) 2016 Cogent Embedded, Inc.
16383+ * Copyright (C) 2016-2017 Cogent Embedded, Inc.
16384 *
16385 * This file is licensed under the terms of the GNU General Public License
16386 * version 2. This program is licensed "as is" without any warranty of any
16387@@ -39,11 +39,34 @@ &extal_clk {
16388 clock-frequency = <20000000>;
16389 };
16390
16391+&pfc {
16392+ scif0_pins: scif0 {
16393+ groups = "scif0_data_d";
16394+ function = "scif0";
16395+ };
16396+
16397+ ether_pins: ether {
16398+ groups = "eth_link", "eth_mdio", "eth_rmii";
16399+ function = "eth";
16400+ };
16401+
16402+ phy1_pins: phy1 {
16403+ groups = "intc_irq0";
16404+ function = "intc";
16405+ };
16406+};
16407+
16408 &scif0 {
16409+ pinctrl-0 = <&scif0_pins>;
16410+ pinctrl-names = "default";
16411+
16412 status = "okay";
16413 };
16414
16415 &ether {
16416+ pinctrl-0 = <&ether_pins &phy1_pins>;
16417+ pinctrl-names = "default";
16418+
16419 phy-handle = <&phy1>;
16420 renesas,ether-link-active-low;
16421 status = "okay";
16422diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
16423index 0ddac81742e4..14222c72f0e0 100644
16424--- a/arch/arm/boot/dts/r8a7743.dtsi
16425+++ b/arch/arm/boot/dts/r8a7743.dtsi
16426@@ -1,7 +1,7 @@
16427 /*
16428 * Device Tree Source for the r8a7743 SoC
16429 *
16430- * Copyright (C) 2016 Cogent Embedded Inc.
16431+ * Copyright (C) 2016-2017 Cogent Embedded Inc.
16432 *
16433 * This file is licensed under the terms of the GNU General Public License
16434 * version 2. This program is licensed "as is" without any warranty of any
16435@@ -18,9 +18,19 @@ / {
16436 #address-cells = <2>;
16437 #size-cells = <2>;
16438
16439+ aliases {
16440+ i2c0 = &i2c0;
16441+ i2c1 = &i2c1;
16442+ i2c2 = &i2c2;
16443+ i2c3 = &i2c3;
16444+ i2c4 = &i2c4;
16445+ i2c5 = &i2c5;
16446+ };
16447+
16448 cpus {
16449 #address-cells = <1>;
16450 #size-cells = <0>;
16451+ enable-method = "renesas,apmu";
16452
16453 cpu0: cpu@0 {
16454 device_type = "cpu";
16455@@ -28,8 +38,26 @@ cpu0: cpu@0 {
16456 reg = <0>;
16457 clock-frequency = <1500000000>;
16458 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
16459+ clock-latency = <300000>; /* 300 us */
16460 power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
16461 next-level-cache = <&L2_CA15>;
16462+
16463+ /* kHz - uV - OPPs unknown yet */
16464+ operating-points = <1500000 1000000>,
16465+ <1312500 1000000>,
16466+ <1125000 1000000>,
16467+ < 937500 1000000>,
16468+ < 750000 1000000>,
16469+ < 375000 1000000>;
16470+ };
16471+
16472+ cpu1: cpu@1 {
16473+ device_type = "cpu";
16474+ compatible = "arm,cortex-a15";
16475+ reg = <1>;
16476+ clock-frequency = <1500000000>;
16477+ power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
16478+ next-level-cache = <&L2_CA15>;
16479 };
16480
16481 L2_CA15: cache-controller-0 {
16482@@ -48,6 +76,12 @@ soc {
16483 #size-cells = <2>;
16484 ranges;
16485
16486+ apmu@e6152000 {
16487+ compatible = "renesas,r8a7743-apmu", "renesas,apmu";
16488+ reg = <0 0xe6152000 0 0x188>;
16489+ cpus = <&cpu0 &cpu1>;
16490+ };
16491+
16492 gic: interrupt-controller@f1001000 {
16493 compatible = "arm,gic-400";
16494 #interrupt-cells = <3>;
16495@@ -65,6 +99,126 @@ gic: interrupt-controller@f1001000 {
16496 resets = <&cpg 408>;
16497 };
16498
16499+ gpio0: gpio@e6050000 {
16500+ compatible = "renesas,gpio-r8a7743",
16501+ "renesas,gpio-rcar";
16502+ reg = <0 0xe6050000 0 0x50>;
16503+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
16504+ #gpio-cells = <2>;
16505+ gpio-controller;
16506+ gpio-ranges = <&pfc 0 0 32>;
16507+ #interrupt-cells = <2>;
16508+ interrupt-controller;
16509+ clocks = <&cpg CPG_MOD 912>;
16510+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16511+ resets = <&cpg 912>;
16512+ };
16513+
16514+ gpio1: gpio@e6051000 {
16515+ compatible = "renesas,gpio-r8a7743",
16516+ "renesas,gpio-rcar";
16517+ reg = <0 0xe6051000 0 0x50>;
16518+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
16519+ #gpio-cells = <2>;
16520+ gpio-controller;
16521+ gpio-ranges = <&pfc 0 32 26>;
16522+ #interrupt-cells = <2>;
16523+ interrupt-controller;
16524+ clocks = <&cpg CPG_MOD 911>;
16525+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16526+ resets = <&cpg 911>;
16527+ };
16528+
16529+ gpio2: gpio@e6052000 {
16530+ compatible = "renesas,gpio-r8a7743",
16531+ "renesas,gpio-rcar";
16532+ reg = <0 0xe6052000 0 0x50>;
16533+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
16534+ #gpio-cells = <2>;
16535+ gpio-controller;
16536+ gpio-ranges = <&pfc 0 64 32>;
16537+ #interrupt-cells = <2>;
16538+ interrupt-controller;
16539+ clocks = <&cpg CPG_MOD 910>;
16540+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16541+ resets = <&cpg 910>;
16542+ };
16543+
16544+ gpio3: gpio@e6053000 {
16545+ compatible = "renesas,gpio-r8a7743",
16546+ "renesas,gpio-rcar";
16547+ reg = <0 0xe6053000 0 0x50>;
16548+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
16549+ #gpio-cells = <2>;
16550+ gpio-controller;
16551+ gpio-ranges = <&pfc 0 96 32>;
16552+ #interrupt-cells = <2>;
16553+ interrupt-controller;
16554+ clocks = <&cpg CPG_MOD 909>;
16555+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16556+ resets = <&cpg 909>;
16557+ };
16558+
16559+ gpio4: gpio@e6054000 {
16560+ compatible = "renesas,gpio-r8a7743",
16561+ "renesas,gpio-rcar";
16562+ reg = <0 0xe6054000 0 0x50>;
16563+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
16564+ #gpio-cells = <2>;
16565+ gpio-controller;
16566+ gpio-ranges = <&pfc 0 128 32>;
16567+ #interrupt-cells = <2>;
16568+ interrupt-controller;
16569+ clocks = <&cpg CPG_MOD 908>;
16570+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16571+ resets = <&cpg 908>;
16572+ };
16573+
16574+ gpio5: gpio@e6055000 {
16575+ compatible = "renesas,gpio-r8a7743",
16576+ "renesas,gpio-rcar";
16577+ reg = <0 0xe6055000 0 0x50>;
16578+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
16579+ #gpio-cells = <2>;
16580+ gpio-controller;
16581+ gpio-ranges = <&pfc 0 160 32>;
16582+ #interrupt-cells = <2>;
16583+ interrupt-controller;
16584+ clocks = <&cpg CPG_MOD 907>;
16585+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16586+ resets = <&cpg 907>;
16587+ };
16588+
16589+ gpio6: gpio@e6055400 {
16590+ compatible = "renesas,gpio-r8a7743",
16591+ "renesas,gpio-rcar";
16592+ reg = <0 0xe6055400 0 0x50>;
16593+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
16594+ #gpio-cells = <2>;
16595+ gpio-controller;
16596+ gpio-ranges = <&pfc 0 192 32>;
16597+ #interrupt-cells = <2>;
16598+ interrupt-controller;
16599+ clocks = <&cpg CPG_MOD 905>;
16600+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16601+ resets = <&cpg 905>;
16602+ };
16603+
16604+ gpio7: gpio@e6055800 {
16605+ compatible = "renesas,gpio-r8a7743",
16606+ "renesas,gpio-rcar";
16607+ reg = <0 0xe6055800 0 0x50>;
16608+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
16609+ #gpio-cells = <2>;
16610+ gpio-controller;
16611+ gpio-ranges = <&pfc 0 224 26>;
16612+ #interrupt-cells = <2>;
16613+ interrupt-controller;
16614+ clocks = <&cpg CPG_MOD 904>;
16615+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16616+ resets = <&cpg 904>;
16617+ };
16618+
16619 irqc: interrupt-controller@e61c0000 {
16620 compatible = "renesas,irqc-r8a7743", "renesas,irqc";
16621 #interrupt-cells = <2>;
16622@@ -123,6 +277,11 @@ sysc: system-controller@e6180000 {
16623 #power-domain-cells = <1>;
16624 };
16625
16626+ pfc: pin-controller@e6060000 {
16627+ compatible = "renesas,pfc-r8a7743";
16628+ reg = <0 0xe6060000 0 0x250>;
16629+ };
16630+
16631 dmac0: dma-controller@e6700000 {
16632 compatible = "renesas,dmac-r8a7743",
16633 "renesas,rcar-dmac";
16634@@ -189,6 +348,94 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
16635 dma-channels = <15>;
16636 };
16637
16638+ /* The memory map in the User's Manual maps the cores to bus
16639+ * numbers
16640+ */
16641+ i2c0: i2c@e6508000 {
16642+ #address-cells = <1>;
16643+ #size-cells = <0>;
16644+ compatible = "renesas,i2c-r8a7743",
16645+ "renesas,rcar-gen2-i2c";
16646+ reg = <0 0xe6508000 0 0x40>;
16647+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
16648+ clocks = <&cpg CPG_MOD 931>;
16649+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16650+ resets = <&cpg 931>;
16651+ i2c-scl-internal-delay-ns = <6>;
16652+ status = "disabled";
16653+ };
16654+
16655+ i2c1: i2c@e6518000 {
16656+ #address-cells = <1>;
16657+ #size-cells = <0>;
16658+ compatible = "renesas,i2c-r8a7743",
16659+ "renesas,rcar-gen2-i2c";
16660+ reg = <0 0xe6518000 0 0x40>;
16661+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
16662+ clocks = <&cpg CPG_MOD 930>;
16663+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16664+ resets = <&cpg 930>;
16665+ i2c-scl-internal-delay-ns = <6>;
16666+ status = "disabled";
16667+ };
16668+
16669+ i2c2: i2c@e6530000 {
16670+ #address-cells = <1>;
16671+ #size-cells = <0>;
16672+ compatible = "renesas,i2c-r8a7743",
16673+ "renesas,rcar-gen2-i2c";
16674+ reg = <0 0xe6530000 0 0x40>;
16675+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
16676+ clocks = <&cpg CPG_MOD 929>;
16677+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16678+ resets = <&cpg 929>;
16679+ i2c-scl-internal-delay-ns = <6>;
16680+ status = "disabled";
16681+ };
16682+
16683+ i2c3: i2c@e6540000 {
16684+ #address-cells = <1>;
16685+ #size-cells = <0>;
16686+ compatible = "renesas,i2c-r8a7743",
16687+ "renesas,rcar-gen2-i2c";
16688+ reg = <0 0xe6540000 0 0x40>;
16689+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
16690+ clocks = <&cpg CPG_MOD 928>;
16691+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16692+ resets = <&cpg 928>;
16693+ i2c-scl-internal-delay-ns = <6>;
16694+ status = "disabled";
16695+ };
16696+
16697+ i2c4: i2c@e6520000 {
16698+ #address-cells = <1>;
16699+ #size-cells = <0>;
16700+ compatible = "renesas,i2c-r8a7743",
16701+ "renesas,rcar-gen2-i2c";
16702+ reg = <0 0xe6520000 0 0x40>;
16703+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
16704+ clocks = <&cpg CPG_MOD 927>;
16705+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16706+ resets = <&cpg 927>;
16707+ i2c-scl-internal-delay-ns = <6>;
16708+ status = "disabled";
16709+ };
16710+
16711+ i2c5: i2c@e6528000 {
16712+ /* doesn't need pinmux */
16713+ #address-cells = <1>;
16714+ #size-cells = <0>;
16715+ compatible = "renesas,i2c-r8a7743",
16716+ "renesas,rcar-gen2-i2c";
16717+ reg = <0 0xe6528000 0 0x40>;
16718+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
16719+ clocks = <&cpg CPG_MOD 925>;
16720+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16721+ resets = <&cpg 925>;
16722+ i2c-scl-internal-delay-ns = <110>;
16723+ status = "disabled";
16724+ };
16725+
16726 scifa0: serial@e6c40000 {
16727 compatible = "renesas,scifa-r8a7743",
16728 "renesas,rcar-gen2-scifa", "renesas,scifa";
16729@@ -468,6 +715,29 @@ hscif2: serial@e62d0000 {
16730 status = "disabled";
16731 };
16732
16733+ icram2: sram@e6300000 {
16734+ compatible = "mmio-sram";
16735+ reg = <0 0xe6300000 0 0x40000>;
16736+ };
16737+
16738+ icram0: sram@e63a0000 {
16739+ compatible = "mmio-sram";
16740+ reg = <0 0xe63a0000 0 0x12000>;
16741+ };
16742+
16743+ icram1: sram@e63c0000 {
16744+ compatible = "mmio-sram";
16745+ reg = <0 0xe63c0000 0 0x1000>;
16746+ #address-cells = <1>;
16747+ #size-cells = <1>;
16748+ ranges = <0 0 0xe63c0000 0x1000>;
16749+
16750+ smp-sram@0 {
16751+ compatible = "renesas,smp-sram";
16752+ reg = <0 0x10>;
16753+ };
16754+ };
16755+
16756 ether: ethernet@ee700000 {
16757 compatible = "renesas,ether-r8a7743";
16758 reg = <0 0xee700000 0 0x400>;
16759@@ -480,6 +750,35 @@ ether: ethernet@ee700000 {
16760 #size-cells = <0>;
16761 status = "disabled";
16762 };
16763+
16764+ avb: ethernet@e6800000 {
16765+ compatible = "renesas,etheravb-r8a7743",
16766+ "renesas,etheravb-rcar-gen2";
16767+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
16768+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
16769+ clocks = <&cpg CPG_MOD 812>;
16770+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16771+ resets = <&cpg 812>;
16772+ #address-cells = <1>;
16773+ #size-cells = <0>;
16774+ status = "disabled";
16775+ };
16776+
16777+ mmcif0: mmc@ee200000 {
16778+ compatible = "renesas,mmcif-r8a7743",
16779+ "renesas,sh-mmcif";
16780+ reg = <0 0xee200000 0 0x80>;
16781+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
16782+ clocks = <&cpg CPG_MOD 315>;
16783+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
16784+ <&dmac1 0xd1>, <&dmac1 0xd2>;
16785+ dma-names = "tx", "rx", "tx", "rx";
16786+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
16787+ resets = <&cpg 315>;
16788+ reg-io-width = <4>;
16789+ max-frequency = <97500000>;
16790+ status = "disabled";
16791+ };
16792 };
16793
16794 /* External root clock */
16795diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
16796index 97840b340197..b4d679b04ad6 100644
16797--- a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
16798+++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
16799@@ -1,7 +1,7 @@
16800 /*
16801 * Device Tree Source for the SK-RZG1E board
16802 *
16803- * Copyright (C) 2016 Cogent Embedded, Inc.
16804+ * Copyright (C) 2016-2017 Cogent Embedded, Inc.
16805 *
16806 * This file is licensed under the terms of the GNU General Public License
16807 * version 2. This program is licensed "as is" without any warranty of any
16808@@ -34,11 +34,34 @@ &extal_clk {
16809 clock-frequency = <20000000>;
16810 };
16811
16812+&pfc {
16813+ scif2_pins: scif2 {
16814+ groups = "scif2_data";
16815+ function = "scif2";
16816+ };
16817+
16818+ ether_pins: ether {
16819+ groups = "eth_link", "eth_mdio", "eth_rmii";
16820+ function = "eth";
16821+ };
16822+
16823+ phy1_pins: phy1 {
16824+ groups = "intc_irq8";
16825+ function = "intc";
16826+ };
16827+};
16828+
16829 &scif2 {
16830+ pinctrl-0 = <&scif2_pins>;
16831+ pinctrl-names = "default";
16832+
16833 status = "okay";
16834 };
16835
16836 &ether {
16837+ pinctrl-0 = <&ether_pins &phy1_pins>;
16838+ pinctrl-names = "default";
16839+
16840 phy-handle = <&phy1>;
16841 renesas,ether-link-active-low;
16842 status = "okay";
16843diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
16844index 2feb0084bb3b..aff90dfb8b32 100644
16845--- a/arch/arm/boot/dts/r8a7745.dtsi
16846+++ b/arch/arm/boot/dts/r8a7745.dtsi
16847@@ -1,7 +1,7 @@
16848 /*
16849 * Device Tree Source for the r8a7745 SoC
16850 *
16851- * Copyright (C) 2016 Cogent Embedded Inc.
16852+ * Copyright (C) 2016-2017 Cogent Embedded Inc.
16853 *
16854 * This file is licensed under the terms of the GNU General Public License
16855 * version 2. This program is licensed "as is" without any warranty of any
16856@@ -123,6 +123,11 @@ sysc: system-controller@e6180000 {
16857 #power-domain-cells = <1>;
16858 };
16859
16860+ pfc: pin-controller@e6060000 {
16861+ compatible = "renesas,pfc-r8a7745";
16862+ reg = <0 0xe6060000 0 0x11c>;
16863+ };
16864+
16865 dmac0: dma-controller@e6700000 {
16866 compatible = "renesas,dmac-r8a7745",
16867 "renesas,rcar-dmac";
16868@@ -468,6 +473,29 @@ hscif2: serial@e62d0000 {
16869 status = "disabled";
16870 };
16871
16872+ icram2: sram@e6300000 {
16873+ compatible = "mmio-sram";
16874+ reg = <0 0xe6300000 0 0x40000>;
16875+ };
16876+
16877+ icram0: sram@e63a0000 {
16878+ compatible = "mmio-sram";
16879+ reg = <0 0xe63a0000 0 0x12000>;
16880+ };
16881+
16882+ icram1: sram@e63c0000 {
16883+ compatible = "mmio-sram";
16884+ reg = <0 0xe63c0000 0 0x1000>;
16885+ #address-cells = <1>;
16886+ #size-cells = <1>;
16887+ ranges = <0 0 0xe63c0000 0x1000>;
16888+
16889+ smp-sram@0 {
16890+ compatible = "renesas,smp-sram";
16891+ reg = <0 0x10>;
16892+ };
16893+ };
16894+
16895 ether: ethernet@ee700000 {
16896 compatible = "renesas,ether-r8a7745";
16897 reg = <0 0xee700000 0 0x400>;
16898diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
16899index 2805a8608d4b..16358bf8d1db 100644
16900--- a/arch/arm/boot/dts/r8a7790.dtsi
16901+++ b/arch/arm/boot/dts/r8a7790.dtsi
16902@@ -830,6 +830,24 @@ hscif1: serial@e62c8000 {
16903 status = "disabled";
16904 };
16905
16906+ icram0: sram@e63a0000 {
16907+ compatible = "mmio-sram";
16908+ reg = <0 0xe63a0000 0 0x12000>;
16909+ };
16910+
16911+ icram1: sram@e63c0000 {
16912+ compatible = "mmio-sram";
16913+ reg = <0 0xe63c0000 0 0x1000>;
16914+ #address-cells = <1>;
16915+ #size-cells = <1>;
16916+ ranges = <0 0 0xe63c0000 0x1000>;
16917+
16918+ smp-sram@0 {
16919+ compatible = "renesas,smp-sram";
16920+ reg = <0 0x10>;
16921+ };
16922+ };
16923+
16924 ether: ethernet@ee700000 {
16925 compatible = "renesas,ether-r8a7790";
16926 reg = <0 0xee700000 0 0x400>;
16927@@ -855,7 +873,7 @@ avb: ethernet@e6800000 {
16928 };
16929
16930 sata0: sata@ee300000 {
16931- compatible = "renesas,sata-r8a7790";
16932+ compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
16933 reg = <0 0xee300000 0 0x2000>;
16934 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
16935 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
16936@@ -864,7 +882,7 @@ sata0: sata@ee300000 {
16937 };
16938
16939 sata1: sata@ee500000 {
16940- compatible = "renesas,sata-r8a7790";
16941+ compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
16942 reg = <0 0xee500000 0 0x2000>;
16943 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
16944 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
16945@@ -909,7 +927,7 @@ usb2: usb-channel@2 {
16946 };
16947
16948 vin0: video@e6ef0000 {
16949- compatible = "renesas,vin-r8a7790";
16950+ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
16951 reg = <0 0xe6ef0000 0 0x1000>;
16952 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
16953 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
16954@@ -918,7 +936,7 @@ vin0: video@e6ef0000 {
16955 };
16956
16957 vin1: video@e6ef1000 {
16958- compatible = "renesas,vin-r8a7790";
16959+ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
16960 reg = <0 0xe6ef1000 0 0x1000>;
16961 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
16962 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
16963@@ -927,7 +945,7 @@ vin1: video@e6ef1000 {
16964 };
16965
16966 vin2: video@e6ef2000 {
16967- compatible = "renesas,vin-r8a7790";
16968+ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
16969 reg = <0 0xe6ef2000 0 0x1000>;
16970 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
16971 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
16972@@ -936,7 +954,7 @@ vin2: video@e6ef2000 {
16973 };
16974
16975 vin3: video@e6ef3000 {
16976- compatible = "renesas,vin-r8a7790";
16977+ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
16978 reg = <0 0xe6ef3000 0 0x1000>;
16979 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
16980 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
16981diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
16982index 001e6116c47c..0ce0b278e1cb 100644
16983--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
16984+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
16985@@ -642,11 +642,19 @@ adv7180: endpoint {
16986 };
16987 };
16988
16989+ cec_clock: cec-clock {
16990+ compatible = "fixed-clock";
16991+ #clock-cells = <0>;
16992+ clock-frequency = <12000000>;
16993+ };
16994+
16995 hdmi@39 {
16996 compatible = "adi,adv7511w";
16997 reg = <0x39>;
16998 interrupt-parent = <&gpio3>;
16999 interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
17000+ clocks = <&cec_clock>;
17001+ clock-names = "cec";
17002
17003 adi,input-depth = <8>;
17004 adi,input-colorspace = "rgb";
17005@@ -702,7 +710,7 @@ adv7612_out: endpoint {
17006 };
17007
17008 eeprom@50 {
17009- compatible = "renesas,24c02";
17010+ compatible = "renesas,24c02", "atmel,24c02";
17011 reg = <0x50>;
17012 pagesize = <16>;
17013 };
17014diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
17015index bd93f699ad84..f1d1a9772153 100644
17016--- a/arch/arm/boot/dts/r8a7791.dtsi
17017+++ b/arch/arm/boot/dts/r8a7791.dtsi
17018@@ -890,6 +890,24 @@ hscif2: serial@e62d0000 {
17019 status = "disabled";
17020 };
17021
17022+ icram0: sram@e63a0000 {
17023+ compatible = "mmio-sram";
17024+ reg = <0 0xe63a0000 0 0x12000>;
17025+ };
17026+
17027+ icram1: sram@e63c0000 {
17028+ compatible = "mmio-sram";
17029+ reg = <0 0xe63c0000 0 0x1000>;
17030+ #address-cells = <1>;
17031+ #size-cells = <1>;
17032+ ranges = <0 0 0xe63c0000 0x1000>;
17033+
17034+ smp-sram@0 {
17035+ compatible = "renesas,smp-sram";
17036+ reg = <0 0x10>;
17037+ };
17038+ };
17039+
17040 ether: ethernet@ee700000 {
17041 compatible = "renesas,ether-r8a7791";
17042 reg = <0 0xee700000 0 0x400>;
17043@@ -915,7 +933,7 @@ avb: ethernet@e6800000 {
17044 };
17045
17046 sata0: sata@ee300000 {
17047- compatible = "renesas,sata-r8a7791";
17048+ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
17049 reg = <0 0xee300000 0 0x2000>;
17050 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
17051 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
17052@@ -924,7 +942,7 @@ sata0: sata@ee300000 {
17053 };
17054
17055 sata1: sata@ee500000 {
17056- compatible = "renesas,sata-r8a7791";
17057+ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
17058 reg = <0 0xee500000 0 0x2000>;
17059 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
17060 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
17061@@ -969,7 +987,7 @@ usb2: usb-channel@2 {
17062 };
17063
17064 vin0: video@e6ef0000 {
17065- compatible = "renesas,vin-r8a7791";
17066+ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
17067 reg = <0 0xe6ef0000 0 0x1000>;
17068 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
17069 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
17070@@ -978,7 +996,7 @@ vin0: video@e6ef0000 {
17071 };
17072
17073 vin1: video@e6ef1000 {
17074- compatible = "renesas,vin-r8a7791";
17075+ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
17076 reg = <0 0xe6ef1000 0 0x1000>;
17077 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
17078 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
17079@@ -987,7 +1005,7 @@ vin1: video@e6ef1000 {
17080 };
17081
17082 vin2: video@e6ef2000 {
17083- compatible = "renesas,vin-r8a7791";
17084+ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
17085 reg = <0 0xe6ef2000 0 0x1000>;
17086 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
17087 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
17088diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
17089index 0efecb232ee5..2623f39bed2b 100644
17090--- a/arch/arm/boot/dts/r8a7792.dtsi
17091+++ b/arch/arm/boot/dts/r8a7792.dtsi
17092@@ -465,6 +465,24 @@ hscif1: serial@e62c8000 {
17093 status = "disabled";
17094 };
17095
17096+ icram0: sram@e63a0000 {
17097+ compatible = "mmio-sram";
17098+ reg = <0 0xe63a0000 0 0x12000>;
17099+ };
17100+
17101+ icram1: sram@e63c0000 {
17102+ compatible = "mmio-sram";
17103+ reg = <0 0xe63c0000 0 0x1000>;
17104+ #address-cells = <1>;
17105+ #size-cells = <1>;
17106+ ranges = <0 0 0xe63c0000 0x1000>;
17107+
17108+ smp-sram@0 {
17109+ compatible = "renesas,smp-sram";
17110+ reg = <0 0x10>;
17111+ };
17112+ };
17113+
17114 sdhi0: sd@ee100000 {
17115 compatible = "renesas,sdhi-r8a7792";
17116 reg = <0 0xee100000 0 0x328>;
17117diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
17118index 13b980f27bbc..497716b6fbe2 100644
17119--- a/arch/arm/boot/dts/r8a7793.dtsi
17120+++ b/arch/arm/boot/dts/r8a7793.dtsi
17121@@ -848,6 +848,24 @@ hscif2: serial@e62d0000 {
17122 status = "disabled";
17123 };
17124
17125+ icram0: sram@e63a0000 {
17126+ compatible = "mmio-sram";
17127+ reg = <0 0xe63a0000 0 0x12000>;
17128+ };
17129+
17130+ icram1: sram@e63c0000 {
17131+ compatible = "mmio-sram";
17132+ reg = <0 0xe63c0000 0 0x1000>;
17133+ #address-cells = <1>;
17134+ #size-cells = <1>;
17135+ ranges = <0 0 0xe63c0000 0x1000>;
17136+
17137+ smp-sram@0 {
17138+ compatible = "renesas,smp-sram";
17139+ reg = <0 0x10>;
17140+ };
17141+ };
17142+
17143 ether: ethernet@ee700000 {
17144 compatible = "renesas,ether-r8a7793";
17145 reg = <0 0xee700000 0 0x400>;
17146diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
17147index 7d9a81d970d8..26535414203a 100644
17148--- a/arch/arm/boot/dts/r8a7794.dtsi
17149+++ b/arch/arm/boot/dts/r8a7794.dtsi
17150@@ -588,6 +588,24 @@ hscif2: serial@e62d0000 {
17151 status = "disabled";
17152 };
17153
17154+ icram0: sram@e63a0000 {
17155+ compatible = "mmio-sram";
17156+ reg = <0 0xe63a0000 0 0x12000>;
17157+ };
17158+
17159+ icram1: sram@e63c0000 {
17160+ compatible = "mmio-sram";
17161+ reg = <0 0xe63c0000 0 0x1000>;
17162+ #address-cells = <1>;
17163+ #size-cells = <1>;
17164+ ranges = <0 0 0xe63c0000 0x1000>;
17165+
17166+ smp-sram@0 {
17167+ compatible = "renesas,smp-sram";
17168+ reg = <0 0x10>;
17169+ };
17170+ };
17171+
17172 ether: ethernet@ee700000 {
17173 compatible = "renesas,ether-r8a7794";
17174 reg = <0 0xee700000 0 0x400>;
17175@@ -783,7 +801,7 @@ qspi: spi@e6b10000 {
17176 };
17177
17178 vin0: video@e6ef0000 {
17179- compatible = "renesas,vin-r8a7794";
17180+ compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
17181 reg = <0 0xe6ef0000 0 0x1000>;
17182 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
17183 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
17184@@ -792,7 +810,7 @@ vin0: video@e6ef0000 {
17185 };
17186
17187 vin1: video@e6ef1000 {
17188- compatible = "renesas,vin-r8a7794";
17189+ compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
17190 reg = <0 0xe6ef1000 0 0x1000>;
17191 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
17192 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
17193diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
17194index 5726135b7f8a..fdb1570bc7d3 100644
17195--- a/arch/arm/boot/dts/rk3036-kylin.dts
17196+++ b/arch/arm/boot/dts/rk3036-kylin.dts
17197@@ -357,7 +357,6 @@ &sdio {
17198 keep-power-in-suspend;
17199 mmc-pwrseq = <&sdio_pwrseq>;
17200 non-removable;
17201- num-slots = <1>;
17202 pinctrl-names = "default";
17203 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
17204 sd-uhs-sdr12;
17205@@ -372,7 +371,6 @@ &sdmmc {
17206 cap-sd-highspeed;
17207 card-detect-delay = <200>;
17208 disable-wp;
17209- num-slots = <1>;
17210 pinctrl-names = "default";
17211 pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
17212 };
17213diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
17214index ec91325d3b6e..4916c65e0ace 100644
17215--- a/arch/arm/boot/dts/rk3036.dtsi
17216+++ b/arch/arm/boot/dts/rk3036.dtsi
17217@@ -287,7 +287,6 @@ emmc: dwmmc@1021c000 {
17218 fifo-depth = <0x100>;
17219 mmc-ddr-1_8v;
17220 non-removable;
17221- num-slots = <1>;
17222 pinctrl-names = "default";
17223 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
17224 resets = <&cru SRST_EMMC>;
17225@@ -599,7 +598,7 @@ sdmmc_cmd: sdmmc-cmd {
17226 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
17227 };
17228
17229- sdmmc_cd: sdmcc-cd {
17230+ sdmmc_cd: sdmmc-cd {
17231 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
17232 };
17233
17234diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
17235index e1f5198723b2..ef1eabf2512c 100644
17236--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
17237+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
17238@@ -190,7 +190,6 @@ vcc28_cif: regulator@12 {
17239 #include "tps65910.dtsi"
17240
17241 &mmc0 { /* sdmmc */
17242- num-slots = <1>;
17243 status = "okay";
17244 pinctrl-names = "default";
17245 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
17246@@ -202,7 +201,6 @@ &mmc0 { /* sdmmc */
17247 };
17248
17249 &mmc1 { /* wifi */
17250- num-slots = <1>;
17251 status = "okay";
17252 non-removable;
17253
17254diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts
17255index 7ca1cf5241e0..13e285c53def 100644
17256--- a/arch/arm/boot/dts/rk3066a-mk808.dts
17257+++ b/arch/arm/boot/dts/rk3066a-mk808.dts
17258@@ -132,7 +132,6 @@ &mmc0 {
17259 bus-width = <4>;
17260 cap-mmc-highspeed;
17261 cap-sd-highspeed;
17262- num-slots = <1>;
17263 vmmc-supply = <&vcc_sd>;
17264 status = "okay";
17265 };
17266@@ -141,7 +140,6 @@ &mmc1 {
17267 bus-width = <4>;
17268 disable-wp;
17269 non-removable;
17270- num-slots = <1>;
17271 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
17272 pinctrl-names = "default";
17273 vmmc-supply = <&vcc_wifi>;
17274diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
17275index 8907deaab18e..400cbf9609e3 100644
17276--- a/arch/arm/boot/dts/rk3066a-rayeager.dts
17277+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
17278@@ -185,7 +185,6 @@ &emmc {
17279 cap-mmc-highspeed;
17280 disable-wp;
17281 non-removable;
17282- num-slots = <1>;
17283 pinctrl-names = "default";
17284 pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>;
17285 vmmc-supply = <&vcc_emmc>;
17286@@ -336,7 +335,6 @@ &i2c4 {
17287 &mmc0 {
17288 bus-width = <4>;
17289 disable-wp;
17290- num-slots = <1>;
17291 pinctrl-names = "default";
17292 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
17293 vmmc-supply = <&vcc_sd>;
17294@@ -349,7 +347,6 @@ &mmc1 {
17295 bus-width = <4>;
17296 disable-wp;
17297 non-removable;
17298- num-slots = <1>;
17299 pinctrl-names = "default";
17300 pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>;
17301 vmmc-supply = <&vccio_wl>;
17302diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts
17303index 5b2a0b6885cd..8ba9e06062f3 100644
17304--- a/arch/arm/boot/dts/rk3188-px3-evb.dts
17305+++ b/arch/arm/boot/dts/rk3188-px3-evb.dts
17306@@ -89,7 +89,6 @@ &emmc {
17307 cap-mmc-highspeed;
17308 disable-wp;
17309 non-removable;
17310- num-slots = <1>;
17311 pinctrl-names = "default";
17312 pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>;
17313 status = "okay";
17314@@ -256,7 +255,6 @@ gsl1680: touchscreen@40 {
17315 };
17316
17317 &mmc0 {
17318- num-slots = <1>;
17319 status = "okay";
17320 pinctrl-names = "default";
17321 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
17322diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
17323index ca0a1c4bc15c..53d6fc2fdbce 100644
17324--- a/arch/arm/boot/dts/rk3188-radxarock.dts
17325+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
17326@@ -296,7 +296,6 @@ vcc28: REG12 {
17327 };
17328
17329 &mmc0 {
17330- num-slots = <1>;
17331 status = "okay";
17332 pinctrl-names = "default";
17333 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
17334diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
17335index 1b55192b7d04..73e384585755 100644
17336--- a/arch/arm/boot/dts/rk3229-evb.dts
17337+++ b/arch/arm/boot/dts/rk3229-evb.dts
17338@@ -40,7 +40,8 @@
17339
17340 /dts-v1/;
17341
17342-#include "rk322x.dtsi"
17343+#include <dt-bindings/input/input.h>
17344+#include "rk3229.dtsi"
17345
17346 / {
17347 model = "Rockchip RK3229 Evaluation board";
17348@@ -51,6 +52,15 @@ memory@60000000 {
17349 reg = <0x60000000 0x40000000>;
17350 };
17351
17352+ dc_12v: dc-12v-regulator {
17353+ compatible = "regulator-fixed";
17354+ regulator-name = "dc_12v";
17355+ regulator-always-on;
17356+ regulator-boot-on;
17357+ regulator-min-microvolt = <12000000>;
17358+ regulator-max-microvolt = <12000000>;
17359+ };
17360+
17361 ext_gmac: ext_gmac {
17362 compatible = "fixed-clock";
17363 clock-frequency = <125000000>;
17364@@ -67,6 +77,7 @@ vcc_host: vcc-host-regulator {
17365 regulator-name = "vcc_host";
17366 regulator-always-on;
17367 regulator-boot-on;
17368+ vin-supply = <&vcc_sys>;
17369 };
17370
17371 vcc_phy: vcc-phy-regulator {
17372@@ -77,9 +88,98 @@ vcc_phy: vcc-phy-regulator {
17373 regulator-max-microvolt = <1800000>;
17374 regulator-always-on;
17375 regulator-boot-on;
17376+ vin-supply = <&vccio_1v8>;
17377+ };
17378+
17379+ vcc_sys: vcc-sys-regulator {
17380+ compatible = "regulator-fixed";
17381+ regulator-name = "vcc_sys";
17382+ regulator-always-on;
17383+ regulator-boot-on;
17384+ regulator-min-microvolt = <5000000>;
17385+ regulator-max-microvolt = <5000000>;
17386+ vin-supply = <&dc_12v>;
17387+ };
17388+
17389+ vccio_1v8: vccio-1v8-regulator {
17390+ compatible = "regulator-fixed";
17391+ regulator-name = "vccio_1v8";
17392+ regulator-min-microvolt = <1800000>;
17393+ regulator-max-microvolt = <1800000>;
17394+ regulator-always-on;
17395+ vin-supply = <&vcc_sys>;
17396+ };
17397+
17398+ vccio_3v3: vccio-3v3-regulator {
17399+ compatible = "regulator-fixed";
17400+ regulator-name = "vccio_3v3";
17401+ regulator-min-microvolt = <3300000>;
17402+ regulator-max-microvolt = <3300000>;
17403+ regulator-always-on;
17404+ vin-supply = <&vcc_sys>;
17405+ };
17406+
17407+ vdd_arm: vdd-arm-regulator {
17408+ compatible = "pwm-regulator";
17409+ pwms = <&pwm1 0 25000 1>;
17410+ pwm-supply = <&vcc_sys>;
17411+ regulator-name = "vdd_arm";
17412+ regulator-min-microvolt = <950000>;
17413+ regulator-max-microvolt = <1400000>;
17414+ regulator-always-on;
17415+ regulator-boot-on;
17416+ };
17417+
17418+ vdd_log: vdd-log-regulator {
17419+ compatible = "pwm-regulator";
17420+ pwms = <&pwm2 0 25000 1>;
17421+ pwm-supply = <&vcc_sys>;
17422+ regulator-name = "vdd_log";
17423+ regulator-min-microvolt = <1000000>;
17424+ regulator-max-microvolt = <1300000>;
17425+ regulator-always-on;
17426+ regulator-boot-on;
17427+ };
17428+
17429+ gpio_keys {
17430+ compatible = "gpio-keys";
17431+ autorepeat;
17432+ pinctrl-names = "default";
17433+ pinctrl-0 = <&pwr_key>;
17434+
17435+ power_key: power-key {
17436+ label = "GPIO Key Power";
17437+ gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
17438+ linux,code = <KEY_POWER>;
17439+ debounce-interval = <100>;
17440+ wakeup-source;
17441+ };
17442 };
17443 };
17444
17445+&cpu0 {
17446+ cpu-supply = <&vdd_arm>;
17447+};
17448+
17449+&cpu1 {
17450+ cpu-supply = <&vdd_arm>;
17451+};
17452+
17453+&cpu2 {
17454+ cpu-supply = <&vdd_arm>;
17455+};
17456+
17457+&cpu3 {
17458+ cpu-supply = <&vdd_arm>;
17459+};
17460+
17461+&emmc {
17462+ cap-mmc-highspeed;
17463+ disable-wp;
17464+ non-removable;
17465+ status = "okay";
17466+};
17467+
17468 &gmac {
17469 assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
17470 assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
17471@@ -96,7 +196,21 @@ &gmac {
17472 status = "okay";
17473 };
17474
17475+&io_domains {
17476+ status = "okay";
17477+
17478+ vccio1-supply = <&vccio_3v3>;
17479+ vccio2-supply = <&vccio_1v8>;
17480+ vccio4-supply = <&vccio_3v3>;
17481+};
17482+
17483 &pinctrl {
17484+ keys {
17485+ pwr_key: pwr-key {
17486+ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
17487+ };
17488+ };
17489+
17490 usb {
17491 host_vbus_drv: host-vbus-drv {
17492 rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
17493@@ -104,6 +218,19 @@ host_vbus_drv: host-vbus-drv {
17494 };
17495 };
17496
17497+&pwm1 {
17498+ status = "okay";
17499+};
17500+
17501+&pwm2 {
17502+ status = "okay";
17503+};
17504+
17505+&tsadc {
17506+ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
17507+ status = "okay";
17508+};
17509+
17510 &uart2 {
17511 status = "okay";
17512 };
17513diff --git a/arch/arm/boot/dts/rk3229.dtsi b/arch/arm/boot/dts/rk3229.dtsi
17514new file mode 100644
17515index 000000000000..6fe6c15fc13a
17516--- /dev/null
17517+++ b/arch/arm/boot/dts/rk3229.dtsi
17518@@ -0,0 +1,89 @@
17519+/*
17520+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
17521+ *
17522+ * This file is dual-licensed: you can use it either under the terms
17523+ * of the GPL or the X11 license, at your option. Note that this dual
17524+ * licensing only applies to this file, and not this project as a
17525+ * whole.
17526+ *
17527+ * a) This library is free software; you can redistribute it and/or
17528+ * modify it under the terms of the GNU General Public License as
17529+ * published by the Free Software Foundation; either version 2 of the
17530+ * License, or (at your option) any later version.
17531+ *
17532+ * This library is distributed in the hope that it will be useful,
17533+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
17534+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17535+ * GNU General Public License for more details.
17536+ *
17537+ * Or, alternatively,
17538+ *
17539+ * b) Permission is hereby granted, free of charge, to any person
17540+ * obtaining a copy of this software and associated documentation
17541+ * files (the "Software"), to deal in the Software without
17542+ * restriction, including without limitation the rights to use,
17543+ * copy, modify, merge, publish, distribute, sublicense, and/or
17544+ * sell copies of the Software, and to permit persons to whom the
17545+ * Software is furnished to do so, subject to the following
17546+ * conditions:
17547+ *
17548+ * The above copyright notice and this permission notice shall be
17549+ * included in all copies or substantial portions of the Software.
17550+ *
17551+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17552+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17553+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17554+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
17555+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
17556+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
17557+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
17558+ * OTHER DEALINGS IN THE SOFTWARE.
17559+ */
17560+
17561+#include "rk322x.dtsi"
17562+
17563+/ {
17564+ compatible = "rockchip,rk3229";
17565+
17566+ /delete-node/ opp-table0;
17567+
17568+ cpu0_opp_table: opp_table0 {
17569+ compatible = "operating-points-v2";
17570+ opp-shared;
17571+
17572+ opp-408000000 {
17573+ opp-hz = /bits/ 64 <408000000>;
17574+ opp-microvolt = <950000>;
17575+ clock-latency-ns = <40000>;
17576+ opp-suspend;
17577+ };
17578+ opp-600000000 {
17579+ opp-hz = /bits/ 64 <600000000>;
17580+ opp-microvolt = <975000>;
17581+ };
17582+ opp-816000000 {
17583+ opp-hz = /bits/ 64 <816000000>;
17584+ opp-microvolt = <1000000>;
17585+ };
17586+ opp-1008000000 {
17587+ opp-hz = /bits/ 64 <1008000000>;
17588+ opp-microvolt = <1175000>;
17589+ };
17590+ opp-1200000000 {
17591+ opp-hz = /bits/ 64 <1200000000>;
17592+ opp-microvolt = <1275000>;
17593+ };
17594+ opp-1296000000 {
17595+ opp-hz = /bits/ 64 <1296000000>;
17596+ opp-microvolt = <1325000>;
17597+ };
17598+ opp-1392000000 {
17599+ opp-hz = /bits/ 64 <1392000000>;
17600+ opp-microvolt = <1375000>;
17601+ };
17602+ opp-1464000000 {
17603+ opp-hz = /bits/ 64 <1464000000>;
17604+ opp-microvolt = <1400000>;
17605+ };
17606+ };
17607+};
17608diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
17609index f3e4ffd9f818..06814421eed2 100644
17610--- a/arch/arm/boot/dts/rk322x.dtsi
17611+++ b/arch/arm/boot/dts/rk322x.dtsi
17612@@ -55,6 +55,7 @@ aliases {
17613 serial0 = &uart0;
17614 serial1 = &uart1;
17615 serial2 = &uart2;
17616+ spi0 = &spi0;
17617 };
17618
17619 cpus {
17620@@ -70,6 +71,7 @@ cpu0: cpu@f00 {
17621 #cooling-cells = <2>; /* min followed by max */
17622 clock-latency = <40000>;
17623 clocks = <&cru ARMCLK>;
17624+ enable-method = "psci";
17625 };
17626
17627 cpu1: cpu@f01 {
17628@@ -78,6 +80,7 @@ cpu1: cpu@f01 {
17629 reg = <0xf01>;
17630 resets = <&cru SRST_CORE1>;
17631 operating-points-v2 = <&cpu0_opp_table>;
17632+ enable-method = "psci";
17633 };
17634
17635 cpu2: cpu@f02 {
17636@@ -86,6 +89,7 @@ cpu2: cpu@f02 {
17637 reg = <0xf02>;
17638 resets = <&cru SRST_CORE2>;
17639 operating-points-v2 = <&cpu0_opp_table>;
17640+ enable-method = "psci";
17641 };
17642
17643 cpu3: cpu@f03 {
17644@@ -94,6 +98,7 @@ cpu3: cpu@f03 {
17645 reg = <0xf03>;
17646 resets = <&cru SRST_CORE3>;
17647 operating-points-v2 = <&cpu0_opp_table>;
17648+ enable-method = "psci";
17649 };
17650 };
17651
17652@@ -151,6 +156,11 @@ arm-pmu {
17653 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
17654 };
17655
17656+ psci {
17657+ compatible = "arm,psci-1.0", "arm,psci-0.2";
17658+ method = "smc";
17659+ };
17660+
17661 timer {
17662 compatible = "arm,armv7-timer";
17663 arm,cpu-registers-not-fw-configured;
17664@@ -196,6 +206,19 @@ i2s0: i2s0@100c0000 {
17665 status = "disabled";
17666 };
17667
17668+ spdif: spdif@100d0000 {
17669+ compatible = "rockchip,rk3228-spdif";
17670+ reg = <0x100d0000 0x1000>;
17671+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
17672+ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
17673+ clock-names = "mclk", "hclk";
17674+ dmas = <&pdma 10>;
17675+ dma-names = "tx";
17676+ pinctrl-names = "default";
17677+ pinctrl-0 = <&spdif_tx>;
17678+ status = "disabled";
17679+ };
17680+
17681 i2s2: i2s2@100e0000 {
17682 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
17683 reg = <0x100e0000 0x4000>;
17684@@ -215,6 +238,11 @@ grf: syscon@11000000 {
17685 #address-cells = <1>;
17686 #size-cells = <1>;
17687
17688+ io_domains: io-domains {
17689+ compatible = "rockchip,rk3228-io-voltage-domain";
17690+ status = "disabled";
17691+ };
17692+
17693 u2phy0: usb2-phy@760 {
17694 compatible = "rockchip,rk3228-usb2phy";
17695 reg = <0x0760 0x0c>;
17696@@ -309,6 +337,23 @@ uart2: serial@11030000 {
17697 status = "disabled";
17698 };
17699
17700+ efuse: efuse@11040000 {
17701+ compatible = "rockchip,rk3228-efuse";
17702+ reg = <0x11040000 0x20>;
17703+ clocks = <&cru PCLK_EFUSE_256>;
17704+ clock-names = "pclk_efuse";
17705+ #address-cells = <1>;
17706+ #size-cells = <1>;
17707+
17708+ /* Data cells */
17709+ efuse_id: id@7 {
17710+ reg = <0x7 0x10>;
17711+ };
17712+ cpu_leakage: cpu_leakage@17 {
17713+ reg = <0x17 0x1>;
17714+ };
17715+ };
17716+
17717 i2c0: i2c@11050000 {
17718 compatible = "rockchip,rk3228-i2c";
17719 reg = <0x11050000 0x1000>;
17720@@ -361,6 +406,19 @@ i2c3: i2c@11080000 {
17721 status = "disabled";
17722 };
17723
17724+ spi0: spi@11090000 {
17725+ compatible = "rockchip,rk3228-spi";
17726+ reg = <0x11090000 0x1000>;
17727+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
17728+ #address-cells = <1>;
17729+ #size-cells = <0>;
17730+ clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
17731+ clock-names = "spiclk", "apb_pclk";
17732+ pinctrl-names = "default";
17733+ pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
17734+ status = "disabled";
17735+ };
17736+
17737 wdt: watchdog@110a0000 {
17738 compatible = "snps,dw-wdt";
17739 reg = <0x110a0000 0x100>;
17740@@ -500,8 +558,70 @@ tsadc: tsadc@11150000 {
17741 status = "disabled";
17742 };
17743
17744+ vpu_mmu: iommu@20020800 {
17745+ compatible = "rockchip,iommu";
17746+ reg = <0x20020800 0x100>;
17747+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
17748+ interrupt-names = "vpu_mmu";
17749+ iommu-cells = <0>;
17750+ status = "disabled";
17751+ };
17752+
17753+ vdec_mmu: iommu@20030480 {
17754+ compatible = "rockchip,iommu";
17755+ reg = <0x20030480 0x40>, <0x200304c0 0x40>;
17756+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
17757+ interrupt-names = "vdec_mmu";
17758+ iommu-cells = <0>;
17759+ status = "disabled";
17760+ };
17761+
17762+ vop_mmu: iommu@20053f00 {
17763+ compatible = "rockchip,iommu";
17764+ reg = <0x20053f00 0x100>;
17765+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
17766+ interrupt-names = "vop_mmu";
17767+ iommu-cells = <0>;
17768+ status = "disabled";
17769+ };
17770+
17771+ iep_mmu: iommu@20070800 {
17772+ compatible = "rockchip,iommu";
17773+ reg = <0x20070800 0x100>;
17774+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
17775+ interrupt-names = "iep_mmu";
17776+ iommu-cells = <0>;
17777+ status = "disabled";
17778+ };
17779+
17780+ sdmmc: dwmmc@30000000 {
17781+ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
17782+ reg = <0x30000000 0x4000>;
17783+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
17784+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
17785+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
17786+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
17787+ fifo-depth = <0x100>;
17788+ pinctrl-names = "default";
17789+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
17790+ status = "disabled";
17791+ };
17792+
17793+ sdio: dwmmc@30010000 {
17794+ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
17795+ reg = <0x30010000 0x4000>;
17796+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
17797+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
17798+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
17799+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
17800+ fifo-depth = <0x100>;
17801+ pinctrl-names = "default";
17802+ pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
17803+ status = "disabled";
17804+ };
17805+
17806 emmc: dwmmc@30020000 {
17807- compatible = "rockchip,rk3288-dw-mshc";
17808+ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
17809 reg = <0x30020000 0x4000>;
17810 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
17811 clock-frequency = <37500000>;
17812@@ -511,7 +631,6 @@ emmc: dwmmc@30020000 {
17813 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
17814 bus-width = <8>;
17815 default-sample-phase = <158>;
17816- num-slots = <1>;
17817 fifo-depth = <0x100>;
17818 pinctrl-names = "default";
17819 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
17820@@ -710,6 +829,40 @@ pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
17821 drive-strength = <12>;
17822 };
17823
17824+ sdmmc {
17825+ sdmmc_clk: sdmmc-clk {
17826+ rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
17827+ };
17828+
17829+ sdmmc_cmd: sdmmc-cmd {
17830+ rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
17831+ };
17832+
17833+ sdmmc_bus4: sdmmc-bus4 {
17834+ rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
17835+ <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
17836+ <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
17837+ <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
17838+ };
17839+ };
17840+
17841+ sdio {
17842+ sdio_clk: sdio-clk {
17843+ rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
17844+ };
17845+
17846+ sdio_cmd: sdio-cmd {
17847+ rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
17848+ };
17849+
17850+ sdio_bus4: sdio-bus4 {
17851+ rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
17852+ <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
17853+ <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
17854+ <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
17855+ };
17856+ };
17857+
17858 emmc {
17859 emmc_clk: emmc-clk {
17860 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
17861@@ -797,6 +950,42 @@ i2c3_xfer: i2c3-xfer {
17862 };
17863 };
17864
17865+ spi-0 {
17866+ spi0_clk: spi0-clk {
17867+ rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>;
17868+ };
17869+ spi0_cs0: spi0-cs0 {
17870+ rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>;
17871+ };
17872+ spi0_tx: spi0-tx {
17873+ rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
17874+ };
17875+ spi0_rx: spi0-rx {
17876+ rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
17877+ };
17878+ spi0_cs1: spi0-cs1 {
17879+ rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>;
17880+ };
17881+ };
17882+
17883+ spi-1 {
17884+ spi1_clk: spi1-clk {
17885+ rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>;
17886+ };
17887+ spi1_cs0: spi1-cs0 {
17888+ rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>;
17889+ };
17890+ spi1_rx: spi1-rx {
17891+ rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>;
17892+ };
17893+ spi1_tx: spi1-tx {
17894+ rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>;
17895+ };
17896+ spi1_cs1: spi1-cs1 {
17897+ rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>;
17898+ };
17899+ };
17900+
17901 i2s1 {
17902 i2s1_bus: i2s1-bus {
17903 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
17904@@ -835,6 +1024,12 @@ pwm3_pin: pwm3-pin {
17905 };
17906 };
17907
17908+ spdif {
17909+ spdif_tx: spdif-tx {
17910+ rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>;
17911+ };
17912+ };
17913+
17914 tsadc {
17915 otp_gpio: otp-gpio {
17916 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
17917diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
17918index 0dec94c3583b..39b61dce97ad 100644
17919--- a/arch/arm/boot/dts/rk3288-evb.dtsi
17920+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
17921@@ -45,7 +45,44 @@
17922 / {
17923 memory@0 {
17924 device_type = "memory";
17925- reg = <0x0 0x80000000>;
17926+ reg = <0x0 0x0 0x0 0x80000000>;
17927+ };
17928+
17929+ adc-keys {
17930+ compatible = "adc-keys";
17931+ io-channels = <&saradc 1>;
17932+ io-channel-names = "buttons";
17933+ keyup-threshold-microvolt = <1800000>;
17934+
17935+ button-up {
17936+ label = "Volume Up";
17937+ linux,code = <KEY_VOLUMEUP>;
17938+ press-threshold-microvolt = <100000>;
17939+ };
17940+
17941+ button-down {
17942+ label = "Volume Down";
17943+ linux,code = <KEY_VOLUMEDOWN>;
17944+ press-threshold-microvolt = <300000>;
17945+ };
17946+
17947+ menu {
17948+ label = "Menu";
17949+ linux,code = <KEY_MENU>;
17950+ press-threshold-microvolt = <640000>;
17951+ };
17952+
17953+ esc {
17954+ label = "Esc";
17955+ linux,code = <KEY_ESC>;
17956+ press-threshold-microvolt = <1000000>;
17957+ };
17958+
17959+ home {
17960+ label = "Home";
17961+ linux,code = <KEY_HOME>;
17962+ press-threshold-microvolt = <1300000>;
17963+ };
17964 };
17965
17966 backlight: backlight {
17967@@ -212,19 +249,22 @@ &emmc {
17968 cap-mmc-highspeed;
17969 disable-wp;
17970 non-removable;
17971- num-slots = <1>;
17972 pinctrl-names = "default";
17973 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
17974 status = "okay";
17975 };
17976
17977+&saradc {
17978+ vref-supply = <&vcc_18>;
17979+ status = "okay";
17980+};
17981+
17982 &sdmmc {
17983 bus-width = <4>;
17984 cap-mmc-highspeed;
17985 cap-sd-highspeed;
17986 card-detect-delay = <200>;
17987 disable-wp; /* wp not hooked up */
17988- num-slots = <1>;
17989 pinctrl-names = "default";
17990 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
17991 status = "okay";
17992@@ -248,6 +288,11 @@ &gmac {
17993 status = "ok";
17994 };
17995
17996+&gpu {
17997+ mali-supply = <&vdd_gpu>;
17998+ status = "okay";
17999+};
18000+
18001 &hdmi {
18002 ddc-i2c-bus = <&i2c5>;
18003 status = "okay";
18004diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts
18005index 61d1c1028317..41405974253a 100644
18006--- a/arch/arm/boot/dts/rk3288-fennec.dts
18007+++ b/arch/arm/boot/dts/rk3288-fennec.dts
18008@@ -47,7 +47,7 @@ / {
18009 compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
18010
18011 memory@0 {
18012- reg = <0x0 0x80000000>;
18013+ reg = <0x0 0x0 0x0 0x80000000>;
18014 device_type = "memory";
18015 };
18016
18017@@ -77,7 +77,6 @@ &emmc {
18018 cap-mmc-highspeed;
18019 disable-wp;
18020 non-removable;
18021- num-slots = <1>;
18022 pinctrl-names = "default";
18023 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
18024 status = "okay";
18025@@ -99,6 +98,11 @@ &gmac {
18026 status = "okay";
18027 };
18028
18029+&gpu {
18030+ mali-supply = <&vdd_gpu>;
18031+ status = "okay";
18032+};
18033+
18034 &hdmi {
18035 status = "okay";
18036 };
18037diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
18038index 813496618d08..5f05815f47e0 100644
18039--- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
18040+++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
18041@@ -47,7 +47,7 @@
18042 / {
18043 memory@0 {
18044 device_type = "memory";
18045- reg = <0 0x80000000>;
18046+ reg = <0x0 0x0 0x0 0x80000000>;
18047 };
18048
18049 ext_gmac: external-gmac-clock {
18050@@ -78,7 +78,6 @@ &emmc {
18051 mmc-ddr-1_8v;
18052 mmc-hs200-1_8v;
18053 non-removable;
18054- num-slots = <1>;
18055 pinctrl-names = "default";
18056 pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
18057 vmmc-supply = <&vcc_io>;
18058diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts
18059index b11a282c334c..7da0947ababb 100644
18060--- a/arch/arm/boot/dts/rk3288-firefly-reload.dts
18061+++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts
18062@@ -269,7 +269,6 @@ &sdmmc {
18063 cap-sd-highspeed;
18064 card-detect-delay = <200>;
18065 disable-wp;
18066- num-slots = <1>;
18067 pinctrl-names = "default";
18068 pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
18069 vmmc-supply = <&vcc_sd>;
18070@@ -284,7 +283,6 @@ &sdio0 {
18071 disable-wp;
18072 mmc-pwrseq = <&sdio_pwrseq>;
18073 non-removable;
18074- num-slots = <1>;
18075 pinctrl-names = "default";
18076 pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>;
18077 sd-uhs-sdr12;
18078diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
18079index 32dabae12e67..b9e6f3a97240 100644
18080--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
18081+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
18082@@ -46,7 +46,7 @@
18083 / {
18084 memory@0 {
18085 device_type = "memory";
18086- reg = <0 0x80000000>;
18087+ reg = <0x0 0x0 0x0 0x80000000>;
18088 };
18089
18090 adc-keys {
18091@@ -208,7 +208,6 @@ &emmc {
18092 cap-mmc-highspeed;
18093 disable-wp;
18094 non-removable;
18095- num-slots = <1>;
18096 pinctrl-names = "default";
18097 pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
18098 vmmc-supply = <&vcc_io>;
18099@@ -527,7 +526,6 @@ &sdio0 {
18100 bus-width = <4>;
18101 disable-wp;
18102 non-removable;
18103- num-slots = <1>;
18104 pinctrl-names = "default";
18105 pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>;
18106 vmmc-supply = <&vbat_wl>;
18107@@ -541,7 +539,6 @@ &sdmmc {
18108 cap-sd-highspeed;
18109 card-detect-delay = <200>;
18110 disable-wp;
18111- num-slots = <1>;
18112 pinctrl-names = "default";
18113 pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
18114 vmmc-supply = <&vcc_sd>;
18115diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
18116index 30e93f694ae8..4d923aa6ed11 100644
18117--- a/arch/arm/boot/dts/rk3288-miqi.dts
18118+++ b/arch/arm/boot/dts/rk3288-miqi.dts
18119@@ -54,7 +54,7 @@ chosen {
18120
18121 memory@0 {
18122 device_type = "memory";
18123- reg = <0 0x80000000>;
18124+ reg = <0x0 0x0 0x0 0x80000000>;
18125 };
18126
18127 ext_gmac: external-gmac-clock {
18128@@ -126,7 +126,6 @@ &emmc {
18129 cap-mmc-highspeed;
18130 disable-wp;
18131 non-removable;
18132- num-slots = <1>;
18133 pinctrl-names = "default";
18134 pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
18135 vmmc-supply = <&vcc_io>;
18136@@ -404,7 +403,6 @@ &sdmmc {
18137 cap-sd-highspeed;
18138 card-detect-delay = <200>;
18139 disable-wp;
18140- num-slots = <1>;
18141 pinctrl-names = "default";
18142 pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
18143 vmmc-supply = <&vcc_sd>;
18144diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
18145index 3dda79579b51..1241cbcfc16f 100644
18146--- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts
18147+++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
18148@@ -263,7 +263,6 @@ &sdmmc {
18149 cap-sd-highspeed;
18150 card-detect-delay = <200>;
18151 disable-wp;
18152- num-slots = <1>;
18153 pinctrl-names = "default";
18154 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
18155 vmmc-supply = <&vdd_io_sd>;
18156diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
18157index 26cd3ad45160..99cfae875e12 100644
18158--- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi
18159+++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
18160@@ -55,7 +55,7 @@ / {
18161 */
18162 memory {
18163 device_type = "memory";
18164- reg = <0 0x8000000>;
18165+ reg = <0x0 0x0 0x0 0x8000000>;
18166 };
18167
18168 aliases {
18169@@ -136,7 +136,6 @@ &emmc {
18170 cap-mmc-highspeed;
18171 disable-wp;
18172 non-removable;
18173- num-slots = <1>;
18174 pinctrl-names = "default";
18175 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
18176 vmmc-supply = <&vdd_3v3_io>;
18177diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
18178index aa1f9ecff231..f084e0c8dcb3 100644
18179--- a/arch/arm/boot/dts/rk3288-popmetal.dts
18180+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
18181@@ -50,7 +50,7 @@ / {
18182
18183 memory@0 {
18184 device_type = "memory";
18185- reg = <0 0x80000000>;
18186+ reg = <0x0 0x0 0x0 0x80000000>;
18187 };
18188
18189 ext_gmac: external-gmac-clock {
18190@@ -150,7 +150,6 @@ &emmc {
18191 mmc-ddr-1_8v;
18192 mmc-hs200-1_8v;
18193 non-removable;
18194- num-slots = <1>;
18195 pinctrl-names = "default";
18196 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
18197 vmmc-supply = <&vcc_io>;
18198@@ -164,7 +163,6 @@ &sdmmc {
18199 cap-sd-highspeed;
18200 card-detect-delay = <200>;
18201 disable-wp; /* wp not hooked up */
18202- num-slots = <1>;
18203 pinctrl-names = "default";
18204 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
18205 sd-uhs-sdr12;
18206diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts
18207index 1145b62edde7..e95215c9788b 100644
18208--- a/arch/arm/boot/dts/rk3288-r89.dts
18209+++ b/arch/arm/boot/dts/rk3288-r89.dts
18210@@ -50,7 +50,7 @@ / {
18211
18212 memory@0 {
18213 device_type = "memory";
18214- reg = <0x0 0x80000000>;
18215+ reg = <0x0 0x0 0x0 0x80000000>;
18216 };
18217
18218 ext_gmac: external-gmac-clock {
18219@@ -354,7 +354,6 @@ &sdmmc {
18220 cap-sd-highspeed;
18221 card-detect-delay = <200>;
18222 disable-wp;
18223- num-slots = <1>;
18224 pinctrl-names = "default";
18225 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
18226 vmmc-supply = <&vcc_sdmmc>;
18227diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
18228index 749a9b86e6e2..b9c471fcbd42 100644
18229--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi
18230+++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
18231@@ -43,7 +43,7 @@
18232
18233 / {
18234 memory@0 {
18235- reg = <0x0 0x80000000>;
18236+ reg = <0x0 0x0 0x0 0x80000000>;
18237 device_type = "memory";
18238 };
18239
18240@@ -89,7 +89,6 @@ &emmc {
18241 cap-mmc-highspeed;
18242 disable-wp;
18243 non-removable;
18244- num-slots = <1>;
18245 mmc-pwrseq = <&emmc_pwrseq>;
18246 pinctrl-names = "default";
18247 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
18248diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts
18249index 8ed25e9f60bc..0e084b8a86ac 100644
18250--- a/arch/arm/boot/dts/rk3288-rock2-square.dts
18251+++ b/arch/arm/boot/dts/rk3288-rock2-square.dts
18252@@ -147,7 +147,6 @@ &sdio0 {
18253 disable-wp;
18254 mmc-pwrseq = <&sdio_pwrseq>;
18255 non-removable;
18256- num-slots = <1>;
18257 pinctrl-names = "default";
18258 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk &sdio0_int>;
18259 vmmc-supply = <&vcc_io>;
18260@@ -161,7 +160,6 @@ &sdmmc {
18261 cap-sd-highspeed;
18262 card-detect-delay = <200>;
18263 disable-wp; /* wp not hooked up */
18264- num-slots = <1>;
18265 pinctrl-names = "default";
18266 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
18267 vmmc-supply = <&vcc_sd>;
18268diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
18269index f601c78386a9..346b0d8b474d 100644
18270--- a/arch/arm/boot/dts/rk3288-tinker.dts
18271+++ b/arch/arm/boot/dts/rk3288-tinker.dts
18272@@ -50,7 +50,7 @@ / {
18273 compatible = "asus,rk3288-tinker", "rockchip,rk3288";
18274
18275 memory {
18276- reg = <0x0 0x80000000>;
18277+ reg = <0x0 0x0 0x0 0x80000000>;
18278 device_type = "memory";
18279 };
18280
18281@@ -156,6 +156,11 @@ &gmac {
18282 status = "ok";
18283 };
18284
18285+&gpu {
18286+ mali-supply = <&vdd_gpu>;
18287+ status = "okay";
18288+};
18289+
18290 &hdmi {
18291 ddc-i2c-bus = <&i2c5>;
18292 status = "okay";
18293@@ -465,7 +470,6 @@ &sdmmc {
18294 cap-sd-highspeed;
18295 card-detect-delay = <200>;
18296 disable-wp; /* wp not hooked up */
18297- num-slots = <1>;
18298 pinctrl-names = "default";
18299 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
18300 status = "okay";
18301diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
18302index aef07101e9ab..95e9bee8bca2 100644
18303--- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
18304+++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
18305@@ -117,7 +117,6 @@ &sdmmc {
18306 card-detect-delay = <200>;
18307 cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>;
18308 rockchip,default-sample-phase = <90>;
18309- num-slots = <1>;
18310 sd-uhs-sdr12;
18311 sd-uhs-sdr25;
18312 sd-uhs-sdr50;
18313diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
18314index d709fa1847f9..6e5bd8974f22 100644
18315--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
18316+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
18317@@ -49,7 +49,7 @@
18318 / {
18319 memory@0 {
18320 device_type = "memory";
18321- reg = <0x0 0x80000000>;
18322+ reg = <0x0 0x0 0x0 0x80000000>;
18323 };
18324
18325 gpio_keys: gpio-keys {
18326@@ -156,7 +156,6 @@ &emmc {
18327 mmc-hs200-1_8v;
18328 mmc-pwrseq = <&emmc_pwrseq>;
18329 non-removable;
18330- num-slots = <1>;
18331 pinctrl-names = "default";
18332 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
18333 };
18334@@ -372,7 +371,6 @@ &sdio0 {
18335 keep-power-in-suspend;
18336 mmc-pwrseq = <&sdio_pwrseq>;
18337 non-removable;
18338- num-slots = <1>;
18339 pinctrl-names = "default";
18340 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
18341 sd-uhs-sdr12;
18342diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
18343index 858e1fed762a..356ed1e62452 100644
18344--- a/arch/arm/boot/dts/rk3288.dtsi
18345+++ b/arch/arm/boot/dts/rk3288.dtsi
18346@@ -49,8 +49,8 @@
18347 #include <dt-bindings/soc/rockchip,boot-mode.h>
18348
18349 / {
18350- #address-cells = <1>;
18351- #size-cells = <1>;
18352+ #address-cells = <2>;
18353+ #size-cells = <2>;
18354
18355 compatible = "rockchip,rk3288";
18356
18357@@ -139,13 +139,13 @@ cpu3: cpu@503 {
18358
18359 amba {
18360 compatible = "simple-bus";
18361- #address-cells = <1>;
18362- #size-cells = <1>;
18363+ #address-cells = <2>;
18364+ #size-cells = <2>;
18365 ranges;
18366
18367 dmac_peri: dma-controller@ff250000 {
18368 compatible = "arm,pl330", "arm,primecell";
18369- reg = <0xff250000 0x4000>;
18370+ reg = <0x0 0xff250000 0x0 0x4000>;
18371 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
18372 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
18373 #dma-cells = <1>;
18374@@ -156,7 +156,7 @@ dmac_peri: dma-controller@ff250000 {
18375
18376 dmac_bus_ns: dma-controller@ff600000 {
18377 compatible = "arm,pl330", "arm,primecell";
18378- reg = <0xff600000 0x4000>;
18379+ reg = <0x0 0xff600000 0x0 0x4000>;
18380 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
18381 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
18382 #dma-cells = <1>;
18383@@ -168,7 +168,7 @@ dmac_bus_ns: dma-controller@ff600000 {
18384
18385 dmac_bus_s: dma-controller@ffb20000 {
18386 compatible = "arm,pl330", "arm,primecell";
18387- reg = <0xffb20000 0x4000>;
18388+ reg = <0x0 0xffb20000 0x0 0x4000>;
18389 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
18390 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
18391 #dma-cells = <1>;
18392@@ -179,8 +179,8 @@ dmac_bus_s: dma-controller@ffb20000 {
18393 };
18394
18395 reserved-memory {
18396- #address-cells = <1>;
18397- #size-cells = <1>;
18398+ #address-cells = <2>;
18399+ #size-cells = <2>;
18400 ranges;
18401
18402 /*
18403@@ -194,7 +194,7 @@ reserved-memory {
18404 * is found.
18405 */
18406 dma-unusable@fe000000 {
18407- reg = <0xfe000000 0x1000000>;
18408+ reg = <0x0 0xfe000000 0x0 0x1000000>;
18409 };
18410 };
18411
18412@@ -217,7 +217,7 @@ timer {
18413
18414 timer: timer@ff810000 {
18415 compatible = "rockchip,rk3288-timer";
18416- reg = <0xff810000 0x20>;
18417+ reg = <0x0 0xff810000 0x0 0x20>;
18418 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
18419 clocks = <&xin24m>, <&cru PCLK_TIMER>;
18420 clock-names = "timer", "pclk";
18421@@ -236,7 +236,7 @@ sdmmc: dwmmc@ff0c0000 {
18422 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
18423 fifo-depth = <0x100>;
18424 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
18425- reg = <0xff0c0000 0x4000>;
18426+ reg = <0x0 0xff0c0000 0x0 0x4000>;
18427 resets = <&cru SRST_MMC0>;
18428 reset-names = "reset";
18429 status = "disabled";
18430@@ -250,7 +250,7 @@ sdio0: dwmmc@ff0d0000 {
18431 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
18432 fifo-depth = <0x100>;
18433 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
18434- reg = <0xff0d0000 0x4000>;
18435+ reg = <0x0 0xff0d0000 0x0 0x4000>;
18436 resets = <&cru SRST_SDIO0>;
18437 reset-names = "reset";
18438 status = "disabled";
18439@@ -264,7 +264,7 @@ sdio1: dwmmc@ff0e0000 {
18440 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
18441 fifo-depth = <0x100>;
18442 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
18443- reg = <0xff0e0000 0x4000>;
18444+ reg = <0x0 0xff0e0000 0x0 0x4000>;
18445 resets = <&cru SRST_SDIO1>;
18446 reset-names = "reset";
18447 status = "disabled";
18448@@ -278,7 +278,7 @@ emmc: dwmmc@ff0f0000 {
18449 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
18450 fifo-depth = <0x100>;
18451 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
18452- reg = <0xff0f0000 0x4000>;
18453+ reg = <0x0 0xff0f0000 0x0 0x4000>;
18454 resets = <&cru SRST_EMMC>;
18455 reset-names = "reset";
18456 status = "disabled";
18457@@ -286,7 +286,7 @@ emmc: dwmmc@ff0f0000 {
18458
18459 saradc: saradc@ff100000 {
18460 compatible = "rockchip,saradc";
18461- reg = <0xff100000 0x100>;
18462+ reg = <0x0 0xff100000 0x0 0x100>;
18463 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
18464 #io-channel-cells = <1>;
18465 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
18466@@ -305,7 +305,7 @@ spi0: spi@ff110000 {
18467 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
18468 pinctrl-names = "default";
18469 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
18470- reg = <0xff110000 0x1000>;
18471+ reg = <0x0 0xff110000 0x0 0x1000>;
18472 #address-cells = <1>;
18473 #size-cells = <0>;
18474 status = "disabled";
18475@@ -320,7 +320,7 @@ spi1: spi@ff120000 {
18476 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
18477 pinctrl-names = "default";
18478 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
18479- reg = <0xff120000 0x1000>;
18480+ reg = <0x0 0xff120000 0x0 0x1000>;
18481 #address-cells = <1>;
18482 #size-cells = <0>;
18483 status = "disabled";
18484@@ -335,7 +335,7 @@ spi2: spi@ff130000 {
18485 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
18486 pinctrl-names = "default";
18487 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
18488- reg = <0xff130000 0x1000>;
18489+ reg = <0x0 0xff130000 0x0 0x1000>;
18490 #address-cells = <1>;
18491 #size-cells = <0>;
18492 status = "disabled";
18493@@ -343,7 +343,7 @@ spi2: spi@ff130000 {
18494
18495 i2c1: i2c@ff140000 {
18496 compatible = "rockchip,rk3288-i2c";
18497- reg = <0xff140000 0x1000>;
18498+ reg = <0x0 0xff140000 0x0 0x1000>;
18499 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
18500 #address-cells = <1>;
18501 #size-cells = <0>;
18502@@ -356,7 +356,7 @@ i2c1: i2c@ff140000 {
18503
18504 i2c3: i2c@ff150000 {
18505 compatible = "rockchip,rk3288-i2c";
18506- reg = <0xff150000 0x1000>;
18507+ reg = <0x0 0xff150000 0x0 0x1000>;
18508 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
18509 #address-cells = <1>;
18510 #size-cells = <0>;
18511@@ -369,7 +369,7 @@ i2c3: i2c@ff150000 {
18512
18513 i2c4: i2c@ff160000 {
18514 compatible = "rockchip,rk3288-i2c";
18515- reg = <0xff160000 0x1000>;
18516+ reg = <0x0 0xff160000 0x0 0x1000>;
18517 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
18518 #address-cells = <1>;
18519 #size-cells = <0>;
18520@@ -382,7 +382,7 @@ i2c4: i2c@ff160000 {
18521
18522 i2c5: i2c@ff170000 {
18523 compatible = "rockchip,rk3288-i2c";
18524- reg = <0xff170000 0x1000>;
18525+ reg = <0x0 0xff170000 0x0 0x1000>;
18526 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
18527 #address-cells = <1>;
18528 #size-cells = <0>;
18529@@ -395,7 +395,7 @@ i2c5: i2c@ff170000 {
18530
18531 uart0: serial@ff180000 {
18532 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
18533- reg = <0xff180000 0x100>;
18534+ reg = <0x0 0xff180000 0x0 0x100>;
18535 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
18536 reg-shift = <2>;
18537 reg-io-width = <4>;
18538@@ -408,7 +408,7 @@ uart0: serial@ff180000 {
18539
18540 uart1: serial@ff190000 {
18541 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
18542- reg = <0xff190000 0x100>;
18543+ reg = <0x0 0xff190000 0x0 0x100>;
18544 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
18545 reg-shift = <2>;
18546 reg-io-width = <4>;
18547@@ -421,7 +421,7 @@ uart1: serial@ff190000 {
18548
18549 uart2: serial@ff690000 {
18550 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
18551- reg = <0xff690000 0x100>;
18552+ reg = <0x0 0xff690000 0x0 0x100>;
18553 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
18554 reg-shift = <2>;
18555 reg-io-width = <4>;
18556@@ -434,7 +434,7 @@ uart2: serial@ff690000 {
18557
18558 uart3: serial@ff1b0000 {
18559 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
18560- reg = <0xff1b0000 0x100>;
18561+ reg = <0x0 0xff1b0000 0x0 0x100>;
18562 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
18563 reg-shift = <2>;
18564 reg-io-width = <4>;
18565@@ -447,7 +447,7 @@ uart3: serial@ff1b0000 {
18566
18567 uart4: serial@ff1c0000 {
18568 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
18569- reg = <0xff1c0000 0x100>;
18570+ reg = <0x0 0xff1c0000 0x0 0x100>;
18571 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
18572 reg-shift = <2>;
18573 reg-io-width = <4>;
18574@@ -535,7 +535,7 @@ map0 {
18575
18576 tsadc: tsadc@ff280000 {
18577 compatible = "rockchip,rk3288-tsadc";
18578- reg = <0xff280000 0x100>;
18579+ reg = <0x0 0xff280000 0x0 0x100>;
18580 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
18581 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
18582 clock-names = "tsadc", "apb_pclk";
18583@@ -552,7 +552,7 @@ tsadc: tsadc@ff280000 {
18584
18585 gmac: ethernet@ff290000 {
18586 compatible = "rockchip,rk3288-gmac";
18587- reg = <0xff290000 0x10000>;
18588+ reg = <0x0 0xff290000 0x0 0x10000>;
18589 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
18590 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
18591 interrupt-names = "macirq", "eth_wake_irq";
18592@@ -572,7 +572,7 @@ gmac: ethernet@ff290000 {
18593
18594 usb_host0_ehci: usb@ff500000 {
18595 compatible = "generic-ehci";
18596- reg = <0xff500000 0x100>;
18597+ reg = <0x0 0xff500000 0x0 0x100>;
18598 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
18599 clocks = <&cru HCLK_USBHOST0>;
18600 clock-names = "usbhost";
18601@@ -586,7 +586,7 @@ usb_host0_ehci: usb@ff500000 {
18602 usb_host1: usb@ff540000 {
18603 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
18604 "snps,dwc2";
18605- reg = <0xff540000 0x40000>;
18606+ reg = <0x0 0xff540000 0x0 0x40000>;
18607 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
18608 clocks = <&cru HCLK_USBHOST1>;
18609 clock-names = "otg";
18610@@ -599,7 +599,7 @@ usb_host1: usb@ff540000 {
18611 usb_otg: usb@ff580000 {
18612 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
18613 "snps,dwc2";
18614- reg = <0xff580000 0x40000>;
18615+ reg = <0x0 0xff580000 0x0 0x40000>;
18616 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
18617 clocks = <&cru HCLK_OTG0>;
18618 clock-names = "otg";
18619@@ -614,7 +614,7 @@ usb_otg: usb@ff580000 {
18620
18621 usb_hsic: usb@ff5c0000 {
18622 compatible = "generic-ehci";
18623- reg = <0xff5c0000 0x100>;
18624+ reg = <0x0 0xff5c0000 0x0 0x100>;
18625 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
18626 clocks = <&cru HCLK_HSIC>;
18627 clock-names = "usbhost";
18628@@ -623,7 +623,7 @@ usb_hsic: usb@ff5c0000 {
18629
18630 i2c0: i2c@ff650000 {
18631 compatible = "rockchip,rk3288-i2c";
18632- reg = <0xff650000 0x1000>;
18633+ reg = <0x0 0xff650000 0x0 0x1000>;
18634 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
18635 #address-cells = <1>;
18636 #size-cells = <0>;
18637@@ -636,7 +636,7 @@ i2c0: i2c@ff650000 {
18638
18639 i2c2: i2c@ff660000 {
18640 compatible = "rockchip,rk3288-i2c";
18641- reg = <0xff660000 0x1000>;
18642+ reg = <0x0 0xff660000 0x0 0x1000>;
18643 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
18644 #address-cells = <1>;
18645 #size-cells = <0>;
18646@@ -649,7 +649,7 @@ i2c2: i2c@ff660000 {
18647
18648 pwm0: pwm@ff680000 {
18649 compatible = "rockchip,rk3288-pwm";
18650- reg = <0xff680000 0x10>;
18651+ reg = <0x0 0xff680000 0x0 0x10>;
18652 #pwm-cells = <3>;
18653 pinctrl-names = "default";
18654 pinctrl-0 = <&pwm0_pin>;
18655@@ -660,7 +660,7 @@ pwm0: pwm@ff680000 {
18656
18657 pwm1: pwm@ff680010 {
18658 compatible = "rockchip,rk3288-pwm";
18659- reg = <0xff680010 0x10>;
18660+ reg = <0x0 0xff680010 0x0 0x10>;
18661 #pwm-cells = <3>;
18662 pinctrl-names = "default";
18663 pinctrl-0 = <&pwm1_pin>;
18664@@ -671,7 +671,7 @@ pwm1: pwm@ff680010 {
18665
18666 pwm2: pwm@ff680020 {
18667 compatible = "rockchip,rk3288-pwm";
18668- reg = <0xff680020 0x10>;
18669+ reg = <0x0 0xff680020 0x0 0x10>;
18670 #pwm-cells = <3>;
18671 pinctrl-names = "default";
18672 pinctrl-0 = <&pwm2_pin>;
18673@@ -682,7 +682,7 @@ pwm2: pwm@ff680020 {
18674
18675 pwm3: pwm@ff680030 {
18676 compatible = "rockchip,rk3288-pwm";
18677- reg = <0xff680030 0x10>;
18678+ reg = <0x0 0xff680030 0x0 0x10>;
18679 #pwm-cells = <2>;
18680 pinctrl-names = "default";
18681 pinctrl-0 = <&pwm3_pin>;
18682@@ -693,10 +693,10 @@ pwm3: pwm@ff680030 {
18683
18684 bus_intmem@ff700000 {
18685 compatible = "mmio-sram";
18686- reg = <0xff700000 0x18000>;
18687+ reg = <0x0 0xff700000 0x0 0x18000>;
18688 #address-cells = <1>;
18689 #size-cells = <1>;
18690- ranges = <0 0xff700000 0x18000>;
18691+ ranges = <0 0x0 0xff700000 0x18000>;
18692 smp-sram@0 {
18693 compatible = "rockchip,rk3066-smp-sram";
18694 reg = <0x00 0x10>;
18695@@ -705,12 +705,12 @@ smp-sram@0 {
18696
18697 sram@ff720000 {
18698 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
18699- reg = <0xff720000 0x1000>;
18700+ reg = <0x0 0xff720000 0x0 0x1000>;
18701 };
18702
18703 pmu: power-management@ff730000 {
18704 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
18705- reg = <0xff730000 0x100>;
18706+ reg = <0x0 0xff730000 0x0 0x100>;
18707
18708 power: power-controller {
18709 compatible = "rockchip,rk3288-power-controller";
18710@@ -831,12 +831,12 @@ reboot-mode {
18711
18712 sgrf: syscon@ff740000 {
18713 compatible = "rockchip,rk3288-sgrf", "syscon";
18714- reg = <0xff740000 0x1000>;
18715+ reg = <0x0 0xff740000 0x0 0x1000>;
18716 };
18717
18718 cru: clock-controller@ff760000 {
18719 compatible = "rockchip,rk3288-cru";
18720- reg = <0xff760000 0x1000>;
18721+ reg = <0x0 0xff760000 0x0 0x1000>;
18722 rockchip,grf = <&grf>;
18723 #clock-cells = <1>;
18724 #reset-cells = <1>;
18725@@ -854,7 +854,7 @@ cru: clock-controller@ff760000 {
18726
18727 grf: syscon@ff770000 {
18728 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
18729- reg = <0xff770000 0x1000>;
18730+ reg = <0x0 0xff770000 0x0 0x1000>;
18731
18732 edp_phy: edp-phy {
18733 compatible = "rockchip,rk3288-dp-phy";
18734@@ -903,7 +903,7 @@ usbphy2: usb-phy@348 {
18735
18736 wdt: watchdog@ff800000 {
18737 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
18738- reg = <0xff800000 0x100>;
18739+ reg = <0x0 0xff800000 0x0 0x100>;
18740 clocks = <&cru PCLK_WDT>;
18741 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
18742 status = "disabled";
18743@@ -911,7 +911,7 @@ wdt: watchdog@ff800000 {
18744
18745 spdif: sound@ff88b0000 {
18746 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
18747- reg = <0xff8b0000 0x10000>;
18748+ reg = <0x0 0xff8b0000 0x0 0x10000>;
18749 #sound-dai-cells = <0>;
18750 clock-names = "hclk", "mclk";
18751 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
18752@@ -926,7 +926,7 @@ spdif: sound@ff88b0000 {
18753
18754 i2s: i2s@ff890000 {
18755 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
18756- reg = <0xff890000 0x10000>;
18757+ reg = <0x0 0xff890000 0x0 0x10000>;
18758 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
18759 #address-cells = <1>;
18760 #size-cells = <0>;
18761@@ -943,7 +943,7 @@ i2s: i2s@ff890000 {
18762
18763 crypto: cypto-controller@ff8a0000 {
18764 compatible = "rockchip,rk3288-crypto";
18765- reg = <0xff8a0000 0x4000>;
18766+ reg = <0x0 0xff8a0000 0x0 0x4000>;
18767 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
18768 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
18769 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
18770@@ -953,9 +953,28 @@ crypto: cypto-controller@ff8a0000 {
18771 status = "okay";
18772 };
18773
18774+ iep_mmu: iommu@ff900800 {
18775+ compatible = "rockchip,iommu";
18776+ reg = <0x0 0xff900800 0x0 0x40>;
18777+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
18778+ interrupt-names = "iep_mmu";
18779+ #iommu-cells = <0>;
18780+ status = "disabled";
18781+ };
18782+
18783+ isp_mmu: iommu@ff914000 {
18784+ compatible = "rockchip,iommu";
18785+ reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
18786+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
18787+ interrupt-names = "isp_mmu";
18788+ #iommu-cells = <0>;
18789+ rockchip,disable-mmu-reset;
18790+ status = "disabled";
18791+ };
18792+
18793 vopb: vop@ff930000 {
18794 compatible = "rockchip,rk3288-vop";
18795- reg = <0xff930000 0x19c>;
18796+ reg = <0x0 0xff930000 0x0 0x19c>;
18797 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
18798 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
18799 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
18800@@ -988,7 +1007,7 @@ vopb_out_mipi: endpoint@2 {
18801
18802 vopb_mmu: iommu@ff930300 {
18803 compatible = "rockchip,iommu";
18804- reg = <0xff930300 0x100>;
18805+ reg = <0x0 0xff930300 0x0 0x100>;
18806 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
18807 interrupt-names = "vopb_mmu";
18808 power-domains = <&power RK3288_PD_VIO>;
18809@@ -998,7 +1017,7 @@ vopb_mmu: iommu@ff930300 {
18810
18811 vopl: vop@ff940000 {
18812 compatible = "rockchip,rk3288-vop";
18813- reg = <0xff940000 0x19c>;
18814+ reg = <0x0 0xff940000 0x0 0x19c>;
18815 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
18816 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
18817 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
18818@@ -1031,7 +1050,7 @@ vopl_out_mipi: endpoint@2 {
18819
18820 vopl_mmu: iommu@ff940300 {
18821 compatible = "rockchip,iommu";
18822- reg = <0xff940300 0x100>;
18823+ reg = <0x0 0xff940300 0x0 0x100>;
18824 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
18825 interrupt-names = "vopl_mmu";
18826 power-domains = <&power RK3288_PD_VIO>;
18827@@ -1041,7 +1060,7 @@ vopl_mmu: iommu@ff940300 {
18828
18829 mipi_dsi: mipi@ff960000 {
18830 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
18831- reg = <0xff960000 0x4000>;
18832+ reg = <0x0 0xff960000 0x0 0x4000>;
18833 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
18834 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
18835 clock-names = "ref", "pclk";
18836@@ -1069,7 +1088,7 @@ mipi_in_vopl: endpoint@1 {
18837
18838 edp: dp@ff970000 {
18839 compatible = "rockchip,rk3288-dp";
18840- reg = <0xff970000 0x4000>;
18841+ reg = <0x0 0xff970000 0x0 0x4000>;
18842 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
18843 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
18844 clock-names = "dp", "pclk";
18845@@ -1101,7 +1120,7 @@ edp_in_vopl: endpoint@1 {
18846
18847 hdmi: hdmi@ff980000 {
18848 compatible = "rockchip,rk3288-dw-hdmi";
18849- reg = <0xff980000 0x20000>;
18850+ reg = <0x0 0xff980000 0x0 0x20000>;
18851 reg-io-width = <4>;
18852 rockchip,grf = <&grf>;
18853 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
18854@@ -1126,9 +1145,27 @@ hdmi_in_vopl: endpoint@1 {
18855 };
18856 };
18857
18858+ vpu_mmu: iommu@ff9a0800 {
18859+ compatible = "rockchip,iommu";
18860+ reg = <0x0 0xff9a0800 0x0 0x100>;
18861+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
18862+ interrupt-names = "vpu_mmu";
18863+ #iommu-cells = <0>;
18864+ status = "disabled";
18865+ };
18866+
18867+ hevc_mmu: iommu@ff9c0440 {
18868+ compatible = "rockchip,iommu";
18869+ reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
18870+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
18871+ interrupt-names = "hevc_mmu";
18872+ #iommu-cells = <0>;
18873+ status = "disabled";
18874+ };
18875+
18876 gpu: gpu@ffa30000 {
18877 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
18878- reg = <0xffa30000 0x10000>;
18879+ reg = <0x0 0xffa30000 0x0 0x10000>;
18880 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
18881 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
18882 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
18883@@ -1170,72 +1207,72 @@ opp@600000000 {
18884
18885 qos_gpu_r: qos@ffaa0000 {
18886 compatible = "syscon";
18887- reg = <0xffaa0000 0x20>;
18888+ reg = <0x0 0xffaa0000 0x0 0x20>;
18889 };
18890
18891 qos_gpu_w: qos@ffaa0080 {
18892 compatible = "syscon";
18893- reg = <0xffaa0080 0x20>;
18894+ reg = <0x0 0xffaa0080 0x0 0x20>;
18895 };
18896
18897 qos_vio1_vop: qos@ffad0000 {
18898 compatible = "syscon";
18899- reg = <0xffad0000 0x20>;
18900+ reg = <0x0 0xffad0000 0x0 0x20>;
18901 };
18902
18903 qos_vio1_isp_w0: qos@ffad0100 {
18904 compatible = "syscon";
18905- reg = <0xffad0100 0x20>;
18906+ reg = <0x0 0xffad0100 0x0 0x20>;
18907 };
18908
18909 qos_vio1_isp_w1: qos@ffad0180 {
18910 compatible = "syscon";
18911- reg = <0xffad0180 0x20>;
18912+ reg = <0x0 0xffad0180 0x0 0x20>;
18913 };
18914
18915 qos_vio0_vop: qos@ffad0400 {
18916 compatible = "syscon";
18917- reg = <0xffad0400 0x20>;
18918+ reg = <0x0 0xffad0400 0x0 0x20>;
18919 };
18920
18921 qos_vio0_vip: qos@ffad0480 {
18922 compatible = "syscon";
18923- reg = <0xffad0480 0x20>;
18924+ reg = <0x0 0xffad0480 0x0 0x20>;
18925 };
18926
18927 qos_vio0_iep: qos@ffad0500 {
18928 compatible = "syscon";
18929- reg = <0xffad0500 0x20>;
18930+ reg = <0x0 0xffad0500 0x0 0x20>;
18931 };
18932
18933 qos_vio2_rga_r: qos@ffad0800 {
18934 compatible = "syscon";
18935- reg = <0xffad0800 0x20>;
18936+ reg = <0x0 0xffad0800 0x0 0x20>;
18937 };
18938
18939 qos_vio2_rga_w: qos@ffad0880 {
18940 compatible = "syscon";
18941- reg = <0xffad0880 0x20>;
18942+ reg = <0x0 0xffad0880 0x0 0x20>;
18943 };
18944
18945 qos_vio1_isp_r: qos@ffad0900 {
18946 compatible = "syscon";
18947- reg = <0xffad0900 0x20>;
18948+ reg = <0x0 0xffad0900 0x0 0x20>;
18949 };
18950
18951 qos_video: qos@ffae0000 {
18952 compatible = "syscon";
18953- reg = <0xffae0000 0x20>;
18954+ reg = <0x0 0xffae0000 0x0 0x20>;
18955 };
18956
18957 qos_hevc_r: qos@ffaf0000 {
18958 compatible = "syscon";
18959- reg = <0xffaf0000 0x20>;
18960+ reg = <0x0 0xffaf0000 0x0 0x20>;
18961 };
18962
18963 qos_hevc_w: qos@ffaf0080 {
18964 compatible = "syscon";
18965- reg = <0xffaf0080 0x20>;
18966+ reg = <0x0 0xffaf0080 0x0 0x20>;
18967 };
18968
18969 gic: interrupt-controller@ffc01000 {
18970@@ -1244,16 +1281,16 @@ gic: interrupt-controller@ffc01000 {
18971 #interrupt-cells = <3>;
18972 #address-cells = <0>;
18973
18974- reg = <0xffc01000 0x1000>,
18975- <0xffc02000 0x2000>,
18976- <0xffc04000 0x2000>,
18977- <0xffc06000 0x2000>;
18978+ reg = <0x0 0xffc01000 0x0 0x1000>,
18979+ <0x0 0xffc02000 0x0 0x2000>,
18980+ <0x0 0xffc04000 0x0 0x2000>,
18981+ <0x0 0xffc06000 0x0 0x2000>;
18982 interrupts = <GIC_PPI 9 0xf04>;
18983 };
18984
18985 efuse: efuse@ffb40000 {
18986 compatible = "rockchip,rk3288-efuse";
18987- reg = <0xffb40000 0x20>;
18988+ reg = <0x0 0xffb40000 0x0 0x20>;
18989 #address-cells = <1>;
18990 #size-cells = <1>;
18991 clocks = <&cru PCLK_EFUSE256>;
18992@@ -1268,13 +1305,13 @@ pinctrl: pinctrl {
18993 compatible = "rockchip,rk3288-pinctrl";
18994 rockchip,grf = <&grf>;
18995 rockchip,pmu = <&pmu>;
18996- #address-cells = <1>;
18997- #size-cells = <1>;
18998+ #address-cells = <2>;
18999+ #size-cells = <2>;
19000 ranges;
19001
19002 gpio0: gpio0@ff750000 {
19003 compatible = "rockchip,gpio-bank";
19004- reg = <0xff750000 0x100>;
19005+ reg = <0x0 0xff750000 0x0 0x100>;
19006 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
19007 clocks = <&cru PCLK_GPIO0>;
19008
19009@@ -1287,7 +1324,7 @@ gpio0: gpio0@ff750000 {
19010
19011 gpio1: gpio1@ff780000 {
19012 compatible = "rockchip,gpio-bank";
19013- reg = <0xff780000 0x100>;
19014+ reg = <0x0 0xff780000 0x0 0x100>;
19015 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
19016 clocks = <&cru PCLK_GPIO1>;
19017
19018@@ -1300,7 +1337,7 @@ gpio1: gpio1@ff780000 {
19019
19020 gpio2: gpio2@ff790000 {
19021 compatible = "rockchip,gpio-bank";
19022- reg = <0xff790000 0x100>;
19023+ reg = <0x0 0xff790000 0x0 0x100>;
19024 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
19025 clocks = <&cru PCLK_GPIO2>;
19026
19027@@ -1313,7 +1350,7 @@ gpio2: gpio2@ff790000 {
19028
19029 gpio3: gpio3@ff7a0000 {
19030 compatible = "rockchip,gpio-bank";
19031- reg = <0xff7a0000 0x100>;
19032+ reg = <0x0 0xff7a0000 0x0 0x100>;
19033 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
19034 clocks = <&cru PCLK_GPIO3>;
19035
19036@@ -1326,7 +1363,7 @@ gpio3: gpio3@ff7a0000 {
19037
19038 gpio4: gpio4@ff7b0000 {
19039 compatible = "rockchip,gpio-bank";
19040- reg = <0xff7b0000 0x100>;
19041+ reg = <0x0 0xff7b0000 0x0 0x100>;
19042 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
19043 clocks = <&cru PCLK_GPIO4>;
19044
19045@@ -1339,7 +1376,7 @@ gpio4: gpio4@ff7b0000 {
19046
19047 gpio5: gpio5@ff7c0000 {
19048 compatible = "rockchip,gpio-bank";
19049- reg = <0xff7c0000 0x100>;
19050+ reg = <0x0 0xff7c0000 0x0 0x100>;
19051 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
19052 clocks = <&cru PCLK_GPIO5>;
19053
19054@@ -1352,7 +1389,7 @@ gpio5: gpio5@ff7c0000 {
19055
19056 gpio6: gpio6@ff7d0000 {
19057 compatible = "rockchip,gpio-bank";
19058- reg = <0xff7d0000 0x100>;
19059+ reg = <0x0 0xff7d0000 0x0 0x100>;
19060 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
19061 clocks = <&cru PCLK_GPIO6>;
19062
19063@@ -1365,7 +1402,7 @@ gpio6: gpio6@ff7d0000 {
19064
19065 gpio7: gpio7@ff7e0000 {
19066 compatible = "rockchip,gpio-bank";
19067- reg = <0xff7e0000 0x100>;
19068+ reg = <0x0 0xff7e0000 0x0 0x100>;
19069 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
19070 clocks = <&cru PCLK_GPIO7>;
19071
19072@@ -1378,7 +1415,7 @@ gpio7: gpio7@ff7e0000 {
19073
19074 gpio8: gpio8@ff7f0000 {
19075 compatible = "rockchip,gpio-bank";
19076- reg = <0xff7f0000 0x100>;
19077+ reg = <0x0 0xff7f0000 0x0 0x100>;
19078 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
19079 clocks = <&cru PCLK_GPIO8>;
19080
19081diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
19082index 58cf4ac079c3..86a57f823616 100644
19083--- a/arch/arm/boot/dts/rv1108-evb.dts
19084+++ b/arch/arm/boot/dts/rv1108-evb.dts
19085@@ -54,6 +54,184 @@ memory@60000000 {
19086 chosen {
19087 stdout-path = "serial2:1500000n8";
19088 };
19089+
19090+ backlight: backlight {
19091+ compatible = "pwm-backlight";
19092+ brightness-levels = <
19093+ 0 1 2 3 4 5 6 7
19094+ 8 9 10 11 12 13 14 15
19095+ 16 17 18 19 20 21 22 23
19096+ 24 25 26 27 28 29 30 31
19097+ 32 33 34 35 36 37 38 39
19098+ 40 41 42 43 44 45 46 47
19099+ 48 49 50 51 52 53 54 55
19100+ 56 57 58 59 60 61 62 63
19101+ 64 65 66 67 68 69 70 71
19102+ 72 73 74 75 76 77 78 79
19103+ 80 81 82 83 84 85 86 87
19104+ 88 89 90 91 92 93 94 95
19105+ 96 97 98 99 100 101 102 103
19106+ 104 105 106 107 108 109 110 111
19107+ 112 113 114 115 116 117 118 119
19108+ 120 121 122 123 124 125 126 127
19109+ 128 129 130 131 132 133 134 135
19110+ 136 137 138 139 140 141 142 143
19111+ 144 145 146 147 148 149 150 151
19112+ 152 153 154 155 156 157 158 159
19113+ 160 161 162 163 164 165 166 167
19114+ 168 169 170 171 172 173 174 175
19115+ 176 177 178 179 180 181 182 183
19116+ 184 185 186 187 188 189 190 191
19117+ 192 193 194 195 196 197 198 199
19118+ 200 201 202 203 204 205 206 207
19119+ 208 209 210 211 212 213 214 215
19120+ 216 217 218 219 220 221 222 223
19121+ 224 225 226 227 228 229 230 231
19122+ 232 233 234 235 236 237 238 239
19123+ 240 241 242 243 244 245 246 247
19124+ 248 249 250 251 252 253 254 255>;
19125+ default-brightness-level = <200>;
19126+ pwms = <&pwm0 0 25000 0>;
19127+ };
19128+
19129+ vcc_sys: vsys-regulator {
19130+ compatible = "regulator-fixed";
19131+ regulator-name = "vsys";
19132+ regulator-min-microvolt = <5000000>;
19133+ regulator-max-microvolt = <5000000>;
19134+ regulator-boot-on;
19135+ };
19136+};
19137+
19138+&cpu0 {
19139+ cpu-supply = <&vdd_core>;
19140+};
19141+
19142+&i2c0 {
19143+ status = "okay";
19144+ i2c-scl-rising-time-ns = <275>;
19145+ i2c-scl-falling-time-ns = <16>;
19146+ clock-frequency = <400000>;
19147+
19148+ rk805: pmic@18 {
19149+ compatible = "rockchip,rk805";
19150+ reg = <0x18>;
19151+ interrupt-parent = <&gpio0>;
19152+ interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
19153+ rockchip,system-power-controller;
19154+
19155+ vcc1-supply = <&vcc_sys>;
19156+ vcc2-supply = <&vcc_sys>;
19157+ vcc3-supply = <&vcc_sys>;
19158+ vcc4-supply = <&vcc_sys>;
19159+ vcc5-supply = <&vcc_sys>;
19160+ vcc6-supply = <&vcc_sys>;
19161+
19162+ regulators {
19163+ vdd_core: DCDC_REG1 {
19164+ regulator-name= "vdd_core";
19165+ regulator-min-microvolt = <700000>;
19166+ regulator-max-microvolt = <1500000>;
19167+ regulator-always-on;
19168+ regulator-boot-on;
19169+ regulator-state-mem {
19170+ regulator-state-enabled;
19171+ regulator-state-uv = <900000>;
19172+ };
19173+ };
19174+
19175+ vdd_cam: DCDC_REG2 {
19176+ regulator-name= "vdd_cam";
19177+ regulator-min-microvolt = <700000>;
19178+ regulator-max-microvolt = <2000000>;
19179+ regulator-state-mem {
19180+ regulator-state-disabled;
19181+ };
19182+ };
19183+
19184+ vcc_ddr: DCDC_REG3 {
19185+ regulator-name= "vcc_ddr";
19186+ regulator-always-on;
19187+ regulator-boot-on;
19188+ regulator-state-mem {
19189+ regulator-state-enabled;
19190+ };
19191+ };
19192+
19193+ vcc_io: DCDC_REG4 {
19194+ regulator-name= "vcc_io";
19195+ regulator-min-microvolt = <3300000>;
19196+ regulator-max-microvolt = <3300000>;
19197+ regulator-always-on;
19198+ regulator-boot-on;
19199+ regulator-state-mem {
19200+ regulator-state-enabled;
19201+ regulator-state-uv = <3300000>;
19202+ };
19203+ };
19204+
19205+ vdd_10: LDO_REG1 {
19206+ regulator-name= "vdd_10";
19207+ regulator-min-microvolt = <1000000>;
19208+ regulator-max-microvolt = <1000000>;
19209+ regulator-always-on;
19210+ regulator-boot-on;
19211+ regulator-state-mem {
19212+ regulator-state-disabled;
19213+ };
19214+ };
19215+
19216+ vcc_18: LDO_REG2 {
19217+ regulator-name= "vcc_18";
19218+ regulator-min-microvolt = <1800000>;
19219+ regulator-max-microvolt = <1800000>;
19220+ regulator-always-on;
19221+ regulator-boot-on;
19222+ regulator-state-mem {
19223+ regulator-state-disabled;
19224+ };
19225+ };
19226+
19227+ vdd10_pmu: LDO_REG3 {
19228+ regulator-name= "vdd10_pmu";
19229+ regulator-min-microvolt = <1000000>;
19230+ regulator-max-microvolt = <1000000>;
19231+ regulator-always-on;
19232+ regulator-boot-on;
19233+ regulator-state-mem {
19234+ regulator-state-enabled;
19235+ regulator-state-uv = <1000000>;
19236+ };
19237+ };
19238+ };
19239+ };
19240+
19241+ bma250: accelerometer@19 {
19242+ compatible = "bosch,bma250e";
19243+ reg = <0x19>;
19244+ interrupt-parent = <&gpio0>;
19245+ interrupts = <RK_PB3 IRQ_TYPE_LEVEL_LOW>;
19246+ };
19247+};
19248+
19249+&pwm0 {
19250+ status = "okay";
19251+};
19252+
19253+&sdmmc {
19254+ status = "okay";
19255+};
19256+
19257+&u2phy {
19258+ status = "okay";
19259+
19260+ u2phy_host: host-port {
19261+ status = "okay";
19262+ };
19263+
19264+ u2phy_otg: otg-port {
19265+ status = "okay";
19266+ };
19267 };
19268
19269 &uart0 {
19270@@ -67,3 +245,15 @@ &uart1 {
19271 &uart2 {
19272 status = "okay";
19273 };
19274+
19275+&usb_host_ehci {
19276+ status = "okay";
19277+};
19278+
19279+&usb_host_ohci {
19280+ status = "okay";
19281+};
19282+
19283+&usb_otg {
19284+ status = "okay";
19285+};
19286diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
19287index 437098b556eb..e7cd1315db1b 100644
19288--- a/arch/arm/boot/dts/rv1108.dtsi
19289+++ b/arch/arm/boot/dts/rv1108.dtsi
19290@@ -52,6 +52,10 @@ / {
19291 interrupt-parent = <&gic>;
19292
19293 aliases {
19294+ i2c0 = &i2c0;
19295+ i2c1 = &i2c1;
19296+ i2c2 = &i2c2;
19297+ i2c3 = &i2c3;
19298 serial0 = &uart0;
19299 serial1 = &uart1;
19300 serial2 = &uart2;
19301@@ -65,6 +69,33 @@ cpu0: cpu@f00 {
19302 device_type = "cpu";
19303 compatible = "arm,cortex-a7";
19304 reg = <0xf00>;
19305+ clocks = <&cru ARMCLK>;
19306+ operating-points-v2 = <&cpu_opp_table>;
19307+ };
19308+ };
19309+
19310+ cpu_opp_table: opp_table {
19311+ compatible = "operating-points-v2";
19312+
19313+ opp-408000000 {
19314+ opp-hz = /bits/ 64 <408000000>;
19315+ opp-microvolt = <975000>;
19316+ clock-latency-ns = <40000>;
19317+ };
19318+ opp-600000000 {
19319+ opp-hz = /bits/ 64 <600000000>;
19320+ opp-microvolt = <975000>;
19321+ clock-latency-ns = <40000>;
19322+ };
19323+ opp-816000000 {
19324+ opp-hz = /bits/ 64 <816000000>;
19325+ opp-microvolt = <1025000>;
19326+ clock-latency-ns = <40000>;
19327+ };
19328+ opp-1008000000 {
19329+ opp-hz = /bits/ 64 <1008000000>;
19330+ opp-microvolt = <1150000>;
19331+ clock-latency-ns = <40000>;
19332 };
19333 };
19334
19335@@ -154,9 +185,221 @@ uart0: serial@10230000 {
19336 status = "disabled";
19337 };
19338
19339+ i2c1: i2c@10240000 {
19340+ compatible = "rockchip,rv1108-i2c";
19341+ reg = <0x10240000 0x1000>;
19342+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
19343+ #address-cells = <1>;
19344+ #size-cells = <0>;
19345+ clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
19346+ clock-names = "i2c", "pclk";
19347+ pinctrl-names = "default";
19348+ pinctrl-0 = <&i2c1_xfer>;
19349+ rockchip,grf = <&grf>;
19350+ status = "disabled";
19351+ };
19352+
19353+ i2c2: i2c@10250000 {
19354+ compatible = "rockchip,rv1108-i2c";
19355+ reg = <0x10250000 0x1000>;
19356+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
19357+ #address-cells = <1>;
19358+ #size-cells = <0>;
19359+ clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
19360+ clock-names = "i2c", "pclk";
19361+ pinctrl-names = "default";
19362+ pinctrl-0 = <&i2c2m1_xfer>;
19363+ rockchip,grf = <&grf>;
19364+ status = "disabled";
19365+ };
19366+
19367+ i2c3: i2c@10260000 {
19368+ compatible = "rockchip,rv1108-i2c";
19369+ reg = <0x10260000 0x1000>;
19370+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
19371+ #address-cells = <1>;
19372+ #size-cells = <0>;
19373+ clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
19374+ clock-names = "i2c", "pclk";
19375+ pinctrl-names = "default";
19376+ pinctrl-0 = <&i2c3_xfer>;
19377+ rockchip,grf = <&grf>;
19378+ status = "disabled";
19379+ };
19380+
19381+ spi: spi@10270000 {
19382+ compatible = "rockchip,rv1108-spi";
19383+ reg = <0x10270000 0x1000>;
19384+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
19385+ clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
19386+ clock-names = "spiclk", "apb_pclk";
19387+ dmas = <&pdma 8>, <&pdma 9>;
19388+ #dma-cells = <2>;
19389+ #address-cells = <1>;
19390+ #size-cells = <0>;
19391+ status = "disabled";
19392+ };
19393+
19394+ pwm4: pwm@10280000 {
19395+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
19396+ reg = <0x10280000 0x10>;
19397+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
19398+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
19399+ clock-names = "pwm", "pclk";
19400+ pinctrl-names = "default";
19401+ pinctrl-0 = <&pwm4_pin>;
19402+ #pwm-cells = <3>;
19403+ status = "disabled";
19404+ };
19405+
19406+ pwm5: pwm@10280010 {
19407+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
19408+ reg = <0x10280010 0x10>;
19409+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
19410+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
19411+ clock-names = "pwm", "pclk";
19412+ pinctrl-names = "default";
19413+ pinctrl-0 = <&pwm5_pin>;
19414+ #pwm-cells = <3>;
19415+ status = "disabled";
19416+ };
19417+
19418+ pwm6: pwm@10280020 {
19419+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
19420+ reg = <0x10280020 0x10>;
19421+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
19422+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
19423+ clock-names = "pwm", "pclk";
19424+ pinctrl-names = "default";
19425+ pinctrl-0 = <&pwm6_pin>;
19426+ #pwm-cells = <3>;
19427+ status = "disabled";
19428+ };
19429+
19430+ pwm7: pwm@10280030 {
19431+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
19432+ reg = <0x10280030 0x10>;
19433+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
19434+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
19435+ clock-names = "pwm", "pclk";
19436+ pinctrl-names = "default";
19437+ pinctrl-0 = <&pwm7_pin>;
19438+ #pwm-cells = <3>;
19439+ status = "disabled";
19440+ };
19441+
19442 grf: syscon@10300000 {
19443- compatible = "rockchip,rv1108-grf", "syscon";
19444+ compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
19445 reg = <0x10300000 0x1000>;
19446+ #address-cells = <1>;
19447+ #size-cells = <1>;
19448+
19449+ u2phy: usb2-phy@100 {
19450+ compatible = "rockchip,rv1108-usb2phy";
19451+ reg = <0x100 0x0c>;
19452+ clocks = <&cru SCLK_USBPHY>;
19453+ clock-names = "phyclk";
19454+ #clock-cells = <0>;
19455+ clock-output-names = "usbphy";
19456+ rockchip,usbgrf = <&usbgrf>;
19457+ status = "disabled";
19458+
19459+ u2phy_otg: otg-port {
19460+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
19461+ interrupt-names = "otg-mux";
19462+ #phy-cells = <0>;
19463+ status = "disabled";
19464+ };
19465+
19466+ u2phy_host: host-port {
19467+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
19468+ interrupt-names = "linestate";
19469+ #phy-cells = <0>;
19470+ status = "disabled";
19471+ };
19472+ };
19473+ };
19474+
19475+ watchdog: wdt@10360000 {
19476+ compatible = "snps,dw-wdt";
19477+ reg = <0x10360000 0x100>;
19478+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
19479+ clocks = <&cru PCLK_WDT>;
19480+ clock-names = "pclk_wdt";
19481+ status = "disabled";
19482+ };
19483+
19484+ adc: adc@1038c000 {
19485+ compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
19486+ reg = <0x1038c000 0x100>;
19487+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
19488+ #io-channel-cells = <1>;
19489+ clock-frequency = <1000000>;
19490+ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
19491+ clock-names = "saradc", "apb_pclk";
19492+ status = "disabled";
19493+ };
19494+
19495+ i2c0: i2c@20000000 {
19496+ compatible = "rockchip,rv1108-i2c";
19497+ reg = <0x20000000 0x1000>;
19498+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
19499+ #address-cells = <1>;
19500+ #size-cells = <0>;
19501+ clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
19502+ clock-names = "i2c", "pclk";
19503+ pinctrl-names = "default";
19504+ pinctrl-0 = <&i2c0_xfer>;
19505+ rockchip,grf = <&grf>;
19506+ status = "disabled";
19507+ };
19508+
19509+ pwm0: pwm@20040000 {
19510+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
19511+ reg = <0x20040000 0x10>;
19512+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
19513+ clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
19514+ clock-names = "pwm", "pclk";
19515+ pinctrl-names = "default";
19516+ pinctrl-0 = <&pwm0_pin>;
19517+ #pwm-cells = <3>;
19518+ status = "disabled";
19519+ };
19520+
19521+ pwm1: pwm@20040010 {
19522+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
19523+ reg = <0x20040010 0x10>;
19524+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
19525+ clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
19526+ clock-names = "pwm", "pclk";
19527+ pinctrl-names = "default";
19528+ pinctrl-0 = <&pwm1_pin>;
19529+ #pwm-cells = <3>;
19530+ status = "disabled";
19531+ };
19532+
19533+ pwm2: pwm@20040020 {
19534+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
19535+ reg = <0x20040020 0x10>;
19536+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
19537+ clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
19538+ clock-names = "pwm", "pclk";
19539+ pinctrl-names = "default";
19540+ pinctrl-0 = <&pwm2_pin>;
19541+ #pwm-cells = <3>;
19542+ status = "disabled";
19543+ };
19544+
19545+ pwm3: pwm@20040030 {
19546+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
19547+ reg = <0x20040030 0x10>;
19548+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
19549+ clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
19550+ clock-names = "pwm", "pclk";
19551+ pinctrl-names = "default";
19552+ pinctrl-0 = <&pwm3_pin>;
19553+ #pwm-cells = <3>;
19554+ status = "disabled";
19555 };
19556
19557 pmugrf: syscon@20060000 {
19558@@ -164,6 +407,11 @@ pmugrf: syscon@20060000 {
19559 reg = <0x20060000 0x1000>;
19560 };
19561
19562+ usbgrf: syscon@202a0000 {
19563+ compatible = "rockchip,rv1108-usbgrf", "syscon";
19564+ reg = <0x202a0000 0x1000>;
19565+ };
19566+
19567 cru: clock-controller@20200000 {
19568 compatible = "rockchip,rv1108-cru";
19569 reg = <0x20200000 0x1000>;
19570@@ -174,37 +422,78 @@ cru: clock-controller@20200000 {
19571
19572 emmc: dwmmc@30110000 {
19573 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
19574- clock-freq-min-max = <400000 150000000>;
19575+ reg = <0x30110000 0x4000>;
19576+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
19577 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
19578 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
19579 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
19580 fifo-depth = <0x100>;
19581- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
19582- reg = <0x30110000 0x4000>;
19583+ max-frequency = <150000000>;
19584 status = "disabled";
19585 };
19586
19587 sdio: dwmmc@30120000 {
19588 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
19589- clock-freq-min-max = <400000 150000000>;
19590+ reg = <0x30120000 0x4000>;
19591+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
19592 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
19593 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
19594 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
19595 fifo-depth = <0x100>;
19596- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
19597- reg = <0x30120000 0x4000>;
19598+ max-frequency = <150000000>;
19599 status = "disabled";
19600 };
19601
19602 sdmmc: dwmmc@30130000 {
19603 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
19604- clock-freq-min-max = <400000 100000000>;
19605+ reg = <0x30130000 0x4000>;
19606+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
19607 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
19608 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
19609 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
19610 fifo-depth = <0x100>;
19611- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
19612- reg = <0x30130000 0x4000>;
19613+ max-frequency = <100000000>;
19614+ pinctrl-names = "default";
19615+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
19616+ status = "disabled";
19617+ };
19618+
19619+ usb_host_ehci: usb@30140000 {
19620+ compatible = "generic-ehci";
19621+ reg = <0x30140000 0x20000>;
19622+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
19623+ clocks = <&cru HCLK_HOST0>, <&u2phy>;
19624+ clock-names = "usbhost", "utmi";
19625+ phys = <&u2phy_host>;
19626+ phy-names = "usb";
19627+ status = "disabled";
19628+ };
19629+
19630+ usb_host_ohci: usb@30160000 {
19631+ compatible = "generic-ohci";
19632+ reg = <0x30160000 0x20000>;
19633+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
19634+ clocks = <&cru HCLK_HOST0>, <&u2phy>;
19635+ clock-names = "usbhost", "utmi";
19636+ phys = <&u2phy_host>;
19637+ phy-names = "usb";
19638+ status = "disabled";
19639+ };
19640+
19641+ usb_otg: usb@30180000 {
19642+ compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
19643+ "snps,dwc2";
19644+ reg = <0x30180000 0x40000>;
19645+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
19646+ clocks = <&cru HCLK_OTG>;
19647+ clock-names = "otg";
19648+ dr_mode = "otg";
19649+ g-np-tx-fifo-size = <16>;
19650+ g-rx-fifo-size = <280>;
19651+ g-tx-fifo-size = <256 128 128 64 32 16>;
19652+ g-use-dma;
19653+ phys = <&u2phy_otg>;
19654+ phy-names = "usb2-phy";
19655 status = "disabled";
19656 };
19657
19658@@ -301,6 +590,11 @@ pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
19659 drive-strength = <12>;
19660 };
19661
19662+ pcfg_pull_none_smt: pcfg-pull-none-smt {
19663+ bias-disable;
19664+ input-schmitt-enable;
19665+ };
19666+
19667 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
19668 bias-pull-up;
19669 drive-strength = <8>;
19670@@ -328,6 +622,13 @@ pcfg_input_high: pcfg-input-high {
19671 input-enable;
19672 };
19673
19674+ i2c0 {
19675+ i2c0_xfer: i2c0-xfer {
19676+ rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
19677+ <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>;
19678+ };
19679+ };
19680+
19681 i2c1 {
19682 i2c1_xfer: i2c1-xfer {
19683 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
19684@@ -366,6 +667,54 @@ i2c3_xfer: i2c3-xfer {
19685 };
19686 };
19687
19688+ pwm0 {
19689+ pwm0_pin: pwm0-pin {
19690+ rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
19691+ };
19692+ };
19693+
19694+ pwm1 {
19695+ pwm1_pin: pwm1-pin {
19696+ rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
19697+ };
19698+ };
19699+
19700+ pwm2 {
19701+ pwm2_pin: pwm2-pin {
19702+ rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
19703+ };
19704+ };
19705+
19706+ pwm3 {
19707+ pwm3_pin: pwm3-pin {
19708+ rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
19709+ };
19710+ };
19711+
19712+ pwm4 {
19713+ pwm4_pin: pwm4-pin {
19714+ rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>;
19715+ };
19716+ };
19717+
19718+ pwm5 {
19719+ pwm5_pin: pwm5-pin {
19720+ rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
19721+ };
19722+ };
19723+
19724+ pwm6 {
19725+ pwm6_pin: pwm6-pin {
19726+ rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
19727+ };
19728+ };
19729+
19730+ pwm7 {
19731+ pwm7_pin: pwm7-pin {
19732+ rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
19733+ };
19734+ };
19735+
19736 sdmmc {
19737 sdmmc_clk: sdmmc-clk {
19738 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
19739diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
19740index 60e69aeacbdb..38d2216c7ead 100644
19741--- a/arch/arm/boot/dts/sama5d2.dtsi
19742+++ b/arch/arm/boot/dts/sama5d2.dtsi
19743@@ -416,6 +416,17 @@ hlcdc_pwm: hlcdc-pwm {
19744 };
19745 };
19746
19747+ isc: isc@f0008000 {
19748+ compatible = "atmel,sama5d2-isc";
19749+ reg = <0xf0008000 0x4000>;
19750+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
19751+ clocks = <&isc_clk>, <&iscck>, <&isc_gclk>;
19752+ clock-names = "hclock", "iscck", "gck";
19753+ #clock-cells = <0>;
19754+ clock-output-names = "isc-mck";
19755+ status = "disabled";
19756+ };
19757+
19758 ramc0: ramc@f000c000 {
19759 compatible = "atmel,sama5d3-ddramc";
19760 reg = <0xf000c000 0x200>;
19761@@ -494,6 +505,24 @@ plladiv: plladivck {
19762 clocks = <&plla>;
19763 };
19764
19765+ audio_pll_frac: audiopll_fracck {
19766+ compatible = "atmel,sama5d2-clk-audio-pll-frac";
19767+ #clock-cells = <0>;
19768+ clocks = <&main>;
19769+ };
19770+
19771+ audio_pll_pad: audiopll_padck {
19772+ compatible = "atmel,sama5d2-clk-audio-pll-pad";
19773+ #clock-cells = <0>;
19774+ clocks = <&audio_pll_frac>;
19775+ };
19776+
19777+ audio_pll_pmc: audiopll_pmcck {
19778+ compatible = "atmel,sama5d2-clk-audio-pll-pmc";
19779+ #clock-cells = <0>;
19780+ clocks = <&audio_pll_frac>;
19781+ };
19782+
19783 utmi: utmick {
19784 compatible = "atmel,at91sam9x5-clk-utmi";
19785 #clock-cells = <0>;
19786@@ -895,7 +924,7 @@ gck {
19787 #address-cells = <1>;
19788 #size-cells = <0>;
19789 interrupt-parent = <&pmc>;
19790- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
19791+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
19792
19793 sdmmc0_gclk: sdmmc0_gclk {
19794 #clock-cells = <0>;
19795@@ -925,6 +954,11 @@ pwm_gclk: pwm_gclk {
19796 atmel,clk-output-range = <0 83000000>;
19797 };
19798
19799+ isc_gclk: isc_gclk {
19800+ #clock-cells = <0>;
19801+ reg = <46>;
19802+ };
19803+
19804 pdmic_gclk: pdmic_gclk {
19805 #clock-cells = <0>;
19806 reg = <48>;
19807@@ -951,9 +985,37 @@ can1_gclk: can1_gclk {
19808 reg = <57>;
19809 atmel,clk-output-range = <0 80000000>;
19810 };
19811+
19812+ classd_gclk: classd_gclk {
19813+ #clock-cells = <0>;
19814+ reg = <59>;
19815+ atmel,clk-output-range = <0 100000000>;
19816+ };
19817 };
19818 };
19819
19820+ qspi0: spi@f0020000 {
19821+ compatible = "atmel,sama5d2-qspi";
19822+ reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
19823+ reg-names = "qspi_base", "qspi_mmap";
19824+ interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
19825+ clocks = <&qspi0_clk>;
19826+ #address-cells = <1>;
19827+ #size-cells = <0>;
19828+ status = "disabled";
19829+ };
19830+
19831+ qspi1: spi@f0024000 {
19832+ compatible = "atmel,sama5d2-qspi";
19833+ reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
19834+ reg-names = "qspi_base", "qspi_mmap";
19835+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
19836+ clocks = <&qspi1_clk>;
19837+ #address-cells = <1>;
19838+ #size-cells = <0>;
19839+ status = "disabled";
19840+ };
19841+
19842 sha@f0028000 {
19843 compatible = "atmel,at91sam9g46-sha";
19844 reg = <0xf0028000 0x100>;
19845@@ -1406,6 +1468,19 @@ AT91_XDMAC_DT_PERID(28))>,
19846 status = "okay";
19847 };
19848
19849+ classd: classd@fc048000 {
19850+ compatible = "atmel,sama5d2-classd";
19851+ reg = <0xfc048000 0x100>;
19852+ interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
19853+ dmas = <&dma0
19854+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
19855+ AT91_XDMAC_DT_PERID(47))>;
19856+ dma-names = "tx";
19857+ clocks = <&classd_clk>, <&classd_gclk>;
19858+ clock-names = "pclk", "gclk";
19859+ status = "disabled";
19860+ };
19861+
19862 can1: can@fc050000 {
19863 compatible = "bosch,m_can";
19864 reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
19865diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
19866index 54bc6d3cf290..40f4ad3c34c6 100644
19867--- a/arch/arm/boot/dts/spear1310.dtsi
19868+++ b/arch/arm/boot/dts/spear1310.dtsi
19869@@ -98,6 +98,7 @@ pcie0: pcie@b1000000 {
19870 device_type = "pci";
19871 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
19872 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
19873+ bus-range = <0x00 0xff>;
19874 status = "disabled";
19875 };
19876
19877@@ -116,6 +117,7 @@ pcie1: pcie@b1800000 {
19878 device_type = "pci";
19879 ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
19880 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
19881+ bus-range = <0x00 0xff>;
19882 status = "disabled";
19883 };
19884
19885@@ -134,6 +136,7 @@ pcie2: pcie@b4000000 {
19886 device_type = "pci";
19887 ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
19888 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
19889+ bus-range = <0x00 0xff>;
19890 status = "disabled";
19891 };
19892
19893diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
19894index df2232d767ed..5f347054527d 100644
19895--- a/arch/arm/boot/dts/spear1340.dtsi
19896+++ b/arch/arm/boot/dts/spear1340.dtsi
19897@@ -63,6 +63,7 @@ pcie0: pcie@b1000000 {
19898 device_type = "pci";
19899 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
19900 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
19901+ bus-range = <0x00 0xff>;
19902 status = "disabled";
19903 };
19904
19905diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
19906index 6c5affe2d0f5..2310a4e97768 100644
19907--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
19908+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
19909@@ -37,6 +37,14 @@ CPU0: cpu@300 {
19910 device_type = "cpu";
19911 compatible = "arm,cortex-a9";
19912 reg = <0x300>;
19913+ /* cpufreq controls */
19914+ operating-points = <998400 0
19915+ 800000 0
19916+ 400000 0
19917+ 200000 0>;
19918+ clocks = <&prcmu_clk PRCMU_ARMSS>;
19919+ clock-names = "cpu";
19920+ clock-latency = <20000>;
19921 };
19922 CPU1: cpu@301 {
19923 device_type = "cpu";
19924@@ -494,13 +502,6 @@ prcmu-timer-4@80157450 {
19925 reg = <0x80157450 0xC>;
19926 };
19927
19928- cpufreq {
19929- compatible = "stericsson,cpufreq-ux500";
19930- clocks = <&prcmu_clk PRCMU_ARMSS>;
19931- clock-names = "armss";
19932- status = "disabled";
19933- };
19934-
19935 thermal@801573c0 {
19936 compatible = "stericsson,db8500-thermal";
19937 reg = <0x801573c0 0x40>;
19938diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
19939index dcda0bbefe5b..97b1c2321ba9 100644
19940--- a/arch/arm/boot/dts/stm32429i-eval.dts
19941+++ b/arch/arm/boot/dts/stm32429i-eval.dts
19942@@ -55,7 +55,7 @@ / {
19943 compatible = "st,stm32429i-eval", "st,stm32f429";
19944
19945 chosen {
19946- bootargs = "root=/dev/ram rdinit=/linuxrc";
19947+ bootargs = "root=/dev/ram";
19948 stdout-path = "serial0:115200n8";
19949 };
19950
19951diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
19952index ae47cde7952f..c66d617e4245 100644
19953--- a/arch/arm/boot/dts/stm32f429-disco.dts
19954+++ b/arch/arm/boot/dts/stm32f429-disco.dts
19955@@ -54,7 +54,7 @@ / {
19956 compatible = "st,stm32f429i-disco", "st,stm32f429";
19957
19958 chosen {
19959- bootargs = "root=/dev/ram rdinit=/linuxrc";
19960+ bootargs = "root=/dev/ram";
19961 stdout-path = "serial0:115200n8";
19962 };
19963
19964diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
19965index a8113dc879cf..dd7e99b1f43b 100644
19966--- a/arch/arm/boot/dts/stm32f429.dtsi
19967+++ b/arch/arm/boot/dts/stm32f429.dtsi
19968@@ -361,6 +361,31 @@ i2c1: i2c@40005400 {
19969 status = "disabled";
19970 };
19971
19972+ dac: dac@40007400 {
19973+ compatible = "st,stm32f4-dac-core";
19974+ reg = <0x40007400 0x400>;
19975+ resets = <&rcc STM32F4_APB1_RESET(DAC)>;
19976+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
19977+ clock-names = "pclk";
19978+ #address-cells = <1>;
19979+ #size-cells = <0>;
19980+ status = "disabled";
19981+
19982+ dac1: dac@1 {
19983+ compatible = "st,stm32-dac";
19984+ #io-channels-cells = <1>;
19985+ reg = <1>;
19986+ status = "disabled";
19987+ };
19988+
19989+ dac2: dac@2 {
19990+ compatible = "st,stm32-dac";
19991+ #io-channels-cells = <1>;
19992+ reg = <2>;
19993+ status = "disabled";
19994+ };
19995+ };
19996+
19997 usart7: serial@40007800 {
19998 compatible = "st,stm32-usart", "st,stm32-uart";
19999 reg = <0x40007800 0x400>;
20000diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
20001index 75470c34b92c..6ae1f037f3f0 100644
20002--- a/arch/arm/boot/dts/stm32f469-disco.dts
20003+++ b/arch/arm/boot/dts/stm32f469-disco.dts
20004@@ -53,7 +53,7 @@ / {
20005 compatible = "st,stm32f469i-disco", "st,stm32f469";
20006
20007 chosen {
20008- bootargs = "root=/dev/ram rdinit=/linuxrc";
20009+ bootargs = "root=/dev/ram";
20010 stdout-path = "serial0:115200n8";
20011 };
20012
20013diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
20014index 4506eb97a4ab..5633860037d2 100644
20015--- a/arch/arm/boot/dts/stm32f746.dtsi
20016+++ b/arch/arm/boot/dts/stm32f746.dtsi
20017@@ -167,6 +167,15 @@ usart5: serial@40005000 {
20018 status = "disabled";
20019 };
20020
20021+ cec: cec@40006c00 {
20022+ compatible = "st,stm32-cec";
20023+ reg = <0x40006C00 0x400>;
20024+ interrupts = <94>;
20025+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
20026+ clock-names = "cec", "hdmi-cec";
20027+ status = "disabled";
20028+ };
20029+
20030 usart7: serial@40007800 {
20031 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
20032 reg = <0x40007800 0x400>;
20033@@ -336,6 +345,15 @@ gpiok: gpio@40022800 {
20034 st,bank-name = "GPIOK";
20035 };
20036
20037+ cec_pins_a: cec@0 {
20038+ pins {
20039+ pinmux = <STM32F746_PA15_FUNC_HDMI_CEC>;
20040+ slew-rate = <0>;
20041+ drive-open-drain;
20042+ bias-disable;
20043+ };
20044+ };
20045+
20046 usart1_pins_a: usart1@0 {
20047 pins1 {
20048 pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
20049@@ -380,6 +398,39 @@ rcc: rcc@40023800 {
20050 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
20051 assigned-clock-rates = <1000000>;
20052 };
20053+
20054+ dma1: dma@40026000 {
20055+ compatible = "st,stm32-dma";
20056+ reg = <0x40026000 0x400>;
20057+ interrupts = <11>,
20058+ <12>,
20059+ <13>,
20060+ <14>,
20061+ <15>,
20062+ <16>,
20063+ <17>,
20064+ <47>;
20065+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
20066+ #dma-cells = <4>;
20067+ status = "disabled";
20068+ };
20069+
20070+ dma2: dma@40026400 {
20071+ compatible = "st,stm32-dma";
20072+ reg = <0x40026400 0x400>;
20073+ interrupts = <56>,
20074+ <57>,
20075+ <58>,
20076+ <59>,
20077+ <60>,
20078+ <68>,
20079+ <69>,
20080+ <70>;
20081+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
20082+ #dma-cells = <4>;
20083+ st,mem2mem;
20084+ status = "disabled";
20085+ };
20086 };
20087 };
20088
20089diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts
20090index 166728aeb166..4463ca13a740 100644
20091--- a/arch/arm/boot/dts/stm32f769-disco.dts
20092+++ b/arch/arm/boot/dts/stm32f769-disco.dts
20093@@ -63,6 +63,12 @@ aliases {
20094
20095 };
20096
20097+&cec {
20098+ pinctrl-0 = <&cec_pins_a>;
20099+ pinctrl-names = "default";
20100+ status = "okay";
20101+};
20102+
20103 &clk_hse {
20104 clock-frequency = <25000000>;
20105 };
20106diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
20107index 36a99db0a3b4..58ec2275181e 100644
20108--- a/arch/arm/boot/dts/stm32h743.dtsi
20109+++ b/arch/arm/boot/dts/stm32h743.dtsi
20110@@ -59,6 +59,45 @@ timer_clk: timer-clk {
20111 };
20112
20113 soc {
20114+ timer5: timer@40000c00 {
20115+ compatible = "st,stm32-timer";
20116+ reg = <0x40000c00 0x400>;
20117+ interrupts = <50>;
20118+ clocks = <&timer_clk>;
20119+ };
20120+
20121+ usart2: serial@40004400 {
20122+ compatible = "st,stm32f7-usart", "st,stm32f7-uart";
20123+ reg = <0x40004400 0x400>;
20124+ interrupts = <38>;
20125+ status = "disabled";
20126+ clocks = <&timer_clk>;
20127+ };
20128+
20129+ dac: dac@40007400 {
20130+ compatible = "st,stm32h7-dac-core";
20131+ reg = <0x40007400 0x400>;
20132+ clocks = <&timer_clk>;
20133+ clock-names = "pclk";
20134+ #address-cells = <1>;
20135+ #size-cells = <0>;
20136+ status = "disabled";
20137+
20138+ dac1: dac@1 {
20139+ compatible = "st,stm32-dac";
20140+ #io-channels-cells = <1>;
20141+ reg = <1>;
20142+ status = "disabled";
20143+ };
20144+
20145+ dac2: dac@2 {
20146+ compatible = "st,stm32-dac";
20147+ #io-channels-cells = <1>;
20148+ reg = <2>;
20149+ status = "disabled";
20150+ };
20151+ };
20152+
20153 usart1: serial@40011000 {
20154 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
20155 reg = <0x40011000 0x400>;
20156@@ -68,19 +107,91 @@ usart1: serial@40011000 {
20157
20158 };
20159
20160- usart2: serial@40004400 {
20161- compatible = "st,stm32f7-usart", "st,stm32f7-uart";
20162- reg = <0x40004400 0x400>;
20163- interrupts = <38>;
20164+ dma1: dma@40020000 {
20165+ compatible = "st,stm32-dma";
20166+ reg = <0x40020000 0x400>;
20167+ interrupts = <11>,
20168+ <12>,
20169+ <13>,
20170+ <14>,
20171+ <15>,
20172+ <16>,
20173+ <17>,
20174+ <47>;
20175+ clocks = <&timer_clk>;
20176+ #dma-cells = <4>;
20177+ st,mem2mem;
20178 status = "disabled";
20179+ };
20180+
20181+ dma2: dma@40020400 {
20182+ compatible = "st,stm32-dma";
20183+ reg = <0x40020400 0x400>;
20184+ interrupts = <56>,
20185+ <57>,
20186+ <58>,
20187+ <59>,
20188+ <60>,
20189+ <68>,
20190+ <69>,
20191+ <70>;
20192 clocks = <&timer_clk>;
20193+ #dma-cells = <4>;
20194+ st,mem2mem;
20195+ status = "disabled";
20196 };
20197
20198- timer5: timer@40000c00 {
20199- compatible = "st,stm32-timer";
20200- reg = <0x40000c00 0x400>;
20201- interrupts = <50>;
20202+ adc_12: adc@40022000 {
20203+ compatible = "st,stm32h7-adc-core";
20204+ reg = <0x40022000 0x400>;
20205+ interrupts = <18>;
20206+ clocks = <&timer_clk>;
20207+ clock-names = "bus";
20208+ interrupt-controller;
20209+ #interrupt-cells = <1>;
20210+ #address-cells = <1>;
20211+ #size-cells = <0>;
20212+ status = "disabled";
20213+
20214+ adc1: adc@0 {
20215+ compatible = "st,stm32h7-adc";
20216+ #io-channel-cells = <1>;
20217+ reg = <0x0>;
20218+ interrupt-parent = <&adc_12>;
20219+ interrupts = <0>;
20220+ status = "disabled";
20221+ };
20222+
20223+ adc2: adc@100 {
20224+ compatible = "st,stm32h7-adc";
20225+ #io-channel-cells = <1>;
20226+ reg = <0x100>;
20227+ interrupt-parent = <&adc_12>;
20228+ interrupts = <1>;
20229+ status = "disabled";
20230+ };
20231+ };
20232+
20233+ adc_3: adc@58026000 {
20234+ compatible = "st,stm32h7-adc-core";
20235+ reg = <0x58026000 0x400>;
20236+ interrupts = <127>;
20237 clocks = <&timer_clk>;
20238+ clock-names = "bus";
20239+ interrupt-controller;
20240+ #interrupt-cells = <1>;
20241+ #address-cells = <1>;
20242+ #size-cells = <0>;
20243+ status = "disabled";
20244+
20245+ adc3: adc@0 {
20246+ compatible = "st,stm32h7-adc";
20247+ #io-channel-cells = <1>;
20248+ reg = <0x0>;
20249+ interrupt-parent = <&adc_3>;
20250+ interrupts = <0>;
20251+ status = "disabled";
20252+ };
20253 };
20254 };
20255 };
20256diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts
20257index c6effbb36e4a..6c07786e7ddb 100644
20258--- a/arch/arm/boot/dts/stm32h743i-eval.dts
20259+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
20260@@ -60,6 +60,24 @@ memory {
20261 aliases {
20262 serial0 = &usart1;
20263 };
20264+
20265+ vdda: regulator-vdda {
20266+ compatible = "regulator-fixed";
20267+ regulator-name = "vdda";
20268+ regulator-min-microvolt = <3300000>;
20269+ regulator-max-microvolt = <3300000>;
20270+ regulator-always-on;
20271+ };
20272+};
20273+
20274+&adc_12 {
20275+ vref-supply = <&vdda>;
20276+ status = "okay";
20277+ adc1: adc@0 {
20278+ /* potentiometer */
20279+ st,adc-channels = <0>;
20280+ status = "okay";
20281+ };
20282 };
20283
20284 &clk_hse {
20285diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
20286index aebc3f9dc7b6..b147cb0dc14b 100644
20287--- a/arch/arm/boot/dts/sun6i-a31.dtsi
20288+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
20289@@ -1155,11 +1155,11 @@ rtc: rtc@01f00000 {
20290 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
20291 };
20292
20293- nmi_intc: interrupt-controller@01f00c0c {
20294- compatible = "allwinner,sun6i-a31-sc-nmi";
20295+ nmi_intc: interrupt-controller@1f00c00 {
20296+ compatible = "allwinner,sun6i-a31-r-intc";
20297 interrupt-controller;
20298 #interrupt-cells = <2>;
20299- reg = <0x01f00c0c 0x38>;
20300+ reg = <0x01f00c00 0x400>;
20301 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
20302 };
20303
20304diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
20305index bb510187602c..852a0aa24dce 100644
20306--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
20307+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
20308@@ -271,6 +271,10 @@ &ac_power_supply {
20309 status = "okay";
20310 };
20311
20312+&battery_power_supply {
20313+ status = "okay";
20314+};
20315+
20316 &reg_dcdc2 {
20317 regulator-always-on;
20318 regulator-min-microvolt = <1000000>;
20319diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
20320index a8b978d0f35b..ea50dda75adc 100644
20321--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
20322+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
20323@@ -519,11 +519,11 @@ rtc: rtc@01f00000 {
20324 #clock-cells = <1>;
20325 };
20326
20327- nmi_intc: interrupt-controller@01f00c0c {
20328- compatible = "allwinner,sun6i-a31-sc-nmi";
20329+ nmi_intc: interrupt-controller@1f00c00 {
20330+ compatible = "allwinner,sun6i-a31-r-intc";
20331 interrupt-controller;
20332 #interrupt-cells = <2>;
20333- reg = <0x01f00c0c 0x38>;
20334+ reg = <0x01f00c00 0x400>;
20335 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
20336 };
20337
20338diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
20339index aecdeeb368ed..1f0d60afb25b 100644
20340--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
20341+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
20342@@ -43,6 +43,7 @@
20343
20344 /dts-v1/;
20345 #include "sun8i-a83t.dtsi"
20346+#include "sunxi-common-regulators.dtsi"
20347
20348 / {
20349 model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
20350@@ -57,8 +58,92 @@ chosen {
20351 };
20352 };
20353
20354+&ehci0 {
20355+ status = "okay";
20356+};
20357+
20358+&mmc0 {
20359+ pinctrl-names = "default";
20360+ pinctrl-0 = <&mmc0_pins>;
20361+ vmmc-supply = <&reg_vcc3v0>;
20362+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
20363+ bus-width = <4>;
20364+ cd-inverted;
20365+ status = "okay";
20366+};
20367+
20368+&mmc2 {
20369+ pinctrl-names = "default";
20370+ pinctrl-0 = <&mmc2_8bit_emmc_pins>;
20371+ vmmc-supply = <&reg_vcc3v0>;
20372+ bus-width = <8>;
20373+ non-removable;
20374+ cap-mmc-hw-reset;
20375+ status = "okay";
20376+};
20377+
20378+&ohci0 {
20379+ status = "okay";
20380+};
20381+
20382+&reg_usb0_vbus {
20383+ gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
20384+ status = "okay";
20385+};
20386+
20387+&reg_usb1_vbus {
20388+ gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
20389+ status = "okay";
20390+};
20391+
20392+&r_rsb {
20393+ status = "okay";
20394+
20395+ axp81x: pmic@3a3 {
20396+ compatible = "x-powers,axp818", "x-powers,axp813";
20397+ reg = <0x3a3>;
20398+ interrupt-parent = <&r_intc>;
20399+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
20400+ };
20401+
20402+ ac100: codec@e89 {
20403+ compatible = "x-powers,ac100";
20404+ reg = <0xe89>;
20405+
20406+ ac100_codec: codec {
20407+ compatible = "x-powers,ac100-codec";
20408+ interrupt-parent = <&r_pio>;
20409+ interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
20410+ #clock-cells = <0>;
20411+ clock-output-names = "4M_adda";
20412+ };
20413+
20414+ ac100_rtc: rtc {
20415+ compatible = "x-powers,ac100-rtc";
20416+ interrupt-parent = <&r_intc>;
20417+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
20418+ clocks = <&ac100_codec>;
20419+ #clock-cells = <1>;
20420+ clock-output-names = "cko1_rtc",
20421+ "cko2_rtc",
20422+ "cko3_rtc";
20423+ };
20424+ };
20425+};
20426+
20427 &uart0 {
20428 pinctrl-names = "default";
20429 pinctrl-0 = <&uart0_pb_pins>;
20430 status = "okay";
20431 };
20432+
20433+&usbphy {
20434+ usb0_vbus-supply = <&reg_usb0_vbus>;
20435+ usb1_vbus-supply = <&reg_usb1_vbus>;
20436+ status = "okay";
20437+};
20438+
20439+&usb_otg {
20440+ dr_mode = "host";
20441+ status = "okay";
20442+};
20443diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
20444new file mode 100644
20445index 000000000000..2bafd7e99ef7
20446--- /dev/null
20447+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
20448@@ -0,0 +1,148 @@
20449+/*
20450+ * Copyright 2017 Chen-Yu Tsai
20451+ *
20452+ * Chen-Yu Tsai <wens@csie.org>
20453+ *
20454+ * This file is dual-licensed: you can use it either under the terms
20455+ * of the GPL or the X11 license, at your option. Note that this dual
20456+ * licensing only applies to this file, and not this project as a
20457+ * whole.
20458+ *
20459+ * a) This file is free software; you can redistribute it and/or
20460+ * modify it under the terms of the GNU General Public License as
20461+ * published by the Free Software Foundation; either version 2 of the
20462+ * License, or (at your option) any later version.
20463+ *
20464+ * This file is distributed in the hope that it will be useful,
20465+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
20466+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20467+ * GNU General Public License for more details.
20468+ *
20469+ * Or, alternatively,
20470+ *
20471+ * b) Permission is hereby granted, free of charge, to any person
20472+ * obtaining a copy of this software and associated documentation
20473+ * files (the "Software"), to deal in the Software without
20474+ * restriction, including without limitation the rights to use,
20475+ * copy, modify, merge, publish, distribute, sublicense, and/or
20476+ * sell copies of the Software, and to permit persons to whom the
20477+ * Software is furnished to do so, subject to the following
20478+ * conditions:
20479+ *
20480+ * The above copyright notice and this permission notice shall be
20481+ * included in all copies or substantial portions of the Software.
20482+ *
20483+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20484+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
20485+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20486+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
20487+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20488+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20489+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20490+ * OTHER DEALINGS IN THE SOFTWARE.
20491+ */
20492+
20493+/dts-v1/;
20494+#include "sun8i-a83t.dtsi"
20495+#include "sunxi-common-regulators.dtsi"
20496+
20497+#include <dt-bindings/gpio/gpio.h>
20498+
20499+/ {
20500+ model = "Banana Pi BPI-M3";
20501+ compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
20502+
20503+ aliases {
20504+ serial0 = &uart0;
20505+ };
20506+
20507+ chosen {
20508+ stdout-path = "serial0:115200n8";
20509+ };
20510+};
20511+
20512+&ehci0 {
20513+ /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
20514+ status = "okay";
20515+
20516+ /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
20517+};
20518+
20519+&mmc0 {
20520+ pinctrl-names = "default";
20521+ pinctrl-0 = <&mmc0_pins>;
20522+ vmmc-supply = <&reg_vcc3v3>;
20523+ bus-width = <4>;
20524+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
20525+ cd-inverted;
20526+ status = "okay";
20527+};
20528+
20529+&mmc2 {
20530+ pinctrl-names = "default";
20531+ pinctrl-0 = <&mmc2_8bit_emmc_pins>;
20532+ vmmc-supply = <&reg_vcc3v3>;
20533+ bus-width = <8>;
20534+ non-removable;
20535+ cap-mmc-hw-reset;
20536+ status = "okay";
20537+};
20538+
20539+&r_rsb {
20540+ status = "okay";
20541+
20542+ axp81x: pmic@3a3 {
20543+ compatible = "x-powers,axp813";
20544+ reg = <0x3a3>;
20545+ interrupt-parent = <&r_intc>;
20546+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
20547+ };
20548+
20549+ ac100: codec@e89 {
20550+ compatible = "x-powers,ac100";
20551+ reg = <0xe89>;
20552+
20553+ ac100_codec: codec {
20554+ compatible = "x-powers,ac100-codec";
20555+ interrupt-parent = <&r_pio>;
20556+ interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
20557+ #clock-cells = <0>;
20558+ clock-output-names = "4M_adda";
20559+ };
20560+
20561+ ac100_rtc: rtc {
20562+ compatible = "x-powers,ac100-rtc";
20563+ interrupt-parent = <&r_intc>;
20564+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
20565+ clocks = <&ac100_codec>;
20566+ #clock-cells = <1>;
20567+ clock-output-names = "cko1_rtc",
20568+ "cko2_rtc",
20569+ "cko3_rtc";
20570+ };
20571+ };
20572+};
20573+
20574+&reg_usb1_vbus {
20575+ gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
20576+ status = "okay";
20577+};
20578+
20579+&reg_vcc3v0 {
20580+ status = "disabled";
20581+};
20582+
20583+&reg_vcc5v0 {
20584+ status = "disabled";
20585+};
20586+
20587+&uart0 {
20588+ pinctrl-names = "default";
20589+ pinctrl-0 = <&uart0_pb_pins>;
20590+ status = "okay";
20591+};
20592+
20593+&usbphy {
20594+ usb1_vbus-supply = <&reg_usb1_vbus>;
20595+ status = "okay";
20596+};
20597diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
20598index cff33454fc24..716a205c6dbb 100644
20599--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
20600+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
20601@@ -44,6 +44,7 @@
20602
20603 /dts-v1/;
20604 #include "sun8i-a83t.dtsi"
20605+#include "sunxi-common-regulators.dtsi"
20606
20607 #include <dt-bindings/gpio/gpio.h>
20608
20609@@ -83,6 +84,17 @@ green {
20610 };
20611 };
20612
20613+ usb-hub {
20614+ /* I2C is not connected */
20615+ compatible = "smsc,usb3503";
20616+ initial-mode = <1>; /* initialize in HUB mode */
20617+ disabled-ports = <1>;
20618+ intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
20619+ reset-gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
20620+ connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
20621+ refclk-frequency = <19200000>;
20622+ };
20623+
20624 sound {
20625 compatible = "simple-audio-card";
20626 simple-audio-card,name = "On-board SPDIF";
20627@@ -102,6 +114,89 @@ spdif_out: spdif-out {
20628 };
20629 };
20630
20631+&ehci0 {
20632+ /* GL830 USB-to-SATA bridge here */
20633+ status = "okay";
20634+};
20635+
20636+&ehci1 {
20637+ /* USB3503 HSIC USB 2.0 hub here */
20638+ status = "okay";
20639+};
20640+
20641+&mmc0 {
20642+ pinctrl-names = "default";
20643+ pinctrl-0 = <&mmc0_pins>;
20644+ vmmc-supply = <&reg_vcc3v3>;
20645+ bus-width = <4>;
20646+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
20647+ cd-inverted;
20648+ status = "okay";
20649+};
20650+
20651+&mmc2 {
20652+ pinctrl-names = "default";
20653+ pinctrl-0 = <&mmc2_8bit_emmc_pins>;
20654+ vmmc-supply = <&reg_vcc3v3>;
20655+ bus-width = <8>;
20656+ non-removable;
20657+ cap-mmc-hw-reset;
20658+ status = "okay";
20659+};
20660+
20661+&r_rsb {
20662+ status = "okay";
20663+
20664+ axp81x: pmic@3a3 {
20665+ compatible = "x-powers,axp818", "x-powers,axp813";
20666+ reg = <0x3a3>;
20667+ interrupt-parent = <&r_intc>;
20668+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
20669+ };
20670+
20671+ ac100: codec@e89 {
20672+ compatible = "x-powers,ac100";
20673+ reg = <0xe89>;
20674+
20675+ ac100_codec: codec {
20676+ compatible = "x-powers,ac100-codec";
20677+ interrupt-parent = <&r_pio>;
20678+ interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
20679+ #clock-cells = <0>;
20680+ clock-output-names = "4M_adda";
20681+ };
20682+
20683+ ac100_rtc: rtc {
20684+ compatible = "x-powers,ac100-rtc";
20685+ interrupt-parent = <&r_intc>;
20686+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
20687+ clocks = <&ac100_codec>;
20688+ #clock-cells = <1>;
20689+ clock-output-names = "cko1_rtc",
20690+ "cko2_rtc",
20691+ "cko3_rtc";
20692+ };
20693+ };
20694+};
20695+
20696+&reg_usb1_vbus {
20697+ gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */
20698+ status = "okay";
20699+};
20700+
20701+&reg_usb2_vbus {
20702+ gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
20703+ status = "okay";
20704+};
20705+
20706+&reg_vcc3v0 {
20707+ status = "disabled";
20708+};
20709+
20710+&reg_vcc5v0 {
20711+ status = "disabled";
20712+};
20713+
20714 &spdif {
20715 status = "okay";
20716 };
20717@@ -111,3 +206,9 @@ &uart0 {
20718 pinctrl-0 = <&uart0_pb_pins>;
20719 status = "okay";
20720 };
20721+
20722+&usbphy {
20723+ usb1_vbus-supply = <&reg_usb1_vbus>;
20724+ usb2_vbus-supply = <&reg_usb2_vbus>;
20725+ status = "okay";
20726+};
20727diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
20728index 19a8f4fcfab5..f996bd343e50 100644
20729--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
20730+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
20731@@ -47,6 +47,7 @@
20732 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
20733 #include <dt-bindings/clock/sun8i-r-ccu.h>
20734 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
20735+#include <dt-bindings/reset/sun8i-r-ccu.h>
20736
20737 / {
20738 interrupt-parent = <&gic>;
20739@@ -182,6 +183,141 @@ dma: dma-controller@1c02000 {
20740 #dma-cells = <1>;
20741 };
20742
20743+ mmc0: mmc@1c0f000 {
20744+ compatible = "allwinner,sun8i-a83t-mmc",
20745+ "allwinner,sun7i-a20-mmc";
20746+ reg = <0x01c0f000 0x1000>;
20747+ clocks = <&ccu CLK_BUS_MMC0>,
20748+ <&ccu CLK_MMC0>,
20749+ <&ccu CLK_MMC0_OUTPUT>,
20750+ <&ccu CLK_MMC0_SAMPLE>;
20751+ clock-names = "ahb",
20752+ "mmc",
20753+ "output",
20754+ "sample";
20755+ resets = <&ccu RST_BUS_MMC0>;
20756+ reset-names = "ahb";
20757+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
20758+ status = "disabled";
20759+ #address-cells = <1>;
20760+ #size-cells = <0>;
20761+ };
20762+
20763+ mmc1: mmc@1c10000 {
20764+ compatible = "allwinner,sun8i-a83t-mmc",
20765+ "allwinner,sun7i-a20-mmc";
20766+ reg = <0x01c10000 0x1000>;
20767+ clocks = <&ccu CLK_BUS_MMC1>,
20768+ <&ccu CLK_MMC1>,
20769+ <&ccu CLK_MMC1_OUTPUT>,
20770+ <&ccu CLK_MMC1_SAMPLE>;
20771+ clock-names = "ahb",
20772+ "mmc",
20773+ "output",
20774+ "sample";
20775+ resets = <&ccu RST_BUS_MMC1>;
20776+ reset-names = "ahb";
20777+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
20778+ status = "disabled";
20779+ #address-cells = <1>;
20780+ #size-cells = <0>;
20781+ };
20782+
20783+ mmc2: mmc@1c11000 {
20784+ compatible = "allwinner,sun8i-a83t-emmc";
20785+ reg = <0x01c11000 0x1000>;
20786+ clocks = <&ccu CLK_BUS_MMC2>,
20787+ <&ccu CLK_MMC2>,
20788+ <&ccu CLK_MMC2_OUTPUT>,
20789+ <&ccu CLK_MMC2_SAMPLE>;
20790+ clock-names = "ahb",
20791+ "mmc",
20792+ "output",
20793+ "sample";
20794+ resets = <&ccu RST_BUS_MMC2>;
20795+ reset-names = "ahb";
20796+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
20797+ status = "disabled";
20798+ #address-cells = <1>;
20799+ #size-cells = <0>;
20800+ };
20801+
20802+ usb_otg: usb@01c19000 {
20803+ compatible = "allwinner,sun8i-a83t-musb",
20804+ "allwinner,sun8i-a33-musb";
20805+ reg = <0x01c19000 0x0400>;
20806+ clocks = <&ccu CLK_BUS_OTG>;
20807+ resets = <&ccu RST_BUS_OTG>;
20808+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
20809+ interrupt-names = "mc";
20810+ phys = <&usbphy 0>;
20811+ phy-names = "usb";
20812+ extcon = <&usbphy 0>;
20813+ status = "disabled";
20814+ };
20815+
20816+ usbphy: phy@1c19400 {
20817+ compatible = "allwinner,sun8i-a83t-usb-phy";
20818+ reg = <0x01c19400 0x10>,
20819+ <0x01c1a800 0x14>,
20820+ <0x01c1b800 0x14>;
20821+ reg-names = "phy_ctrl",
20822+ "pmu1",
20823+ "pmu2";
20824+ clocks = <&ccu CLK_USB_PHY0>,
20825+ <&ccu CLK_USB_PHY1>,
20826+ <&ccu CLK_USB_HSIC>,
20827+ <&ccu CLK_USB_HSIC_12M>;
20828+ clock-names = "usb0_phy",
20829+ "usb1_phy",
20830+ "usb2_phy",
20831+ "usb2_hsic_12M";
20832+ resets = <&ccu RST_USB_PHY0>,
20833+ <&ccu RST_USB_PHY1>,
20834+ <&ccu RST_USB_HSIC>;
20835+ reset-names = "usb0_reset",
20836+ "usb1_reset",
20837+ "usb2_reset";
20838+ status = "disabled";
20839+ #phy-cells = <1>;
20840+ };
20841+
20842+ ehci0: usb@1c1a000 {
20843+ compatible = "allwinner,sun8i-a83t-ehci",
20844+ "generic-ehci";
20845+ reg = <0x01c1a000 0x100>;
20846+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
20847+ clocks = <&ccu CLK_BUS_EHCI0>;
20848+ resets = <&ccu RST_BUS_EHCI0>;
20849+ phys = <&usbphy 1>;
20850+ phy-names = "usb";
20851+ status = "disabled";
20852+ };
20853+
20854+ ohci0: usb@1c1a400 {
20855+ compatible = "allwinner,sun8i-a83t-ohci",
20856+ "generic-ohci";
20857+ reg = <0x01c1a400 0x100>;
20858+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
20859+ clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
20860+ resets = <&ccu RST_BUS_OHCI0>;
20861+ phys = <&usbphy 1>;
20862+ phy-names = "usb";
20863+ status = "disabled";
20864+ };
20865+
20866+ ehci1: usb@1c1b000 {
20867+ compatible = "allwinner,sun8i-a83t-ehci",
20868+ "generic-ehci";
20869+ reg = <0x01c1b000 0x100>;
20870+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
20871+ clocks = <&ccu CLK_BUS_EHCI1>;
20872+ resets = <&ccu RST_BUS_EHCI1>;
20873+ phys = <&usbphy 2>;
20874+ phy-names = "usb";
20875+ status = "disabled";
20876+ };
20877+
20878 ccu: clock@1c20000 {
20879 compatible = "allwinner,sun8i-a83t-ccu";
20880 reg = <0x01c20000 0x400>;
20881@@ -212,6 +348,15 @@ mmc0_pins: mmc0-pins {
20882 bias-pull-up;
20883 };
20884
20885+ mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
20886+ pins = "PC5", "PC6", "PC8", "PC9",
20887+ "PC10", "PC11", "PC12", "PC13",
20888+ "PC14", "PC15", "PC16";
20889+ function = "mmc2";
20890+ drive-strength = <30>;
20891+ bias-pull-up;
20892+ };
20893+
20894 spdif_tx_pin: spdif-tx-pin {
20895 pins = "PE18";
20896 function = "spdif";
20897@@ -281,6 +426,15 @@ gic: interrupt-controller@1c81000 {
20898 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
20899 };
20900
20901+ r_intc: interrupt-controller@1f00c00 {
20902+ compatible = "allwinner,sun8i-a83t-r-intc",
20903+ "allwinner,sun6i-a31-r-intc";
20904+ interrupt-controller;
20905+ #interrupt-cells = <2>;
20906+ reg = <0x01f00c00 0x400>;
20907+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
20908+ };
20909+
20910 r_ccu: clock@1f01400 {
20911 compatible = "allwinner,sun8i-a83t-r-ccu";
20912 reg = <0x01f01400 0x400>;
20913@@ -302,6 +456,28 @@ r_pio: pinctrl@1f02c00 {
20914 #gpio-cells = <3>;
20915 interrupt-controller;
20916 #interrupt-cells = <3>;
20917+
20918+ r_rsb_pins: r-rsb-pins {
20919+ pins = "PL0", "PL1";
20920+ function = "s_rsb";
20921+ drive-strength = <20>;
20922+ bias-pull-up;
20923+ };
20924+ };
20925+
20926+ r_rsb: rsb@1f03400 {
20927+ compatible = "allwinner,sun8i-a83t-rsb",
20928+ "allwinner,sun8i-a23-rsb";
20929+ reg = <0x01f03400 0x400>;
20930+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
20931+ clocks = <&r_ccu CLK_APB0_RSB>;
20932+ clock-frequency = <3000000>;
20933+ resets = <&r_ccu RST_APB0_RSB>;
20934+ pinctrl-names = "default";
20935+ pinctrl-0 = <&r_rsb_pins>;
20936+ status = "disabled";
20937+ #address-cells = <1>;
20938+ #size-cells = <0>;
20939 };
20940 };
20941 };
20942diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
20943index e7fae65eb5d3..10da56e86ab8 100644
20944--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
20945+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
20946@@ -100,6 +100,10 @@ spdif_out: spdif-out {
20947 };
20948 };
20949
20950+&ehci0 {
20951+ status = "okay";
20952+};
20953+
20954 &ehci1 {
20955 status = "okay";
20956 };
20957@@ -147,10 +151,19 @@ &mmc2 {
20958 status = "okay";
20959 };
20960
20961+&ohci0 {
20962+ status = "okay";
20963+};
20964+
20965 &ohci1 {
20966 status = "okay";
20967 };
20968
20969+&reg_usb0_vbus {
20970+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
20971+ status = "okay";
20972+};
20973+
20974 &spdif {
20975 pinctrl-names = "default";
20976 pinctrl-0 = <&spdif_tx_pins_a>;
20977@@ -163,7 +176,14 @@ &uart0 {
20978 status = "okay";
20979 };
20980
20981+&usb_otg {
20982+ dr_mode = "otg";
20983+ status = "okay";
20984+};
20985+
20986 &usbphy {
20987- /* USB VBUS is on as long as VCC-IO is on */
20988+ /* USB VBUS is always on except for the OTG port */
20989 status = "okay";
20990+ usb0_id_det-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA07 */
20991+ usb0_vbus-supply = <&reg_usb0_vbus>;
20992 };
20993diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
20994new file mode 100644
20995index 000000000000..eaf09666720d
20996--- /dev/null
20997+++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
20998@@ -0,0 +1,321 @@
20999+/*
21000+ * Copyright (c) 2017 Free Electrons <maxime.ripard@free-electrons.com>
21001+ *
21002+ * This file is dual-licensed: you can use it either under the terms
21003+ * of the GPL or the X11 license, at your option. Note that this dual
21004+ * licensing only applies to this file, and not this project as a
21005+ * whole.
21006+ *
21007+ * a) This file is free software; you can redistribute it and/or
21008+ * modify it under the terms of the GNU General Public License as
21009+ * published by the Free Software Foundation; either version 2 of the
21010+ * License, or (at your option) any later version.
21011+ *
21012+ * This file is distributed in the hope that it will be useful,
21013+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
21014+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21015+ * GNU General Public License for more details.
21016+ *
21017+ * Or, alternatively,
21018+ *
21019+ * b) Permission is hereby granted, free of charge, to any person
21020+ * obtaining a copy of this software and associated documentation
21021+ * files (the "Software"), to deal in the Software without
21022+ * restriction, including without limitation the rights to use,
21023+ * copy, modify, merge, publish, distribute, sublicense, and/or
21024+ * sell copies of the Software, and to permit persons to whom the
21025+ * Software is furnished to do so, subject to the following
21026+ * conditions:
21027+ *
21028+ * The above copyright notice and this permission notice shall be
21029+ * included in all copies or substantial portions of the Software.
21030+ *
21031+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21032+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
21033+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
21034+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
21035+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
21036+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21037+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21038+ * OTHER DEALINGS IN THE SOFTWARE.
21039+ */
21040+
21041+/dts-v1/;
21042+#include "sun8i-a33.dtsi"
21043+
21044+#include <dt-bindings/gpio/gpio.h>
21045+
21046+/ {
21047+ model = "BananaPi M2 Magic";
21048+ compatible = "sinovoip,bananapi-m2m", "allwinner,sun8i-a33";
21049+
21050+ aliases {
21051+ i2c0 = &i2c0;
21052+ i2c1 = &i2c1;
21053+ i2c2 = &i2c2;
21054+ serial0 = &uart0;
21055+ serial1 = &uart1;
21056+ };
21057+
21058+ chosen {
21059+ stdout-path = "serial0:115200n8";
21060+ };
21061+
21062+ leds {
21063+ compatible = "gpio-leds";
21064+
21065+ blue {
21066+ label = "bpi-m2m:blue:usr";
21067+ gpios = <&pio 2 7 GPIO_ACTIVE_LOW>;
21068+ };
21069+
21070+ green {
21071+ label = "bpi-m2m:green:usr";
21072+ gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>;
21073+ };
21074+
21075+ red {
21076+ label = "bpi-m2m:red:power";
21077+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
21078+ default-state = "on";
21079+ };
21080+ };
21081+
21082+ reg_vcc5v0: vcc5v0 {
21083+ compatible = "regulator-fixed";
21084+ regulator-name = "vcc5v0";
21085+ regulator-min-microvolt = <5000000>;
21086+ regulator-max-microvolt = <5000000>;
21087+ };
21088+
21089+ wifi_pwrseq: wifi_pwrseq {
21090+ compatible = "mmc-pwrseq-simple";
21091+ reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
21092+ };
21093+};
21094+
21095+&codec {
21096+ status = "okay";
21097+};
21098+
21099+&cpu0 {
21100+ cpu-supply = <&reg_dcdc3>;
21101+};
21102+
21103+&cpu0_opp_table {
21104+ opp@1104000000 {
21105+ opp-hz = /bits/ 64 <1104000000>;
21106+ opp-microvolt = <1320000>;
21107+ clock-latency-ns = <244144>; /* 8 32k periods */
21108+ };
21109+
21110+ opp@1200000000 {
21111+ opp-hz = /bits/ 64 <1200000000>;
21112+ opp-microvolt = <1320000>;
21113+ clock-latency-ns = <244144>; /* 8 32k periods */
21114+ };
21115+};
21116+
21117+&dai {
21118+ status = "okay";
21119+};
21120+
21121+&ehci0 {
21122+ status = "okay";
21123+};
21124+
21125+/* This is the i2c bus exposed on the DSI connector for the touch panel */
21126+&i2c0 {
21127+ pinctrl-names = "default";
21128+ pinctrl-0 = <&i2c0_pins_a>;
21129+ status = "disabled";
21130+};
21131+
21132+/* This is the i2c bus exposed on the GPIO header */
21133+&i2c1 {
21134+ pinctrl-names = "default";
21135+ pinctrl-0 = <&i2c1_pins_a>;
21136+ status = "disabled";
21137+};
21138+
21139+/* This is the i2c bus exposed on the CSI connector to control the sensor */
21140+&i2c2 {
21141+ pinctrl-names = "default";
21142+ pinctrl-0 = <&i2c2_pins_a>;
21143+ status = "disabled";
21144+};
21145+
21146+&mmc0 {
21147+ pinctrl-names = "default";
21148+ pinctrl-0 = <&mmc0_pins_a>;
21149+ vmmc-supply = <&reg_dcdc1>;
21150+ bus-width = <4>;
21151+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
21152+ cd-inverted;
21153+ status = "okay";
21154+};
21155+
21156+&mmc1 {
21157+ pinctrl-names = "default";
21158+ pinctrl-0 = <&mmc1_pins_a>;
21159+ vmmc-supply = <&reg_aldo1>;
21160+ mmc-pwrseq = <&wifi_pwrseq>;
21161+ bus-width = <4>;
21162+ non-removable;
21163+ status = "okay";
21164+};
21165+
21166+&mmc2 {
21167+ pinctrl-names = "default";
21168+ pinctrl-0 = <&mmc2_8bit_pins>;
21169+ vmmc-supply = <&reg_dcdc1>;
21170+ bus-width = <8>;
21171+ non-removable;
21172+ cap-mmc-hw-reset;
21173+ status = "okay";
21174+};
21175+
21176+&ohci0 {
21177+ status = "okay";
21178+};
21179+
21180+&r_rsb {
21181+ status = "okay";
21182+
21183+ axp22x: pmic@3a3 {
21184+ compatible = "x-powers,axp223";
21185+ reg = <0x3a3>;
21186+ interrupt-parent = <&nmi_intc>;
21187+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
21188+ eldoin-supply = <&reg_dcdc1>;
21189+ x-powers,drive-vbus-en;
21190+ };
21191+};
21192+
21193+#include "axp223.dtsi"
21194+
21195+&ac_power_supply {
21196+ status = "okay";
21197+};
21198+
21199+&reg_aldo1 {
21200+ regulator-always-on;
21201+ regulator-min-microvolt = <3000000>;
21202+ regulator-max-microvolt = <3000000>;
21203+ regulator-name = "vcc-io";
21204+};
21205+
21206+&reg_aldo2 {
21207+ regulator-always-on;
21208+ regulator-min-microvolt = <2500000>;
21209+ regulator-max-microvolt = <2500000>;
21210+ regulator-name = "vdd-dll";
21211+};
21212+
21213+&reg_aldo3 {
21214+ regulator-always-on;
21215+ regulator-min-microvolt = <3000000>;
21216+ regulator-max-microvolt = <3000000>;
21217+ regulator-name = "avcc";
21218+};
21219+
21220+&reg_dc1sw {
21221+ regulator-name = "vcc-lcd";
21222+};
21223+
21224+&reg_dc5ldo {
21225+ regulator-always-on;
21226+ regulator-min-microvolt = <900000>;
21227+ regulator-max-microvolt = <1400000>;
21228+ regulator-name = "vdd-cpus";
21229+};
21230+
21231+&reg_dcdc1 {
21232+ regulator-always-on;
21233+ regulator-min-microvolt = <3000000>;
21234+ regulator-max-microvolt = <3000000>;
21235+ regulator-name = "vcc-3v0";
21236+};
21237+
21238+&reg_dcdc2 {
21239+ regulator-always-on;
21240+ regulator-min-microvolt = <900000>;
21241+ regulator-max-microvolt = <1400000>;
21242+ regulator-name = "vdd-sys";
21243+};
21244+
21245+&reg_dcdc3 {
21246+ regulator-always-on;
21247+ regulator-min-microvolt = <900000>;
21248+ regulator-max-microvolt = <1400000>;
21249+ regulator-name = "vdd-cpu";
21250+};
21251+
21252+&reg_dcdc5 {
21253+ regulator-always-on;
21254+ regulator-min-microvolt = <1500000>;
21255+ regulator-max-microvolt = <1500000>;
21256+ regulator-name = "vcc-dram";
21257+};
21258+
21259+/*
21260+ * Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same
21261+ * time, with the two being in sync. Since this is not really
21262+ * supported right now, just use the two as always on, and we will fix
21263+ * it later.
21264+ */
21265+&reg_dldo1 {
21266+ regulator-always-on;
21267+ regulator-min-microvolt = <3300000>;
21268+ regulator-max-microvolt = <3300000>;
21269+ regulator-name = "vcc-wifi0";
21270+};
21271+
21272+&reg_dldo2 {
21273+ regulator-always-on;
21274+ regulator-min-microvolt = <3300000>;
21275+ regulator-max-microvolt = <3300000>;
21276+ regulator-name = "vcc-wifi1";
21277+};
21278+
21279+&reg_drivevbus {
21280+ regulator-name = "usb0-vbus";
21281+ status = "okay";
21282+};
21283+
21284+&reg_rtc_ldo {
21285+ regulator-name = "vcc-rtc";
21286+};
21287+
21288+&sound {
21289+ status = "okay";
21290+};
21291+
21292+&uart0 {
21293+ pinctrl-names = "default";
21294+ pinctrl-0 = <&uart0_pins_b>;
21295+ status = "okay";
21296+};
21297+
21298+&uart1 {
21299+ pinctrl-names = "default";
21300+ pinctrl-0 = <&uart1_pins_a>, <&uart1_pins_cts_rts_a>;
21301+ status = "okay";
21302+};
21303+
21304+&usb_otg {
21305+ dr_mode = "otg";
21306+ status = "okay";
21307+};
21308+
21309+&usb_power_supply {
21310+ status = "okay";
21311+};
21312+
21313+&usbphy {
21314+ usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
21315+ usb0_vbus_power-supply = <&usb_power_supply>;
21316+ usb0_vbus-supply = <&reg_drivevbus>;
21317+ usb1_vbus-supply = <&reg_vcc5v0>;
21318+ status = "okay";
21319+};
21320diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
21321index 1444fbd543e7..5af4dd321952 100644
21322--- a/arch/arm/boot/dts/tegra114-dalmore.dts
21323+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
21324@@ -1122,6 +1122,16 @@ sdhci@78000600 {
21325 non-removable;
21326 };
21327
21328+ usb@7d000000 {
21329+ compatible = "nvidia,tegra114-udc";
21330+ status = "okay";
21331+ dr_mode = "peripheral";
21332+ };
21333+
21334+ usb-phy@7d000000 {
21335+ status = "okay";
21336+ };
21337+
21338 usb@7d008000 {
21339 status = "okay";
21340 };
21341diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
21342index 7bacb2954f58..61873d642a45 100644
21343--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
21344+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
21345@@ -1722,7 +1722,7 @@ usb2 {
21346
21347 lanes {
21348 usb2-0 {
21349- nvidia,function = "xusb";
21350+ nvidia,function = "snps";
21351 status = "okay";
21352 };
21353
21354@@ -1829,6 +1829,16 @@ i2s@70301100 {
21355 };
21356 };
21357
21358+ usb@7d000000 {
21359+ compatible = "nvidia,tegra124-udc";
21360+ status = "okay";
21361+ dr_mode = "peripheral";
21362+ };
21363+
21364+ usb-phy@7d000000 {
21365+ status = "okay";
21366+ };
21367+
21368 /* mini-PCIe USB */
21369 usb@7d004000 {
21370 status = "okay";
21371diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
21372index 1b10b14a6abd..8baf00b89efb 100644
21373--- a/arch/arm/boot/dts/tegra124.dtsi
21374+++ b/arch/arm/boot/dts/tegra124.dtsi
21375@@ -87,6 +87,7 @@ host1x@50000000 {
21376 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
21377 resets = <&tegra_car 28>;
21378 reset-names = "host1x";
21379+ iommus = <&mc TEGRA_SWGROUP_HC>;
21380
21381 #address-cells = <2>;
21382 #size-cells = <2>;
21383diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
21384index b4bfa5586c23..bfa9421fcf94 100644
21385--- a/arch/arm/boot/dts/tegra20-paz00.dts
21386+++ b/arch/arm/boot/dts/tegra20-paz00.dts
21387@@ -452,7 +452,9 @@ pmc@7000e400 {
21388 };
21389
21390 usb@c5000000 {
21391+ compatible = "nvidia,tegra20-udc";
21392 status = "okay";
21393+ dr_mode = "peripheral";
21394 };
21395
21396 usb-phy@c5000000 {
21397diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
21398index 4f41b18d9547..3e104ddeb220 100644
21399--- a/arch/arm/boot/dts/tegra30-beaver.dts
21400+++ b/arch/arm/boot/dts/tegra30-beaver.dts
21401@@ -1927,6 +1927,16 @@ sdhci@78000600 {
21402 non-removable;
21403 };
21404
21405+ usb@7d000000 {
21406+ compatible = "nvidia,tegra30-udc";
21407+ status = "okay";
21408+ dr_mode = "peripheral";
21409+ };
21410+
21411+ usb-phy@7d000000 {
21412+ status = "okay";
21413+ };
21414+
21415 usb@7d004000 {
21416 status = "okay";
21417 };
21418diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi
21419index 02de56b55823..399baaa0a2ab 100644
21420--- a/arch/arm/boot/dts/tps65217.dtsi
21421+++ b/arch/arm/boot/dts/tps65217.dtsi
21422@@ -18,11 +18,14 @@ &tps {
21423
21424 charger {
21425 compatible = "ti,tps65217-charger";
21426+ interrupts = <0>, <1>;
21427+ interrupt-names = "USB", "AC";
21428 status = "disabled";
21429 };
21430
21431 pwrbutton {
21432 compatible = "ti,tps65217-pwrbutton";
21433+ interrupts = <2>;
21434 status = "disabled";
21435 };
21436
21437diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts
21438index 4817ebb28eb2..b3aaab354f3e 100644
21439--- a/arch/arm/boot/dts/uniphier-ld4-ref.dts
21440+++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts
21441@@ -8,9 +8,9 @@
21442 */
21443
21444 /dts-v1/;
21445-/include/ "uniphier-ld4.dtsi"
21446-/include/ "uniphier-ref-daughter.dtsi"
21447-/include/ "uniphier-support-card.dtsi"
21448+#include "uniphier-ld4.dtsi"
21449+#include "uniphier-ref-daughter.dtsi"
21450+#include "uniphier-support-card.dtsi"
21451
21452 / {
21453 model = "UniPhier LD4 Reference Board";
21454@@ -64,3 +64,7 @@ &usb0 {
21455 &usb1 {
21456 status = "okay";
21457 };
21458+
21459+&nand {
21460+ status = "okay";
21461+};
21462diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
21463index fb2fd9605b9d..79183db5b386 100644
21464--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
21465+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
21466@@ -270,6 +270,13 @@ intc: interrupt-controller@60001000 {
21467 interrupt-controller;
21468 };
21469
21470+ aidet: aidet@61830000 {
21471+ compatible = "socionext,uniphier-ld4-aidet";
21472+ reg = <0x61830000 0x200>;
21473+ interrupt-controller;
21474+ #interrupt-cells = <2>;
21475+ };
21476+
21477 sysctrl@61840000 {
21478 compatible = "socionext,uniphier-ld4-sysctrl",
21479 "simple-mfd", "syscon";
21480@@ -285,7 +292,18 @@ sys_rst: reset {
21481 #reset-cells = <1>;
21482 };
21483 };
21484+
21485+ nand: nand@68000000 {
21486+ compatible = "socionext,uniphier-denali-nand-v5a";
21487+ status = "disabled";
21488+ reg-names = "nand_data", "denali_reg";
21489+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
21490+ interrupts = <0 65 4>;
21491+ pinctrl-names = "default";
21492+ pinctrl-0 = <&pinctrl_nand2cs>;
21493+ clocks = <&sys_clk 2>;
21494+ };
21495 };
21496 };
21497
21498-/include/ "uniphier-pinctrl.dtsi"
21499+#include "uniphier-pinctrl.dtsi"
21500diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts
21501index 96db4abc02c3..2188d114d79b 100644
21502--- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts
21503+++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts
21504@@ -8,9 +8,9 @@
21505 */
21506
21507 /dts-v1/;
21508-/include/ "uniphier-ld6b.dtsi"
21509-/include/ "uniphier-ref-daughter.dtsi"
21510-/include/ "uniphier-support-card.dtsi"
21511+#include "uniphier-ld6b.dtsi"
21512+#include "uniphier-ref-daughter.dtsi"
21513+#include "uniphier-support-card.dtsi"
21514
21515 / {
21516 model = "UniPhier LD6b Reference Board";
21517@@ -58,3 +58,7 @@ &serial2 {
21518 &i2c0 {
21519 status = "okay";
21520 };
21521+
21522+&nand {
21523+ status = "okay";
21524+};
21525diff --git a/arch/arm/boot/dts/uniphier-ld6b.dtsi b/arch/arm/boot/dts/uniphier-ld6b.dtsi
21526index 8b9a79731bd3..9a7b25cc8233 100644
21527--- a/arch/arm/boot/dts/uniphier-ld6b.dtsi
21528+++ b/arch/arm/boot/dts/uniphier-ld6b.dtsi
21529@@ -12,7 +12,7 @@
21530 * The D-chip (digital chip) is the same as the PXs2 die.
21531 * Reuse the PXs2 device tree with some properties overridden.
21532 */
21533-/include/ "uniphier-pxs2.dtsi"
21534+#include "uniphier-pxs2.dtsi"
21535
21536 / {
21537 compatible = "socionext,uniphier-ld6b";
21538diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
21539index 246f35ffb638..be82cddc4072 100644
21540--- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi
21541+++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
21542@@ -4,51 +4,35 @@
21543 * Copyright (C) 2015-2017 Socionext Inc.
21544 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
21545 *
21546- * This file is dual-licensed: you can use it either under the terms
21547- * of the GPL or the X11 license, at your option. Note that this dual
21548- * licensing only applies to this file, and not this project as a
21549- * whole.
21550- *
21551- * a) This file is free software; you can redistribute it and/or
21552- * modify it under the terms of the GNU General Public License as
21553- * published by the Free Software Foundation; either version 2 of the
21554- * License, or (at your option) any later version.
21555- *
21556- * This file is distributed in the hope that it will be useful,
21557- * but WITHOUT ANY WARRANTY; without even the implied warranty of
21558- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21559- * GNU General Public License for more details.
21560- *
21561- * Or, alternatively,
21562- *
21563- * b) Permission is hereby granted, free of charge, to any person
21564- * obtaining a copy of this software and associated documentation
21565- * files (the "Software"), to deal in the Software without
21566- * restriction, including without limitation the rights to use,
21567- * copy, modify, merge, publish, distribute, sublicense, and/or
21568- * sell copies of the Software, and to permit persons to whom the
21569- * Software is furnished to do so, subject to the following
21570- * conditions:
21571- *
21572- * The above copyright notice and this permission notice shall be
21573- * included in all copies or substantial portions of the Software.
21574- *
21575- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21576- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
21577- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
21578- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
21579- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
21580- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21581- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21582- * OTHER DEALINGS IN THE SOFTWARE.
21583+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
21584 */
21585
21586 &pinctrl {
21587+ pinctrl_aout: aout_grp {
21588+ groups = "aout";
21589+ function = "aout";
21590+ };
21591+
21592 pinctrl_emmc: emmc_grp {
21593 groups = "emmc", "emmc_dat8";
21594 function = "emmc";
21595 };
21596
21597+ pinctrl_ether_mii: ether_mii_grp {
21598+ groups = "ether_mii";
21599+ function = "ether_mii";
21600+ };
21601+
21602+ pinctrl_ether_rgmii: ether_rgmii_grp {
21603+ groups = "ether_rgmii";
21604+ function = "ether_rgmii";
21605+ };
21606+
21607+ pinctrl_ether_rmii: ether_rmii_grp {
21608+ groups = "ether_rmii";
21609+ function = "ether_rmii";
21610+ };
21611+
21612 pinctrl_i2c0: i2c0_grp {
21613 groups = "i2c0";
21614 function = "i2c0";
21615diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts
21616index 11690b57931c..089419cee273 100644
21617--- a/arch/arm/boot/dts/uniphier-pro4-ace.dts
21618+++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts
21619@@ -8,7 +8,7 @@
21620 */
21621
21622 /dts-v1/;
21623-/include/ "uniphier-pro4.dtsi"
21624+#include "uniphier-pro4.dtsi"
21625
21626 / {
21627 model = "UniPhier Pro4 Ace Board";
21628diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts
21629index 4cf539245f2e..903df6348e77 100644
21630--- a/arch/arm/boot/dts/uniphier-pro4-ref.dts
21631+++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts
21632@@ -8,9 +8,9 @@
21633 */
21634
21635 /dts-v1/;
21636-/include/ "uniphier-pro4.dtsi"
21637-/include/ "uniphier-ref-daughter.dtsi"
21638-/include/ "uniphier-support-card.dtsi"
21639+#include "uniphier-pro4.dtsi"
21640+#include "uniphier-ref-daughter.dtsi"
21641+#include "uniphier-support-card.dtsi"
21642
21643 / {
21644 model = "UniPhier Pro4 Reference Board";
21645@@ -66,3 +66,7 @@ &usb2 {
21646 &usb3 {
21647 status = "okay";
21648 };
21649+
21650+&nand {
21651+ status = "okay";
21652+};
21653diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-pro4-sanji.dts
21654index 2763cebcd76a..adef212b45b2 100644
21655--- a/arch/arm/boot/dts/uniphier-pro4-sanji.dts
21656+++ b/arch/arm/boot/dts/uniphier-pro4-sanji.dts
21657@@ -8,7 +8,7 @@
21658 */
21659
21660 /dts-v1/;
21661-/include/ "uniphier-pro4.dtsi"
21662+#include "uniphier-pro4.dtsi"
21663
21664 / {
21665 model = "UniPhier Pro4 Sanji Board";
21666diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
21667index 37400becf4ba..b3dbbd9b6e39 100644
21668--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
21669+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
21670@@ -268,6 +268,13 @@ pinctrl: pinctrl {
21671 };
21672 };
21673
21674+ aidet: aidet@5fc20000 {
21675+ compatible = "socionext,uniphier-pro4-aidet";
21676+ reg = <0x5fc20000 0x200>;
21677+ interrupt-controller;
21678+ #interrupt-cells = <2>;
21679+ };
21680+
21681 timer@60000200 {
21682 compatible = "arm,cortex-a9-global-timer";
21683 reg = <0x60000200 0x20>;
21684@@ -305,7 +312,18 @@ sys_rst: reset {
21685 #reset-cells = <1>;
21686 };
21687 };
21688+
21689+ nand: nand@68000000 {
21690+ compatible = "socionext,uniphier-denali-nand-v5a";
21691+ status = "disabled";
21692+ reg-names = "nand_data", "denali_reg";
21693+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
21694+ interrupts = <0 65 4>;
21695+ pinctrl-names = "default";
21696+ pinctrl-0 = <&pinctrl_nand>;
21697+ clocks = <&sys_clk 2>;
21698+ };
21699 };
21700 };
21701
21702-/include/ "uniphier-pinctrl.dtsi"
21703+#include "uniphier-pinctrl.dtsi"
21704diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
21705index 9577769a0add..b026bcd42a06 100644
21706--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
21707+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
21708@@ -4,43 +4,7 @@
21709 * Copyright (C) 2015-2016 Socionext Inc.
21710 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
21711 *
21712- * This file is dual-licensed: you can use it either under the terms
21713- * of the GPL or the X11 license, at your option. Note that this dual
21714- * licensing only applies to this file, and not this project as a
21715- * whole.
21716- *
21717- * a) This file is free software; you can redistribute it and/or
21718- * modify it under the terms of the GNU General Public License as
21719- * published by the Free Software Foundation; either version 2 of the
21720- * License, or (at your option) any later version.
21721- *
21722- * This file is distributed in the hope that it will be useful,
21723- * but WITHOUT ANY WARRANTY; without even the implied warranty of
21724- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21725- * GNU General Public License for more details.
21726- *
21727- * Or, alternatively,
21728- *
21729- * b) Permission is hereby granted, free of charge, to any person
21730- * obtaining a copy of this software and associated documentation
21731- * files (the "Software"), to deal in the Software without
21732- * restriction, including without limitation the rights to use,
21733- * copy, modify, merge, publish, distribute, sublicense, and/or
21734- * sell copies of the Software, and to permit persons to whom the
21735- * Software is furnished to do so, subject to the following
21736- * conditions:
21737- *
21738- * The above copyright notice and this permission notice shall be
21739- * included in all copies or substantial portions of the Software.
21740- *
21741- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21742- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
21743- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
21744- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
21745- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
21746- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21747- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21748- * OTHER DEALINGS IN THE SOFTWARE.
21749+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
21750 */
21751
21752 / {
21753@@ -328,7 +292,7 @@ smpctrl@59801000 {
21754 sdctrl@59810000 {
21755 compatible = "socionext,uniphier-pro5-sdctrl",
21756 "simple-mfd", "syscon";
21757- reg = <0x59810000 0x800>;
21758+ reg = <0x59810000 0x400>;
21759
21760 sd_clk: clock {
21761 compatible = "socionext,uniphier-pro5-sd-clock";
21762@@ -367,6 +331,13 @@ pinctrl: pinctrl {
21763 };
21764 };
21765
21766+ aidet: aidet@5fc20000 {
21767+ compatible = "socionext,uniphier-pro5-aidet";
21768+ reg = <0x5fc20000 0x200>;
21769+ interrupt-controller;
21770+ #interrupt-cells = <2>;
21771+ };
21772+
21773 timer@60000200 {
21774 compatible = "arm,cortex-a9-global-timer";
21775 reg = <0x60000200 0x20>;
21776@@ -404,7 +375,18 @@ sys_rst: reset {
21777 #reset-cells = <1>;
21778 };
21779 };
21780+
21781+ nand: nand@68000000 {
21782+ compatible = "socionext,uniphier-denali-nand-v5b";
21783+ status = "disabled";
21784+ reg-names = "nand_data", "denali_reg";
21785+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
21786+ interrupts = <0 65 4>;
21787+ pinctrl-names = "default";
21788+ pinctrl-0 = <&pinctrl_nand2cs>;
21789+ clocks = <&sys_clk 2>;
21790+ };
21791 };
21792 };
21793
21794-/include/ "uniphier-pinctrl.dtsi"
21795+#include "uniphier-pinctrl.dtsi"
21796diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
21797index 81560f75bfa7..7dfae2667f50 100644
21798--- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
21799+++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
21800@@ -8,7 +8,7 @@
21801 */
21802
21803 /dts-v1/;
21804-/include/ "uniphier-pxs2.dtsi"
21805+#include "uniphier-pxs2.dtsi"
21806
21807 / {
21808 model = "UniPhier PXs2 Gentil Board";
21809diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
21810index dc2d0579c666..0cf615463a82 100644
21811--- a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
21812+++ b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
21813@@ -8,7 +8,7 @@
21814 */
21815
21816 /dts-v1/;
21817-/include/ "uniphier-pxs2.dtsi"
21818+#include "uniphier-pxs2.dtsi"
21819
21820 / {
21821 model = "UniPhier PXs2 Vodka Board";
21822diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
21823index bace751d4023..90b020c95083 100644
21824--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
21825+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
21826@@ -276,7 +276,7 @@ smpctrl@59801000 {
21827 sdctrl@59810000 {
21828 compatible = "socionext,uniphier-pxs2-sdctrl",
21829 "simple-mfd", "syscon";
21830- reg = <0x59810000 0x800>;
21831+ reg = <0x59810000 0x400>;
21832
21833 sd_clk: clock {
21834 compatible = "socionext,uniphier-pxs2-sd-clock";
21835@@ -315,6 +315,13 @@ pinctrl: pinctrl {
21836 };
21837 };
21838
21839+ aidet: aidet@5fc20000 {
21840+ compatible = "socionext,uniphier-pxs2-aidet";
21841+ reg = <0x5fc20000 0x200>;
21842+ interrupt-controller;
21843+ #interrupt-cells = <2>;
21844+ };
21845+
21846 timer@60000200 {
21847 compatible = "arm,cortex-a9-global-timer";
21848 reg = <0x60000200 0x20>;
21849@@ -352,7 +359,18 @@ sys_rst: reset {
21850 #reset-cells = <1>;
21851 };
21852 };
21853+
21854+ nand: nand@68000000 {
21855+ compatible = "socionext,uniphier-denali-nand-v5b";
21856+ status = "disabled";
21857+ reg-names = "nand_data", "denali_reg";
21858+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
21859+ interrupts = <0 65 4>;
21860+ pinctrl-names = "default";
21861+ pinctrl-0 = <&pinctrl_nand2cs>;
21862+ clocks = <&sys_clk 2>;
21863+ };
21864 };
21865 };
21866
21867-/include/ "uniphier-pinctrl.dtsi"
21868+#include "uniphier-pinctrl.dtsi"
21869diff --git a/arch/arm/boot/dts/uniphier-sld3-ref.dts b/arch/arm/boot/dts/uniphier-sld3-ref.dts
21870deleted file mode 100644
21871index 70cda39a3dd2..000000000000
21872--- a/arch/arm/boot/dts/uniphier-sld3-ref.dts
21873+++ /dev/null
21874@@ -1,75 +0,0 @@
21875-/*
21876- * Device Tree Source for UniPhier sLD3 Reference Board
21877- *
21878- * Copyright (C) 2015-2016 Socionext Inc.
21879- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
21880- *
21881- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
21882- */
21883-
21884-/dts-v1/;
21885-/include/ "uniphier-sld3.dtsi"
21886-/include/ "uniphier-ref-daughter.dtsi"
21887-/include/ "uniphier-support-card.dtsi"
21888-
21889-/ {
21890- model = "UniPhier sLD3 Reference Board";
21891- compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3";
21892-
21893- chosen {
21894- stdout-path = "serial0:115200n8";
21895- };
21896-
21897- aliases {
21898- serial0 = &serial0;
21899- serial1 = &serial1;
21900- serial2 = &serial2;
21901- i2c0 = &i2c0;
21902- i2c1 = &i2c1;
21903- i2c2 = &i2c2;
21904- i2c3 = &i2c3;
21905- i2c4 = &i2c4;
21906- };
21907-
21908- memory@8000000 {
21909- device_type = "memory";
21910- reg = <0x80000000 0x20000000
21911- 0xc0000000 0x20000000>;
21912- };
21913-};
21914-
21915-&ethsc {
21916- interrupts = <0 49 4>;
21917-};
21918-
21919-&serial0 {
21920- status = "okay";
21921-};
21922-
21923-&serial1 {
21924- status = "okay";
21925-};
21926-
21927-&serial2 {
21928- status = "okay";
21929-};
21930-
21931-&i2c0 {
21932- status = "okay";
21933-};
21934-
21935-&usb0 {
21936- status = "okay";
21937-};
21938-
21939-&usb1 {
21940- status = "okay";
21941-};
21942-
21943-&usb2 {
21944- status = "okay";
21945-};
21946-
21947-&usb3 {
21948- status = "okay";
21949-};
21950diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi
21951deleted file mode 100644
21952index 408287936613..000000000000
21953--- a/arch/arm/boot/dts/uniphier-sld3.dtsi
21954+++ /dev/null
21955@@ -1,260 +0,0 @@
21956-/*
21957- * Device Tree Source for UniPhier sLD3 SoC
21958- *
21959- * Copyright (C) 2015-2016 Socionext Inc.
21960- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
21961- *
21962- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
21963- */
21964-
21965-/ {
21966- compatible = "socionext,uniphier-sld3";
21967- #address-cells = <1>;
21968- #size-cells = <1>;
21969-
21970- cpus {
21971- #address-cells = <1>;
21972- #size-cells = <0>;
21973-
21974- cpu@0 {
21975- device_type = "cpu";
21976- compatible = "arm,cortex-a9";
21977- reg = <0>;
21978- enable-method = "psci";
21979- next-level-cache = <&l2>;
21980- };
21981-
21982- cpu@1 {
21983- device_type = "cpu";
21984- compatible = "arm,cortex-a9";
21985- reg = <1>;
21986- enable-method = "psci";
21987- next-level-cache = <&l2>;
21988- };
21989- };
21990-
21991- psci {
21992- compatible = "arm,psci-0.2";
21993- method = "smc";
21994- };
21995-
21996- clocks {
21997- refclk: ref {
21998- #clock-cells = <0>;
21999- compatible = "fixed-clock";
22000- clock-frequency = <24576000>;
22001- };
22002-
22003- arm_timer_clk: arm_timer_clk {
22004- #clock-cells = <0>;
22005- compatible = "fixed-clock";
22006- clock-frequency = <50000000>;
22007- };
22008- };
22009-
22010- soc {
22011- compatible = "simple-bus";
22012- #address-cells = <1>;
22013- #size-cells = <1>;
22014- ranges;
22015- interrupt-parent = <&intc>;
22016-
22017- timer@20000200 {
22018- compatible = "arm,cortex-a9-global-timer";
22019- reg = <0x20000200 0x20>;
22020- interrupts = <1 11 0x304>;
22021- clocks = <&arm_timer_clk>;
22022- };
22023-
22024- timer@20000600 {
22025- compatible = "arm,cortex-a9-twd-timer";
22026- reg = <0x20000600 0x20>;
22027- interrupts = <1 13 0x304>;
22028- clocks = <&arm_timer_clk>;
22029- };
22030-
22031- intc: interrupt-controller@20001000 {
22032- compatible = "arm,cortex-a9-gic";
22033- #interrupt-cells = <3>;
22034- interrupt-controller;
22035- reg = <0x20001000 0x1000>,
22036- <0x20000100 0x100>;
22037- };
22038-
22039- l2: l2-cache@500c0000 {
22040- compatible = "socionext,uniphier-system-cache";
22041- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
22042- <0x506c0000 0x400>;
22043- interrupts = <0 174 4>, <0 175 4>;
22044- cache-unified;
22045- cache-size = <(512 * 1024)>;
22046- cache-sets = <256>;
22047- cache-line-size = <128>;
22048- cache-level = <2>;
22049- };
22050-
22051- serial0: serial@54006800 {
22052- compatible = "socionext,uniphier-uart";
22053- status = "disabled";
22054- reg = <0x54006800 0x40>;
22055- interrupts = <0 33 4>;
22056- clocks = <&sys_clk 0>;
22057- };
22058-
22059- serial1: serial@54006900 {
22060- compatible = "socionext,uniphier-uart";
22061- status = "disabled";
22062- reg = <0x54006900 0x40>;
22063- interrupts = <0 35 4>;
22064- clocks = <&sys_clk 0>;
22065- };
22066-
22067- serial2: serial@54006a00 {
22068- compatible = "socionext,uniphier-uart";
22069- status = "disabled";
22070- reg = <0x54006a00 0x40>;
22071- interrupts = <0 37 4>;
22072- clocks = <&sys_clk 0>;
22073- };
22074-
22075- i2c0: i2c@58400000 {
22076- compatible = "socionext,uniphier-i2c";
22077- status = "disabled";
22078- reg = <0x58400000 0x40>;
22079- #address-cells = <1>;
22080- #size-cells = <0>;
22081- interrupts = <0 41 1>;
22082- clocks = <&sys_clk 1>;
22083- clock-frequency = <100000>;
22084- };
22085-
22086- i2c1: i2c@58480000 {
22087- compatible = "socionext,uniphier-i2c";
22088- status = "disabled";
22089- reg = <0x58480000 0x40>;
22090- #address-cells = <1>;
22091- #size-cells = <0>;
22092- interrupts = <0 42 1>;
22093- clocks = <&sys_clk 1>;
22094- clock-frequency = <100000>;
22095- };
22096-
22097- i2c2: i2c@58500000 {
22098- compatible = "socionext,uniphier-i2c";
22099- status = "disabled";
22100- reg = <0x58500000 0x40>;
22101- #address-cells = <1>;
22102- #size-cells = <0>;
22103- interrupts = <0 43 1>;
22104- clocks = <&sys_clk 1>;
22105- clock-frequency = <100000>;
22106- };
22107-
22108- i2c3: i2c@58580000 {
22109- compatible = "socionext,uniphier-i2c";
22110- status = "disabled";
22111- reg = <0x58580000 0x40>;
22112- #address-cells = <1>;
22113- #size-cells = <0>;
22114- interrupts = <0 44 1>;
22115- clocks = <&sys_clk 1>;
22116- clock-frequency = <100000>;
22117- };
22118-
22119- /* chip-internal connection for DMD */
22120- i2c4: i2c@58600000 {
22121- compatible = "socionext,uniphier-i2c";
22122- reg = <0x58600000 0x40>;
22123- #address-cells = <1>;
22124- #size-cells = <0>;
22125- interrupts = <0 45 1>;
22126- clocks = <&sys_clk 1>;
22127- clock-frequency = <400000>;
22128- };
22129-
22130- system_bus: system-bus@58c00000 {
22131- compatible = "socionext,uniphier-system-bus";
22132- status = "disabled";
22133- reg = <0x58c00000 0x400>;
22134- #address-cells = <2>;
22135- #size-cells = <1>;
22136- };
22137-
22138- smpctrl@59801000 {
22139- compatible = "socionext,uniphier-smpctrl";
22140- reg = <0x59801000 0x400>;
22141- };
22142-
22143- mioctrl@59810000 {
22144- compatible = "socionext,uniphier-sld3-mioctrl",
22145- "simple-mfd", "syscon";
22146- reg = <0x59810000 0x800>;
22147-
22148- mio_clk: clock {
22149- compatible = "socionext,uniphier-sld3-mio-clock";
22150- #clock-cells = <1>;
22151- };
22152-
22153- mio_rst: reset {
22154- compatible = "socionext,uniphier-sld3-mio-reset";
22155- #reset-cells = <1>;
22156- };
22157- };
22158-
22159- usb0: usb@5a800100 {
22160- compatible = "socionext,uniphier-ehci", "generic-ehci";
22161- status = "disabled";
22162- reg = <0x5a800100 0x100>;
22163- interrupts = <0 80 4>;
22164- clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
22165- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
22166- <&mio_rst 12>;
22167- };
22168-
22169- usb1: usb@5a810100 {
22170- compatible = "socionext,uniphier-ehci", "generic-ehci";
22171- status = "disabled";
22172- reg = <0x5a810100 0x100>;
22173- interrupts = <0 81 4>;
22174- clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
22175- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
22176- <&mio_rst 13>;
22177- };
22178-
22179- usb2: usb@5a820100 {
22180- compatible = "socionext,uniphier-ehci", "generic-ehci";
22181- status = "disabled";
22182- reg = <0x5a820100 0x100>;
22183- interrupts = <0 82 4>;
22184- clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
22185- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
22186- <&mio_rst 14>;
22187- };
22188-
22189- usb3: usb@5a830100 {
22190- compatible = "socionext,uniphier-ehci", "generic-ehci";
22191- status = "disabled";
22192- reg = <0x5a830100 0x100>;
22193- interrupts = <0 83 4>;
22194- clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
22195- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
22196- <&mio_rst 15>;
22197- };
22198-
22199- sysctrl@f1840000 {
22200- compatible = "socionext,uniphier-sld3-sysctrl",
22201- "simple-mfd", "syscon";
22202- reg = <0xf1840000 0x10000>;
22203-
22204- sys_clk: clock {
22205- compatible = "socionext,uniphier-sld3-clock";
22206- #clock-cells = <1>;
22207- };
22208-
22209- sys_rst: reset {
22210- compatible = "socionext,uniphier-sld3-reset";
22211- #reset-cells = <1>;
22212- };
22213- };
22214- };
22215-};
22216diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts
22217index 4536d5b71297..5accd3cc76e4 100644
22218--- a/arch/arm/boot/dts/uniphier-sld8-ref.dts
22219+++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts
22220@@ -8,9 +8,9 @@
22221 */
22222
22223 /dts-v1/;
22224-/include/ "uniphier-sld8.dtsi"
22225-/include/ "uniphier-ref-daughter.dtsi"
22226-/include/ "uniphier-support-card.dtsi"
22227+#include "uniphier-sld8.dtsi"
22228+#include "uniphier-ref-daughter.dtsi"
22229+#include "uniphier-support-card.dtsi"
22230
22231 / {
22232 model = "UniPhier sLD8 Reference Board";
22233@@ -68,3 +68,7 @@ &usb1 {
22234 &usb2 {
22235 status = "okay";
22236 };
22237+
22238+&nand {
22239+ status = "okay";
22240+};
22241diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
22242index 9fb9167f2db4..b08390332971 100644
22243--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
22244+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
22245@@ -270,6 +270,13 @@ intc: interrupt-controller@60001000 {
22246 interrupt-controller;
22247 };
22248
22249+ aidet: aidet@61830000 {
22250+ compatible = "socionext,uniphier-sld8-aidet";
22251+ reg = <0x61830000 0x200>;
22252+ interrupt-controller;
22253+ #interrupt-cells = <2>;
22254+ };
22255+
22256 sysctrl@61840000 {
22257 compatible = "socionext,uniphier-sld8-sysctrl",
22258 "simple-mfd", "syscon";
22259@@ -285,7 +292,18 @@ sys_rst: reset {
22260 #reset-cells = <1>;
22261 };
22262 };
22263+
22264+ nand: nand@68000000 {
22265+ compatible = "socionext,uniphier-denali-nand-v5a";
22266+ status = "disabled";
22267+ reg-names = "nand_data", "denali_reg";
22268+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
22269+ interrupts = <0 65 4>;
22270+ pinctrl-names = "default";
22271+ pinctrl-0 = <&pinctrl_nand2cs>;
22272+ clocks = <&sys_clk 2>;
22273+ };
22274 };
22275 };
22276
22277-/include/ "uniphier-pinctrl.dtsi"
22278+#include "uniphier-pinctrl.dtsi"
22279diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
22280index 06e2331f666d..9abe26028c8b 100644
22281--- a/arch/arm/boot/dts/versatile-pb.dts
22282+++ b/arch/arm/boot/dts/versatile-pb.dts
22283@@ -39,7 +39,7 @@ gpio3: gpio@101e7000 {
22284 clock-names = "apb_pclk";
22285 };
22286
22287- pci-controller@10001000 {
22288+ pci@10001000 {
22289 compatible = "arm,versatile-pci";
22290 device_type = "pci";
22291 reg = <0x10001000 0x1000
22292diff --git a/arch/arm/boot/dts/zx296702-ad1.dts b/arch/arm/boot/dts/zx296702-ad1.dts
22293index 081f980cfbe6..b0183c3a1d7c 100644
22294--- a/arch/arm/boot/dts/zx296702-ad1.dts
22295+++ b/arch/arm/boot/dts/zx296702-ad1.dts
22296@@ -18,7 +18,6 @@ memory {
22297 };
22298
22299 &mmc0 {
22300- num-slots = <1>;
22301 supports-highspeed;
22302 non-removable;
22303 disable-wp;
22304@@ -31,7 +30,6 @@ slot@0 {
22305 };
22306
22307 &mmc1 {
22308- num-slots = <1>;
22309 supports-highspeed;
22310 non-removable;
22311 disable-wp;
22312diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
22313index f3ac9bfe580e..0f79fe1ccd9d 100644
22314--- a/arch/arm/boot/dts/zynq-7000.dtsi
22315+++ b/arch/arm/boot/dts/zynq-7000.dtsi
22316@@ -42,6 +42,14 @@ cpu1: cpu@1 {
22317 };
22318 };
22319
22320+ fpga_full: fpga-full {
22321+ compatible = "fpga-region";
22322+ fpga-mgr = <&devcfg>;
22323+ #address-cells = <1>;
22324+ #size-cells = <1>;
22325+ ranges;
22326+ };
22327+
22328 pmu@f8891000 {
22329 compatible = "arm,cortex-a9-pmu";
22330 interrupts = <0 5 4>, <0 6 4>;
22331diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
22332index 64a6390fc501..0144acfa9793 100644
22333--- a/arch/arm/boot/dts/zynq-parallella.dts
22334+++ b/arch/arm/boot/dts/zynq-parallella.dts
22335@@ -34,7 +34,7 @@ memory@0 {
22336 };
22337
22338 chosen {
22339- bootargs = "earlycon root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
22340+ bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
22341 stdout-path = "serial0:115200n8";
22342 };
22343 };
22344@@ -54,6 +54,7 @@ ethernet_phy: ethernet-phy@0 {
22345 compatible = "ethernet-phy-id0141.0e90",
22346 "ethernet-phy-ieee802.3-c22";
22347 reg = <0>;
22348+ device_type = "ethernet-phy";
22349 marvell,reg-init = <0x3 0x10 0xff00 0x1e>,
22350 <0x3 0x11 0xfff0 0xa>;
22351 };
22352diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
22353index 0cdad2cc8b78..34e8277fce0d 100644
22354--- a/arch/arm/boot/dts/zynq-zc702.dts
22355+++ b/arch/arm/boot/dts/zynq-zc702.dts
22356@@ -12,7 +12,7 @@
22357 * GNU General Public License for more details.
22358 */
22359 /dts-v1/;
22360-/include/ "zynq-7000.dtsi"
22361+#include "zynq-7000.dtsi"
22362
22363 / {
22364 model = "Zynq ZC702 Development Board";
22365@@ -30,7 +30,7 @@ memory@0 {
22366 };
22367
22368 chosen {
22369- bootargs = "earlycon";
22370+ bootargs = "";
22371 stdout-path = "serial0:115200n8";
22372 };
22373
22374@@ -97,6 +97,7 @@ &gem0 {
22375
22376 ethernet_phy: ethernet-phy@7 {
22377 reg = <7>;
22378+ device_type = "ethernet-phy";
22379 };
22380 };
22381
22382@@ -131,6 +132,21 @@ si570: clock-generator@5d {
22383 };
22384 };
22385
22386+ i2c@1 {
22387+ #address-cells = <1>;
22388+ #size-cells = <0>;
22389+ reg = <1>;
22390+ adv7511: hdmi-tx@39 {
22391+ compatible = "adi,adv7511";
22392+ reg = <0x39>;
22393+ adi,input-depth = <8>;
22394+ adi,input-colorspace = "yuv422";
22395+ adi,input-clock = "1x";
22396+ adi,input-style = <3>;
22397+ adi,input-justification = "right";
22398+ };
22399+ };
22400+
22401 i2c@2 {
22402 #address-cells = <1>;
22403 #size-cells = <0>;
22404diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
22405index ad4bb06dba25..7ebc8c5ae39d 100644
22406--- a/arch/arm/boot/dts/zynq-zc706.dts
22407+++ b/arch/arm/boot/dts/zynq-zc706.dts
22408@@ -12,7 +12,7 @@
22409 * GNU General Public License for more details.
22410 */
22411 /dts-v1/;
22412-/include/ "zynq-7000.dtsi"
22413+#include "zynq-7000.dtsi"
22414
22415 / {
22416 model = "Zynq ZC706 Development Board";
22417@@ -30,7 +30,7 @@ memory@0 {
22418 };
22419
22420 chosen {
22421- bootargs = "earlycon";
22422+ bootargs = "";
22423 stdout-path = "serial0:115200n8";
22424 };
22425
22426@@ -53,6 +53,7 @@ &gem0 {
22427
22428 ethernet_phy: ethernet-phy@7 {
22429 reg = <7>;
22430+ device_type = "ethernet-phy";
22431 };
22432 };
22433
22434@@ -87,6 +88,21 @@ si570: clock-generator@5d {
22435 };
22436 };
22437
22438+ i2c@1 {
22439+ #address-cells = <1>;
22440+ #size-cells = <0>;
22441+ reg = <1>;
22442+ adv7511: hdmi-tx@39 {
22443+ compatible = "adi,adv7511";
22444+ reg = <0x39>;
22445+ adi,input-depth = <8>;
22446+ adi,input-colorspace = "yuv422";
22447+ adi,input-clock = "1x";
22448+ adi,input-style = <3>;
22449+ adi,input-justification = "evenly";
22450+ };
22451+ };
22452+
22453 i2c@2 {
22454 #address-cells = <1>;
22455 #size-cells = <0>;
22456diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
22457index 325379f7983c..5e44dc12fd60 100644
22458--- a/arch/arm/boot/dts/zynq-zed.dts
22459+++ b/arch/arm/boot/dts/zynq-zed.dts
22460@@ -12,7 +12,7 @@
22461 * GNU General Public License for more details.
22462 */
22463 /dts-v1/;
22464-/include/ "zynq-7000.dtsi"
22465+#include "zynq-7000.dtsi"
22466
22467 / {
22468 model = "Zynq Zed Development Board";
22469@@ -29,7 +29,7 @@ memory@0 {
22470 };
22471
22472 chosen {
22473- bootargs = "earlycon";
22474+ bootargs = "";
22475 stdout-path = "serial0:115200n8";
22476 };
22477
22478@@ -50,6 +50,7 @@ &gem0 {
22479
22480 ethernet_phy: ethernet-phy@0 {
22481 reg = <0>;
22482+ device_type = "ethernet-phy";
22483 };
22484 };
22485
22486diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts
22487index 590ec24b8749..e40cafc5ee5b 100644
22488--- a/arch/arm/boot/dts/zynq-zybo.dts
22489+++ b/arch/arm/boot/dts/zynq-zybo.dts
22490@@ -12,7 +12,7 @@
22491 * GNU General Public License for more details.
22492 */
22493 /dts-v1/;
22494-/include/ "zynq-7000.dtsi"
22495+#include "zynq-7000.dtsi"
22496
22497 / {
22498 model = "Zynq ZYBO Development Board";
22499@@ -29,7 +29,7 @@ memory@0 {
22500 };
22501
22502 chosen {
22503- bootargs = "earlycon";
22504+ bootargs = "";
22505 stdout-path = "serial0:115200n8";
22506 };
22507
22508@@ -51,6 +51,7 @@ &gem0 {
22509
22510 ethernet_phy: ethernet-phy@0 {
22511 reg = <0>;
22512+ device_type = "ethernet-phy";
22513 };
22514 };
22515
22516diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
22517index b65a7e876a26..6b54ee8c1262 100644
22518--- a/arch/arm64/Kconfig.platforms
22519+++ b/arch/arm64/Kconfig.platforms
22520@@ -184,6 +184,12 @@ config ARCH_R8A7796
22521 help
22522 This enables support for the Renesas R-Car M3-W SoC.
22523
22524+config ARCH_R8A77995
22525+ bool "Renesas R-Car D3 SoC Platform"
22526+ depends on ARCH_RENESAS
22527+ help
22528+ This enables support for the Renesas R-Car D3 SoC.
22529+
22530 config ARCH_STRATIX10
22531 bool "Altera's Stratix 10 SoCFPGA Family"
22532 help
22533diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
22534index 108f12ce6d1d..19c3fbd75eda 100644
22535--- a/arch/arm64/boot/dts/allwinner/Makefile
22536+++ b/arch/arm64/boot/dts/allwinner/Makefile
22537@@ -1,4 +1,6 @@
22538 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb
22539+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb
22540+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
22541 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
22542 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
22543 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
22544diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi
22545new file mode 100644
22546index 000000000000..ff8af52743ff
22547--- /dev/null
22548+++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi
22549@@ -0,0 +1,150 @@
22550+/*
22551+ * Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz>
22552+ *
22553+ * This file is dual-licensed: you can use it either under the terms
22554+ * of the GPL or the X11 license, at your option. Note that this dual
22555+ * licensing only applies to this file, and not this project as a
22556+ * whole.
22557+ *
22558+ * a) This file is free software; you can redistribute it and/or
22559+ * modify it under the terms of the GNU General Public License as
22560+ * published by the Free Software Foundation; either version 2 of the
22561+ * License, or (at your option) any later version.
22562+ *
22563+ * This file is distributed in the hope that it will be useful,
22564+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
22565+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22566+ * GNU General Public License for more details.
22567+ *
22568+ * Or, alternatively,
22569+ *
22570+ * b) Permission is hereby granted, free of charge, to any person
22571+ * obtaining a copy of this software and associated documentation
22572+ * files (the "Software"), to deal in the Software without
22573+ * restriction, including without limitation the rights to use,
22574+ * copy, modify, merge, publish, distribute, sublicense, and/or
22575+ * sell copies of the Software, and to permit persons to whom the
22576+ * Software is furnished to do so, subject to the following
22577+ * conditions:
22578+ *
22579+ * The above copyright notice and this permission notice shall be
22580+ * included in all copies or substantial portions of the Software.
22581+ *
22582+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22583+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
22584+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22585+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
22586+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
22587+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22588+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22589+ * OTHER DEALINGS IN THE SOFTWARE.
22590+ */
22591+
22592+/*
22593+ * AXP803 Integrated Power Management Chip
22594+ * http://files.pine64.org/doc/datasheet/pine64/AXP803_Datasheet_V1.0.pdf
22595+ */
22596+
22597+&axp803 {
22598+ interrupt-controller;
22599+ #interrupt-cells = <1>;
22600+
22601+ regulators {
22602+ /* Default work frequency for buck regulators */
22603+ x-powers,dcdc-freq = <3000>;
22604+
22605+ reg_aldo1: aldo1 {
22606+ regulator-name = "aldo1";
22607+ };
22608+
22609+ reg_aldo2: aldo2 {
22610+ regulator-name = "aldo2";
22611+ };
22612+
22613+ reg_aldo3: aldo3 {
22614+ regulator-name = "aldo3";
22615+ };
22616+
22617+ reg_dc1sw: dc1sw {
22618+ regulator-name = "dc1sw";
22619+ };
22620+
22621+ reg_dcdc1: dcdc1 {
22622+ regulator-name = "dcdc1";
22623+ };
22624+
22625+ reg_dcdc2: dcdc2 {
22626+ regulator-name = "dcdc2";
22627+ };
22628+
22629+ reg_dcdc3: dcdc3 {
22630+ regulator-name = "dcdc3";
22631+ };
22632+
22633+ reg_dcdc4: dcdc4 {
22634+ regulator-name = "dcdc4";
22635+ };
22636+
22637+ reg_dcdc5: dcdc5 {
22638+ regulator-name = "dcdc5";
22639+ };
22640+
22641+ reg_dcdc6: dcdc6 {
22642+ regulator-name = "dcdc6";
22643+ };
22644+
22645+ reg_dldo1: dldo1 {
22646+ regulator-name = "dldo1";
22647+ };
22648+
22649+ reg_dldo2: dldo2 {
22650+ regulator-name = "dldo2";
22651+ };
22652+
22653+ reg_dldo3: dldo3 {
22654+ regulator-name = "dldo3";
22655+ };
22656+
22657+ reg_dldo4: dldo4 {
22658+ regulator-name = "dldo4";
22659+ };
22660+
22661+ reg_eldo1: eldo1 {
22662+ regulator-name = "eldo1";
22663+ };
22664+
22665+ reg_eldo2: eldo2 {
22666+ regulator-name = "eldo2";
22667+ };
22668+
22669+ reg_eldo3: eldo3 {
22670+ regulator-name = "eldo3";
22671+ };
22672+
22673+ reg_fldo1: fldo1 {
22674+ regulator-name = "fldo1";
22675+ };
22676+
22677+ reg_fldo2: fldo2 {
22678+ regulator-name = "fldo2";
22679+ };
22680+
22681+ reg_ldo_io0: ldo-io0 {
22682+ regulator-name = "ldo-io0";
22683+ status = "disabled";
22684+ };
22685+
22686+ reg_ldo_io1: ldo-io1 {
22687+ regulator-name = "ldo-io1";
22688+ status = "disabled";
22689+ };
22690+
22691+ reg_rtc_ldo: rtc-ldo {
22692+ /* RTC_LDO is a fixed, always-on regulator */
22693+ regulator-always-on;
22694+ regulator-min-microvolt = <3000000>;
22695+ regulator-max-microvolt = <3000000>;
22696+ regulator-name = "rtc-ldo";
22697+ };
22698+ };
22699+};
22700diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
22701index 6872135d7f84..d347f52e27f6 100644
22702--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
22703+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
22704@@ -59,14 +59,16 @@ chosen {
22705 stdout-path = "serial0:115200n8";
22706 };
22707
22708- reg_vcc3v3: vcc3v3 {
22709- compatible = "regulator-fixed";
22710- regulator-name = "vcc3v3";
22711- regulator-min-microvolt = <3300000>;
22712- regulator-max-microvolt = <3300000>;
22713+ wifi_pwrseq: wifi_pwrseq {
22714+ compatible = "mmc-pwrseq-simple";
22715+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
22716 };
22717 };
22718
22719+&ehci1 {
22720+ status = "okay";
22721+};
22722+
22723 &i2c1 {
22724 pinctrl-names = "default";
22725 pinctrl-0 = <&i2c1_pins>;
22726@@ -80,7 +82,7 @@ &i2c1_pins {
22727 &mmc0 {
22728 pinctrl-names = "default";
22729 pinctrl-0 = <&mmc0_pins>;
22730- vmmc-supply = <&reg_vcc3v3>;
22731+ vmmc-supply = <&reg_dcdc1>;
22732 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
22733 cd-inverted;
22734 disable-wp;
22735@@ -91,22 +93,143 @@ &mmc0 {
22736 &mmc1 {
22737 pinctrl-names = "default";
22738 pinctrl-0 = <&mmc1_pins>;
22739- vmmc-supply = <&reg_vcc3v3>;
22740+ vmmc-supply = <&reg_dldo2>;
22741+ vqmmc-supply = <&reg_dldo4>;
22742+ mmc-pwrseq = <&wifi_pwrseq>;
22743 bus-width = <4>;
22744 non-removable;
22745 status = "okay";
22746+
22747+ brcmf: wifi@1 {
22748+ reg = <1>;
22749+ compatible = "brcm,bcm4329-fmac";
22750+ interrupt-parent = <&r_pio>;
22751+ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
22752+ interrupt-names = "host-wake";
22753+ };
22754 };
22755
22756 &mmc2 {
22757 pinctrl-names = "default";
22758 pinctrl-0 = <&mmc2_pins>;
22759- vmmc-supply = <&reg_vcc3v3>;
22760+ vmmc-supply = <&reg_dcdc1>;
22761 bus-width = <8>;
22762 non-removable;
22763 cap-mmc-hw-reset;
22764 status = "okay";
22765 };
22766
22767+&ohci1 {
22768+ status = "okay";
22769+};
22770+
22771+&r_rsb {
22772+ status = "okay";
22773+
22774+ axp803: pmic@3a3 {
22775+ compatible = "x-powers,axp803";
22776+ reg = <0x3a3>;
22777+ interrupt-parent = <&r_intc>;
22778+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
22779+ };
22780+};
22781+
22782+#include "axp803.dtsi"
22783+
22784+&reg_aldo2 {
22785+ regulator-always-on;
22786+ regulator-min-microvolt = <1800000>;
22787+ regulator-max-microvolt = <3300000>;
22788+ regulator-name = "vcc-pl";
22789+};
22790+
22791+&reg_aldo3 {
22792+ regulator-always-on;
22793+ regulator-min-microvolt = <3000000>;
22794+ regulator-max-microvolt = <3000000>;
22795+ regulator-name = "vcc-pll-avcc";
22796+};
22797+
22798+&reg_dc1sw {
22799+ regulator-name = "vcc-phy";
22800+};
22801+
22802+&reg_dcdc1 {
22803+ regulator-always-on;
22804+ regulator-min-microvolt = <3300000>;
22805+ regulator-max-microvolt = <3300000>;
22806+ regulator-name = "vcc-3v3";
22807+};
22808+
22809+&reg_dcdc2 {
22810+ regulator-always-on;
22811+ regulator-min-microvolt = <1040000>;
22812+ regulator-max-microvolt = <1300000>;
22813+ regulator-name = "vdd-cpux";
22814+};
22815+
22816+/* DCDC3 is polyphased with DCDC2 */
22817+
22818+&reg_dcdc5 {
22819+ regulator-always-on;
22820+ regulator-min-microvolt = <1500000>;
22821+ regulator-max-microvolt = <1500000>;
22822+ regulator-name = "vcc-dram";
22823+};
22824+
22825+&reg_dcdc6 {
22826+ regulator-always-on;
22827+ regulator-min-microvolt = <1100000>;
22828+ regulator-max-microvolt = <1100000>;
22829+ regulator-name = "vdd-sys";
22830+};
22831+
22832+&reg_dldo1 {
22833+ regulator-min-microvolt = <3300000>;
22834+ regulator-max-microvolt = <3300000>;
22835+ regulator-name = "vcc-hdmi-dsi";
22836+};
22837+
22838+&reg_dldo2 {
22839+ regulator-min-microvolt = <3300000>;
22840+ regulator-max-microvolt = <3300000>;
22841+ regulator-name = "vcc-wifi";
22842+};
22843+
22844+&reg_dldo4 {
22845+ regulator-min-microvolt = <1800000>;
22846+ regulator-max-microvolt = <3300000>;
22847+ regulator-name = "vcc-wifi-io";
22848+};
22849+
22850+&reg_eldo1 {
22851+ regulator-min-microvolt = <1800000>;
22852+ regulator-max-microvolt = <1800000>;
22853+ regulator-name = "cpvdd";
22854+};
22855+
22856+&reg_fldo1 {
22857+ regulator-min-microvolt = <1200000>;
22858+ regulator-max-microvolt = <1200000>;
22859+ regulator-name = "vcc-1v2-hsic";
22860+};
22861+
22862+/*
22863+ * The A64 chip cannot work without this regulator off, although
22864+ * it seems to be only driving the AR100 core.
22865+ * Maybe we don't still know well about CPUs domain.
22866+ */
22867+&reg_fldo2 {
22868+ regulator-always-on;
22869+ regulator-min-microvolt = <1100000>;
22870+ regulator-max-microvolt = <1100000>;
22871+ regulator-name = "vdd-cpus";
22872+};
22873+
22874+&reg_rtc_ldo {
22875+ regulator-name = "vcc-rtc";
22876+};
22877+
22878 &uart0 {
22879 pinctrl-names = "default";
22880 pinctrl-0 = <&uart0_pins_a>;
22881@@ -118,3 +241,7 @@ &uart1 {
22882 pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
22883 status = "okay";
22884 };
22885+
22886+&usbphy {
22887+ status = "okay";
22888+};
22889diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
22890new file mode 100644
22891index 000000000000..2beef9e6cb88
22892--- /dev/null
22893+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
22894@@ -0,0 +1,207 @@
22895+/*
22896+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
22897+ *
22898+ * This file is dual-licensed: you can use it either under the terms
22899+ * of the GPL or the X11 license, at your option. Note that this dual
22900+ * licensing only applies to this file, and not this project as a
22901+ * whole.
22902+ *
22903+ * a) This library is free software; you can redistribute it and/or
22904+ * modify it under the terms of the GNU General Public License as
22905+ * published by the Free Software Foundation; either version 2 of the
22906+ * License, or (at your option) any later version.
22907+ *
22908+ * This library is distributed in the hope that it will be useful,
22909+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
22910+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22911+ * GNU General Public License for more details.
22912+ *
22913+ * Or, alternatively,
22914+ *
22915+ * b) Permission is hereby granted, free of charge, to any person
22916+ * obtaining a copy of this software and associated documentation
22917+ * files (the "Software"), to deal in the Software without
22918+ * restriction, including without limitation the rights to use,
22919+ * copy, modify, merge, publish, distribute, sublicense, and/or
22920+ * sell copies of the Software, and to permit persons to whom the
22921+ * Software is furnished to do so, subject to the following
22922+ * conditions:
22923+ *
22924+ * The above copyright notice and this permission notice shall be
22925+ * included in all copies or substantial portions of the Software.
22926+ *
22927+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22928+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
22929+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22930+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
22931+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
22932+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22933+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22934+ * OTHER DEALINGS IN THE SOFTWARE.
22935+ */
22936+
22937+/dts-v1/;
22938+
22939+#include "sun50i-a64.dtsi"
22940+
22941+#include <dt-bindings/gpio/gpio.h>
22942+
22943+/ {
22944+ model = "FriendlyARM NanoPi A64";
22945+ compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64";
22946+
22947+ aliases {
22948+ serial0 = &uart0;
22949+ };
22950+
22951+ chosen {
22952+ stdout-path = "serial0:115200n8";
22953+ };
22954+};
22955+
22956+&ehci0 {
22957+ status = "okay";
22958+};
22959+
22960+&ehci1 {
22961+ status = "okay";
22962+};
22963+
22964+/* i2c1 connected with gpio headers like pine64, bananapi */
22965+&i2c1 {
22966+ pinctrl-names = "default";
22967+ pinctrl-0 = <&i2c1_pins>;
22968+ status = "disabled";
22969+};
22970+
22971+&i2c1_pins {
22972+ bias-pull-up;
22973+};
22974+
22975+&mmc0 {
22976+ pinctrl-names = "default";
22977+ pinctrl-0 = <&mmc0_pins>;
22978+ vmmc-supply = <&reg_dcdc1>;
22979+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
22980+ cd-inverted;
22981+ disable-wp;
22982+ bus-width = <4>;
22983+ status = "okay";
22984+};
22985+
22986+&ohci0 {
22987+ status = "okay";
22988+};
22989+
22990+&ohci1 {
22991+ status = "okay";
22992+};
22993+
22994+&r_rsb {
22995+ status = "okay";
22996+
22997+ axp803: pmic@3a3 {
22998+ compatible = "x-powers,axp803";
22999+ reg = <0x3a3>;
23000+ interrupt-parent = <&r_intc>;
23001+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
23002+ };
23003+};
23004+
23005+#include "axp803.dtsi"
23006+
23007+&reg_aldo2 {
23008+ regulator-always-on;
23009+ regulator-min-microvolt = <1800000>;
23010+ regulator-max-microvolt = <3300000>;
23011+ regulator-name = "vcc-pl";
23012+};
23013+
23014+&reg_aldo3 {
23015+ regulator-always-on;
23016+ regulator-min-microvolt = <3000000>;
23017+ regulator-max-microvolt = <3000000>;
23018+ regulator-name = "vcc-pll-avcc";
23019+};
23020+
23021+&reg_dcdc1 {
23022+ regulator-always-on;
23023+ regulator-min-microvolt = <3000000>;
23024+ regulator-max-microvolt = <3000000>;
23025+ regulator-name = "vcc-3v";
23026+};
23027+
23028+&reg_dcdc2 {
23029+ regulator-always-on;
23030+ regulator-min-microvolt = <1040000>;
23031+ regulator-max-microvolt = <1300000>;
23032+ regulator-name = "vdd-cpux";
23033+};
23034+
23035+/* DCDC3 is polyphased with DCDC2 */
23036+
23037+&reg_dcdc5 {
23038+ regulator-always-on;
23039+ regulator-min-microvolt = <1500000>;
23040+ regulator-max-microvolt = <1500000>;
23041+ regulator-name = "vcc-dram";
23042+};
23043+
23044+&reg_dcdc6 {
23045+ regulator-always-on;
23046+ regulator-min-microvolt = <1100000>;
23047+ regulator-max-microvolt = <1100000>;
23048+ regulator-name = "vdd-sys";
23049+};
23050+
23051+&reg_dldo1 {
23052+ regulator-always-on;
23053+ regulator-min-microvolt = <3300000>;
23054+ regulator-max-microvolt = <3300000>;
23055+ regulator-name = "vcc-hdmi-dsi";
23056+};
23057+
23058+&reg_dldo4 {
23059+ regulator-always-on;
23060+ regulator-min-microvolt = <3000000>;
23061+ regulator-max-microvolt = <3000000>;
23062+ regulator-name = "vcc-pg-wifi-io";
23063+};
23064+
23065+&reg_eldo1 {
23066+ regulator-min-microvolt = <1800000>;
23067+ regulator-max-microvolt = <1800000>;
23068+ regulator-name = "cpvdd";
23069+};
23070+
23071+&reg_fldo1 {
23072+ regulator-min-microvolt = <1200000>;
23073+ regulator-max-microvolt = <1200000>;
23074+ regulator-name = "vcc-1v2-hsic";
23075+};
23076+
23077+/*
23078+ * The A64 chip cannot work without this regulator off, although
23079+ * it seems to be only driving the AR100 core.
23080+ * Maybe we don't still know well about CPUs domain.
23081+ */
23082+&reg_fldo2 {
23083+ regulator-always-on;
23084+ regulator-min-microvolt = <1100000>;
23085+ regulator-max-microvolt = <1100000>;
23086+ regulator-name = "vdd-cpus";
23087+};
23088+
23089+&reg_rtc_ldo {
23090+ regulator-name = "vcc-rtc";
23091+};
23092+
23093+&uart0 {
23094+ pinctrl-names = "default";
23095+ pinctrl-0 = <&uart0_pins_a>;
23096+ status = "okay";
23097+};
23098+
23099+&usbphy {
23100+ status = "okay";
23101+};
23102diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
23103new file mode 100644
23104index 000000000000..338e786155b1
23105--- /dev/null
23106+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
23107@@ -0,0 +1,199 @@
23108+/*
23109+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
23110+ *
23111+ * This file is dual-licensed: you can use it either under the terms
23112+ * of the GPL or the X11 license, at your option. Note that this dual
23113+ * licensing only applies to this file, and not this project as a
23114+ * whole.
23115+ *
23116+ * a) This library is free software; you can redistribute it and/or
23117+ * modify it under the terms of the GNU General Public License as
23118+ * published by the Free Software Foundation; either version 2 of the
23119+ * License, or (at your option) any later version.
23120+ *
23121+ * This library is distributed in the hope that it will be useful,
23122+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
23123+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23124+ * GNU General Public License for more details.
23125+ *
23126+ * Or, alternatively,
23127+ *
23128+ * b) Permission is hereby granted, free of charge, to any person
23129+ * obtaining a copy of this software and associated documentation
23130+ * files (the "Software"), to deal in the Software without
23131+ * restriction, including without limitation the rights to use,
23132+ * copy, modify, merge, publish, distribute, sublicense, and/or
23133+ * sell copies of the Software, and to permit persons to whom the
23134+ * Software is furnished to do so, subject to the following
23135+ * conditions:
23136+ *
23137+ * The above copyright notice and this permission notice shall be
23138+ * included in all copies or substantial portions of the Software.
23139+ *
23140+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23141+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
23142+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
23143+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
23144+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23145+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23146+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23147+ * OTHER DEALINGS IN THE SOFTWARE.
23148+ */
23149+
23150+/dts-v1/;
23151+
23152+#include "sun50i-a64.dtsi"
23153+
23154+#include <dt-bindings/gpio/gpio.h>
23155+
23156+/ {
23157+ model = "Olimex A64-Olinuxino";
23158+ compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64";
23159+
23160+ aliases {
23161+ serial0 = &uart0;
23162+ };
23163+
23164+ chosen {
23165+ stdout-path = "serial0:115200n8";
23166+ };
23167+};
23168+
23169+&mmc0 {
23170+ pinctrl-names = "default";
23171+ pinctrl-0 = <&mmc0_pins>;
23172+ vmmc-supply = <&reg_dcdc1>;
23173+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
23174+ cd-inverted;
23175+ disable-wp;
23176+ bus-width = <4>;
23177+ status = "okay";
23178+};
23179+
23180+&r_rsb {
23181+ status = "okay";
23182+
23183+ axp803: pmic@3a3 {
23184+ compatible = "x-powers,axp803";
23185+ reg = <0x3a3>;
23186+ interrupt-parent = <&r_intc>;
23187+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
23188+ };
23189+};
23190+
23191+#include "axp803.dtsi"
23192+
23193+&reg_aldo1 {
23194+ regulator-always-on;
23195+ regulator-min-microvolt = <2800000>;
23196+ regulator-max-microvolt = <2800000>;
23197+ regulator-name = "vcc-pe";
23198+};
23199+
23200+&reg_aldo2 {
23201+ regulator-always-on;
23202+ regulator-min-microvolt = <3300000>;
23203+ regulator-max-microvolt = <3300000>;
23204+ regulator-name = "vcc-pl";
23205+};
23206+
23207+&reg_aldo3 {
23208+ regulator-always-on;
23209+ regulator-min-microvolt = <3000000>;
23210+ regulator-max-microvolt = <3000000>;
23211+ regulator-name = "vcc-pll-avcc";
23212+};
23213+
23214+&reg_dcdc1 {
23215+ regulator-always-on;
23216+ regulator-min-microvolt = <3300000>;
23217+ regulator-max-microvolt = <3300000>;
23218+ regulator-name = "vcc-3v3";
23219+};
23220+
23221+&reg_dcdc2 {
23222+ regulator-always-on;
23223+ regulator-min-microvolt = <1040000>;
23224+ regulator-max-microvolt = <1300000>;
23225+ regulator-name = "vdd-cpux";
23226+};
23227+
23228+/* DCDC3 is polyphased with DCDC2 */
23229+
23230+&reg_dcdc5 {
23231+ regulator-always-on;
23232+ regulator-min-microvolt = <1500000>;
23233+ regulator-max-microvolt = <1500000>;
23234+ regulator-name = "vcc-ddr3";
23235+};
23236+
23237+&reg_dcdc6 {
23238+ regulator-always-on;
23239+ regulator-min-microvolt = <1100000>;
23240+ regulator-max-microvolt = <1100000>;
23241+ regulator-name = "vdd-sys";
23242+};
23243+
23244+&reg_dldo1 {
23245+ regulator-min-microvolt = <3300000>;
23246+ regulator-max-microvolt = <3300000>;
23247+ regulator-name = "vcc-hdmi";
23248+};
23249+
23250+&reg_dldo2 {
23251+ regulator-min-microvolt = <3300000>;
23252+ regulator-max-microvolt = <3300000>;
23253+ regulator-name = "vcc-mipi";
23254+};
23255+
23256+&reg_dldo3 {
23257+ regulator-min-microvolt = <2800000>;
23258+ regulator-max-microvolt = <2800000>;
23259+ regulator-name = "vcc-avdd-csi";
23260+};
23261+
23262+&reg_dldo4 {
23263+ regulator-min-microvolt = <3300000>;
23264+ regulator-max-microvolt = <3300000>;
23265+ regulator-name = "vcc-wifi-io";
23266+};
23267+
23268+&reg_eldo1 {
23269+ regulator-min-microvolt = <1800000>;
23270+ regulator-max-microvolt = <1800000>;
23271+ regulator-name = "cpvdd";
23272+};
23273+
23274+&reg_eldo2 {
23275+ regulator-min-microvolt = <1800000>;
23276+ regulator-max-microvolt = <1800000>;
23277+ regulator-name = "vcc-dvdd-csi";
23278+};
23279+
23280+&reg_fldo1 {
23281+ regulator-min-microvolt = <1200000>;
23282+ regulator-max-microvolt = <1200000>;
23283+ regulator-name = "vcc-1v2-hsic";
23284+};
23285+
23286+/*
23287+ * The A64 chip cannot work without this regulator off, although
23288+ * it seems to be only driving the AR100 core.
23289+ * Maybe we don't still know well about CPUs domain.
23290+ */
23291+&reg_fldo2 {
23292+ regulator-always-on;
23293+ regulator-min-microvolt = <1100000>;
23294+ regulator-max-microvolt = <1100000>;
23295+ regulator-name = "vdd-cpus";
23296+};
23297+
23298+&reg_rtc_ldo {
23299+ regulator-name = "vcc-rtc";
23300+};
23301+
23302+&uart0 {
23303+ pinctrl-names = "default";
23304+ pinctrl-0 = <&uart0_pins_a>;
23305+ status = "okay";
23306+};
23307diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
23308index 7c533b6d4ba9..caf8b6fbe5e3 100644
23309--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
23310+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
23311@@ -107,6 +107,118 @@ &ohci1 {
23312 status = "okay";
23313 };
23314
23315+&r_rsb {
23316+ status = "okay";
23317+
23318+ axp803: pmic@3a3 {
23319+ compatible = "x-powers,axp803";
23320+ reg = <0x3a3>;
23321+ interrupt-parent = <&r_intc>;
23322+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
23323+ };
23324+};
23325+
23326+#include "axp803.dtsi"
23327+
23328+&reg_aldo2 {
23329+ regulator-always-on;
23330+ regulator-min-microvolt = <1800000>;
23331+ regulator-max-microvolt = <3300000>;
23332+ regulator-name = "vcc-pl";
23333+};
23334+
23335+&reg_aldo3 {
23336+ regulator-always-on;
23337+ regulator-min-microvolt = <3000000>;
23338+ regulator-max-microvolt = <3000000>;
23339+ regulator-name = "vcc-pll-avcc";
23340+};
23341+
23342+&reg_dc1sw {
23343+ regulator-name = "vcc-phy";
23344+};
23345+
23346+&reg_dcdc1 {
23347+ regulator-always-on;
23348+ regulator-min-microvolt = <3300000>;
23349+ regulator-max-microvolt = <3300000>;
23350+ regulator-name = "vcc-3v3";
23351+};
23352+
23353+&reg_dcdc2 {
23354+ regulator-always-on;
23355+ regulator-min-microvolt = <1040000>;
23356+ regulator-max-microvolt = <1300000>;
23357+ regulator-name = "vdd-cpux";
23358+};
23359+
23360+/* DCDC3 is polyphased with DCDC2 */
23361+
23362+/*
23363+ * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can
23364+ * work at 1.35V with less power consumption.
23365+ * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead.
23366+ */
23367+&reg_dcdc5 {
23368+ regulator-always-on;
23369+ regulator-min-microvolt = <1360000>;
23370+ regulator-max-microvolt = <1360000>;
23371+ regulator-name = "vcc-dram";
23372+};
23373+
23374+&reg_dcdc6 {
23375+ regulator-always-on;
23376+ regulator-min-microvolt = <1100000>;
23377+ regulator-max-microvolt = <1100000>;
23378+ regulator-name = "vdd-sys";
23379+};
23380+
23381+&reg_dldo1 {
23382+ regulator-min-microvolt = <3300000>;
23383+ regulator-max-microvolt = <3300000>;
23384+ regulator-name = "vcc-hdmi";
23385+};
23386+
23387+&reg_dldo2 {
23388+ regulator-min-microvolt = <3300000>;
23389+ regulator-max-microvolt = <3300000>;
23390+ regulator-name = "vcc-mipi";
23391+};
23392+
23393+&reg_dldo4 {
23394+ regulator-min-microvolt = <3300000>;
23395+ regulator-max-microvolt = <3300000>;
23396+ regulator-name = "vcc-wifi";
23397+};
23398+
23399+&reg_eldo1 {
23400+ regulator-min-microvolt = <1800000>;
23401+ regulator-max-microvolt = <1800000>;
23402+ regulator-name = "cpvdd";
23403+};
23404+
23405+&reg_fldo1 {
23406+ regulator-min-microvolt = <1200000>;
23407+ regulator-max-microvolt = <1200000>;
23408+ regulator-name = "vcc-1v2-hsic";
23409+};
23410+
23411+/*
23412+ * The A64 chip cannot work without this regulator off, although
23413+ * it seems to be only driving the AR100 core.
23414+ * Maybe we don't still know well about CPUs domain.
23415+ */
23416+&reg_fldo2 {
23417+ regulator-always-on;
23418+ regulator-min-microvolt = <1100000>;
23419+ regulator-max-microvolt = <1100000>;
23420+ regulator-name = "vdd-cpus";
23421+};
23422+
23423+&reg_rtc_ldo {
23424+ regulator-name = "vcc-rtc";
23425+};
23426+
23427 /* On Exp and Euler connectors */
23428 &uart0 {
23429 pinctrl-names = "default";
23430diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
23431index d891a1a27f6c..17ccc12b58df 100644
23432--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
23433+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
23434@@ -95,6 +95,28 @@ &ohci1 {
23435 status = "okay";
23436 };
23437
23438+&reg_dc1sw {
23439+ regulator-name = "vcc-phy";
23440+};
23441+
23442+&reg_dldo1 {
23443+ regulator-min-microvolt = <3300000>;
23444+ regulator-max-microvolt = <3300000>;
23445+ regulator-name = "vcc-hdmi";
23446+};
23447+
23448+&reg_dldo2 {
23449+ regulator-min-microvolt = <3300000>;
23450+ regulator-max-microvolt = <3300000>;
23451+ regulator-name = "vcc-mipi";
23452+};
23453+
23454+&reg_dldo4 {
23455+ regulator-min-microvolt = <3300000>;
23456+ regulator-max-microvolt = <3300000>;
23457+ regulator-name = "vcc-wifi";
23458+};
23459+
23460 &uart0 {
23461 pinctrl-names = "default";
23462 pinctrl-0 = <&uart0_pins_a>;
23463diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
23464index 475518b031dd..a5da18a6f286 100644
23465--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
23466+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
23467@@ -63,3 +63,89 @@ &mmc0 {
23468 bus-width = <4>;
23469 status = "okay";
23470 };
23471+
23472+&r_rsb {
23473+ status = "okay";
23474+
23475+ axp803: pmic@3a3 {
23476+ compatible = "x-powers,axp803";
23477+ reg = <0x3a3>;
23478+ interrupt-parent = <&r_intc>;
23479+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
23480+ };
23481+};
23482+
23483+#include "axp803.dtsi"
23484+
23485+&reg_aldo2 {
23486+ regulator-always-on;
23487+ regulator-min-microvolt = <1800000>;
23488+ regulator-max-microvolt = <3300000>;
23489+ regulator-name = "vcc-pl";
23490+};
23491+
23492+&reg_aldo3 {
23493+ regulator-always-on;
23494+ regulator-min-microvolt = <3000000>;
23495+ regulator-max-microvolt = <3000000>;
23496+ regulator-name = "vcc-pll-avcc";
23497+};
23498+
23499+&reg_dcdc1 {
23500+ regulator-always-on;
23501+ regulator-min-microvolt = <3300000>;
23502+ regulator-max-microvolt = <3300000>;
23503+ regulator-name = "vcc-3v3";
23504+};
23505+
23506+&reg_dcdc2 {
23507+ regulator-always-on;
23508+ regulator-min-microvolt = <1040000>;
23509+ regulator-max-microvolt = <1300000>;
23510+ regulator-name = "vdd-cpux";
23511+};
23512+
23513+/* DCDC3 is polyphased with DCDC2 */
23514+
23515+&reg_dcdc5 {
23516+ regulator-always-on;
23517+ regulator-min-microvolt = <1200000>;
23518+ regulator-max-microvolt = <1200000>;
23519+ regulator-name = "vcc-dram";
23520+};
23521+
23522+&reg_dcdc6 {
23523+ regulator-always-on;
23524+ regulator-min-microvolt = <1100000>;
23525+ regulator-max-microvolt = <1100000>;
23526+ regulator-name = "vdd-sys";
23527+};
23528+
23529+&reg_eldo1 {
23530+ regulator-always-on;
23531+ regulator-min-microvolt = <1800000>;
23532+ regulator-max-microvolt = <1800000>;
23533+ regulator-name = "vdd-1v8-lpddr";
23534+};
23535+
23536+&reg_fldo1 {
23537+ regulator-min-microvolt = <1200000>;
23538+ regulator-max-microvolt = <1200000>;
23539+ regulator-name = "vcc-1v2-hsic";
23540+};
23541+
23542+/*
23543+ * The A64 chip cannot work without this regulator off, although
23544+ * it seems to be only driving the AR100 core.
23545+ * Maybe we don't still know well about CPUs domain.
23546+ */
23547+&reg_fldo2 {
23548+ regulator-always-on;
23549+ regulator-min-microvolt = <1100000>;
23550+ regulator-max-microvolt = <1100000>;
23551+ regulator-name = "vdd-cpus";
23552+};
23553+
23554+&reg_rtc_ldo {
23555+ regulator-name = "vcc-rtc";
23556+};
23557diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
23558index 68aadc9b96dc..8c8db1b057df 100644
23559--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
23560+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
23561@@ -467,6 +467,15 @@ rtc: rtc@1f00000 {
23562 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
23563 };
23564
23565+ r_intc: interrupt-controller@1f00c00 {
23566+ compatible = "allwinner,sun50i-a64-r-intc",
23567+ "allwinner,sun6i-a31-r-intc";
23568+ interrupt-controller;
23569+ #interrupt-cells = <2>;
23570+ reg = <0x01f00c00 0x400>;
23571+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
23572+ };
23573+
23574 r_ccu: clock@1f01400 {
23575 compatible = "allwinner,sun50i-a64-r-ccu";
23576 reg = <0x01f01400 0x100>;
23577diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
23578index dc478d094c11..c89010e56488 100644
23579--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
23580+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
23581@@ -121,6 +121,13 @@ hdmi_connector_in: endpoint {
23582 };
23583 };
23584
23585+&cec_AO {
23586+ status = "okay";
23587+ pinctrl-0 = <&ao_cec_pins>;
23588+ pinctrl-names = "default";
23589+ hdmi-phandle = <&hdmi_tx>;
23590+};
23591+
23592 &cvbs_vdac_port {
23593 cvbs_vdac_out: endpoint {
23594 remote-endpoint = <&cvbs_connector_in>;
23595diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
23596index 738ed689ff69..f175db846286 100644
23597--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
23598+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
23599@@ -225,7 +225,7 @@ reset: reset-controller@4404 {
23600 };
23601
23602 uart_A: serial@84c0 {
23603- compatible = "amlogic,meson-uart";
23604+ compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
23605 reg = <0x0 0x84c0 0x0 0x14>;
23606 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
23607 clocks = <&xtal>;
23608@@ -233,7 +233,7 @@ uart_A: serial@84c0 {
23609 };
23610
23611 uart_B: serial@84dc {
23612- compatible = "amlogic,meson-uart";
23613+ compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
23614 reg = <0x0 0x84dc 0x0 0x14>;
23615 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
23616 clocks = <&xtal>;
23617@@ -279,7 +279,7 @@ pwm_ef: pwm@86c0 {
23618 };
23619
23620 uart_C: serial@8700 {
23621- compatible = "amlogic,meson-uart";
23622+ compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
23623 reg = <0x0 0x8700 0x0 0x14>;
23624 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
23625 clocks = <&xtal>;
23626@@ -367,26 +367,40 @@ aobus: aobus@c8100000 {
23627 #size-cells = <2>;
23628 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
23629
23630- clkc_AO: clock-controller@040 {
23631- compatible = "amlogic,gx-aoclkc", "amlogic,gxbb-aoclkc";
23632- reg = <0x0 0x00040 0x0 0x4>;
23633- #clock-cells = <1>;
23634- #reset-cells = <1>;
23635+ sysctrl_AO: sys-ctrl@0 {
23636+ compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
23637+ reg = <0x0 0x0 0x0 0x100>;
23638+
23639+ clkc_AO: clock-controller {
23640+ compatible = "amlogic,meson-gx-aoclkc";
23641+ #clock-cells = <1>;
23642+ #reset-cells = <1>;
23643+ };
23644+ };
23645+
23646+ cec_AO: cec@100 {
23647+ compatible = "amlogic,meson-gx-ao-cec";
23648+ reg = <0x0 0x00100 0x0 0x14>;
23649+ interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
23650+ };
23651+
23652+ sec_AO: ao-secure@140 {
23653+ compatible = "amlogic,meson-gx-ao-secure", "syscon";
23654+ reg = <0x0 0x140 0x0 0x140>;
23655+ amlogic,has-chip-id;
23656 };
23657
23658 uart_AO: serial@4c0 {
23659- compatible = "amlogic,meson-uart";
23660+ compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart";
23661 reg = <0x0 0x004c0 0x0 0x14>;
23662 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
23663- clocks = <&xtal>;
23664 status = "disabled";
23665 };
23666
23667 uart_AO_B: serial@4e0 {
23668- compatible = "amlogic,meson-uart";
23669+ compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart";
23670 reg = <0x0 0x004e0 0x0 0x14>;
23671 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
23672- clocks = <&xtal>;
23673 status = "disabled";
23674 };
23675
23676@@ -437,9 +451,9 @@ hiubus: hiubus@c883c000 {
23677 mailbox: mailbox@404 {
23678 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
23679 reg = <0 0x404 0 0x4c>;
23680- interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
23681- <0 209 IRQ_TYPE_EDGE_RISING>,
23682- <0 210 IRQ_TYPE_EDGE_RISING>;
23683+ interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
23684+ <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
23685+ <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
23686 #mbox-cells = <1>;
23687 };
23688 };
23689@@ -448,7 +462,7 @@ ethmac: ethernet@c9410000 {
23690 compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
23691 reg = <0x0 0xc9410000 0x0 0x10000
23692 0x0 0xc8834540 0x0 0x4>;
23693- interrupts = <0 8 1>;
23694+ interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
23695 interrupt-names = "macirq";
23696 status = "disabled";
23697 };
23698diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
23699index fa462831ccaf..9697a7a79464 100644
23700--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
23701+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
23702@@ -175,6 +175,64 @@ &ir {
23703 pinctrl-names = "default";
23704 };
23705
23706+&pinctrl_aobus {
23707+ gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In",
23708+ "VCCK En", "CON1 Header Pin31",
23709+ "I2S Header Pin6", "IR In", "I2S Header Pin7",
23710+ "I2S Header Pin3", "I2S Header Pin4",
23711+ "I2S Header Pin5", "HDMI CEC", "SYS LED";
23712+};
23713+
23714+&pinctrl_periphs {
23715+ gpio-line-names = /* Bank GPIOZ */
23716+ "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
23717+ "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2",
23718+ "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
23719+ "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
23720+ "Eth PHY nRESET", "Eth PHY Intc",
23721+ /* Bank GPIOH */
23722+ "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL",
23723+ "CON1 Header Pin33",
23724+ /* Bank BOOT */
23725+ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
23726+ "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
23727+ "eMMC Reset", "eMMC CMD",
23728+ "", "", "", "", "eMMC DS",
23729+ "", "",
23730+ /* Bank CARD */
23731+ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
23732+ "SDCard D3", "SDCard D2", "SDCard Det",
23733+ /* Bank GPIODV */
23734+ "", "", "", "", "", "", "", "", "", "", "", "", "",
23735+ "", "", "", "", "", "", "", "", "", "", "",
23736+ "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
23737+ "VDDEE Regulator", "VCCK Regulator",
23738+ /* Bank GPIOY */
23739+ "CON1 Header Pin7", "CON1 Header Pin11",
23740+ "CON1 Header Pin13", "CON1 Header Pin15",
23741+ "CON1 Header Pin18", "CON1 Header Pin19",
23742+ "CON1 Header Pin22", "CON1 Header Pin21",
23743+ "CON1 Header Pin24", "CON1 Header Pin23",
23744+ "CON1 Header Pin26", "CON1 Header Pin29",
23745+ "CON1 Header Pin32", "CON1 Header Pin8",
23746+ "CON1 Header Pin10", "CON1 Header Pin16",
23747+ "CON1 Header Pin12",
23748+ /* Bank GPIOX */
23749+ "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2",
23750+ "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
23751+ "WIFI Power Enable", "WIFI WAKE HOST",
23752+ "Bluetooth PCM DOUT", "Bluetooth PCM DIN",
23753+ "Bluetooth PCM SYNC", "Bluetooth PCM CLK",
23754+ "Bluetooth UART TX", "Bluetooth UART RX",
23755+ "Bluetooth UART CTS", "Bluetooth UART RTS",
23756+ "", "", "", "WIFI 32K", "Bluetooth Enable",
23757+ "Bluetooth WAKE HOST",
23758+ /* Bank GPIOCLK */
23759+ "", "CON1 Header Pin35", "", "",
23760+ /* GPIO_TEST_N */
23761+ "";
23762+};
23763+
23764 &pwm_ef {
23765 status = "okay";
23766 pinctrl-0 = <&pwm_e_pins>;
23767diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
23768index a1078b3e1c76..9c59c3c6d1b6 100644
23769--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
23770+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
23771@@ -171,6 +171,13 @@ cvbs_vdac_out: endpoint {
23772 };
23773 };
23774
23775+&cec_AO {
23776+ status = "okay";
23777+ pinctrl-0 = <&ao_cec_pins>;
23778+ pinctrl-names = "default";
23779+ hdmi-phandle = <&hdmi_tx>;
23780+};
23781+
23782 &ethmac {
23783 status = "okay";
23784 pinctrl-0 = <&eth_rmii_pins>;
23785diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
23786index d904deb1018c..81ffc689a5bf 100644
23787--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
23788+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
23789@@ -84,6 +84,9 @@ vddio_card: gpio-regulator {
23790 /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
23791 states = <1800000 0
23792 3300000 1>;
23793+
23794+ regulator-settling-time-up-us = <10000>;
23795+ regulator-settling-time-down-us = <150000>;
23796 };
23797
23798 vddio_boot: regulator-vddio_boot {
23799@@ -148,6 +151,13 @@ hdmi_connector_in: endpoint {
23800 };
23801 };
23802
23803+&cec_AO {
23804+ status = "okay";
23805+ pinctrl-0 = <&ao_cec_pins>;
23806+ pinctrl-names = "default";
23807+ hdmi-phandle = <&hdmi_tx>;
23808+};
23809+
23810 &cvbs_vdac_port {
23811 cvbs_vdac_out: endpoint {
23812 remote-endpoint = <&cvbs_connector_in>;
23813diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
23814index e76ac313fef9..f7144fd5e03f 100644
23815--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
23816+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
23817@@ -108,6 +108,12 @@ hdmi_connector_in: endpoint {
23818 };
23819 };
23820
23821+&cec_AO {
23822+ status = "okay";
23823+ pinctrl-0 = <&ao_cec_pins>;
23824+ pinctrl-names = "default";
23825+ hdmi-phandle = <&hdmi_tx>;
23826+};
23827
23828 &cvbs_vdac_port {
23829 cvbs_vdac_out: endpoint {
23830diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
23831index 17d3efdf1469..52f1687e7a09 100644
23832--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
23833+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
23834@@ -307,6 +307,15 @@ spifc: spi@8c80 {
23835 };
23836 };
23837
23838+&cec_AO {
23839+ clocks = <&clkc_AO CLKID_AO_CEC_32K>;
23840+ clock-names = "core";
23841+};
23842+
23843+&clkc_AO {
23844+ compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
23845+};
23846+
23847 &ethmac {
23848 clocks = <&clkc CLKID_ETH>,
23849 <&clkc CLKID_FCLK_DIV2>,
23850@@ -682,6 +691,31 @@ &spifc {
23851 clocks = <&clkc CLKID_SPI>;
23852 };
23853
23854+&uart_A {
23855+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
23856+ clock-names = "xtal", "pclk", "baud";
23857+};
23858+
23859+&uart_AO {
23860+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
23861+ clock-names = "xtal", "pclk", "baud";
23862+};
23863+
23864+&uart_AO_B {
23865+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
23866+ clock-names = "xtal", "pclk", "baud";
23867+};
23868+
23869+&uart_B {
23870+ clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
23871+ clock-names = "xtal", "core", "baud";
23872+};
23873+
23874+&uart_C {
23875+ clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
23876+ clock-names = "xtal", "core", "baud";
23877+};
23878+
23879 &vpu {
23880 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
23881 };
23882diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
23883index 3e0c023d6abd..6827f235d7cf 100644
23884--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
23885+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
23886@@ -97,6 +97,13 @@ hdmi_connector_in: endpoint {
23887 };
23888 };
23889
23890+&cec_AO {
23891+ status = "okay";
23892+ pinctrl-0 = <&ao_cec_pins>;
23893+ pinctrl-names = "default";
23894+ hdmi-phandle = <&hdmi_tx>;
23895+};
23896+
23897 /* P230 has exclusive choice between internal or external PHY */
23898 &ethmac {
23899 pinctrl-0 = <&eth_pins>;
23900@@ -124,7 +131,6 @@ external_phy: ethernet-phy@0 {
23901 };
23902 };
23903
23904-
23905 &hdmi_tx {
23906 status = "okay";
23907 pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
23908diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
23909index 94567eb17875..edc512ad0bac 100644
23910--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
23911+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
23912@@ -67,6 +67,13 @@ hdmi_connector_in: endpoint {
23913 };
23914 };
23915
23916+&cec_AO {
23917+ status = "okay";
23918+ pinctrl-0 = <&ao_cec_pins>;
23919+ pinctrl-names = "default";
23920+ hdmi-phandle = <&hdmi_tx>;
23921+};
23922+
23923 &hdmi_tx {
23924 status = "okay";
23925 pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
23926@@ -105,6 +112,62 @@ &ir {
23927 linux,rc-map-name = "rc-geekbox";
23928 };
23929
23930+&pinctrl_aobus {
23931+ gpio-line-names = "UART TX",
23932+ "UART RX",
23933+ "Power Key In",
23934+ "J9 Header Pin35",
23935+ "J9 Header Pin16",
23936+ "J9 Header Pin15",
23937+ "J9 Header Pin33",
23938+ "IR In",
23939+ "HDMI CEC",
23940+ "SYS LED";
23941+};
23942+
23943+&pinctrl_periphs {
23944+ gpio-line-names = /* Bank GPIOZ */
23945+ "", "", "", "", "", "", "",
23946+ "", "", "", "", "", "", "",
23947+ "Power OFF",
23948+ "VCCK Enable",
23949+ /* Bank GPIOH */
23950+ "HDMI HPD", "HDMI SDA", "HDMI SCL",
23951+ "HDMI_5V_EN", "SPDIF",
23952+ "J9 Header Pin37",
23953+ "J9 Header Pin30",
23954+ "J9 Header Pin29",
23955+ "J9 Header Pin32",
23956+ "J9 Header Pin31",
23957+ /* Bank BOOT */
23958+ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
23959+ "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
23960+ "eMMC Clk", "eMMC Reset", "eMMC CMD",
23961+ "", "BOOT_MODE", "", "", "eMMC Data Strobe",
23962+ /* Bank CARD */
23963+ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
23964+ "SDCard D3", "SDCard D2", "SDCard Det",
23965+ /* Bank GPIODV */
23966+ "", "", "", "", "", "", "", "", "", "", "", "",
23967+ "", "", "", "", "", "", "", "", "", "", "", "",
23968+ "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
23969+ "VCCK Regulator", "VDDEE Regulator",
23970+ /* Bank GPIOX */
23971+ "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2",
23972+ "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
23973+ "WIFI Power Enable", "WIFI WAKE HOST",
23974+ "Bluetooth PCM DOUT", "Bluetooth PCM DIN",
23975+ "Bluetooth PCM SYNC", "Bluetooth PCM CLK",
23976+ "Bluetooth UART TX", "Bluetooth UART RX",
23977+ "Bluetooth UART CTS", "Bluetooth UART RTS",
23978+ "WIFI 32K", "Bluetooth Enable",
23979+ "Bluetooth WAKE HOST",
23980+ /* Bank GPIOCLK */
23981+ "", "J9 Header Pin39",
23982+ /* GPIO_TEST_N */
23983+ "";
23984+};
23985+
23986 &pwm_AO_ab {
23987 status = "okay";
23988 pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
23989diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
23990index 266fbcf3e47f..69ca14ac10fa 100644
23991--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
23992+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
23993@@ -101,6 +101,13 @@ vddio_boot: regulator-vddio_boot {
23994 };
23995 };
23996
23997+&cec_AO {
23998+ status = "okay";
23999+ pinctrl-0 = <&ao_cec_pins>;
24000+ pinctrl-names = "default";
24001+ hdmi-phandle = <&hdmi_tx>;
24002+};
24003+
24004 &cvbs_vdac_port {
24005 cvbs_vdac_out: endpoint {
24006 remote-endpoint = <&cvbs_connector_in>;
24007@@ -129,6 +136,63 @@ hdmi_tx_tmds_out: endpoint {
24008 };
24009 };
24010
24011+&pinctrl_aobus {
24012+ gpio-line-names = "UART TX",
24013+ "UART RX",
24014+ "Blue LED",
24015+ "SDCard Voltage Switch",
24016+ "7J1 Header Pin5",
24017+ "7J1 Header Pin3",
24018+ "7J1 Header Pin12",
24019+ "IR In",
24020+ "9J3 Switch HDMI CEC/7J1 Header Pin11",
24021+ "7J1 Header Pin13";
24022+};
24023+
24024+&pinctrl_periphs {
24025+ gpio-line-names = /* Bank GPIOZ */
24026+ "", "", "", "", "", "", "",
24027+ "", "", "", "", "", "", "",
24028+ "Eth Link LED", "Eth Activity LED",
24029+ /* Bank GPIOH */
24030+ "HDMI HPD", "HDMI SDA", "HDMI SCL",
24031+ "HDMI_5V_EN", "9J1 Header Pin2",
24032+ "Analog Audio Mute",
24033+ "2J3 Header Pin6",
24034+ "2J3 Header Pin5",
24035+ "2J3 Header Pin4",
24036+ "2J3 Header Pin3",
24037+ /* Bank BOOT */
24038+ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
24039+ "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
24040+ "eMMC Clk", "eMMC Reset", "eMMC CMD",
24041+ "ALT BOOT MODE", "", "", "", "eMMC Data Strobe",
24042+ /* Bank CARD */
24043+ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
24044+ "SDCard D3", "SDCard D2", "SDCard Det",
24045+ /* Bank GPIODV */
24046+ "", "", "", "", "", "", "", "", "", "", "", "",
24047+ "", "", "", "", "", "", "", "", "", "", "", "",
24048+ "Green LED", "VCCK Enable",
24049+ "7J1 Header Pin27", "7J1 Header Pin28",
24050+ "VCCK Regulator", "VDDEE Regulator",
24051+ /* Bank GPIOX */
24052+ "7J1 Header Pin22", "7J1 Header Pin26",
24053+ "7J1 Header Pin36", "7J1 Header Pin38",
24054+ "7J1 Header Pin40", "7J1 Header Pin37",
24055+ "7J1 Header Pin33", "7J1 Header Pin35",
24056+ "7J1 Header Pin19", "7J1 Header Pin21",
24057+ "7J1 Header Pin24", "7J1 Header Pin23",
24058+ "7J1 Header Pin8", "7J1 Header Pin10",
24059+ "7J1 Header Pin16", "7J1 Header Pin18",
24060+ "7J1 Header Pin32", "7J1 Header Pin29",
24061+ "7J1 Header Pin31",
24062+ /* Bank GPIOCLK */
24063+ "7J1 Header Pin7", "",
24064+ /* GPIO_TEST_N */
24065+ "7J1 Header Pin15";
24066+};
24067+
24068 /* SD card */
24069 &sd_emmc_b {
24070 status = "okay";
24071diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
24072index 6633a5d8fdd3..4c2ac7650fcd 100644
24073--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
24074+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
24075@@ -140,6 +140,13 @@ hdmi_connector_in: endpoint {
24076 };
24077 };
24078
24079+&cec_AO {
24080+ status = "okay";
24081+ pinctrl-0 = <&ao_cec_pins>;
24082+ pinctrl-names = "default";
24083+ hdmi-phandle = <&hdmi_tx>;
24084+};
24085+
24086 &cvbs_vdac_port {
24087 cvbs_vdac_out: endpoint {
24088 remote-endpoint = <&cvbs_connector_in>;
24089diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
24090index 6ab17c1eeefd..6e2bf858291c 100644
24091--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
24092+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
24093@@ -71,6 +71,13 @@ hdmi_connector_in: endpoint {
24094 };
24095 };
24096
24097+&cec_AO {
24098+ status = "okay";
24099+ pinctrl-0 = <&ao_cec_pins>;
24100+ pinctrl-names = "default";
24101+ hdmi-phandle = <&hdmi_tx>;
24102+};
24103+
24104 &cvbs_vdac_port {
24105 cvbs_vdac_out: endpoint {
24106 remote-endpoint = <&cvbs_connector_in>;
24107diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
24108index 8d4f3160a0ee..d6876e64979e 100644
24109--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
24110+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
24111@@ -43,6 +43,7 @@
24112
24113 #include "meson-gx.dtsi"
24114 #include <dt-bindings/clock/gxbb-clkc.h>
24115+#include <dt-bindings/clock/gxbb-aoclkc.h>
24116 #include <dt-bindings/gpio/meson-gxl-gpio.h>
24117 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
24118
24119@@ -207,6 +208,15 @@ mux {
24120 };
24121 };
24122
24123+&cec_AO {
24124+ clocks = <&clkc_AO CLKID_AO_CEC_32K>;
24125+ clock-names = "core";
24126+};
24127+
24128+&clkc_AO {
24129+ compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
24130+};
24131+
24132 &hdmi_tx {
24133 compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
24134 resets = <&reset RESET_HDMITX_CAPB3>,
24135@@ -623,6 +633,31 @@ &spifc {
24136 clocks = <&clkc CLKID_SPI>;
24137 };
24138
24139+&uart_A {
24140+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
24141+ clock-names = "xtal", "core", "baud";
24142+};
24143+
24144+&uart_AO {
24145+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
24146+ clock-names = "xtal", "pclk", "baud";
24147+};
24148+
24149+&uart_AO_B {
24150+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
24151+ clock-names = "xtal", "pclk", "baud";
24152+};
24153+
24154+&uart_B {
24155+ clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
24156+ clock-names = "xtal", "core", "baud";
24157+};
24158+
24159+&uart_C {
24160+ clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
24161+ clock-names = "xtal", "core", "baud";
24162+};
24163+
24164 &vpu {
24165 compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
24166 };
24167diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
24168index 5f626d683088..9b10c5f4f8c0 100644
24169--- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
24170+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
24171@@ -113,6 +113,13 @@ hdmi_connector_in: endpoint {
24172 };
24173 };
24174
24175+&cec_AO {
24176+ status = "okay";
24177+ pinctrl-0 = <&ao_cec_pins>;
24178+ pinctrl-names = "default";
24179+ hdmi-phandle = <&hdmi_tx>;
24180+};
24181+
24182 &cvbs_vdac_port {
24183 cvbs_vdac_out: endpoint {
24184 remote-endpoint = <&cvbs_connector_in>;
24185diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
24186index fe451cce93e7..19a798d2ae2f 100644
24187--- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
24188+++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
24189@@ -117,6 +117,10 @@ cpu7: cpu@103 {
24190 };
24191 };
24192
24193+&clkc_AO {
24194+ compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
24195+};
24196+
24197 &saradc {
24198 compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
24199 };
24200diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
24201index 72720e9132a1..c9ffffb96e43 100644
24202--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
24203+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
24204@@ -626,6 +626,7 @@ pcie0: pcie@1f2b0000 {
24205 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
24206 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
24207 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
24208+ bus-range = <0x00 0xff>;
24209 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
24210 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
24211 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
24212@@ -651,6 +652,7 @@ pcie1: pcie@1f2c0000 {
24213 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
24214 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
24215 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
24216+ bus-range = <0x00 0xff>;
24217 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
24218 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
24219 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
24220diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
24221index 63be8e51eaa8..c09a36fed917 100644
24222--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
24223+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
24224@@ -626,6 +626,7 @@ pcie0: pcie@1f2b0000 {
24225 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
24226 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
24227 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
24228+ bus-range = <0x00 0xff>;
24229 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
24230 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
24231 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
24232@@ -651,6 +652,7 @@ pcie1: pcie@1f2c0000 {
24233 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
24234 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
24235 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
24236+ bus-range = <0x00 0xff>;
24237 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
24238 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
24239 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
24240@@ -676,6 +678,7 @@ pcie2: pcie@1f2d0000 {
24241 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
24242 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
24243 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
24244+ bus-range = <0x00 0xff>;
24245 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
24246 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
24247 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
24248@@ -701,6 +704,7 @@ pcie3: pcie@1f500000 {
24249 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
24250 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
24251 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
24252+ bus-range = <0x00 0xff>;
24253 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
24254 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
24255 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
24256@@ -726,6 +730,7 @@ pcie4: pcie@1f510000 {
24257 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
24258 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
24259 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
24260+ bus-range = <0x00 0xff>;
24261 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
24262 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
24263 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
24264diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
24265index 7cfa8e414e7f..8ecdd4331980 100644
24266--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi
24267+++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
24268@@ -226,7 +226,7 @@ v2m_serial3: uart@0c0000 {
24269 clock-names = "uartclk", "apb_pclk";
24270 };
24271
24272- virtio_block@0130000 {
24273+ virtio-block@0130000 {
24274 compatible = "virtio,mmio";
24275 reg = <0x130000 0x200>;
24276 interrupts = <42>;
24277diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
24278index e8b7413ec890..fbafe62d6b22 100644
24279--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
24280+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
24281@@ -201,7 +201,7 @@ stm_out_port: endpoint {
24282 };
24283 };
24284
24285- cpu_debug0: cpu_debug@22010000 {
24286+ cpu_debug0: cpu-debug@22010000 {
24287 compatible = "arm,coresight-cpu-debug", "arm,primecell";
24288 reg = <0x0 0x22010000 0x0 0x1000>;
24289
24290@@ -260,7 +260,7 @@ cluster0_funnel_in_port1: endpoint {
24291 };
24292 };
24293
24294- cpu_debug1: cpu_debug@22110000 {
24295+ cpu_debug1: cpu-debug@22110000 {
24296 compatible = "arm,coresight-cpu-debug", "arm,primecell";
24297 reg = <0x0 0x22110000 0x0 0x1000>;
24298
24299@@ -283,7 +283,7 @@ cluster0_etm1_out_port: endpoint {
24300 };
24301 };
24302
24303- cpu_debug2: cpu_debug@23010000 {
24304+ cpu_debug2: cpu-debug@23010000 {
24305 compatible = "arm,coresight-cpu-debug", "arm,primecell";
24306 reg = <0x0 0x23010000 0x0 0x1000>;
24307
24308@@ -356,7 +356,7 @@ cluster1_funnel_in_port3: endpoint {
24309 };
24310 };
24311
24312- cpu_debug3: cpu_debug@23110000 {
24313+ cpu_debug3: cpu-debug@23110000 {
24314 compatible = "arm,coresight-cpu-debug", "arm,primecell";
24315 reg = <0x0 0x23110000 0x0 0x1000>;
24316
24317@@ -379,7 +379,7 @@ cluster1_etm1_out_port: endpoint {
24318 };
24319 };
24320
24321- cpu_debug4: cpu_debug@23210000 {
24322+ cpu_debug4: cpu-debug@23210000 {
24323 compatible = "arm,coresight-cpu-debug", "arm,primecell";
24324 reg = <0x0 0x23210000 0x0 0x1000>;
24325
24326@@ -402,7 +402,7 @@ cluster1_etm2_out_port: endpoint {
24327 };
24328 };
24329
24330- cpu_debug5: cpu_debug@23310000 {
24331+ cpu_debug5: cpu-debug@23310000 {
24332 compatible = "arm,coresight-cpu-debug", "arm,primecell";
24333 reg = <0x0 0x23310000 0x0 0x1000>;
24334
24335@@ -426,7 +426,7 @@ cluster1_etm3_out_port: endpoint {
24336 };
24337
24338 replicator@20120000 {
24339- compatible = "qcom,coresight-replicator1x", "arm,primecell";
24340+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
24341 reg = <0 0x20120000 0 0x1000>;
24342
24343 clocks = <&soc_smc50mhz>;
24344diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
24345index 161ac98418a3..528875c75598 100644
24346--- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
24347+++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
24348@@ -219,7 +219,7 @@ panel-timing {
24349 };
24350 };
24351
24352- virtio_block@0130000 {
24353+ virtio-block@0130000 {
24354 compatible = "virtio,mmio";
24355 reg = <0x130000 0x200>;
24356 interrupts = <42>;
24357diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile
24358index f11bdd6689ea..3eaef3895d66 100644
24359--- a/arch/arm64/boot/dts/broadcom/Makefile
24360+++ b/arch/arm64/boot/dts/broadcom/Makefile
24361@@ -1,7 +1,7 @@
24362 dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb
24363-dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb
24364
24365-dts-dirs := stingray
24366+dts-dirs += northstar2
24367+dts-dirs += stingray
24368 always := $(dtb-y)
24369 subdir-y := $(dts-dirs)
24370 clean-files := *.dtb
24371diff --git a/arch/arm64/boot/dts/broadcom/bcm2835-rpi.dtsi b/arch/arm64/boot/dts/broadcom/bcm2835-rpi.dtsi
24372deleted file mode 120000
24373index 3937b77cb310..000000000000
24374--- a/arch/arm64/boot/dts/broadcom/bcm2835-rpi.dtsi
24375+++ /dev/null
24376@@ -1 +0,0 @@
24377-../../../../arm/boot/dts/bcm2835-rpi.dtsi
24378\ No newline at end of file
24379diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
24380index 972f14db28ac..699d340a3437 100644
24381--- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
24382+++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
24383@@ -1,41 +1 @@
24384-/dts-v1/;
24385-#include "bcm2837.dtsi"
24386-#include "bcm2835-rpi.dtsi"
24387-#include "bcm283x-rpi-smsc9514.dtsi"
24388-#include "bcm283x-rpi-usb-host.dtsi"
24389-
24390-/ {
24391- compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
24392- model = "Raspberry Pi 3 Model B";
24393-
24394- memory {
24395- reg = <0 0x40000000>;
24396- };
24397-
24398- leds {
24399- act {
24400- gpios = <&gpio 47 0>;
24401- };
24402- };
24403-};
24404-
24405-&uart1 {
24406- status = "okay";
24407-};
24408-
24409-/* SDHCI is used to control the SDIO for wireless */
24410-&sdhci {
24411- pinctrl-names = "default";
24412- pinctrl-0 = <&emmc_gpio34>;
24413- status = "okay";
24414- bus-width = <4>;
24415- non-removable;
24416-};
24417-
24418-/* SDHOST is used to drive the SD card */
24419-&sdhost {
24420- pinctrl-names = "default";
24421- pinctrl-0 = <&sdhost_gpio48>;
24422- status = "okay";
24423- bus-width = <4>;
24424-};
24425+#include "arm/bcm2837-rpi-3-b.dts"
24426diff --git a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
24427deleted file mode 100644
24428index 2d5de6f0f78d..000000000000
24429--- a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
24430+++ /dev/null
24431@@ -1,86 +0,0 @@
24432-#include "bcm283x.dtsi"
24433-
24434-/ {
24435- compatible = "brcm,bcm2837";
24436-
24437- soc {
24438- ranges = <0x7e000000 0x3f000000 0x1000000>,
24439- <0x40000000 0x40000000 0x00001000>;
24440- dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
24441-
24442- local_intc: local_intc {
24443- compatible = "brcm,bcm2836-l1-intc";
24444- reg = <0x40000000 0x100>;
24445- interrupt-controller;
24446- #interrupt-cells = <1>;
24447- interrupt-parent = <&local_intc>;
24448- };
24449- };
24450-
24451- timer {
24452- compatible = "arm,armv7-timer";
24453- interrupt-parent = <&local_intc>;
24454- interrupts = <0>, // PHYS_SECURE_PPI
24455- <1>, // PHYS_NONSECURE_PPI
24456- <3>, // VIRT_PPI
24457- <2>; // HYP_PPI
24458- always-on;
24459- };
24460-
24461- cpus: cpus {
24462- #address-cells = <1>;
24463- #size-cells = <0>;
24464-
24465- cpu0: cpu@0 {
24466- device_type = "cpu";
24467- compatible = "arm,cortex-a53";
24468- reg = <0>;
24469- enable-method = "spin-table";
24470- cpu-release-addr = <0x0 0x000000d8>;
24471- };
24472-
24473- cpu1: cpu@1 {
24474- device_type = "cpu";
24475- compatible = "arm,cortex-a53";
24476- reg = <1>;
24477- enable-method = "spin-table";
24478- cpu-release-addr = <0x0 0x000000e0>;
24479- };
24480-
24481- cpu2: cpu@2 {
24482- device_type = "cpu";
24483- compatible = "arm,cortex-a53";
24484- reg = <2>;
24485- enable-method = "spin-table";
24486- cpu-release-addr = <0x0 0x000000e8>;
24487- };
24488-
24489- cpu3: cpu@3 {
24490- device_type = "cpu";
24491- compatible = "arm,cortex-a53";
24492- reg = <3>;
24493- enable-method = "spin-table";
24494- cpu-release-addr = <0x0 0x000000f0>;
24495- };
24496- };
24497-};
24498-
24499-/* Make the BCM2835-style global interrupt controller be a child of the
24500- * CPU-local interrupt controller.
24501- */
24502-&intc {
24503- compatible = "brcm,bcm2836-armctrl-ic";
24504- reg = <0x7e00b200 0x200>;
24505- interrupt-parent = <&local_intc>;
24506- interrupts = <8>;
24507-};
24508-
24509-&cpu_thermal {
24510- coefficients = <(-538) 412000>;
24511-};
24512-
24513-/* enable thermal sensor with the correct compatible property set */
24514-&thermal {
24515- compatible = "brcm,bcm2837-thermal";
24516- status = "okay";
24517-};
24518diff --git a/arch/arm64/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi
24519deleted file mode 120000
24520index dca7c057d5a5..000000000000
24521--- a/arch/arm64/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi
24522+++ /dev/null
24523@@ -1 +0,0 @@
24524-../../../../arm/boot/dts/bcm283x-rpi-smsc9514.dtsi
24525\ No newline at end of file
24526diff --git a/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi
24527deleted file mode 120000
24528index cbeebe312ff8..000000000000
24529--- a/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi
24530+++ /dev/null
24531@@ -1 +0,0 @@
24532-../../../../arm/boot/dts/bcm283x-rpi-usb-host.dtsi
24533\ No newline at end of file
24534diff --git a/arch/arm64/boot/dts/broadcom/bcm283x.dtsi b/arch/arm64/boot/dts/broadcom/bcm283x.dtsi
24535deleted file mode 120000
24536index 5f54e4cab99b..000000000000
24537--- a/arch/arm64/boot/dts/broadcom/bcm283x.dtsi
24538+++ /dev/null
24539@@ -1 +0,0 @@
24540-../../../../arm/boot/dts/bcm283x.dtsi
24541\ No newline at end of file
24542diff --git a/arch/arm64/boot/dts/broadcom/northstar2/Makefile b/arch/arm64/boot/dts/broadcom/northstar2/Makefile
24543new file mode 100644
24544index 000000000000..e01a1485b813
24545--- /dev/null
24546+++ b/arch/arm64/boot/dts/broadcom/northstar2/Makefile
24547@@ -0,0 +1,6 @@
24548+dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb
24549+dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-xmc.dtb
24550+
24551+always := $(dtb-y)
24552+subdir-y := $(dts-dirs)
24553+clean-files := *.dtb
24554diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi
24555new file mode 100644
24556index 000000000000..99009fdf10a4
24557--- /dev/null
24558+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi
24559@@ -0,0 +1,105 @@
24560+/*
24561+ * BSD LICENSE
24562+ *
24563+ * Copyright (c) 2016 Broadcom. All rights reserved.
24564+ *
24565+ * Redistribution and use in source and binary forms, with or without
24566+ * modification, are permitted provided that the following conditions
24567+ * are met:
24568+ *
24569+ * * Redistributions of source code must retain the above copyright
24570+ * notice, this list of conditions and the following disclaimer.
24571+ * * Redistributions in binary form must reproduce the above copyright
24572+ * notice, this list of conditions and the following disclaimer in
24573+ * the documentation and/or other materials provided with the
24574+ * distribution.
24575+ * * Neither the name of Broadcom Corporation nor the names of its
24576+ * contributors may be used to endorse or promote products derived
24577+ * from this software without specific prior written permission.
24578+ *
24579+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24580+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24581+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24582+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24583+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24584+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24585+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24586+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24587+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24588+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24589+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24590+ */
24591+
24592+#include <dt-bindings/clock/bcm-ns2.h>
24593+
24594+ osc: oscillator {
24595+ #clock-cells = <0>;
24596+ compatible = "fixed-clock";
24597+ clock-frequency = <25000000>;
24598+ };
24599+
24600+ lcpll_ddr: lcpll_ddr@6501d058 {
24601+ #clock-cells = <1>;
24602+ compatible = "brcm,ns2-lcpll-ddr";
24603+ reg = <0x6501d058 0x20>,
24604+ <0x6501c020 0x4>,
24605+ <0x6501d04c 0x4>;
24606+ clocks = <&osc>;
24607+ clock-output-names = "lcpll_ddr", "pcie_sata_usb",
24608+ "ddr", "ddr_ch2_unused",
24609+ "ddr_ch3_unused", "ddr_ch4_unused",
24610+ "ddr_ch5_unused";
24611+ };
24612+
24613+ lcpll_ports: lcpll_ports@6501d078 {
24614+ #clock-cells = <1>;
24615+ compatible = "brcm,ns2-lcpll-ports";
24616+ reg = <0x6501d078 0x20>,
24617+ <0x6501c020 0x4>,
24618+ <0x6501d054 0x4>;
24619+ clocks = <&osc>;
24620+ clock-output-names = "lcpll_ports", "wan", "rgmii",
24621+ "ports_ch2_unused",
24622+ "ports_ch3_unused",
24623+ "ports_ch4_unused",
24624+ "ports_ch5_unused";
24625+ };
24626+
24627+ genpll_scr: genpll_scr@6501d098 {
24628+ #clock-cells = <1>;
24629+ compatible = "brcm,ns2-genpll-scr";
24630+ reg = <0x6501d098 0x32>,
24631+ <0x6501c020 0x4>,
24632+ <0x6501d044 0x4>;
24633+ clocks = <&osc>;
24634+ clock-output-names = "genpll_scr", "scr", "fs",
24635+ "audio_ref", "scr_ch3_unused",
24636+ "scr_ch4_unused", "scr_ch5_unused";
24637+ };
24638+
24639+ iprocmed: iprocmed {
24640+ #clock-cells = <0>;
24641+ compatible = "fixed-factor-clock";
24642+ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
24643+ clock-div = <2>;
24644+ clock-mult = <1>;
24645+ };
24646+
24647+ iprocslow: iprocslow {
24648+ #clock-cells = <0>;
24649+ compatible = "fixed-factor-clock";
24650+ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
24651+ clock-div = <4>;
24652+ clock-mult = <1>;
24653+ };
24654+
24655+ genpll_sw: genpll_sw@6501d0c4 {
24656+ #clock-cells = <1>;
24657+ compatible = "brcm,ns2-genpll-sw";
24658+ reg = <0x6501d0c4 0x32>,
24659+ <0x6501c020 0x4>,
24660+ <0x6501d044 0x4>;
24661+ clocks = <&osc>;
24662+ clock-output-names = "genpll_sw", "rpe", "250", "nic",
24663+ "chimp", "port", "sdio";
24664+ };
24665diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts
24666new file mode 100644
24667index 000000000000..ec19fbf928a1
24668--- /dev/null
24669+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts
24670@@ -0,0 +1,236 @@
24671+/*
24672+ * BSD LICENSE
24673+ *
24674+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
24675+ *
24676+ * Redistribution and use in source and binary forms, with or without
24677+ * modification, are permitted provided that the following conditions
24678+ * are met:
24679+ *
24680+ * * Redistributions of source code must retain the above copyright
24681+ * notice, this list of conditions and the following disclaimer.
24682+ * * Redistributions in binary form must reproduce the above copyright
24683+ * notice, this list of conditions and the following disclaimer in
24684+ * the documentation and/or other materials provided with the
24685+ * distribution.
24686+ * * Neither the name of Broadcom Corporation nor the names of its
24687+ * contributors may be used to endorse or promote products derived
24688+ * from this software without specific prior written permission.
24689+ *
24690+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24691+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24692+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24693+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24694+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24695+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24696+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24697+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24698+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24699+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24700+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24701+ */
24702+
24703+/dts-v1/;
24704+
24705+#include "ns2.dtsi"
24706+
24707+/ {
24708+ model = "Broadcom NS2 SVK";
24709+ compatible = "brcm,ns2-svk", "brcm,ns2";
24710+
24711+ aliases {
24712+ serial0 = &uart3;
24713+ serial1 = &uart0;
24714+ serial2 = &uart1;
24715+ serial3 = &uart2;
24716+ };
24717+
24718+ chosen {
24719+ stdout-path = "serial0:115200n8";
24720+ bootargs = "earlycon=uart8250,mmio32,0x66130000";
24721+ };
24722+
24723+ memory {
24724+ device_type = "memory";
24725+ reg = <0x000000000 0x80000000 0x00000000 0x40000000>;
24726+ };
24727+};
24728+
24729+&enet {
24730+ status = "okay";
24731+};
24732+
24733+&pci_phy0 {
24734+ status = "okay";
24735+};
24736+
24737+&pci_phy1 {
24738+ status = "okay";
24739+};
24740+
24741+&pcie0 {
24742+ status = "okay";
24743+};
24744+
24745+&pcie4 {
24746+ status = "okay";
24747+};
24748+
24749+&pcie8 {
24750+ status = "okay";
24751+};
24752+
24753+&i2c0 {
24754+ status = "okay";
24755+};
24756+
24757+&i2c1 {
24758+ status = "okay";
24759+};
24760+
24761+&uart0 {
24762+ status = "okay";
24763+};
24764+
24765+&uart1 {
24766+ status = "okay";
24767+};
24768+
24769+&uart2 {
24770+ status = "okay";
24771+};
24772+
24773+&uart3 {
24774+ status = "okay";
24775+};
24776+
24777+&ssp0 {
24778+ status = "okay";
24779+
24780+ slic@0 {
24781+ compatible = "silabs,si3226x";
24782+ reg = <0>;
24783+ spi-max-frequency = <5000000>;
24784+ spi-cpha = <1>;
24785+ spi-cpol = <1>;
24786+ pl022,hierarchy = <0>;
24787+ pl022,interface = <0>;
24788+ pl022,slave-tx-disable = <0>;
24789+ pl022,com-mode = <0>;
24790+ pl022,rx-level-trig = <1>;
24791+ pl022,tx-level-trig = <1>;
24792+ pl022,ctrl-len = <11>;
24793+ pl022,wait-state = <0>;
24794+ pl022,duplex = <0>;
24795+ };
24796+};
24797+
24798+&ssp1 {
24799+ status = "okay";
24800+
24801+ at25@0 {
24802+ compatible = "atmel,at25";
24803+ reg = <0>;
24804+ spi-max-frequency = <5000000>;
24805+ at25,byte-len = <0x8000>;
24806+ at25,addr-mode = <2>;
24807+ at25,page-size = <64>;
24808+ spi-cpha = <1>;
24809+ spi-cpol = <1>;
24810+ pl022,hierarchy = <0>;
24811+ pl022,interface = <0>;
24812+ pl022,slave-tx-disable = <0>;
24813+ pl022,com-mode = <0>;
24814+ pl022,rx-level-trig = <1>;
24815+ pl022,tx-level-trig = <1>;
24816+ pl022,ctrl-len = <11>;
24817+ pl022,wait-state = <0>;
24818+ pl022,duplex = <0>;
24819+ };
24820+};
24821+
24822+&sata_phy0 {
24823+ status = "okay";
24824+};
24825+
24826+&sata_phy1 {
24827+ status = "okay";
24828+};
24829+
24830+&sata {
24831+ status = "okay";
24832+};
24833+
24834+&sdio0 {
24835+ status = "okay";
24836+};
24837+
24838+&sdio1 {
24839+ status = "okay";
24840+};
24841+
24842+&nand {
24843+ nandcs@0 {
24844+ compatible = "brcm,nandcs";
24845+ reg = <0>;
24846+ nand-ecc-mode = "hw";
24847+ nand-ecc-strength = <8>;
24848+ nand-ecc-step-size = <512>;
24849+ nand-bus-width = <16>;
24850+ brcm,nand-oob-sector-size = <16>;
24851+ #address-cells = <1>;
24852+ #size-cells = <1>;
24853+ };
24854+};
24855+
24856+&mdio_mux_iproc {
24857+ mdio@10 {
24858+ gphy0: eth-phy@10 {
24859+ enet-phy-lane-swap;
24860+ reg = <0x10>;
24861+ };
24862+ };
24863+};
24864+
24865+&pinctrl {
24866+ pinctrl-names = "default";
24867+ pinctrl-0 = <&nand_sel>;
24868+ nand_sel: nand_sel {
24869+ function = "nand";
24870+ groups = "nand_grp";
24871+ };
24872+};
24873+
24874+&qspi {
24875+ bspi-sel = <0>;
24876+ flash: m25p80@0 {
24877+ #address-cells = <1>;
24878+ #size-cells = <1>;
24879+ compatible = "m25p80";
24880+ reg = <0x0>;
24881+ spi-max-frequency = <12500000>;
24882+ m25p,fast-read;
24883+ spi-cpol;
24884+ spi-cpha;
24885+
24886+ partition@0 {
24887+ label = "boot";
24888+ reg = <0x00000000 0x000a0000>;
24889+ };
24890+
24891+ partition@a0000 {
24892+ label = "env";
24893+ reg = <0x000a0000 0x00060000>;
24894+ };
24895+
24896+ partition@100000 {
24897+ label = "system";
24898+ reg = <0x00100000 0x00600000>;
24899+ };
24900+
24901+ partition@700000 {
24902+ label = "rootfs";
24903+ reg = <0x00700000 0x01900000>;
24904+ };
24905+ };
24906+};
24907diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts
24908new file mode 100644
24909index 000000000000..ab4ae1a32fab
24910--- /dev/null
24911+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts
24912@@ -0,0 +1,191 @@
24913+/*
24914+ * BSD LICENSE
24915+ *
24916+ * Copyright(c) 2016 Broadcom. All rights reserved.
24917+ *
24918+ * Redistribution and use in source and binary forms, with or without
24919+ * modification, are permitted provided that the following conditions
24920+ * are met:
24921+ *
24922+ * * Redistributions of source code must retain the above copyright
24923+ * notice, this list of conditions and the following disclaimer.
24924+ * * Redistributions in binary form must reproduce the above copyright
24925+ * notice, this list of conditions and the following disclaimer in
24926+ * the documentation and/or other materials provided with the
24927+ * distribution.
24928+ * * Neither the name of Broadcom Corporation nor the names of its
24929+ * contributors may be used to endorse or promote products derived
24930+ * from this software without specific prior written permission.
24931+ *
24932+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24933+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24934+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24935+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24936+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24937+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24938+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24939+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24940+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24941+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24942+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24943+ */
24944+
24945+/dts-v1/;
24946+
24947+#include "ns2.dtsi"
24948+
24949+/ {
24950+ model = "Broadcom NS2 XMC";
24951+ compatible = "brcm,ns2-xmc", "brcm,ns2";
24952+
24953+ aliases {
24954+ serial0 = &uart3;
24955+ };
24956+
24957+ chosen {
24958+ stdout-path = "serial0:115200n8";
24959+ bootargs = "earlycon=uart8250,mmio32,0x66130000";
24960+ };
24961+
24962+ memory {
24963+ device_type = "memory";
24964+ reg = <0x000000000 0x80000000 0x00000001 0x00000000>;
24965+ };
24966+};
24967+
24968+&enet {
24969+ status = "okay";
24970+};
24971+
24972+&i2c0 {
24973+ status = "okay";
24974+};
24975+
24976+&i2c1 {
24977+ status = "okay";
24978+};
24979+
24980+&mdio_mux_iproc {
24981+ mdio@10 {
24982+ gphy0: eth-phy@10 {
24983+ reg = <0x10>;
24984+ };
24985+ };
24986+};
24987+
24988+&nand {
24989+ nandcs@0 {
24990+ compatible = "brcm,nandcs";
24991+ reg = <0>;
24992+ nand-ecc-mode = "hw";
24993+ nand-ecc-strength = <8>;
24994+ nand-ecc-step-size = <512>;
24995+ nand-bus-width = <16>;
24996+ brcm,nand-oob-sector-size = <16>;
24997+ #address-cells = <1>;
24998+ #size-cells = <1>;
24999+
25000+ partition@0 {
25001+ label = "nboot";
25002+ reg = <0x00000000 0x00280000>; /* 2.5MB */
25003+ read-only;
25004+ };
25005+
25006+ partition@280000 {
25007+ label = "nenv";
25008+ reg = <0x00280000 0x00040000>; /* 0.25MB */
25009+ read-only;
25010+ };
25011+
25012+ partition@2c0000 {
25013+ label = "ndtb";
25014+ reg = <0x002c0000 0x00040000>; /* 0.25MB */
25015+ read-only;
25016+ };
25017+
25018+ partition@300000 {
25019+ label = "nsystem";
25020+ reg = <0x00300000 0x03d00000>; /* 61MB */
25021+ read-only;
25022+ };
25023+
25024+ partition@4000000 {
25025+ label = "nrootfs";
25026+ reg = <0x04000000 0x06400000>; /* 100MB */
25027+ };
25028+
25029+ partition@0a400000{
25030+ label = "ncustfs";
25031+ reg = <0x0a400000 0x35c00000>; /* 860MB */
25032+ };
25033+ };
25034+};
25035+
25036+&pci_phy0 {
25037+ status = "okay";
25038+};
25039+
25040+&pcie0 {
25041+ status = "okay";
25042+};
25043+
25044+&pcie8 {
25045+ status = "okay";
25046+};
25047+
25048+&sata_phy0 {
25049+ status = "okay";
25050+};
25051+
25052+&sata_phy1 {
25053+ status = "okay";
25054+};
25055+
25056+&sata {
25057+ status = "okay";
25058+};
25059+
25060+&qspi {
25061+ flash: m25p80@0 {
25062+ #address-cells = <1>;
25063+ #size-cells = <1>;
25064+ compatible = "m25p80";
25065+ spi-max-frequency = <62500000>;
25066+ m25p,default-addr-width = <3>;
25067+ reg = <0x0 0x0>;
25068+
25069+ partition@0 {
25070+ label = "bl0";
25071+ reg = <0x00000000 0x00080000>; /* 512KB */
25072+ };
25073+
25074+ partition@80000 {
25075+ label = "fip";
25076+ reg = <0x00080000 0x00150000>; /* 1344KB */
25077+ };
25078+
25079+ partition@1e0000 {
25080+ label = "env";
25081+ reg = <0x001e0000 0x00010000>;/* 64KB */
25082+ };
25083+
25084+ partition@1f0000 {
25085+ label = "dtb";
25086+ reg = <0x001f0000 0x00010000>; /* 64KB */
25087+ };
25088+
25089+ partition@200000 {
25090+ label = "kernel";
25091+ reg = <0x00200000 0x00e00000>; /* 14MB */
25092+ };
25093+
25094+ partition@1000000 {
25095+ label = "rootfs";
25096+ reg = <0x01000000 0x01000000>; /* 16MB */
25097+ };
25098+ };
25099+};
25100+
25101+&uart3 {
25102+ status = "okay";
25103+};
25104diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
25105new file mode 100644
25106index 000000000000..35c8457e3d1f
25107--- /dev/null
25108+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
25109@@ -0,0 +1,765 @@
25110+/*
25111+ * BSD LICENSE
25112+ *
25113+ * Copyright (c) 2015 Broadcom. All rights reserved.
25114+ *
25115+ * Redistribution and use in source and binary forms, with or without
25116+ * modification, are permitted provided that the following conditions
25117+ * are met:
25118+ *
25119+ * * Redistributions of source code must retain the above copyright
25120+ * notice, this list of conditions and the following disclaimer.
25121+ * * Redistributions in binary form must reproduce the above copyright
25122+ * notice, this list of conditions and the following disclaimer in
25123+ * the documentation and/or other materials provided with the
25124+ * distribution.
25125+ * * Neither the name of Broadcom Corporation nor the names of its
25126+ * contributors may be used to endorse or promote products derived
25127+ * from this software without specific prior written permission.
25128+ *
25129+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25130+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25131+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25132+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25133+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25134+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25135+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25136+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25137+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25138+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25139+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25140+ */
25141+
25142+/memreserve/ 0x81000000 0x00200000;
25143+
25144+#include <dt-bindings/interrupt-controller/arm-gic.h>
25145+#include <dt-bindings/clock/bcm-ns2.h>
25146+
25147+/ {
25148+ compatible = "brcm,ns2";
25149+ interrupt-parent = <&gic>;
25150+ #address-cells = <2>;
25151+ #size-cells = <2>;
25152+
25153+ cpus {
25154+ #address-cells = <2>;
25155+ #size-cells = <0>;
25156+
25157+ A57_0: cpu@0 {
25158+ device_type = "cpu";
25159+ compatible = "arm,cortex-a57", "arm,armv8";
25160+ reg = <0 0>;
25161+ enable-method = "psci";
25162+ next-level-cache = <&CLUSTER0_L2>;
25163+ };
25164+
25165+ A57_1: cpu@1 {
25166+ device_type = "cpu";
25167+ compatible = "arm,cortex-a57", "arm,armv8";
25168+ reg = <0 1>;
25169+ enable-method = "psci";
25170+ next-level-cache = <&CLUSTER0_L2>;
25171+ };
25172+
25173+ A57_2: cpu@2 {
25174+ device_type = "cpu";
25175+ compatible = "arm,cortex-a57", "arm,armv8";
25176+ reg = <0 2>;
25177+ enable-method = "psci";
25178+ next-level-cache = <&CLUSTER0_L2>;
25179+ };
25180+
25181+ A57_3: cpu@3 {
25182+ device_type = "cpu";
25183+ compatible = "arm,cortex-a57", "arm,armv8";
25184+ reg = <0 3>;
25185+ enable-method = "psci";
25186+ next-level-cache = <&CLUSTER0_L2>;
25187+ };
25188+
25189+ CLUSTER0_L2: l2-cache@000 {
25190+ compatible = "cache";
25191+ };
25192+ };
25193+
25194+ psci {
25195+ compatible = "arm,psci-1.0";
25196+ method = "smc";
25197+ };
25198+
25199+ timer {
25200+ compatible = "arm,armv8-timer";
25201+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
25202+ IRQ_TYPE_LEVEL_LOW)>,
25203+ <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
25204+ IRQ_TYPE_LEVEL_LOW)>,
25205+ <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
25206+ IRQ_TYPE_LEVEL_LOW)>,
25207+ <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
25208+ IRQ_TYPE_LEVEL_LOW)>;
25209+ };
25210+
25211+ pmu {
25212+ compatible = "arm,armv8-pmuv3";
25213+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
25214+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
25215+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
25216+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
25217+ interrupt-affinity = <&A57_0>,
25218+ <&A57_1>,
25219+ <&A57_2>,
25220+ <&A57_3>;
25221+ };
25222+
25223+ pcie0: pcie@20020000 {
25224+ compatible = "brcm,iproc-pcie";
25225+ reg = <0 0x20020000 0 0x1000>;
25226+ dma-coherent;
25227+
25228+ #interrupt-cells = <1>;
25229+ interrupt-map-mask = <0 0 0 0>;
25230+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_NONE>;
25231+
25232+ linux,pci-domain = <0>;
25233+
25234+ bus-range = <0x00 0xff>;
25235+
25236+ #address-cells = <3>;
25237+ #size-cells = <2>;
25238+ device_type = "pci";
25239+ ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
25240+
25241+ brcm,pcie-ob;
25242+ brcm,pcie-ob-oarr-size;
25243+ brcm,pcie-ob-axi-offset = <0x00000000>;
25244+ brcm,pcie-ob-window-size = <256>;
25245+
25246+ status = "disabled";
25247+
25248+ phys = <&pci_phy0>;
25249+ phy-names = "pcie-phy";
25250+
25251+ msi-parent = <&v2m0>;
25252+ };
25253+
25254+ pcie4: pcie@50020000 {
25255+ compatible = "brcm,iproc-pcie";
25256+ reg = <0 0x50020000 0 0x1000>;
25257+ dma-coherent;
25258+
25259+ #interrupt-cells = <1>;
25260+ interrupt-map-mask = <0 0 0 0>;
25261+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_NONE>;
25262+
25263+ linux,pci-domain = <4>;
25264+
25265+ bus-range = <0x00 0xff>;
25266+
25267+ #address-cells = <3>;
25268+ #size-cells = <2>;
25269+ device_type = "pci";
25270+ ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
25271+
25272+ brcm,pcie-ob;
25273+ brcm,pcie-ob-oarr-size;
25274+ brcm,pcie-ob-axi-offset = <0x30000000>;
25275+ brcm,pcie-ob-window-size = <256>;
25276+
25277+ status = "disabled";
25278+
25279+ phys = <&pci_phy1>;
25280+ phy-names = "pcie-phy";
25281+
25282+ msi-parent = <&v2m0>;
25283+ };
25284+
25285+ pcie8: pcie@60c00000 {
25286+ compatible = "brcm,iproc-pcie-paxc";
25287+ reg = <0 0x60c00000 0 0x1000>;
25288+ dma-coherent;
25289+ linux,pci-domain = <8>;
25290+
25291+ bus-range = <0x0 0x1>;
25292+
25293+ #address-cells = <3>;
25294+ #size-cells = <2>;
25295+ device_type = "pci";
25296+ ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>;
25297+
25298+ status = "disabled";
25299+
25300+ msi-parent = <&v2m0>;
25301+ };
25302+
25303+ soc: soc {
25304+ compatible = "simple-bus";
25305+ #address-cells = <1>;
25306+ #size-cells = <1>;
25307+ ranges = <0 0 0 0xffffffff>;
25308+
25309+ #include "ns2-clock.dtsi"
25310+
25311+ enet: ethernet@61000000 {
25312+ compatible = "brcm,ns2-amac";
25313+ reg = <0x61000000 0x1000>,
25314+ <0x61090000 0x1000>,
25315+ <0x61030000 0x100>;
25316+ reg-names = "amac_base", "idm_base", "nicpm_base";
25317+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
25318+ dma-coherent;
25319+ phy-handle = <&gphy0>;
25320+ phy-mode = "rgmii";
25321+ status = "disabled";
25322+ };
25323+
25324+ pdc0: iproc-pdc0@612c0000 {
25325+ compatible = "brcm,iproc-pdc-mbox";
25326+ reg = <0x612c0000 0x445>; /* PDC FS0 regs */
25327+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
25328+ #mbox-cells = <1>;
25329+ dma-coherent;
25330+ brcm,rx-status-len = <32>;
25331+ brcm,use-bcm-hdr;
25332+ };
25333+
25334+ crypto0: crypto@612d0000 {
25335+ compatible = "brcm,spum-crypto";
25336+ reg = <0x612d0000 0x900>;
25337+ mboxes = <&pdc0 0>;
25338+ };
25339+
25340+ pdc1: iproc-pdc1@612e0000 {
25341+ compatible = "brcm,iproc-pdc-mbox";
25342+ reg = <0x612e0000 0x445>; /* PDC FS1 regs */
25343+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
25344+ #mbox-cells = <1>;
25345+ dma-coherent;
25346+ brcm,rx-status-len = <32>;
25347+ brcm,use-bcm-hdr;
25348+ };
25349+
25350+ crypto1: crypto@612f0000 {
25351+ compatible = "brcm,spum-crypto";
25352+ reg = <0x612f0000 0x900>;
25353+ mboxes = <&pdc1 0>;
25354+ };
25355+
25356+ pdc2: iproc-pdc2@61300000 {
25357+ compatible = "brcm,iproc-pdc-mbox";
25358+ reg = <0x61300000 0x445>; /* PDC FS2 regs */
25359+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
25360+ #mbox-cells = <1>;
25361+ dma-coherent;
25362+ brcm,rx-status-len = <32>;
25363+ brcm,use-bcm-hdr;
25364+ };
25365+
25366+ crypto2: crypto@61310000 {
25367+ compatible = "brcm,spum-crypto";
25368+ reg = <0x61310000 0x900>;
25369+ mboxes = <&pdc2 0>;
25370+ };
25371+
25372+ pdc3: iproc-pdc3@61320000 {
25373+ compatible = "brcm,iproc-pdc-mbox";
25374+ reg = <0x61320000 0x445>; /* PDC FS3 regs */
25375+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
25376+ #mbox-cells = <1>;
25377+ dma-coherent;
25378+ brcm,rx-status-len = <32>;
25379+ brcm,use-bcm-hdr;
25380+ };
25381+
25382+ crypto3: crypto@61330000 {
25383+ compatible = "brcm,spum-crypto";
25384+ reg = <0x61330000 0x900>;
25385+ mboxes = <&pdc3 0>;
25386+ };
25387+
25388+ dma0: dma@61360000 {
25389+ compatible = "arm,pl330", "arm,primecell";
25390+ reg = <0x61360000 0x1000>;
25391+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
25392+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
25393+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
25394+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
25395+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
25396+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
25397+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
25398+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
25399+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
25400+ #dma-cells = <1>;
25401+ #dma-channels = <8>;
25402+ #dma-requests = <32>;
25403+ clocks = <&iprocslow>;
25404+ clock-names = "apb_pclk";
25405+ };
25406+
25407+ smmu: mmu@64000000 {
25408+ compatible = "arm,mmu-500";
25409+ reg = <0x64000000 0x40000>;
25410+ #global-interrupts = <2>;
25411+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
25412+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
25413+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
25414+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
25415+ <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
25416+ <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
25417+ <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
25418+ <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
25419+ <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
25420+ <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
25421+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
25422+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
25423+ <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
25424+ <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
25425+ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
25426+ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
25427+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
25428+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
25429+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
25430+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
25431+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
25432+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
25433+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
25434+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
25435+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
25436+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
25437+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
25438+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
25439+ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
25440+ <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
25441+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
25442+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
25443+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
25444+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
25445+ #iommu-cells = <1>;
25446+ };
25447+
25448+ pinctrl: pinctrl@6501d130 {
25449+ compatible = "brcm,ns2-pinmux";
25450+ reg = <0x6501d130 0x08>,
25451+ <0x660a0028 0x04>,
25452+ <0x660009b0 0x40>;
25453+ };
25454+
25455+ gpio_aon: gpio@65024800 {
25456+ compatible = "brcm,iproc-gpio";
25457+ reg = <0x65024800 0x50>,
25458+ <0x65024008 0x18>;
25459+ ngpios = <6>;
25460+ #gpio-cells = <2>;
25461+ gpio-controller;
25462+ };
25463+
25464+ gic: interrupt-controller@65210000 {
25465+ compatible = "arm,gic-400";
25466+ #interrupt-cells = <3>;
25467+ interrupt-controller;
25468+ reg = <0x65210000 0x1000>,
25469+ <0x65220000 0x1000>,
25470+ <0x65240000 0x2000>,
25471+ <0x65260000 0x1000>;
25472+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
25473+ IRQ_TYPE_LEVEL_HIGH)>;
25474+
25475+ #address-cells = <1>;
25476+ #size-cells = <1>;
25477+ ranges = <0 0x652e0000 0x80000>;
25478+
25479+ v2m0: v2m@00000 {
25480+ compatible = "arm,gic-v2m-frame";
25481+ interrupt-parent = <&gic>;
25482+ msi-controller;
25483+ reg = <0x00000 0x1000>;
25484+ arm,msi-base-spi = <72>;
25485+ arm,msi-num-spis = <16>;
25486+ };
25487+
25488+ v2m1: v2m@10000 {
25489+ compatible = "arm,gic-v2m-frame";
25490+ interrupt-parent = <&gic>;
25491+ msi-controller;
25492+ reg = <0x10000 0x1000>;
25493+ arm,msi-base-spi = <88>;
25494+ arm,msi-num-spis = <16>;
25495+ };
25496+
25497+ v2m2: v2m@20000 {
25498+ compatible = "arm,gic-v2m-frame";
25499+ interrupt-parent = <&gic>;
25500+ msi-controller;
25501+ reg = <0x20000 0x1000>;
25502+ arm,msi-base-spi = <104>;
25503+ arm,msi-num-spis = <16>;
25504+ };
25505+
25506+ v2m3: v2m@30000 {
25507+ compatible = "arm,gic-v2m-frame";
25508+ interrupt-parent = <&gic>;
25509+ msi-controller;
25510+ reg = <0x30000 0x1000>;
25511+ arm,msi-base-spi = <120>;
25512+ arm,msi-num-spis = <16>;
25513+ };
25514+
25515+ v2m4: v2m@40000 {
25516+ compatible = "arm,gic-v2m-frame";
25517+ interrupt-parent = <&gic>;
25518+ msi-controller;
25519+ reg = <0x40000 0x1000>;
25520+ arm,msi-base-spi = <136>;
25521+ arm,msi-num-spis = <16>;
25522+ };
25523+
25524+ v2m5: v2m@50000 {
25525+ compatible = "arm,gic-v2m-frame";
25526+ interrupt-parent = <&gic>;
25527+ msi-controller;
25528+ reg = <0x50000 0x1000>;
25529+ arm,msi-base-spi = <152>;
25530+ arm,msi-num-spis = <16>;
25531+ };
25532+
25533+ v2m6: v2m@60000 {
25534+ compatible = "arm,gic-v2m-frame";
25535+ interrupt-parent = <&gic>;
25536+ msi-controller;
25537+ reg = <0x60000 0x1000>;
25538+ arm,msi-base-spi = <168>;
25539+ arm,msi-num-spis = <16>;
25540+ };
25541+
25542+ v2m7: v2m@70000 {
25543+ compatible = "arm,gic-v2m-frame";
25544+ interrupt-parent = <&gic>;
25545+ msi-controller;
25546+ reg = <0x70000 0x1000>;
25547+ arm,msi-base-spi = <184>;
25548+ arm,msi-num-spis = <16>;
25549+ };
25550+ };
25551+
25552+ cci@65590000 {
25553+ compatible = "arm,cci-400";
25554+ #address-cells = <1>;
25555+ #size-cells = <1>;
25556+ reg = <0x65590000 0x1000>;
25557+ ranges = <0 0x65590000 0x10000>;
25558+
25559+ pmu@9000 {
25560+ compatible = "arm,cci-400-pmu,r1",
25561+ "arm,cci-400-pmu";
25562+ reg = <0x9000 0x4000>;
25563+ interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
25564+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
25565+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
25566+ <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
25567+ <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
25568+ <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
25569+ };
25570+ };
25571+
25572+ usbdrd_phy: phy@66000960 {
25573+ #phy-cells = <0>;
25574+ compatible = "brcm,ns2-drd-phy";
25575+ reg = <0x66000960 0x24>,
25576+ <0x67012800 0x4>,
25577+ <0x6501d148 0x4>,
25578+ <0x664d0700 0x4>;
25579+ reg-names = "icfg", "rst-ctrl",
25580+ "crmu-ctrl", "usb2-strap";
25581+ id-gpios = <&gpio_g 30 0>;
25582+ vbus-gpios = <&gpio_g 31 0>;
25583+ status = "disabled";
25584+ };
25585+
25586+ pwm: pwm@66010000 {
25587+ compatible = "brcm,iproc-pwm";
25588+ reg = <0x66010000 0x28>;
25589+ clocks = <&osc>;
25590+ #pwm-cells = <3>;
25591+ status = "disabled";
25592+ };
25593+
25594+ mdio_mux_iproc: mdio-mux@6602023c {
25595+ compatible = "brcm,mdio-mux-iproc";
25596+ reg = <0x6602023c 0x14>;
25597+ #address-cells = <1>;
25598+ #size-cells = <0>;
25599+
25600+ mdio@0 {
25601+ reg = <0x0>;
25602+ #address-cells = <1>;
25603+ #size-cells = <0>;
25604+
25605+ pci_phy0: pci-phy@0 {
25606+ compatible = "brcm,ns2-pcie-phy";
25607+ reg = <0x0>;
25608+ #phy-cells = <0>;
25609+ status = "disabled";
25610+ };
25611+ };
25612+
25613+ mdio@7 {
25614+ reg = <0x7>;
25615+ #address-cells = <1>;
25616+ #size-cells = <0>;
25617+
25618+ pci_phy1: pci-phy@0 {
25619+ compatible = "brcm,ns2-pcie-phy";
25620+ reg = <0x0>;
25621+ #phy-cells = <0>;
25622+ status = "disabled";
25623+ };
25624+ };
25625+
25626+ mdio@10 {
25627+ reg = <0x10>;
25628+ #address-cells = <1>;
25629+ #size-cells = <0>;
25630+ };
25631+ };
25632+
25633+ timer0: timer@66030000 {
25634+ compatible = "arm,sp804", "arm,primecell";
25635+ reg = <0x66030000 0x1000>;
25636+ interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
25637+ clocks = <&iprocslow>,
25638+ <&iprocslow>,
25639+ <&iprocslow>;
25640+ clock-names = "timer1", "timer2", "apb_pclk";
25641+ };
25642+
25643+ timer1: timer@66040000 {
25644+ compatible = "arm,sp804", "arm,primecell";
25645+ reg = <0x66040000 0x1000>;
25646+ interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
25647+ clocks = <&iprocslow>,
25648+ <&iprocslow>,
25649+ <&iprocslow>;
25650+ clock-names = "timer1", "timer2", "apb_pclk";
25651+ };
25652+
25653+ timer2: timer@66050000 {
25654+ compatible = "arm,sp804", "arm,primecell";
25655+ reg = <0x66050000 0x1000>;
25656+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
25657+ clocks = <&iprocslow>,
25658+ <&iprocslow>,
25659+ <&iprocslow>;
25660+ clock-names = "timer1", "timer2", "apb_pclk";
25661+ };
25662+
25663+ timer3: timer@66060000 {
25664+ compatible = "arm,sp804", "arm,primecell";
25665+ reg = <0x66060000 0x1000>;
25666+ interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
25667+ clocks = <&iprocslow>,
25668+ <&iprocslow>,
25669+ <&iprocslow>;
25670+ clock-names = "timer1", "timer2", "apb_pclk";
25671+ };
25672+
25673+ i2c0: i2c@66080000 {
25674+ compatible = "brcm,iproc-i2c";
25675+ reg = <0x66080000 0x100>;
25676+ #address-cells = <1>;
25677+ #size-cells = <0>;
25678+ interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
25679+ clock-frequency = <100000>;
25680+ status = "disabled";
25681+ };
25682+
25683+ wdt0: watchdog@66090000 {
25684+ compatible = "arm,sp805", "arm,primecell";
25685+ reg = <0x66090000 0x1000>;
25686+ interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
25687+ clocks = <&iprocslow>, <&iprocslow>;
25688+ clock-names = "wdogclk", "apb_pclk";
25689+ };
25690+
25691+ gpio_g: gpio@660a0000 {
25692+ compatible = "brcm,iproc-gpio";
25693+ reg = <0x660a0000 0x50>;
25694+ ngpios = <32>;
25695+ #gpio-cells = <2>;
25696+ gpio-controller;
25697+ interrupt-controller;
25698+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
25699+ };
25700+
25701+ i2c1: i2c@660b0000 {
25702+ compatible = "brcm,iproc-i2c";
25703+ reg = <0x660b0000 0x100>;
25704+ #address-cells = <1>;
25705+ #size-cells = <0>;
25706+ interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
25707+ clock-frequency = <100000>;
25708+ status = "disabled";
25709+ };
25710+
25711+ uart0: serial@66100000 {
25712+ compatible = "snps,dw-apb-uart";
25713+ reg = <0x66100000 0x100>;
25714+ interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
25715+ clocks = <&iprocslow>;
25716+ reg-shift = <2>;
25717+ reg-io-width = <4>;
25718+ status = "disabled";
25719+ };
25720+
25721+ uart1: serial@66110000 {
25722+ compatible = "snps,dw-apb-uart";
25723+ reg = <0x66110000 0x100>;
25724+ interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
25725+ clocks = <&iprocslow>;
25726+ reg-shift = <2>;
25727+ reg-io-width = <4>;
25728+ status = "disabled";
25729+ };
25730+
25731+ uart2: serial@66120000 {
25732+ compatible = "snps,dw-apb-uart";
25733+ reg = <0x66120000 0x100>;
25734+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
25735+ clocks = <&iprocslow>;
25736+ reg-shift = <2>;
25737+ reg-io-width = <4>;
25738+ status = "disabled";
25739+ };
25740+
25741+ uart3: serial@66130000 {
25742+ compatible = "snps,dw-apb-uart";
25743+ reg = <0x66130000 0x100>;
25744+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
25745+ reg-shift = <2>;
25746+ reg-io-width = <4>;
25747+ clocks = <&osc>;
25748+ status = "disabled";
25749+ };
25750+
25751+ ssp0: ssp@66180000 {
25752+ compatible = "arm,pl022", "arm,primecell";
25753+ reg = <0x66180000 0x1000>;
25754+ interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
25755+ clocks = <&iprocslow>, <&iprocslow>;
25756+ clock-names = "spiclk", "apb_pclk";
25757+ #address-cells = <1>;
25758+ #size-cells = <0>;
25759+ status = "disabled";
25760+ };
25761+
25762+ ssp1: ssp@66190000 {
25763+ compatible = "arm,pl022", "arm,primecell";
25764+ reg = <0x66190000 0x1000>;
25765+ interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
25766+ clocks = <&iprocslow>, <&iprocslow>;
25767+ clock-names = "spiclk", "apb_pclk";
25768+ #address-cells = <1>;
25769+ #size-cells = <0>;
25770+ status = "disabled";
25771+ };
25772+
25773+ hwrng: hwrng@66220000 {
25774+ compatible = "brcm,iproc-rng200";
25775+ reg = <0x66220000 0x28>;
25776+ };
25777+
25778+ sata_phy: sata_phy@663f0100 {
25779+ compatible = "brcm,iproc-ns2-sata-phy";
25780+ reg = <0x663f0100 0x1f00>,
25781+ <0x663f004c 0x10>;
25782+ reg-names = "phy", "phy-ctrl";
25783+ #address-cells = <1>;
25784+ #size-cells = <0>;
25785+
25786+ sata_phy0: sata-phy@0 {
25787+ reg = <0>;
25788+ #phy-cells = <0>;
25789+ status = "disabled";
25790+ };
25791+
25792+ sata_phy1: sata-phy@1 {
25793+ reg = <1>;
25794+ #phy-cells = <0>;
25795+ status = "disabled";
25796+ };
25797+ };
25798+
25799+ sata: ahci@663f2000 {
25800+ compatible = "brcm,iproc-ahci", "generic-ahci";
25801+ reg = <0x663f2000 0x1000>;
25802+ dma-coherent;
25803+ reg-names = "ahci";
25804+ interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
25805+ #address-cells = <1>;
25806+ #size-cells = <0>;
25807+ status = "disabled";
25808+
25809+ sata0: sata-port@0 {
25810+ reg = <0>;
25811+ phys = <&sata_phy0>;
25812+ phy-names = "sata-phy";
25813+ };
25814+
25815+ sata1: sata-port@1 {
25816+ reg = <1>;
25817+ phys = <&sata_phy1>;
25818+ phy-names = "sata-phy";
25819+ };
25820+ };
25821+
25822+ sdio0: sdhci@66420000 {
25823+ compatible = "brcm,sdhci-iproc-cygnus";
25824+ reg = <0x66420000 0x100>;
25825+ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
25826+ dma-coherent;
25827+ bus-width = <8>;
25828+ clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
25829+ status = "disabled";
25830+ };
25831+
25832+ sdio1: sdhci@66430000 {
25833+ compatible = "brcm,sdhci-iproc-cygnus";
25834+ reg = <0x66430000 0x100>;
25835+ interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
25836+ dma-coherent;
25837+ bus-width = <8>;
25838+ clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
25839+ status = "disabled";
25840+ };
25841+
25842+ nand: nand@66460000 {
25843+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
25844+ reg = <0x66460000 0x600>,
25845+ <0x67015408 0x600>,
25846+ <0x66460f00 0x20>;
25847+ reg-names = "nand", "iproc-idm", "iproc-ext";
25848+ interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
25849+
25850+ #address-cells = <1>;
25851+ #size-cells = <0>;
25852+
25853+ brcm,nand-has-wp;
25854+ };
25855+
25856+ qspi: spi@66470200 {
25857+ compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
25858+ reg = <0x66470200 0x184>,
25859+ <0x66470000 0x124>,
25860+ <0x67017408 0x004>,
25861+ <0x664703a0 0x01c>;
25862+ reg-names = "mspi", "bspi", "intr_regs",
25863+ "intr_status_reg";
25864+ interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
25865+ interrupt-names = "spi_l1_intr";
25866+ clocks = <&iprocmed>;
25867+ clock-names = "iprocmed";
25868+ num-cs = <2>;
25869+ #address-cells = <1>;
25870+ #size-cells = <0>;
25871+ };
25872+
25873+ };
25874+};
25875diff --git a/arch/arm64/boot/dts/broadcom/ns2-clock.dtsi b/arch/arm64/boot/dts/broadcom/ns2-clock.dtsi
25876deleted file mode 100644
25877index 99009fdf10a4..000000000000
25878--- a/arch/arm64/boot/dts/broadcom/ns2-clock.dtsi
25879+++ /dev/null
25880@@ -1,105 +0,0 @@
25881-/*
25882- * BSD LICENSE
25883- *
25884- * Copyright (c) 2016 Broadcom. All rights reserved.
25885- *
25886- * Redistribution and use in source and binary forms, with or without
25887- * modification, are permitted provided that the following conditions
25888- * are met:
25889- *
25890- * * Redistributions of source code must retain the above copyright
25891- * notice, this list of conditions and the following disclaimer.
25892- * * Redistributions in binary form must reproduce the above copyright
25893- * notice, this list of conditions and the following disclaimer in
25894- * the documentation and/or other materials provided with the
25895- * distribution.
25896- * * Neither the name of Broadcom Corporation nor the names of its
25897- * contributors may be used to endorse or promote products derived
25898- * from this software without specific prior written permission.
25899- *
25900- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25901- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25902- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25903- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25904- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25905- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25906- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25907- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25908- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25909- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25910- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25911- */
25912-
25913-#include <dt-bindings/clock/bcm-ns2.h>
25914-
25915- osc: oscillator {
25916- #clock-cells = <0>;
25917- compatible = "fixed-clock";
25918- clock-frequency = <25000000>;
25919- };
25920-
25921- lcpll_ddr: lcpll_ddr@6501d058 {
25922- #clock-cells = <1>;
25923- compatible = "brcm,ns2-lcpll-ddr";
25924- reg = <0x6501d058 0x20>,
25925- <0x6501c020 0x4>,
25926- <0x6501d04c 0x4>;
25927- clocks = <&osc>;
25928- clock-output-names = "lcpll_ddr", "pcie_sata_usb",
25929- "ddr", "ddr_ch2_unused",
25930- "ddr_ch3_unused", "ddr_ch4_unused",
25931- "ddr_ch5_unused";
25932- };
25933-
25934- lcpll_ports: lcpll_ports@6501d078 {
25935- #clock-cells = <1>;
25936- compatible = "brcm,ns2-lcpll-ports";
25937- reg = <0x6501d078 0x20>,
25938- <0x6501c020 0x4>,
25939- <0x6501d054 0x4>;
25940- clocks = <&osc>;
25941- clock-output-names = "lcpll_ports", "wan", "rgmii",
25942- "ports_ch2_unused",
25943- "ports_ch3_unused",
25944- "ports_ch4_unused",
25945- "ports_ch5_unused";
25946- };
25947-
25948- genpll_scr: genpll_scr@6501d098 {
25949- #clock-cells = <1>;
25950- compatible = "brcm,ns2-genpll-scr";
25951- reg = <0x6501d098 0x32>,
25952- <0x6501c020 0x4>,
25953- <0x6501d044 0x4>;
25954- clocks = <&osc>;
25955- clock-output-names = "genpll_scr", "scr", "fs",
25956- "audio_ref", "scr_ch3_unused",
25957- "scr_ch4_unused", "scr_ch5_unused";
25958- };
25959-
25960- iprocmed: iprocmed {
25961- #clock-cells = <0>;
25962- compatible = "fixed-factor-clock";
25963- clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
25964- clock-div = <2>;
25965- clock-mult = <1>;
25966- };
25967-
25968- iprocslow: iprocslow {
25969- #clock-cells = <0>;
25970- compatible = "fixed-factor-clock";
25971- clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
25972- clock-div = <4>;
25973- clock-mult = <1>;
25974- };
25975-
25976- genpll_sw: genpll_sw@6501d0c4 {
25977- #clock-cells = <1>;
25978- compatible = "brcm,ns2-genpll-sw";
25979- reg = <0x6501d0c4 0x32>,
25980- <0x6501c020 0x4>,
25981- <0x6501d044 0x4>;
25982- clocks = <&osc>;
25983- clock-output-names = "genpll_sw", "rpe", "250", "nic",
25984- "chimp", "port", "sdio";
25985- };
25986diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
25987deleted file mode 100644
25988index ec19fbf928a1..000000000000
25989--- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
25990+++ /dev/null
25991@@ -1,236 +0,0 @@
25992-/*
25993- * BSD LICENSE
25994- *
25995- * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
25996- *
25997- * Redistribution and use in source and binary forms, with or without
25998- * modification, are permitted provided that the following conditions
25999- * are met:
26000- *
26001- * * Redistributions of source code must retain the above copyright
26002- * notice, this list of conditions and the following disclaimer.
26003- * * Redistributions in binary form must reproduce the above copyright
26004- * notice, this list of conditions and the following disclaimer in
26005- * the documentation and/or other materials provided with the
26006- * distribution.
26007- * * Neither the name of Broadcom Corporation nor the names of its
26008- * contributors may be used to endorse or promote products derived
26009- * from this software without specific prior written permission.
26010- *
26011- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26012- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26013- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26014- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26015- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26016- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26017- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26018- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26019- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26020- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26021- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26022- */
26023-
26024-/dts-v1/;
26025-
26026-#include "ns2.dtsi"
26027-
26028-/ {
26029- model = "Broadcom NS2 SVK";
26030- compatible = "brcm,ns2-svk", "brcm,ns2";
26031-
26032- aliases {
26033- serial0 = &uart3;
26034- serial1 = &uart0;
26035- serial2 = &uart1;
26036- serial3 = &uart2;
26037- };
26038-
26039- chosen {
26040- stdout-path = "serial0:115200n8";
26041- bootargs = "earlycon=uart8250,mmio32,0x66130000";
26042- };
26043-
26044- memory {
26045- device_type = "memory";
26046- reg = <0x000000000 0x80000000 0x00000000 0x40000000>;
26047- };
26048-};
26049-
26050-&enet {
26051- status = "okay";
26052-};
26053-
26054-&pci_phy0 {
26055- status = "okay";
26056-};
26057-
26058-&pci_phy1 {
26059- status = "okay";
26060-};
26061-
26062-&pcie0 {
26063- status = "okay";
26064-};
26065-
26066-&pcie4 {
26067- status = "okay";
26068-};
26069-
26070-&pcie8 {
26071- status = "okay";
26072-};
26073-
26074-&i2c0 {
26075- status = "okay";
26076-};
26077-
26078-&i2c1 {
26079- status = "okay";
26080-};
26081-
26082-&uart0 {
26083- status = "okay";
26084-};
26085-
26086-&uart1 {
26087- status = "okay";
26088-};
26089-
26090-&uart2 {
26091- status = "okay";
26092-};
26093-
26094-&uart3 {
26095- status = "okay";
26096-};
26097-
26098-&ssp0 {
26099- status = "okay";
26100-
26101- slic@0 {
26102- compatible = "silabs,si3226x";
26103- reg = <0>;
26104- spi-max-frequency = <5000000>;
26105- spi-cpha = <1>;
26106- spi-cpol = <1>;
26107- pl022,hierarchy = <0>;
26108- pl022,interface = <0>;
26109- pl022,slave-tx-disable = <0>;
26110- pl022,com-mode = <0>;
26111- pl022,rx-level-trig = <1>;
26112- pl022,tx-level-trig = <1>;
26113- pl022,ctrl-len = <11>;
26114- pl022,wait-state = <0>;
26115- pl022,duplex = <0>;
26116- };
26117-};
26118-
26119-&ssp1 {
26120- status = "okay";
26121-
26122- at25@0 {
26123- compatible = "atmel,at25";
26124- reg = <0>;
26125- spi-max-frequency = <5000000>;
26126- at25,byte-len = <0x8000>;
26127- at25,addr-mode = <2>;
26128- at25,page-size = <64>;
26129- spi-cpha = <1>;
26130- spi-cpol = <1>;
26131- pl022,hierarchy = <0>;
26132- pl022,interface = <0>;
26133- pl022,slave-tx-disable = <0>;
26134- pl022,com-mode = <0>;
26135- pl022,rx-level-trig = <1>;
26136- pl022,tx-level-trig = <1>;
26137- pl022,ctrl-len = <11>;
26138- pl022,wait-state = <0>;
26139- pl022,duplex = <0>;
26140- };
26141-};
26142-
26143-&sata_phy0 {
26144- status = "okay";
26145-};
26146-
26147-&sata_phy1 {
26148- status = "okay";
26149-};
26150-
26151-&sata {
26152- status = "okay";
26153-};
26154-
26155-&sdio0 {
26156- status = "okay";
26157-};
26158-
26159-&sdio1 {
26160- status = "okay";
26161-};
26162-
26163-&nand {
26164- nandcs@0 {
26165- compatible = "brcm,nandcs";
26166- reg = <0>;
26167- nand-ecc-mode = "hw";
26168- nand-ecc-strength = <8>;
26169- nand-ecc-step-size = <512>;
26170- nand-bus-width = <16>;
26171- brcm,nand-oob-sector-size = <16>;
26172- #address-cells = <1>;
26173- #size-cells = <1>;
26174- };
26175-};
26176-
26177-&mdio_mux_iproc {
26178- mdio@10 {
26179- gphy0: eth-phy@10 {
26180- enet-phy-lane-swap;
26181- reg = <0x10>;
26182- };
26183- };
26184-};
26185-
26186-&pinctrl {
26187- pinctrl-names = "default";
26188- pinctrl-0 = <&nand_sel>;
26189- nand_sel: nand_sel {
26190- function = "nand";
26191- groups = "nand_grp";
26192- };
26193-};
26194-
26195-&qspi {
26196- bspi-sel = <0>;
26197- flash: m25p80@0 {
26198- #address-cells = <1>;
26199- #size-cells = <1>;
26200- compatible = "m25p80";
26201- reg = <0x0>;
26202- spi-max-frequency = <12500000>;
26203- m25p,fast-read;
26204- spi-cpol;
26205- spi-cpha;
26206-
26207- partition@0 {
26208- label = "boot";
26209- reg = <0x00000000 0x000a0000>;
26210- };
26211-
26212- partition@a0000 {
26213- label = "env";
26214- reg = <0x000a0000 0x00060000>;
26215- };
26216-
26217- partition@100000 {
26218- label = "system";
26219- reg = <0x00100000 0x00600000>;
26220- };
26221-
26222- partition@700000 {
26223- label = "rootfs";
26224- reg = <0x00700000 0x01900000>;
26225- };
26226- };
26227-};
26228diff --git a/arch/arm64/boot/dts/broadcom/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/ns2-xmc.dts
26229deleted file mode 100644
26230index ab4ae1a32fab..000000000000
26231--- a/arch/arm64/boot/dts/broadcom/ns2-xmc.dts
26232+++ /dev/null
26233@@ -1,191 +0,0 @@
26234-/*
26235- * BSD LICENSE
26236- *
26237- * Copyright(c) 2016 Broadcom. All rights reserved.
26238- *
26239- * Redistribution and use in source and binary forms, with or without
26240- * modification, are permitted provided that the following conditions
26241- * are met:
26242- *
26243- * * Redistributions of source code must retain the above copyright
26244- * notice, this list of conditions and the following disclaimer.
26245- * * Redistributions in binary form must reproduce the above copyright
26246- * notice, this list of conditions and the following disclaimer in
26247- * the documentation and/or other materials provided with the
26248- * distribution.
26249- * * Neither the name of Broadcom Corporation nor the names of its
26250- * contributors may be used to endorse or promote products derived
26251- * from this software without specific prior written permission.
26252- *
26253- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26254- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26255- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26256- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26257- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26258- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26259- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26260- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26261- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26262- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26263- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26264- */
26265-
26266-/dts-v1/;
26267-
26268-#include "ns2.dtsi"
26269-
26270-/ {
26271- model = "Broadcom NS2 XMC";
26272- compatible = "brcm,ns2-xmc", "brcm,ns2";
26273-
26274- aliases {
26275- serial0 = &uart3;
26276- };
26277-
26278- chosen {
26279- stdout-path = "serial0:115200n8";
26280- bootargs = "earlycon=uart8250,mmio32,0x66130000";
26281- };
26282-
26283- memory {
26284- device_type = "memory";
26285- reg = <0x000000000 0x80000000 0x00000001 0x00000000>;
26286- };
26287-};
26288-
26289-&enet {
26290- status = "okay";
26291-};
26292-
26293-&i2c0 {
26294- status = "okay";
26295-};
26296-
26297-&i2c1 {
26298- status = "okay";
26299-};
26300-
26301-&mdio_mux_iproc {
26302- mdio@10 {
26303- gphy0: eth-phy@10 {
26304- reg = <0x10>;
26305- };
26306- };
26307-};
26308-
26309-&nand {
26310- nandcs@0 {
26311- compatible = "brcm,nandcs";
26312- reg = <0>;
26313- nand-ecc-mode = "hw";
26314- nand-ecc-strength = <8>;
26315- nand-ecc-step-size = <512>;
26316- nand-bus-width = <16>;
26317- brcm,nand-oob-sector-size = <16>;
26318- #address-cells = <1>;
26319- #size-cells = <1>;
26320-
26321- partition@0 {
26322- label = "nboot";
26323- reg = <0x00000000 0x00280000>; /* 2.5MB */
26324- read-only;
26325- };
26326-
26327- partition@280000 {
26328- label = "nenv";
26329- reg = <0x00280000 0x00040000>; /* 0.25MB */
26330- read-only;
26331- };
26332-
26333- partition@2c0000 {
26334- label = "ndtb";
26335- reg = <0x002c0000 0x00040000>; /* 0.25MB */
26336- read-only;
26337- };
26338-
26339- partition@300000 {
26340- label = "nsystem";
26341- reg = <0x00300000 0x03d00000>; /* 61MB */
26342- read-only;
26343- };
26344-
26345- partition@4000000 {
26346- label = "nrootfs";
26347- reg = <0x04000000 0x06400000>; /* 100MB */
26348- };
26349-
26350- partition@0a400000{
26351- label = "ncustfs";
26352- reg = <0x0a400000 0x35c00000>; /* 860MB */
26353- };
26354- };
26355-};
26356-
26357-&pci_phy0 {
26358- status = "okay";
26359-};
26360-
26361-&pcie0 {
26362- status = "okay";
26363-};
26364-
26365-&pcie8 {
26366- status = "okay";
26367-};
26368-
26369-&sata_phy0 {
26370- status = "okay";
26371-};
26372-
26373-&sata_phy1 {
26374- status = "okay";
26375-};
26376-
26377-&sata {
26378- status = "okay";
26379-};
26380-
26381-&qspi {
26382- flash: m25p80@0 {
26383- #address-cells = <1>;
26384- #size-cells = <1>;
26385- compatible = "m25p80";
26386- spi-max-frequency = <62500000>;
26387- m25p,default-addr-width = <3>;
26388- reg = <0x0 0x0>;
26389-
26390- partition@0 {
26391- label = "bl0";
26392- reg = <0x00000000 0x00080000>; /* 512KB */
26393- };
26394-
26395- partition@80000 {
26396- label = "fip";
26397- reg = <0x00080000 0x00150000>; /* 1344KB */
26398- };
26399-
26400- partition@1e0000 {
26401- label = "env";
26402- reg = <0x001e0000 0x00010000>;/* 64KB */
26403- };
26404-
26405- partition@1f0000 {
26406- label = "dtb";
26407- reg = <0x001f0000 0x00010000>; /* 64KB */
26408- };
26409-
26410- partition@200000 {
26411- label = "kernel";
26412- reg = <0x00200000 0x00e00000>; /* 14MB */
26413- };
26414-
26415- partition@1000000 {
26416- label = "rootfs";
26417- reg = <0x01000000 0x01000000>; /* 16MB */
26418- };
26419- };
26420-};
26421-
26422-&uart3 {
26423- status = "okay";
26424-};
26425diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
26426deleted file mode 100644
26427index 35c8457e3d1f..000000000000
26428--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
26429+++ /dev/null
26430@@ -1,765 +0,0 @@
26431-/*
26432- * BSD LICENSE
26433- *
26434- * Copyright (c) 2015 Broadcom. All rights reserved.
26435- *
26436- * Redistribution and use in source and binary forms, with or without
26437- * modification, are permitted provided that the following conditions
26438- * are met:
26439- *
26440- * * Redistributions of source code must retain the above copyright
26441- * notice, this list of conditions and the following disclaimer.
26442- * * Redistributions in binary form must reproduce the above copyright
26443- * notice, this list of conditions and the following disclaimer in
26444- * the documentation and/or other materials provided with the
26445- * distribution.
26446- * * Neither the name of Broadcom Corporation nor the names of its
26447- * contributors may be used to endorse or promote products derived
26448- * from this software without specific prior written permission.
26449- *
26450- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26451- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26452- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26453- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26454- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26455- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26456- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26457- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26458- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26459- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26460- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26461- */
26462-
26463-/memreserve/ 0x81000000 0x00200000;
26464-
26465-#include <dt-bindings/interrupt-controller/arm-gic.h>
26466-#include <dt-bindings/clock/bcm-ns2.h>
26467-
26468-/ {
26469- compatible = "brcm,ns2";
26470- interrupt-parent = <&gic>;
26471- #address-cells = <2>;
26472- #size-cells = <2>;
26473-
26474- cpus {
26475- #address-cells = <2>;
26476- #size-cells = <0>;
26477-
26478- A57_0: cpu@0 {
26479- device_type = "cpu";
26480- compatible = "arm,cortex-a57", "arm,armv8";
26481- reg = <0 0>;
26482- enable-method = "psci";
26483- next-level-cache = <&CLUSTER0_L2>;
26484- };
26485-
26486- A57_1: cpu@1 {
26487- device_type = "cpu";
26488- compatible = "arm,cortex-a57", "arm,armv8";
26489- reg = <0 1>;
26490- enable-method = "psci";
26491- next-level-cache = <&CLUSTER0_L2>;
26492- };
26493-
26494- A57_2: cpu@2 {
26495- device_type = "cpu";
26496- compatible = "arm,cortex-a57", "arm,armv8";
26497- reg = <0 2>;
26498- enable-method = "psci";
26499- next-level-cache = <&CLUSTER0_L2>;
26500- };
26501-
26502- A57_3: cpu@3 {
26503- device_type = "cpu";
26504- compatible = "arm,cortex-a57", "arm,armv8";
26505- reg = <0 3>;
26506- enable-method = "psci";
26507- next-level-cache = <&CLUSTER0_L2>;
26508- };
26509-
26510- CLUSTER0_L2: l2-cache@000 {
26511- compatible = "cache";
26512- };
26513- };
26514-
26515- psci {
26516- compatible = "arm,psci-1.0";
26517- method = "smc";
26518- };
26519-
26520- timer {
26521- compatible = "arm,armv8-timer";
26522- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
26523- IRQ_TYPE_LEVEL_LOW)>,
26524- <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
26525- IRQ_TYPE_LEVEL_LOW)>,
26526- <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
26527- IRQ_TYPE_LEVEL_LOW)>,
26528- <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
26529- IRQ_TYPE_LEVEL_LOW)>;
26530- };
26531-
26532- pmu {
26533- compatible = "arm,armv8-pmuv3";
26534- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
26535- <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
26536- <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
26537- <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
26538- interrupt-affinity = <&A57_0>,
26539- <&A57_1>,
26540- <&A57_2>,
26541- <&A57_3>;
26542- };
26543-
26544- pcie0: pcie@20020000 {
26545- compatible = "brcm,iproc-pcie";
26546- reg = <0 0x20020000 0 0x1000>;
26547- dma-coherent;
26548-
26549- #interrupt-cells = <1>;
26550- interrupt-map-mask = <0 0 0 0>;
26551- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_NONE>;
26552-
26553- linux,pci-domain = <0>;
26554-
26555- bus-range = <0x00 0xff>;
26556-
26557- #address-cells = <3>;
26558- #size-cells = <2>;
26559- device_type = "pci";
26560- ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
26561-
26562- brcm,pcie-ob;
26563- brcm,pcie-ob-oarr-size;
26564- brcm,pcie-ob-axi-offset = <0x00000000>;
26565- brcm,pcie-ob-window-size = <256>;
26566-
26567- status = "disabled";
26568-
26569- phys = <&pci_phy0>;
26570- phy-names = "pcie-phy";
26571-
26572- msi-parent = <&v2m0>;
26573- };
26574-
26575- pcie4: pcie@50020000 {
26576- compatible = "brcm,iproc-pcie";
26577- reg = <0 0x50020000 0 0x1000>;
26578- dma-coherent;
26579-
26580- #interrupt-cells = <1>;
26581- interrupt-map-mask = <0 0 0 0>;
26582- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_NONE>;
26583-
26584- linux,pci-domain = <4>;
26585-
26586- bus-range = <0x00 0xff>;
26587-
26588- #address-cells = <3>;
26589- #size-cells = <2>;
26590- device_type = "pci";
26591- ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
26592-
26593- brcm,pcie-ob;
26594- brcm,pcie-ob-oarr-size;
26595- brcm,pcie-ob-axi-offset = <0x30000000>;
26596- brcm,pcie-ob-window-size = <256>;
26597-
26598- status = "disabled";
26599-
26600- phys = <&pci_phy1>;
26601- phy-names = "pcie-phy";
26602-
26603- msi-parent = <&v2m0>;
26604- };
26605-
26606- pcie8: pcie@60c00000 {
26607- compatible = "brcm,iproc-pcie-paxc";
26608- reg = <0 0x60c00000 0 0x1000>;
26609- dma-coherent;
26610- linux,pci-domain = <8>;
26611-
26612- bus-range = <0x0 0x1>;
26613-
26614- #address-cells = <3>;
26615- #size-cells = <2>;
26616- device_type = "pci";
26617- ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>;
26618-
26619- status = "disabled";
26620-
26621- msi-parent = <&v2m0>;
26622- };
26623-
26624- soc: soc {
26625- compatible = "simple-bus";
26626- #address-cells = <1>;
26627- #size-cells = <1>;
26628- ranges = <0 0 0 0xffffffff>;
26629-
26630- #include "ns2-clock.dtsi"
26631-
26632- enet: ethernet@61000000 {
26633- compatible = "brcm,ns2-amac";
26634- reg = <0x61000000 0x1000>,
26635- <0x61090000 0x1000>,
26636- <0x61030000 0x100>;
26637- reg-names = "amac_base", "idm_base", "nicpm_base";
26638- interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
26639- dma-coherent;
26640- phy-handle = <&gphy0>;
26641- phy-mode = "rgmii";
26642- status = "disabled";
26643- };
26644-
26645- pdc0: iproc-pdc0@612c0000 {
26646- compatible = "brcm,iproc-pdc-mbox";
26647- reg = <0x612c0000 0x445>; /* PDC FS0 regs */
26648- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
26649- #mbox-cells = <1>;
26650- dma-coherent;
26651- brcm,rx-status-len = <32>;
26652- brcm,use-bcm-hdr;
26653- };
26654-
26655- crypto0: crypto@612d0000 {
26656- compatible = "brcm,spum-crypto";
26657- reg = <0x612d0000 0x900>;
26658- mboxes = <&pdc0 0>;
26659- };
26660-
26661- pdc1: iproc-pdc1@612e0000 {
26662- compatible = "brcm,iproc-pdc-mbox";
26663- reg = <0x612e0000 0x445>; /* PDC FS1 regs */
26664- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
26665- #mbox-cells = <1>;
26666- dma-coherent;
26667- brcm,rx-status-len = <32>;
26668- brcm,use-bcm-hdr;
26669- };
26670-
26671- crypto1: crypto@612f0000 {
26672- compatible = "brcm,spum-crypto";
26673- reg = <0x612f0000 0x900>;
26674- mboxes = <&pdc1 0>;
26675- };
26676-
26677- pdc2: iproc-pdc2@61300000 {
26678- compatible = "brcm,iproc-pdc-mbox";
26679- reg = <0x61300000 0x445>; /* PDC FS2 regs */
26680- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
26681- #mbox-cells = <1>;
26682- dma-coherent;
26683- brcm,rx-status-len = <32>;
26684- brcm,use-bcm-hdr;
26685- };
26686-
26687- crypto2: crypto@61310000 {
26688- compatible = "brcm,spum-crypto";
26689- reg = <0x61310000 0x900>;
26690- mboxes = <&pdc2 0>;
26691- };
26692-
26693- pdc3: iproc-pdc3@61320000 {
26694- compatible = "brcm,iproc-pdc-mbox";
26695- reg = <0x61320000 0x445>; /* PDC FS3 regs */
26696- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
26697- #mbox-cells = <1>;
26698- dma-coherent;
26699- brcm,rx-status-len = <32>;
26700- brcm,use-bcm-hdr;
26701- };
26702-
26703- crypto3: crypto@61330000 {
26704- compatible = "brcm,spum-crypto";
26705- reg = <0x61330000 0x900>;
26706- mboxes = <&pdc3 0>;
26707- };
26708-
26709- dma0: dma@61360000 {
26710- compatible = "arm,pl330", "arm,primecell";
26711- reg = <0x61360000 0x1000>;
26712- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
26713- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
26714- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
26715- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
26716- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
26717- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
26718- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
26719- <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
26720- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
26721- #dma-cells = <1>;
26722- #dma-channels = <8>;
26723- #dma-requests = <32>;
26724- clocks = <&iprocslow>;
26725- clock-names = "apb_pclk";
26726- };
26727-
26728- smmu: mmu@64000000 {
26729- compatible = "arm,mmu-500";
26730- reg = <0x64000000 0x40000>;
26731- #global-interrupts = <2>;
26732- interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
26733- <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
26734- <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
26735- <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
26736- <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
26737- <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
26738- <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
26739- <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
26740- <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
26741- <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
26742- <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
26743- <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
26744- <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
26745- <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
26746- <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
26747- <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
26748- <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
26749- <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
26750- <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
26751- <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
26752- <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
26753- <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
26754- <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
26755- <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
26756- <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
26757- <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
26758- <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
26759- <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
26760- <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
26761- <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
26762- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
26763- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
26764- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
26765- <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
26766- #iommu-cells = <1>;
26767- };
26768-
26769- pinctrl: pinctrl@6501d130 {
26770- compatible = "brcm,ns2-pinmux";
26771- reg = <0x6501d130 0x08>,
26772- <0x660a0028 0x04>,
26773- <0x660009b0 0x40>;
26774- };
26775-
26776- gpio_aon: gpio@65024800 {
26777- compatible = "brcm,iproc-gpio";
26778- reg = <0x65024800 0x50>,
26779- <0x65024008 0x18>;
26780- ngpios = <6>;
26781- #gpio-cells = <2>;
26782- gpio-controller;
26783- };
26784-
26785- gic: interrupt-controller@65210000 {
26786- compatible = "arm,gic-400";
26787- #interrupt-cells = <3>;
26788- interrupt-controller;
26789- reg = <0x65210000 0x1000>,
26790- <0x65220000 0x1000>,
26791- <0x65240000 0x2000>,
26792- <0x65260000 0x1000>;
26793- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
26794- IRQ_TYPE_LEVEL_HIGH)>;
26795-
26796- #address-cells = <1>;
26797- #size-cells = <1>;
26798- ranges = <0 0x652e0000 0x80000>;
26799-
26800- v2m0: v2m@00000 {
26801- compatible = "arm,gic-v2m-frame";
26802- interrupt-parent = <&gic>;
26803- msi-controller;
26804- reg = <0x00000 0x1000>;
26805- arm,msi-base-spi = <72>;
26806- arm,msi-num-spis = <16>;
26807- };
26808-
26809- v2m1: v2m@10000 {
26810- compatible = "arm,gic-v2m-frame";
26811- interrupt-parent = <&gic>;
26812- msi-controller;
26813- reg = <0x10000 0x1000>;
26814- arm,msi-base-spi = <88>;
26815- arm,msi-num-spis = <16>;
26816- };
26817-
26818- v2m2: v2m@20000 {
26819- compatible = "arm,gic-v2m-frame";
26820- interrupt-parent = <&gic>;
26821- msi-controller;
26822- reg = <0x20000 0x1000>;
26823- arm,msi-base-spi = <104>;
26824- arm,msi-num-spis = <16>;
26825- };
26826-
26827- v2m3: v2m@30000 {
26828- compatible = "arm,gic-v2m-frame";
26829- interrupt-parent = <&gic>;
26830- msi-controller;
26831- reg = <0x30000 0x1000>;
26832- arm,msi-base-spi = <120>;
26833- arm,msi-num-spis = <16>;
26834- };
26835-
26836- v2m4: v2m@40000 {
26837- compatible = "arm,gic-v2m-frame";
26838- interrupt-parent = <&gic>;
26839- msi-controller;
26840- reg = <0x40000 0x1000>;
26841- arm,msi-base-spi = <136>;
26842- arm,msi-num-spis = <16>;
26843- };
26844-
26845- v2m5: v2m@50000 {
26846- compatible = "arm,gic-v2m-frame";
26847- interrupt-parent = <&gic>;
26848- msi-controller;
26849- reg = <0x50000 0x1000>;
26850- arm,msi-base-spi = <152>;
26851- arm,msi-num-spis = <16>;
26852- };
26853-
26854- v2m6: v2m@60000 {
26855- compatible = "arm,gic-v2m-frame";
26856- interrupt-parent = <&gic>;
26857- msi-controller;
26858- reg = <0x60000 0x1000>;
26859- arm,msi-base-spi = <168>;
26860- arm,msi-num-spis = <16>;
26861- };
26862-
26863- v2m7: v2m@70000 {
26864- compatible = "arm,gic-v2m-frame";
26865- interrupt-parent = <&gic>;
26866- msi-controller;
26867- reg = <0x70000 0x1000>;
26868- arm,msi-base-spi = <184>;
26869- arm,msi-num-spis = <16>;
26870- };
26871- };
26872-
26873- cci@65590000 {
26874- compatible = "arm,cci-400";
26875- #address-cells = <1>;
26876- #size-cells = <1>;
26877- reg = <0x65590000 0x1000>;
26878- ranges = <0 0x65590000 0x10000>;
26879-
26880- pmu@9000 {
26881- compatible = "arm,cci-400-pmu,r1",
26882- "arm,cci-400-pmu";
26883- reg = <0x9000 0x4000>;
26884- interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
26885- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
26886- <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
26887- <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
26888- <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
26889- <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
26890- };
26891- };
26892-
26893- usbdrd_phy: phy@66000960 {
26894- #phy-cells = <0>;
26895- compatible = "brcm,ns2-drd-phy";
26896- reg = <0x66000960 0x24>,
26897- <0x67012800 0x4>,
26898- <0x6501d148 0x4>,
26899- <0x664d0700 0x4>;
26900- reg-names = "icfg", "rst-ctrl",
26901- "crmu-ctrl", "usb2-strap";
26902- id-gpios = <&gpio_g 30 0>;
26903- vbus-gpios = <&gpio_g 31 0>;
26904- status = "disabled";
26905- };
26906-
26907- pwm: pwm@66010000 {
26908- compatible = "brcm,iproc-pwm";
26909- reg = <0x66010000 0x28>;
26910- clocks = <&osc>;
26911- #pwm-cells = <3>;
26912- status = "disabled";
26913- };
26914-
26915- mdio_mux_iproc: mdio-mux@6602023c {
26916- compatible = "brcm,mdio-mux-iproc";
26917- reg = <0x6602023c 0x14>;
26918- #address-cells = <1>;
26919- #size-cells = <0>;
26920-
26921- mdio@0 {
26922- reg = <0x0>;
26923- #address-cells = <1>;
26924- #size-cells = <0>;
26925-
26926- pci_phy0: pci-phy@0 {
26927- compatible = "brcm,ns2-pcie-phy";
26928- reg = <0x0>;
26929- #phy-cells = <0>;
26930- status = "disabled";
26931- };
26932- };
26933-
26934- mdio@7 {
26935- reg = <0x7>;
26936- #address-cells = <1>;
26937- #size-cells = <0>;
26938-
26939- pci_phy1: pci-phy@0 {
26940- compatible = "brcm,ns2-pcie-phy";
26941- reg = <0x0>;
26942- #phy-cells = <0>;
26943- status = "disabled";
26944- };
26945- };
26946-
26947- mdio@10 {
26948- reg = <0x10>;
26949- #address-cells = <1>;
26950- #size-cells = <0>;
26951- };
26952- };
26953-
26954- timer0: timer@66030000 {
26955- compatible = "arm,sp804", "arm,primecell";
26956- reg = <0x66030000 0x1000>;
26957- interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
26958- clocks = <&iprocslow>,
26959- <&iprocslow>,
26960- <&iprocslow>;
26961- clock-names = "timer1", "timer2", "apb_pclk";
26962- };
26963-
26964- timer1: timer@66040000 {
26965- compatible = "arm,sp804", "arm,primecell";
26966- reg = <0x66040000 0x1000>;
26967- interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
26968- clocks = <&iprocslow>,
26969- <&iprocslow>,
26970- <&iprocslow>;
26971- clock-names = "timer1", "timer2", "apb_pclk";
26972- };
26973-
26974- timer2: timer@66050000 {
26975- compatible = "arm,sp804", "arm,primecell";
26976- reg = <0x66050000 0x1000>;
26977- interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
26978- clocks = <&iprocslow>,
26979- <&iprocslow>,
26980- <&iprocslow>;
26981- clock-names = "timer1", "timer2", "apb_pclk";
26982- };
26983-
26984- timer3: timer@66060000 {
26985- compatible = "arm,sp804", "arm,primecell";
26986- reg = <0x66060000 0x1000>;
26987- interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
26988- clocks = <&iprocslow>,
26989- <&iprocslow>,
26990- <&iprocslow>;
26991- clock-names = "timer1", "timer2", "apb_pclk";
26992- };
26993-
26994- i2c0: i2c@66080000 {
26995- compatible = "brcm,iproc-i2c";
26996- reg = <0x66080000 0x100>;
26997- #address-cells = <1>;
26998- #size-cells = <0>;
26999- interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
27000- clock-frequency = <100000>;
27001- status = "disabled";
27002- };
27003-
27004- wdt0: watchdog@66090000 {
27005- compatible = "arm,sp805", "arm,primecell";
27006- reg = <0x66090000 0x1000>;
27007- interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
27008- clocks = <&iprocslow>, <&iprocslow>;
27009- clock-names = "wdogclk", "apb_pclk";
27010- };
27011-
27012- gpio_g: gpio@660a0000 {
27013- compatible = "brcm,iproc-gpio";
27014- reg = <0x660a0000 0x50>;
27015- ngpios = <32>;
27016- #gpio-cells = <2>;
27017- gpio-controller;
27018- interrupt-controller;
27019- interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
27020- };
27021-
27022- i2c1: i2c@660b0000 {
27023- compatible = "brcm,iproc-i2c";
27024- reg = <0x660b0000 0x100>;
27025- #address-cells = <1>;
27026- #size-cells = <0>;
27027- interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
27028- clock-frequency = <100000>;
27029- status = "disabled";
27030- };
27031-
27032- uart0: serial@66100000 {
27033- compatible = "snps,dw-apb-uart";
27034- reg = <0x66100000 0x100>;
27035- interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
27036- clocks = <&iprocslow>;
27037- reg-shift = <2>;
27038- reg-io-width = <4>;
27039- status = "disabled";
27040- };
27041-
27042- uart1: serial@66110000 {
27043- compatible = "snps,dw-apb-uart";
27044- reg = <0x66110000 0x100>;
27045- interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
27046- clocks = <&iprocslow>;
27047- reg-shift = <2>;
27048- reg-io-width = <4>;
27049- status = "disabled";
27050- };
27051-
27052- uart2: serial@66120000 {
27053- compatible = "snps,dw-apb-uart";
27054- reg = <0x66120000 0x100>;
27055- interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
27056- clocks = <&iprocslow>;
27057- reg-shift = <2>;
27058- reg-io-width = <4>;
27059- status = "disabled";
27060- };
27061-
27062- uart3: serial@66130000 {
27063- compatible = "snps,dw-apb-uart";
27064- reg = <0x66130000 0x100>;
27065- interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
27066- reg-shift = <2>;
27067- reg-io-width = <4>;
27068- clocks = <&osc>;
27069- status = "disabled";
27070- };
27071-
27072- ssp0: ssp@66180000 {
27073- compatible = "arm,pl022", "arm,primecell";
27074- reg = <0x66180000 0x1000>;
27075- interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
27076- clocks = <&iprocslow>, <&iprocslow>;
27077- clock-names = "spiclk", "apb_pclk";
27078- #address-cells = <1>;
27079- #size-cells = <0>;
27080- status = "disabled";
27081- };
27082-
27083- ssp1: ssp@66190000 {
27084- compatible = "arm,pl022", "arm,primecell";
27085- reg = <0x66190000 0x1000>;
27086- interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
27087- clocks = <&iprocslow>, <&iprocslow>;
27088- clock-names = "spiclk", "apb_pclk";
27089- #address-cells = <1>;
27090- #size-cells = <0>;
27091- status = "disabled";
27092- };
27093-
27094- hwrng: hwrng@66220000 {
27095- compatible = "brcm,iproc-rng200";
27096- reg = <0x66220000 0x28>;
27097- };
27098-
27099- sata_phy: sata_phy@663f0100 {
27100- compatible = "brcm,iproc-ns2-sata-phy";
27101- reg = <0x663f0100 0x1f00>,
27102- <0x663f004c 0x10>;
27103- reg-names = "phy", "phy-ctrl";
27104- #address-cells = <1>;
27105- #size-cells = <0>;
27106-
27107- sata_phy0: sata-phy@0 {
27108- reg = <0>;
27109- #phy-cells = <0>;
27110- status = "disabled";
27111- };
27112-
27113- sata_phy1: sata-phy@1 {
27114- reg = <1>;
27115- #phy-cells = <0>;
27116- status = "disabled";
27117- };
27118- };
27119-
27120- sata: ahci@663f2000 {
27121- compatible = "brcm,iproc-ahci", "generic-ahci";
27122- reg = <0x663f2000 0x1000>;
27123- dma-coherent;
27124- reg-names = "ahci";
27125- interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
27126- #address-cells = <1>;
27127- #size-cells = <0>;
27128- status = "disabled";
27129-
27130- sata0: sata-port@0 {
27131- reg = <0>;
27132- phys = <&sata_phy0>;
27133- phy-names = "sata-phy";
27134- };
27135-
27136- sata1: sata-port@1 {
27137- reg = <1>;
27138- phys = <&sata_phy1>;
27139- phy-names = "sata-phy";
27140- };
27141- };
27142-
27143- sdio0: sdhci@66420000 {
27144- compatible = "brcm,sdhci-iproc-cygnus";
27145- reg = <0x66420000 0x100>;
27146- interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
27147- dma-coherent;
27148- bus-width = <8>;
27149- clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
27150- status = "disabled";
27151- };
27152-
27153- sdio1: sdhci@66430000 {
27154- compatible = "brcm,sdhci-iproc-cygnus";
27155- reg = <0x66430000 0x100>;
27156- interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
27157- dma-coherent;
27158- bus-width = <8>;
27159- clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
27160- status = "disabled";
27161- };
27162-
27163- nand: nand@66460000 {
27164- compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
27165- reg = <0x66460000 0x600>,
27166- <0x67015408 0x600>,
27167- <0x66460f00 0x20>;
27168- reg-names = "nand", "iproc-idm", "iproc-ext";
27169- interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
27170-
27171- #address-cells = <1>;
27172- #size-cells = <0>;
27173-
27174- brcm,nand-has-wp;
27175- };
27176-
27177- qspi: spi@66470200 {
27178- compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
27179- reg = <0x66470200 0x184>,
27180- <0x66470000 0x124>,
27181- <0x67017408 0x004>,
27182- <0x664703a0 0x01c>;
27183- reg-names = "mspi", "bspi", "intr_regs",
27184- "intr_status_reg";
27185- interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
27186- interrupt-names = "spi_l1_intr";
27187- clocks = <&iprocmed>;
27188- clock-names = "iprocmed";
27189- num-cs = <2>;
27190- #address-cells = <1>;
27191- #size-cells = <0>;
27192- };
27193-
27194- };
27195-};
27196diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
27197index 5dca7d10253b..8862ec907fd8 100644
27198--- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
27199+++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
27200@@ -72,6 +72,78 @@ &memory { /* Default DRAM banks */
27201 <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
27202 };
27203
27204+&sata0 {
27205+ status = "okay";
27206+};
27207+
27208+&sata_phy0{
27209+ status = "okay";
27210+};
27211+
27212+&sata1 {
27213+ status = "okay";
27214+};
27215+
27216+&sata_phy1{
27217+ status = "okay";
27218+};
27219+
27220+&sata2 {
27221+ status = "okay";
27222+};
27223+
27224+&sata_phy2{
27225+ status = "okay";
27226+};
27227+
27228+&sata3 {
27229+ status = "okay";
27230+};
27231+
27232+&sata_phy3{
27233+ status = "okay";
27234+};
27235+
27236+&sata4 {
27237+ status = "okay";
27238+};
27239+
27240+&sata_phy4{
27241+ status = "okay";
27242+};
27243+
27244+&sata5 {
27245+ status = "okay";
27246+};
27247+
27248+&sata_phy5{
27249+ status = "okay";
27250+};
27251+
27252+&sata6 {
27253+ status = "okay";
27254+};
27255+
27256+&sata_phy6{
27257+ status = "okay";
27258+};
27259+
27260+&sata7 {
27261+ status = "okay";
27262+};
27263+
27264+&sata_phy7{
27265+ status = "okay";
27266+};
27267+
27268+&mdio_mux_iproc {
27269+ mdio@10 {
27270+ gphy0: eth-phy@10 {
27271+ reg = <0x10>;
27272+ };
27273+ };
27274+};
27275+
27276 &uart1 {
27277 status = "okay";
27278 };
27279@@ -102,6 +174,12 @@ pcf8574: pcf8574@20 {
27280 };
27281 };
27282
27283+&enet {
27284+ phy-mode = "rgmii-id";
27285+ phy-handle = <&gphy0>;
27286+ status = "okay";
27287+};
27288+
27289 &nand {
27290 status = "ok";
27291 nandcs@0 {
27292diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
27293index 5671669ba348..eb6f08cdbd79 100644
27294--- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
27295+++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
27296@@ -39,6 +39,10 @@ / {
27297 model = "Stingray Combo SVK (BCM958742K)";
27298 };
27299
27300+&gphy0 {
27301+ enet-phy-lane-swap;
27302+};
27303+
27304 &uart2 {
27305 status = "okay";
27306 };
27307diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
27308index 6ebe399fda6a..5084b037320f 100644
27309--- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
27310+++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
27311@@ -38,3 +38,7 @@ / {
27312 compatible = "brcm,bcm958742t", "brcm,stingray";
27313 model = "Stingray SST100 (BCM958742T)";
27314 };
27315+
27316+&gphy0 {
27317+ enet-phy-lane-swap;
27318+};
27319diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi
27320new file mode 100644
27321index 000000000000..8bf1dc6b46ca
27322--- /dev/null
27323+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi
27324@@ -0,0 +1,118 @@
27325+/*
27326+ * BSD LICENSE
27327+ *
27328+ * Copyright(c) 2016-2017 Broadcom. All rights reserved.
27329+ *
27330+ * Redistribution and use in source and binary forms, with or without
27331+ * modification, are permitted provided that the following conditions
27332+ * are met:
27333+ *
27334+ * * Redistributions of source code must retain the above copyright
27335+ * notice, this list of conditions and the following disclaimer.
27336+ * * Redistributions in binary form must reproduce the above copyright
27337+ * notice, this list of conditions and the following disclaimer in
27338+ * the documentation and/or other materials provided with the
27339+ * distribution.
27340+ * * Neither the name of Broadcom nor the names of its
27341+ * contributors may be used to endorse or promote products derived
27342+ * from this software without specific prior written permission.
27343+ *
27344+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27345+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27346+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27347+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27348+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27349+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27350+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27351+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27352+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27353+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27354+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27355+ */
27356+
27357+ fs4: fs4 {
27358+ compatible = "simple-bus";
27359+ #address-cells = <1>;
27360+ #size-cells = <1>;
27361+ ranges = <0x0 0x0 0x67000000 0x00800000>;
27362+
27363+ crypto_mbox: crypto_mbox@00000000 {
27364+ compatible = "brcm,iproc-flexrm-mbox";
27365+ reg = <0x00000000 0x200000>;
27366+ msi-parent = <&gic_its 0x4100>;
27367+ #mbox-cells = <3>;
27368+ dma-coherent;
27369+ };
27370+
27371+ raid_mbox: raid_mbox@00400000 {
27372+ compatible = "brcm,iproc-flexrm-mbox";
27373+ reg = <0x00400000 0x200000>;
27374+ dma-coherent;
27375+ msi-parent = <&gic_its 0x4300>;
27376+ #mbox-cells = <3>;
27377+ };
27378+
27379+ raid0: raid@0 {
27380+ compatible = "brcm,iproc-sba-v2";
27381+ mboxes = <&raid_mbox 0 0x1 0xff00>,
27382+ <&raid_mbox 1 0x1 0xff00>,
27383+ <&raid_mbox 2 0x1 0xff00>,
27384+ <&raid_mbox 3 0x1 0xff00>;
27385+ };
27386+
27387+ raid1: raid@1 {
27388+ compatible = "brcm,iproc-sba-v2";
27389+ mboxes = <&raid_mbox 4 0x1 0xff00>,
27390+ <&raid_mbox 5 0x1 0xff00>,
27391+ <&raid_mbox 6 0x1 0xff00>,
27392+ <&raid_mbox 7 0x1 0xff00>;
27393+ };
27394+
27395+ raid2: raid@2 {
27396+ compatible = "brcm,iproc-sba-v2";
27397+ mboxes = <&raid_mbox 8 0x1 0xff00>,
27398+ <&raid_mbox 9 0x1 0xff00>,
27399+ <&raid_mbox 10 0x1 0xff00>,
27400+ <&raid_mbox 11 0x1 0xff00>;
27401+ };
27402+
27403+ raid3: raid@3 {
27404+ compatible = "brcm,iproc-sba-v2";
27405+ mboxes = <&raid_mbox 12 0x1 0xff00>,
27406+ <&raid_mbox 13 0x1 0xff00>,
27407+ <&raid_mbox 14 0x1 0xff00>,
27408+ <&raid_mbox 15 0x1 0xff00>;
27409+ };
27410+
27411+ raid4: raid@4 {
27412+ compatible = "brcm,iproc-sba-v2";
27413+ mboxes = <&raid_mbox 16 0x1 0xff00>,
27414+ <&raid_mbox 17 0x1 0xff00>,
27415+ <&raid_mbox 18 0x1 0xff00>,
27416+ <&raid_mbox 19 0x1 0xff00>;
27417+ };
27418+
27419+ raid5: raid@5 {
27420+ compatible = "brcm,iproc-sba-v2";
27421+ mboxes = <&raid_mbox 20 0x1 0xff00>,
27422+ <&raid_mbox 21 0x1 0xff00>,
27423+ <&raid_mbox 22 0x1 0xff00>,
27424+ <&raid_mbox 23 0x1 0xff00>;
27425+ };
27426+
27427+ raid6: raid@6 {
27428+ compatible = "brcm,iproc-sba-v2";
27429+ mboxes = <&raid_mbox 24 0x1 0xff00>,
27430+ <&raid_mbox 25 0x1 0xff00>,
27431+ <&raid_mbox 26 0x1 0xff00>,
27432+ <&raid_mbox 27 0x1 0xff00>;
27433+ };
27434+
27435+ raid7: raid@7 {
27436+ compatible = "brcm,iproc-sba-v2";
27437+ mboxes = <&raid_mbox 28 0x1 0xff00>,
27438+ <&raid_mbox 29 0x1 0xff00>,
27439+ <&raid_mbox 30 0x1 0xff00>,
27440+ <&raid_mbox 31 0x1 0xff00>;
27441+ };
27442+ };
27443diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi
27444new file mode 100644
27445index 000000000000..a774709388df
27446--- /dev/null
27447+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi
27448@@ -0,0 +1,278 @@
27449+/*
27450+ * BSD LICENSE
27451+ *
27452+ * Copyright(c) 2016-2017 Broadcom. All rights reserved.
27453+ *
27454+ * Redistribution and use in source and binary forms, with or without
27455+ * modification, are permitted provided that the following conditions
27456+ * are met:
27457+ *
27458+ * * Redistributions of source code must retain the above copyright
27459+ * notice, this list of conditions and the following disclaimer.
27460+ * * Redistributions in binary form must reproduce the above copyright
27461+ * notice, this list of conditions and the following disclaimer in
27462+ * the documentation and/or other materials provided with the
27463+ * distribution.
27464+ * * Neither the name of Broadcom nor the names of its
27465+ * contributors may be used to endorse or promote products derived
27466+ * from this software without specific prior written permission.
27467+ *
27468+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27469+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27470+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27471+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27472+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27473+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27474+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27475+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27476+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27477+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27478+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27479+ */
27480+
27481+ sata {
27482+ compatible = "simple-bus";
27483+ #address-cells = <1>;
27484+ #size-cells = <1>;
27485+ ranges = <0x0 0x0 0x67d00000 0x00800000>;
27486+
27487+ sata0: ahci@00210000 {
27488+ compatible = "brcm,iproc-ahci", "generic-ahci";
27489+ reg = <0x00210000 0x1000>;
27490+ reg-names = "ahci";
27491+ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
27492+ #address-cells = <1>;
27493+ #size-cells = <0>;
27494+ status = "disabled";
27495+
27496+ sata0_port0: sata-port@0 {
27497+ reg = <0>;
27498+ phys = <&sata0_phy0>;
27499+ phy-names = "sata-phy";
27500+ };
27501+ };
27502+
27503+ sata_phy0: sata_phy@00212100 {
27504+ compatible = "brcm,iproc-sr-sata-phy";
27505+ reg = <0x00212100 0x1000>;
27506+ reg-names = "phy";
27507+ #address-cells = <1>;
27508+ #size-cells = <0>;
27509+ status = "disabled";
27510+
27511+ sata0_phy0: sata-phy@0 {
27512+ reg = <0>;
27513+ #phy-cells = <0>;
27514+ };
27515+ };
27516+
27517+ sata1: ahci@00310000 {
27518+ compatible = "brcm,iproc-ahci", "generic-ahci";
27519+ reg = <0x00310000 0x1000>;
27520+ reg-names = "ahci";
27521+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
27522+ #address-cells = <1>;
27523+ #size-cells = <0>;
27524+ status = "disabled";
27525+
27526+ sata1_port0: sata-port@0 {
27527+ reg = <0>;
27528+ phys = <&sata1_phy0>;
27529+ phy-names = "sata-phy";
27530+ };
27531+ };
27532+
27533+ sata_phy1: sata_phy@00312100 {
27534+ compatible = "brcm,iproc-sr-sata-phy";
27535+ reg = <0x00312100 0x1000>;
27536+ reg-names = "phy";
27537+ #address-cells = <1>;
27538+ #size-cells = <0>;
27539+ status = "disabled";
27540+
27541+ sata1_phy0: sata-phy@0 {
27542+ reg = <0>;
27543+ #phy-cells = <0>;
27544+ };
27545+ };
27546+
27547+ sata2: ahci@00120000 {
27548+ compatible = "brcm,iproc-ahci", "generic-ahci";
27549+ reg = <0x00120000 0x1000>;
27550+ reg-names = "ahci";
27551+ interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
27552+ #address-cells = <1>;
27553+ #size-cells = <0>;
27554+ status = "disabled";
27555+
27556+ sata2_port0: sata-port@0 {
27557+ reg = <0>;
27558+ phys = <&sata2_phy0>;
27559+ phy-names = "sata-phy";
27560+ };
27561+ };
27562+
27563+ sata_phy2: sata_phy@00122100 {
27564+ compatible = "brcm,iproc-sr-sata-phy";
27565+ reg = <0x00122100 0x1000>;
27566+ reg-names = "phy";
27567+ #address-cells = <1>;
27568+ #size-cells = <0>;
27569+ status = "disabled";
27570+
27571+ sata2_phy0: sata-phy@0 {
27572+ reg = <0>;
27573+ #phy-cells = <0>;
27574+ };
27575+ };
27576+
27577+ sata3: ahci@00130000 {
27578+ compatible = "brcm,iproc-ahci", "generic-ahci";
27579+ reg = <0x00130000 0x1000>;
27580+ reg-names = "ahci";
27581+ interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
27582+ #address-cells = <1>;
27583+ #size-cells = <0>;
27584+ status = "disabled";
27585+
27586+ sata3_port0: sata-port@0 {
27587+ reg = <0>;
27588+ phys = <&sata3_phy0>;
27589+ phy-names = "sata-phy";
27590+ };
27591+ };
27592+
27593+ sata_phy3: sata_phy@00132100 {
27594+ compatible = "brcm,iproc-sr-sata-phy";
27595+ reg = <0x00132100 0x1000>;
27596+ reg-names = "phy";
27597+ #address-cells = <1>;
27598+ #size-cells = <0>;
27599+ status = "disabled";
27600+
27601+ sata3_phy0: sata-phy@0 {
27602+ reg = <0>;
27603+ #phy-cells = <0>;
27604+ };
27605+ };
27606+
27607+ sata4: ahci@00330000 {
27608+ compatible = "brcm,iproc-ahci", "generic-ahci";
27609+ reg = <0x00330000 0x1000>;
27610+ reg-names = "ahci";
27611+ interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
27612+ #address-cells = <1>;
27613+ #size-cells = <0>;
27614+ status = "disabled";
27615+
27616+ sata4_port0: sata-port@0 {
27617+ reg = <0>;
27618+ phys = <&sata4_phy0>;
27619+ phy-names = "sata-phy";
27620+ };
27621+ };
27622+
27623+ sata_phy4: sata_phy@00332100 {
27624+ compatible = "brcm,iproc-sr-sata-phy";
27625+ reg = <0x00332100 0x1000>;
27626+ reg-names = "phy";
27627+ #address-cells = <1>;
27628+ #size-cells = <0>;
27629+ status = "disabled";
27630+
27631+ sata4_phy0: sata-phy@0 {
27632+ reg = <0>;
27633+ #phy-cells = <0>;
27634+ };
27635+ };
27636+
27637+ sata5: ahci@00400000 {
27638+ compatible = "brcm,iproc-ahci", "generic-ahci";
27639+ reg = <0x00400000 0x1000>;
27640+ reg-names = "ahci";
27641+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
27642+ #address-cells = <1>;
27643+ #size-cells = <0>;
27644+ status = "disabled";
27645+
27646+ sata5_port0: sata-port@0 {
27647+ reg = <0>;
27648+ phys = <&sata5_phy0>;
27649+ phy-names = "sata-phy";
27650+ };
27651+ };
27652+
27653+ sata_phy5: sata_phy@00402100 {
27654+ compatible = "brcm,iproc-sr-sata-phy";
27655+ reg = <0x00402100 0x1000>;
27656+ reg-names = "phy";
27657+ #address-cells = <1>;
27658+ #size-cells = <0>;
27659+ status = "disabled";
27660+
27661+ sata5_phy0: sata-phy@0 {
27662+ reg = <0>;
27663+ #phy-cells = <0>;
27664+ };
27665+ };
27666+
27667+ sata6: ahci@00410000 {
27668+ compatible = "brcm,iproc-ahci", "generic-ahci";
27669+ reg = <0x00410000 0x1000>;
27670+ reg-names = "ahci";
27671+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
27672+ #address-cells = <1>;
27673+ #size-cells = <0>;
27674+ status = "disabled";
27675+
27676+ sata6_port0: sata-port@0 {
27677+ reg = <0>;
27678+ phys = <&sata6_phy0>;
27679+ phy-names = "sata-phy";
27680+ };
27681+ };
27682+
27683+ sata_phy6: sata_phy@00412100 {
27684+ compatible = "brcm,iproc-sr-sata-phy";
27685+ reg = <0x00412100 0x1000>;
27686+ reg-names = "phy";
27687+ #address-cells = <1>;
27688+ #size-cells = <0>;
27689+ status = "disabled";
27690+
27691+ sata6_phy0: sata-phy@0 {
27692+ reg = <0>;
27693+ #phy-cells = <0>;
27694+ };
27695+ };
27696+
27697+ sata7: ahci@00420000 {
27698+ compatible = "brcm,iproc-ahci", "generic-ahci";
27699+ reg = <0x00420000 0x1000>;
27700+ reg-names = "ahci";
27701+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
27702+ #address-cells = <1>;
27703+ #size-cells = <0>;
27704+ status = "disabled";
27705+
27706+ sata7_port0: sata-port@0 {
27707+ reg = <0>;
27708+ phys = <&sata7_phy0>;
27709+ phy-names = "sata-phy";
27710+ };
27711+ };
27712+
27713+ sata_phy7: sata_phy@00422100 {
27714+ compatible = "brcm,iproc-sr-sata-phy";
27715+ reg = <0x00422100 0x1000>;
27716+ reg-names = "phy";
27717+ #address-cells = <1>;
27718+ #size-cells = <0>;
27719+ status = "disabled";
27720+
27721+ sata7_phy0: sata-phy@0 {
27722+ reg = <0>;
27723+ #phy-cells = <0>;
27724+ };
27725+ };
27726+ };
27727diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
27728index 49933cf16c92..e6f75c633623 100644
27729--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
27730+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
27731@@ -152,6 +152,12 @@ scr {
27732 #size-cells = <1>;
27733 ranges = <0x0 0x0 0x61000000 0x05000000>;
27734
27735+ ccn: ccn@00000000 {
27736+ compatible = "arm,ccn-502";
27737+ reg = <0x00000000 0x900000>;
27738+ interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
27739+ };
27740+
27741 gic: interrupt-controller@02c00000 {
27742 compatible = "arm,gic-v3";
27743 #interrupt-cells = <3>;
27744@@ -261,6 +267,9 @@ gpio_crmu: gpio@00024800 {
27745 };
27746 };
27747
27748+ #include "stingray-fs4.dtsi"
27749+ #include "stingray-sata.dtsi"
27750+
27751 hsls {
27752 compatible = "simple-bus";
27753 #address-cells = <1>;
27754@@ -269,6 +278,37 @@ hsls {
27755
27756 #include "stingray-pinctrl.dtsi"
27757
27758+ mdio_mux_iproc: mdio-mux@0002023c {
27759+ compatible = "brcm,mdio-mux-iproc";
27760+ reg = <0x0002023c 0x14>;
27761+ #address-cells = <1>;
27762+ #size-cells = <0>;
27763+
27764+ mdio@0 { /* PCIe serdes */
27765+ reg = <0x0>;
27766+ #address-cells = <1>;
27767+ #size-cells = <0>;
27768+ };
27769+
27770+ mdio@2 { /* SATA */
27771+ reg = <0x2>;
27772+ #address-cells = <1>;
27773+ #size-cells = <0>;
27774+ };
27775+
27776+ mdio@3 { /* USB */
27777+ reg = <0x3>;
27778+ #address-cells = <1>;
27779+ #size-cells = <0>;
27780+ };
27781+
27782+ mdio@10 { /* RGMII */
27783+ reg = <0x10>;
27784+ #address-cells = <1>;
27785+ #size-cells = <0>;
27786+ };
27787+ };
27788+
27789 pwm: pwm@00010000 {
27790 compatible = "brcm,iproc-pwm";
27791 reg = <0x00010000 0x1000>;
27792@@ -277,6 +317,93 @@ pwm: pwm@00010000 {
27793 status = "disabled";
27794 };
27795
27796+ timer0: timer@00030000 {
27797+ compatible = "arm,sp804", "arm,primecell";
27798+ reg = <0x00030000 0x1000>;
27799+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
27800+ clocks = <&hsls_25m_div2_clk>,
27801+ <&hsls_25m_div2_clk>,
27802+ <&hsls_div4_clk>;
27803+ clock-names = "timer1", "timer2", "apb_pclk";
27804+ status = "disabled";
27805+ };
27806+
27807+ timer1: timer@00040000 {
27808+ compatible = "arm,sp804", "arm,primecell";
27809+ reg = <0x00040000 0x1000>;
27810+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
27811+ clocks = <&hsls_25m_div2_clk>,
27812+ <&hsls_25m_div2_clk>,
27813+ <&hsls_div4_clk>;
27814+ clock-names = "timer1", "timer2", "apb_pclk";
27815+ };
27816+
27817+ timer2: timer@00050000 {
27818+ compatible = "arm,sp804", "arm,primecell";
27819+ reg = <0x00050000 0x1000>;
27820+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
27821+ clocks = <&hsls_25m_div2_clk>,
27822+ <&hsls_25m_div2_clk>,
27823+ <&hsls_div4_clk>;
27824+ clock-names = "timer1", "timer2", "apb_pclk";
27825+ status = "disabled";
27826+ };
27827+
27828+ timer3: timer@00060000 {
27829+ compatible = "arm,sp804", "arm,primecell";
27830+ reg = <0x00060000 0x1000>;
27831+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
27832+ clocks = <&hsls_25m_div2_clk>,
27833+ <&hsls_25m_div2_clk>,
27834+ <&hsls_div4_clk>;
27835+ clock-names = "timer1", "timer2", "apb_pclk";
27836+ status = "disabled";
27837+ };
27838+
27839+ timer4: timer@00070000 {
27840+ compatible = "arm,sp804", "arm,primecell";
27841+ reg = <0x00070000 0x1000>;
27842+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
27843+ clocks = <&hsls_25m_div2_clk>,
27844+ <&hsls_25m_div2_clk>,
27845+ <&hsls_div4_clk>;
27846+ clock-names = "timer1", "timer2", "apb_pclk";
27847+ status = "disabled";
27848+ };
27849+
27850+ timer5: timer@00080000 {
27851+ compatible = "arm,sp804", "arm,primecell";
27852+ reg = <0x00080000 0x1000>;
27853+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
27854+ clocks = <&hsls_25m_div2_clk>,
27855+ <&hsls_25m_div2_clk>,
27856+ <&hsls_div4_clk>;
27857+ clock-names = "timer1", "timer2", "apb_pclk";
27858+ status = "disabled";
27859+ };
27860+
27861+ timer6: timer@00090000 {
27862+ compatible = "arm,sp804", "arm,primecell";
27863+ reg = <0x00090000 0x1000>;
27864+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
27865+ clocks = <&hsls_25m_div2_clk>,
27866+ <&hsls_25m_div2_clk>,
27867+ <&hsls_div4_clk>;
27868+ clock-names = "timer1", "timer2", "apb_pclk";
27869+ status = "disabled";
27870+ };
27871+
27872+ timer7: timer@000a0000 {
27873+ compatible = "arm,sp804", "arm,primecell";
27874+ reg = <0x000a0000 0x1000>;
27875+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
27876+ clocks = <&hsls_25m_div2_clk>,
27877+ <&hsls_25m_div2_clk>,
27878+ <&hsls_div4_clk>;
27879+ clock-names = "timer1", "timer2", "apb_pclk";
27880+ status = "disabled";
27881+ };
27882+
27883 i2c0: i2c@000b0000 {
27884 compatible = "brcm,iproc-i2c";
27885 reg = <0x000b0000 0x100>;
27886@@ -424,6 +551,15 @@ dma0: dma@00310000 {
27887 iommus = <&smmu 0x6000 0x0000>;
27888 };
27889
27890+ enet: ethernet@00340000{
27891+ compatible = "brcm,amac";
27892+ reg = <0x00340000 0x1000>;
27893+ reg-names = "amac_base";
27894+ dma-coherent;
27895+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
27896+ status= "disabled";
27897+ };
27898+
27899 nand: nand@00360000 {
27900 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
27901 reg = <0x00360000 0x600>,
27902diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
27903index 105b2938082f..297597442c44 100644
27904--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
27905+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
27906@@ -307,20 +307,6 @@ &dsi {
27907 samsung,pll-clock-frequency = <24000000>;
27908 pinctrl-names = "default";
27909 pinctrl-0 = <&te_irq>;
27910-
27911- ports {
27912- #address-cells = <1>;
27913- #size-cells = <0>;
27914-
27915- port@1 {
27916- reg = <1>;
27917-
27918- dsi_out: endpoint {
27919- samsung,burst-clock-frequency = <512000000>;
27920- samsung,esc-clock-frequency = <16000000>;
27921- };
27922- };
27923- };
27924 };
27925
27926 &hdmi {
27927@@ -843,7 +829,6 @@ &i2s0 {
27928
27929 &mshc_0 {
27930 status = "okay";
27931- num-slots = <1>;
27932 mmc-hs200-1_8v;
27933 mmc-hs400-1_8v;
27934 cap-mmc-highspeed;
27935@@ -865,7 +850,6 @@ &mshc_0 {
27936
27937 &mshc_2 {
27938 status = "okay";
27939- num-slots = <1>;
27940 cap-sd-highspeed;
27941 disable-wp;
27942 cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
27943@@ -1210,8 +1194,9 @@ &usbdrd30 {
27944 status = "okay";
27945 };
27946
27947-&usbdrd_dwc3_0 {
27948+&usbdrd_dwc3 {
27949 dr_mode = "otg";
27950+ extcon = <&muic>;
27951 };
27952
27953 &usbdrd30_phy {
27954diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
27955index 727f36abf3d4..7fe994b750da 100644
27956--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
27957+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
27958@@ -1367,7 +1367,7 @@ usbdrd30: usbdrd {
27959 ranges;
27960 status = "disabled";
27961
27962- dwc3@15400000 {
27963+ usbdrd_dwc3: dwc3@15400000 {
27964 compatible = "snps,dwc3";
27965 reg = <0x15400000 0x10000>;
27966 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
27967@@ -1414,7 +1414,7 @@ usbhost30: usbhost {
27968 ranges;
27969 status = "disabled";
27970
27971- usbdrd_dwc3_0: dwc3@15a00000 {
27972+ usbhost_dwc3: dwc3@15a00000 {
27973 compatible = "snps,dwc3";
27974 reg = <0x15a00000 0x10000>;
27975 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
27976diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
27977index e5892bb0ae6e..4a8b1fb51243 100644
27978--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
27979+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
27980@@ -359,7 +359,6 @@ pmic_irq: pmic-irq {
27981
27982 &mmc_0 {
27983 status = "okay";
27984- num-slots = <1>;
27985 cap-mmc-highspeed;
27986 mmc-hs200-1_8v;
27987 non-removable;
27988@@ -375,7 +374,6 @@ &mmc_0 {
27989
27990 &mmc_2 {
27991 status = "okay";
27992- num-slots = <1>;
27993 cap-sd-highspeed;
27994 card-detect-delay = <200>;
27995 clock-frequency = <400000000>;
27996diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
27997index b1554cbd2c54..df83915d6ea6 100644
27998--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
27999+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
28000@@ -444,6 +444,15 @@ edma0: edma@2c00000 {
28001 <&clockgen 4 3>;
28002 };
28003
28004+ usb0: usb3@2f00000 {
28005+ compatible = "snps,dwc3";
28006+ reg = <0x0 0x2f00000 0x0 0x10000>;
28007+ interrupts = <0 60 0x4>;
28008+ dr_mode = "host";
28009+ snps,quirk-frame-length-adjustment = <0x20>;
28010+ snps,dis_rxdet_inp3_quirk;
28011+ };
28012+
28013 sata: sata@3200000 {
28014 compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
28015 reg = <0x0 0x3200000 0x0 0x10000>,
28016@@ -454,5 +463,13 @@ sata: sata@3200000 {
28017 dma-coherent;
28018 status = "disabled";
28019 };
28020+
28021+ usb1: usb2@8600000 {
28022+ compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
28023+ reg = <0x0 0x8600000 0x0 0x1000>;
28024+ interrupts = <0 139 0x4>;
28025+ dr_mode = "host";
28026+ phy_type = "ulpi";
28027+ };
28028 };
28029 };
28030diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
28031index 213abb72de93..0f6fcda36b9e 100644
28032--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
28033+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
28034@@ -49,7 +49,7 @@
28035 #include "fsl-ls1088a.dtsi"
28036
28037 / {
28038- model = "L1088A RDB Board";
28039+ model = "LS1088A RDB Board";
28040 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
28041 };
28042
28043diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
28044index c144d06a6e33..33797b373674 100644
28045--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
28046+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
28047@@ -52,6 +52,10 @@ / {
28048 #address-cells = <2>;
28049 #size-cells = <2>;
28050
28051+ aliases {
28052+ crypto = &crypto;
28053+ };
28054+
28055 cpus {
28056 #address-cells = <1>;
28057 #size-cells = <0>;
28058@@ -62,6 +66,7 @@ cpu0: cpu@0 {
28059 compatible = "arm,cortex-a53";
28060 reg = <0x0>;
28061 clocks = <&clockgen 1 0>;
28062+ cpu-idle-states = <&CPU_PH20>;
28063 #cooling-cells = <2>;
28064 };
28065
28066@@ -70,6 +75,7 @@ cpu1: cpu@1 {
28067 compatible = "arm,cortex-a53";
28068 reg = <0x1>;
28069 clocks = <&clockgen 1 0>;
28070+ cpu-idle-states = <&CPU_PH20>;
28071 };
28072
28073 cpu2: cpu@2 {
28074@@ -77,6 +83,7 @@ cpu2: cpu@2 {
28075 compatible = "arm,cortex-a53";
28076 reg = <0x2>;
28077 clocks = <&clockgen 1 0>;
28078+ cpu-idle-states = <&CPU_PH20>;
28079 };
28080
28081 cpu3: cpu@3 {
28082@@ -84,6 +91,7 @@ cpu3: cpu@3 {
28083 compatible = "arm,cortex-a53";
28084 reg = <0x3>;
28085 clocks = <&clockgen 1 0>;
28086+ cpu-idle-states = <&CPU_PH20>;
28087 };
28088
28089 cpu4: cpu@100 {
28090@@ -91,6 +99,7 @@ cpu4: cpu@100 {
28091 compatible = "arm,cortex-a53";
28092 reg = <0x100>;
28093 clocks = <&clockgen 1 1>;
28094+ cpu-idle-states = <&CPU_PH20>;
28095 #cooling-cells = <2>;
28096 };
28097
28098@@ -99,6 +108,7 @@ cpu5: cpu@101 {
28099 compatible = "arm,cortex-a53";
28100 reg = <0x101>;
28101 clocks = <&clockgen 1 1>;
28102+ cpu-idle-states = <&CPU_PH20>;
28103 };
28104
28105 cpu6: cpu@102 {
28106@@ -106,6 +116,7 @@ cpu6: cpu@102 {
28107 compatible = "arm,cortex-a53";
28108 reg = <0x102>;
28109 clocks = <&clockgen 1 1>;
28110+ cpu-idle-states = <&CPU_PH20>;
28111 };
28112
28113 cpu7: cpu@103 {
28114@@ -113,6 +124,16 @@ cpu7: cpu@103 {
28115 compatible = "arm,cortex-a53";
28116 reg = <0x103>;
28117 clocks = <&clockgen 1 1>;
28118+ cpu-idle-states = <&CPU_PH20>;
28119+ };
28120+
28121+ CPU_PH20: cpu-ph20 {
28122+ compatible = "arm,idle-state";
28123+ idle-state-name = "PH20";
28124+ arm,psci-suspend-param = <0x00010000>;
28125+ entry-latency-us = <1000>;
28126+ exit-latency-us = <1000>;
28127+ min-residency-us = <3000>;
28128 };
28129 };
28130
28131@@ -136,6 +157,11 @@ timer {
28132 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
28133 };
28134
28135+ psci {
28136+ compatible = "arm,psci-0.2";
28137+ method = "smc";
28138+ };
28139+
28140 sysclk: sysclk {
28141 compatible = "fixed-clock";
28142 #clock-cells = <0>;
28143@@ -369,6 +395,45 @@ sata: sata@3200000 {
28144 dma-coherent;
28145 status = "disabled";
28146 };
28147+
28148+ crypto: crypto@8000000 {
28149+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
28150+ fsl,sec-era = <8>;
28151+ #address-cells = <1>;
28152+ #size-cells = <1>;
28153+ ranges = <0x0 0x00 0x8000000 0x100000>;
28154+ reg = <0x00 0x8000000 0x0 0x100000>;
28155+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
28156+ dma-coherent;
28157+
28158+ sec_jr0: jr@10000 {
28159+ compatible = "fsl,sec-v5.0-job-ring",
28160+ "fsl,sec-v4.0-job-ring";
28161+ reg = <0x10000 0x10000>;
28162+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
28163+ };
28164+
28165+ sec_jr1: jr@20000 {
28166+ compatible = "fsl,sec-v5.0-job-ring",
28167+ "fsl,sec-v4.0-job-ring";
28168+ reg = <0x20000 0x10000>;
28169+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
28170+ };
28171+
28172+ sec_jr2: jr@30000 {
28173+ compatible = "fsl,sec-v5.0-job-ring",
28174+ "fsl,sec-v4.0-job-ring";
28175+ reg = <0x30000 0x10000>;
28176+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
28177+ };
28178+
28179+ sec_jr3: jr@40000 {
28180+ compatible = "fsl,sec-v5.0-job-ring",
28181+ "fsl,sec-v4.0-job-ring";
28182+ reg = <0x40000 0x10000>;
28183+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
28184+ };
28185+ };
28186 };
28187
28188 };
28189diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
28190index ed209cd57283..3c99608b9b45 100644
28191--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
28192+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
28193@@ -55,11 +55,6 @@ / {
28194 model = "Freescale Layerscape 2080a QDS Board";
28195 compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
28196
28197- aliases {
28198- serial0 = &serial0;
28199- serial1 = &serial1;
28200- };
28201-
28202 chosen {
28203 stdout-path = "serial0:115200n8";
28204 };
28205diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
28206index 67ec3f9c81a1..a4e7de9f70d8 100644
28207--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
28208+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
28209@@ -55,11 +55,6 @@ / {
28210 model = "Freescale Layerscape 2080a RDB Board";
28211 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
28212
28213- aliases {
28214- serial0 = &serial0;
28215- serial1 = &serial1;
28216- };
28217-
28218 chosen {
28219 stdout-path = "serial1:115200n8";
28220 };
28221diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
28222index 3ee718f0aaf8..fbbb73e571c0 100644
28223--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
28224+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
28225@@ -52,11 +52,6 @@ / {
28226 model = "Freescale Layerscape 2080a software Simulator model";
28227 compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
28228
28229- aliases {
28230- serial0 = &serial0;
28231- serial1 = &serial1;
28232- };
28233-
28234 ethernet@2210000 {
28235 compatible = "smsc,lan91c111";
28236 reg = <0x0 0x2210000 0x0 0x100>;
28237diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
28238index d789c6814e6a..8d739301e7b8 100644
28239--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
28240+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
28241@@ -53,6 +53,7 @@ cpu0: cpu@0 {
28242 compatible = "arm,cortex-a57";
28243 reg = <0x0>;
28244 clocks = <&clockgen 1 0>;
28245+ cpu-idle-states = <&CPU_PW20>;
28246 next-level-cache = <&cluster0_l2>;
28247 #cooling-cells = <2>;
28248 };
28249@@ -62,6 +63,7 @@ cpu1: cpu@1 {
28250 compatible = "arm,cortex-a57";
28251 reg = <0x1>;
28252 clocks = <&clockgen 1 0>;
28253+ cpu-idle-states = <&CPU_PW20>;
28254 next-level-cache = <&cluster0_l2>;
28255 };
28256
28257@@ -70,6 +72,7 @@ cpu2: cpu@100 {
28258 compatible = "arm,cortex-a57";
28259 reg = <0x100>;
28260 clocks = <&clockgen 1 1>;
28261+ cpu-idle-states = <&CPU_PW20>;
28262 next-level-cache = <&cluster1_l2>;
28263 #cooling-cells = <2>;
28264 };
28265@@ -79,6 +82,7 @@ cpu3: cpu@101 {
28266 compatible = "arm,cortex-a57";
28267 reg = <0x101>;
28268 clocks = <&clockgen 1 1>;
28269+ cpu-idle-states = <&CPU_PW20>;
28270 next-level-cache = <&cluster1_l2>;
28271 };
28272
28273@@ -87,6 +91,7 @@ cpu4: cpu@200 {
28274 compatible = "arm,cortex-a57";
28275 reg = <0x200>;
28276 clocks = <&clockgen 1 2>;
28277+ cpu-idle-states = <&CPU_PW20>;
28278 next-level-cache = <&cluster2_l2>;
28279 #cooling-cells = <2>;
28280 };
28281@@ -96,6 +101,7 @@ cpu5: cpu@201 {
28282 compatible = "arm,cortex-a57";
28283 reg = <0x201>;
28284 clocks = <&clockgen 1 2>;
28285+ cpu-idle-states = <&CPU_PW20>;
28286 next-level-cache = <&cluster2_l2>;
28287 };
28288
28289@@ -105,6 +111,7 @@ cpu6: cpu@300 {
28290 reg = <0x300>;
28291 clocks = <&clockgen 1 3>;
28292 next-level-cache = <&cluster3_l2>;
28293+ cpu-idle-states = <&CPU_PW20>;
28294 #cooling-cells = <2>;
28295 };
28296
28297@@ -113,6 +120,7 @@ cpu7: cpu@301 {
28298 compatible = "arm,cortex-a57";
28299 reg = <0x301>;
28300 clocks = <&clockgen 1 3>;
28301+ cpu-idle-states = <&CPU_PW20>;
28302 next-level-cache = <&cluster3_l2>;
28303 };
28304
28305@@ -131,6 +139,15 @@ cluster2_l2: l2-cache2 {
28306 cluster3_l2: l2-cache3 {
28307 compatible = "cache";
28308 };
28309+
28310+ CPU_PW20: cpu-pw20 {
28311+ compatible = "arm,idle-state";
28312+ idle-state-name = "PW20";
28313+ arm,psci-suspend-param = <0x00010000>;
28314+ entry-latency-us = <2000>;
28315+ exit-latency-us = <2000>;
28316+ min-residency-us = <6000>;
28317+ };
28318 };
28319
28320 &pcie1 {
28321diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
28322index 4a1df5ce3229..eaee5b1c3a44 100644
28323--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
28324+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
28325@@ -54,11 +54,6 @@ / {
28326 model = "Freescale Layerscape 2088A QDS Board";
28327 compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
28328
28329- aliases {
28330- serial0 = &serial0;
28331- serial1 = &serial1;
28332- };
28333-
28334 chosen {
28335 stdout-path = "serial0:115200n8";
28336 };
28337diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
28338index a76d4b4debd1..c411442cac62 100644
28339--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
28340+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
28341@@ -54,11 +54,6 @@ / {
28342 model = "Freescale Layerscape 2088A RDB Board";
28343 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
28344
28345- aliases {
28346- serial0 = &serial0;
28347- serial1 = &serial1;
28348- };
28349-
28350 chosen {
28351 stdout-path = "serial1:115200n8";
28352 };
28353diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
28354index 5c695c658056..6aa319dae396 100644
28355--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
28356+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
28357@@ -53,6 +53,7 @@ cpu0: cpu@0 {
28358 compatible = "arm,cortex-a72";
28359 reg = <0x0>;
28360 clocks = <&clockgen 1 0>;
28361+ cpu-idle-states = <&CPU_PW20>;
28362 next-level-cache = <&cluster0_l2>;
28363 #cooling-cells = <2>;
28364 };
28365@@ -62,6 +63,7 @@ cpu1: cpu@1 {
28366 compatible = "arm,cortex-a72";
28367 reg = <0x1>;
28368 clocks = <&clockgen 1 0>;
28369+ cpu-idle-states = <&CPU_PW20>;
28370 next-level-cache = <&cluster0_l2>;
28371 };
28372
28373@@ -70,6 +72,7 @@ cpu2: cpu@100 {
28374 compatible = "arm,cortex-a72";
28375 reg = <0x100>;
28376 clocks = <&clockgen 1 1>;
28377+ cpu-idle-states = <&CPU_PW20>;
28378 next-level-cache = <&cluster1_l2>;
28379 #cooling-cells = <2>;
28380 };
28381@@ -79,6 +82,7 @@ cpu3: cpu@101 {
28382 compatible = "arm,cortex-a72";
28383 reg = <0x101>;
28384 clocks = <&clockgen 1 1>;
28385+ cpu-idle-states = <&CPU_PW20>;
28386 next-level-cache = <&cluster1_l2>;
28387 };
28388
28389@@ -88,6 +92,7 @@ cpu4: cpu@200 {
28390 reg = <0x200>;
28391 clocks = <&clockgen 1 2>;
28392 next-level-cache = <&cluster2_l2>;
28393+ cpu-idle-states = <&CPU_PW20>;
28394 #cooling-cells = <2>;
28395 };
28396
28397@@ -96,6 +101,7 @@ cpu5: cpu@201 {
28398 compatible = "arm,cortex-a72";
28399 reg = <0x201>;
28400 clocks = <&clockgen 1 2>;
28401+ cpu-idle-states = <&CPU_PW20>;
28402 next-level-cache = <&cluster2_l2>;
28403 };
28404
28405@@ -104,6 +110,7 @@ cpu6: cpu@300 {
28406 compatible = "arm,cortex-a72";
28407 reg = <0x300>;
28408 clocks = <&clockgen 1 3>;
28409+ cpu-idle-states = <&CPU_PW20>;
28410 next-level-cache = <&cluster3_l2>;
28411 #cooling-cells = <2>;
28412 };
28413@@ -113,6 +120,7 @@ cpu7: cpu@301 {
28414 compatible = "arm,cortex-a72";
28415 reg = <0x301>;
28416 clocks = <&clockgen 1 3>;
28417+ cpu-idle-states = <&CPU_PW20>;
28418 next-level-cache = <&cluster3_l2>;
28419 };
28420
28421@@ -131,6 +139,15 @@ cluster2_l2: l2-cache2 {
28422 cluster3_l2: l2-cache3 {
28423 compatible = "cache";
28424 };
28425+
28426+ CPU_PW20: cpu-pw20 {
28427+ compatible = "arm,idle-state";
28428+ idle-state-name = "PW20";
28429+ arm,psci-suspend-param = <0x00010000>;
28430+ entry-latency-us = <2000>;
28431+ exit-latency-us = <2000>;
28432+ min-residency-us = <6000>;
28433+ };
28434 };
28435
28436 &pcie1 {
28437diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
28438index 94cdd3045037..4fb9a0966a84 100644
28439--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
28440+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
28441@@ -46,6 +46,7 @@
28442 */
28443
28444 #include <dt-bindings/thermal/thermal.h>
28445+#include <dt-bindings/interrupt-controller/arm-gic.h>
28446
28447 / {
28448 compatible = "fsl,ls2080a";
28449@@ -53,6 +54,12 @@ / {
28450 #address-cells = <2>;
28451 #size-cells = <2>;
28452
28453+ aliases {
28454+ crypto = &crypto;
28455+ serial0 = &serial0;
28456+ serial1 = &serial1;
28457+ };
28458+
28459 cpu: cpus {
28460 #address-cells = <1>;
28461 #size-cells = <0>;
28462@@ -118,6 +125,11 @@ pmu {
28463 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
28464 };
28465
28466+ psci {
28467+ compatible = "arm,psci-0.2";
28468+ method = "smc";
28469+ };
28470+
28471 soc {
28472 compatible = "simple-bus";
28473 #address-cells = <2>;
28474@@ -301,6 +313,45 @@ cluster4_core1_watchdog: wdt@c310000 {
28475 clock-names = "apb_pclk", "wdog_clk";
28476 };
28477
28478+ crypto: crypto@8000000 {
28479+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
28480+ fsl,sec-era = <8>;
28481+ #address-cells = <1>;
28482+ #size-cells = <1>;
28483+ ranges = <0x0 0x00 0x8000000 0x100000>;
28484+ reg = <0x00 0x8000000 0x0 0x100000>;
28485+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
28486+ dma-coherent;
28487+
28488+ sec_jr0: jr@10000 {
28489+ compatible = "fsl,sec-v5.0-job-ring",
28490+ "fsl,sec-v4.0-job-ring";
28491+ reg = <0x10000 0x10000>;
28492+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
28493+ };
28494+
28495+ sec_jr1: jr@20000 {
28496+ compatible = "fsl,sec-v5.0-job-ring",
28497+ "fsl,sec-v4.0-job-ring";
28498+ reg = <0x20000 0x10000>;
28499+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
28500+ };
28501+
28502+ sec_jr2: jr@30000 {
28503+ compatible = "fsl,sec-v5.0-job-ring",
28504+ "fsl,sec-v4.0-job-ring";
28505+ reg = <0x30000 0x10000>;
28506+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
28507+ };
28508+
28509+ sec_jr3: jr@40000 {
28510+ compatible = "fsl,sec-v5.0-job-ring",
28511+ "fsl,sec-v4.0-job-ring";
28512+ reg = <0x40000 0x10000>;
28513+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
28514+ };
28515+ };
28516+
28517 fsl_mc: fsl-mc@80c000000 {
28518 compatible = "fsl,qoriq-mc";
28519 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
28520diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
28521index 6609b0fe7a8b..fd4705c451e2 100644
28522--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
28523+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
28524@@ -39,6 +39,34 @@ memory@0 {
28525 reg = <0x0 0x0 0x0 0x0>;
28526 };
28527
28528+ reserved-memory {
28529+ #address-cells = <2>;
28530+ #size-cells = <2>;
28531+ ranges;
28532+
28533+ ramoops@32000000 {
28534+ compatible = "ramoops";
28535+ reg = <0x0 0x32000000 0x0 0x00100000>;
28536+ record-size = <0x00020000>;
28537+ console-size = <0x00020000>;
28538+ ftrace-size = <0x00020000>;
28539+ };
28540+ };
28541+
28542+ reboot-mode-syscon@32100000 {
28543+ compatible = "syscon", "simple-mfd";
28544+ reg = <0x0 0x32100000 0x0 0x00001000>;
28545+
28546+ reboot-mode {
28547+ compatible = "syscon-reboot-mode";
28548+ offset = <0x0>;
28549+
28550+ mode-normal = <0x77665501>;
28551+ mode-bootloader = <0x77665500>;
28552+ mode-recovery = <0x77665502>;
28553+ };
28554+ };
28555+
28556 keys {
28557 compatible = "gpio-keys";
28558 pinctrl-names = "default";
28559@@ -159,6 +187,13 @@ wlan_en: wlan-en-1-8v {
28560 startup-delay-us = <70000>;
28561 enable-active-high;
28562 };
28563+
28564+ firmware {
28565+ optee {
28566+ compatible = "linaro,optee-tz";
28567+ method = "smc";
28568+ };
28569+ };
28570 };
28571
28572 &i2c0 {
28573@@ -195,7 +230,7 @@ &uart4 {
28574 bluetooth {
28575 compatible = "ti,wl1837-st";
28576 enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>;
28577- max-speed = <921600>;
28578+ max-speed = <3000000>;
28579 };
28580 };
28581
28582diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
28583index c6a1961e8d55..b7a90d632959 100644
28584--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
28585+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
28586@@ -58,6 +58,8 @@ cpu0: cpu@0 {
28587 device_type = "cpu";
28588 reg = <0x0 0x0>;
28589 enable-method = "psci";
28590+ next-level-cache = <&A53_L2>;
28591+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
28592 };
28593
28594 cpu1: cpu@1 {
28595@@ -65,6 +67,8 @@ cpu1: cpu@1 {
28596 device_type = "cpu";
28597 reg = <0x0 0x1>;
28598 enable-method = "psci";
28599+ next-level-cache = <&A53_L2>;
28600+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
28601 };
28602
28603 cpu2: cpu@2 {
28604@@ -72,6 +76,8 @@ cpu2: cpu@2 {
28605 device_type = "cpu";
28606 reg = <0x0 0x2>;
28607 enable-method = "psci";
28608+ next-level-cache = <&A53_L2>;
28609+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
28610 };
28611
28612 cpu3: cpu@3 {
28613@@ -79,6 +85,8 @@ cpu3: cpu@3 {
28614 device_type = "cpu";
28615 reg = <0x0 0x3>;
28616 enable-method = "psci";
28617+ next-level-cache = <&A53_L2>;
28618+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
28619 };
28620
28621 cpu4: cpu@100 {
28622@@ -86,6 +94,12 @@ cpu4: cpu@100 {
28623 device_type = "cpu";
28624 reg = <0x0 0x100>;
28625 enable-method = "psci";
28626+ next-level-cache = <&A73_L2>;
28627+ cpu-idle-states = <
28628+ &CPU_NAP
28629+ &CPU_SLEEP
28630+ &CLUSTER_SLEEP_1
28631+ >;
28632 };
28633
28634 cpu5: cpu@101 {
28635@@ -93,6 +107,12 @@ cpu5: cpu@101 {
28636 device_type = "cpu";
28637 reg = <0x0 0x101>;
28638 enable-method = "psci";
28639+ next-level-cache = <&A73_L2>;
28640+ cpu-idle-states = <
28641+ &CPU_NAP
28642+ &CPU_SLEEP
28643+ &CLUSTER_SLEEP_1
28644+ >;
28645 };
28646
28647 cpu6: cpu@102 {
28648@@ -100,6 +120,12 @@ cpu6: cpu@102 {
28649 device_type = "cpu";
28650 reg = <0x0 0x102>;
28651 enable-method = "psci";
28652+ next-level-cache = <&A73_L2>;
28653+ cpu-idle-states = <
28654+ &CPU_NAP
28655+ &CPU_SLEEP
28656+ &CLUSTER_SLEEP_1
28657+ >;
28658 };
28659
28660 cpu7: cpu@103 {
28661@@ -107,6 +133,59 @@ cpu7: cpu@103 {
28662 device_type = "cpu";
28663 reg = <0x0 0x103>;
28664 enable-method = "psci";
28665+ next-level-cache = <&A73_L2>;
28666+ cpu-idle-states = <
28667+ &CPU_NAP
28668+ &CPU_SLEEP
28669+ &CLUSTER_SLEEP_1
28670+ >;
28671+ };
28672+
28673+ idle-states {
28674+ entry-method = "psci";
28675+
28676+ CPU_NAP: cpu-nap {
28677+ compatible = "arm,idle-state";
28678+ arm,psci-suspend-param = <0x0000001>;
28679+ entry-latency-us = <7>;
28680+ exit-latency-us = <2>;
28681+ min-residency-us = <15>;
28682+ };
28683+
28684+ CPU_SLEEP: cpu-sleep {
28685+ compatible = "arm,idle-state";
28686+ local-timer-stop;
28687+ arm,psci-suspend-param = <0x0010000>;
28688+ entry-latency-us = <40>;
28689+ exit-latency-us = <70>;
28690+ min-residency-us = <3000>;
28691+ };
28692+
28693+ CLUSTER_SLEEP_0: cluster-sleep-0 {
28694+ compatible = "arm,idle-state";
28695+ local-timer-stop;
28696+ arm,psci-suspend-param = <0x1010000>;
28697+ entry-latency-us = <500>;
28698+ exit-latency-us = <5000>;
28699+ min-residency-us = <20000>;
28700+ };
28701+
28702+ CLUSTER_SLEEP_1: cluster-sleep-1 {
28703+ compatible = "arm,idle-state";
28704+ local-timer-stop;
28705+ arm,psci-suspend-param = <0x1010000>;
28706+ entry-latency-us = <1000>;
28707+ exit-latency-us = <5000>;
28708+ min-residency-us = <20000>;
28709+ };
28710+ };
28711+
28712+ A53_L2: l2-cache0 {
28713+ compatible = "cache";
28714+ };
28715+
28716+ A73_L2: l2-cache1 {
28717+ compatible = "cache";
28718 };
28719 };
28720
28721@@ -123,6 +202,26 @@ gic: interrupt-controller@e82b0000 {
28722 IRQ_TYPE_LEVEL_HIGH)>;
28723 };
28724
28725+ pmu {
28726+ compatible = "arm,armv8-pmuv3";
28727+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
28728+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
28729+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
28730+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
28731+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
28732+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
28733+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
28734+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
28735+ interrupt-affinity = <&cpu0>,
28736+ <&cpu1>,
28737+ <&cpu2>,
28738+ <&cpu3>,
28739+ <&cpu4>,
28740+ <&cpu5>,
28741+ <&cpu6>,
28742+ <&cpu7>;
28743+ };
28744+
28745 timer {
28746 compatible = "arm,armv8-timer";
28747 interrupt-parent = <&gic>;
28748@@ -337,6 +436,19 @@ uart6: serial@fff32000 {
28749 status = "disabled";
28750 };
28751
28752+ dma0: dma@fdf30000 {
28753+ compatible = "hisilicon,k3-dma-1.0";
28754+ reg = <0x0 0xfdf30000 0x0 0x1000>;
28755+ #dma-cells = <1>;
28756+ dma-channels = <16>;
28757+ dma-requests = <32>;
28758+ dma-min-chan = <1>;
28759+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
28760+ clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
28761+ dma-no-cci;
28762+ dma-type = "hi3660_dma";
28763+ };
28764+
28765 rtc0: rtc@fff04000 {
28766 compatible = "arm,pl031", "arm,primecell";
28767 reg = <0x0 0Xfff04000 0x0 0x1000>;
28768@@ -810,6 +922,7 @@ dwmmc1: dwmmc1@ff37f000 {
28769 clock-names = "ciu", "biu";
28770 clock-frequency = <3200000>;
28771 resets = <&crg_rst 0x94 18>;
28772+ reset-names = "reset";
28773 cd-gpios = <&gpio25 3 0>;
28774 hisilicon,peripheral-syscon = <&sctrl>;
28775 pinctrl-names = "default";
28776@@ -839,6 +952,7 @@ dwmmc2: dwmmc2@ff3ff000 {
28777 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
28778 clock-names = "ciu", "biu";
28779 resets = <&crg_rst 0x94 20>;
28780+ reset-names = "reset";
28781 card-detect-delay = <200>;
28782 supports-highspeed;
28783 keep-power-in-suspend;
28784@@ -848,5 +962,21 @@ &sdio_clk_cfg_func
28785 &sdio_cfg_func>;
28786 status = "disabled";
28787 };
28788+
28789+ watchdog0: watchdog@e8a06000 {
28790+ compatible = "arm,sp805-wdt", "arm,primecell";
28791+ reg = <0x0 0xe8a06000 0x0 0x1000>;
28792+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
28793+ clocks = <&crg_ctrl HI3660_OSC32K>;
28794+ clock-names = "apb_pclk";
28795+ };
28796+
28797+ watchdog1: watchdog@e8a07000 {
28798+ compatible = "arm,sp805-wdt", "arm,primecell";
28799+ reg = <0x0 0xe8a07000 0x0 0x1000>;
28800+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
28801+ clocks = <&crg_ctrl HI3660_OSC32K>;
28802+ clock-names = "apb_pclk";
28803+ };
28804 };
28805 };
28806diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
28807index eacbe0db5bc2..02a3aa4b2165 100644
28808--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
28809+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
28810@@ -262,6 +262,12 @@ pm_ctrl: pm_ctrl@f7032000 {
28811 #clock-cells = <1>;
28812 };
28813
28814+ acpu_sctrl: acpu_sctrl@f6504000 {
28815+ compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
28816+ reg = <0x0 0xf6504000 0x0 0x1000>;
28817+ #clock-cells = <1>;
28818+ };
28819+
28820 medianoc_ade: medianoc_ade@f4520000 {
28821 compatible = "syscon";
28822 reg = <0x0 0xf4520000 0x0 0x4000>;
28823@@ -755,7 +761,8 @@ usb: usb@f72c0000 {
28824 dr_mode = "otg";
28825 g-rx-fifo-size = <512>;
28826 g-np-tx-fifo-size = <128>;
28827- g-tx-fifo-size = <128 128 128 128 128 128>;
28828+ g-tx-fifo-size = <128 128 128 128 128 128 128 128
28829+ 16 16 16 16 16 16 16>;
28830 interrupts = <0 77 0x4>;
28831 };
28832
28833diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
28834index f5d7f0889b41..fe7c16c36025 100644
28835--- a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
28836+++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
28837@@ -84,3 +84,7 @@ &eth3 {
28838 &sas1 {
28839 status = "ok";
28840 };
28841+
28842+&p0_pcie2_a {
28843+ status = "ok";
28844+};
28845diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
28846index 283d7b532e16..2c01a21c3665 100644
28847--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
28848+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
28849@@ -1534,5 +1534,27 @@ sas2: sas@a3000000 {
28850 <637 1>,<638 1>,<639 1>;
28851 status = "disabled";
28852 };
28853+
28854+ p0_pcie2_a: pcie@a00a0000 {
28855+ compatible = "hisilicon,hip07-pcie-ecam";
28856+ reg = <0 0xaf800000 0 0x800000>,
28857+ <0 0xa00a0000 0 0x10000>;
28858+ bus-range = <0xf8 0xff>;
28859+ msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>;
28860+ msi-map-mask = <0xffff>;
28861+ #address-cells = <3>;
28862+ #size-cells = <2>;
28863+ device_type = "pci";
28864+ dma-coherent;
28865+ ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000
28866+ 0x01000000 0 0 0 0xaf7f0000 0 0x10000>;
28867+ #interrupt-cells = <1>;
28868+ interrupt-map-mask = <0xf800 0 0 7>;
28869+ interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4
28870+ 0x0 0 0 2 &mbigen_pcie2_a 671 4
28871+ 0x0 0 0 3 &mbigen_pcie2_a 671 4
28872+ 0x0 0 0 4 &mbigen_pcie2_a 671 4>;
28873+ status = "disabled";
28874+ };
28875 };
28876 };
28877diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
28878index 3e6ce6c15a74..6cff81eeaae2 100644
28879--- a/arch/arm64/boot/dts/marvell/Makefile
28880+++ b/arch/arm64/boot/dts/marvell/Makefile
28881@@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
28882 dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
28883 dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
28884 dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
28885+dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
28886
28887 always := $(dtb-y)
28888 subdir-y := $(dts-dirs)
28889diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
28890index e3a136ed77b0..2ce52ba74f73 100644
28891--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
28892+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
28893@@ -45,6 +45,7 @@
28894
28895 /dts-v1/;
28896
28897+#include <dt-bindings/gpio/gpio.h>
28898 #include "armada-372x.dtsi"
28899
28900 / {
28901@@ -59,6 +60,20 @@ memory@0 {
28902 device_type = "memory";
28903 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
28904 };
28905+
28906+ vcc_sd_reg1: regulator {
28907+ compatible = "regulator-gpio";
28908+ regulator-name = "vcc_sd1";
28909+ regulator-min-microvolt = <1800000>;
28910+ regulator-max-microvolt = <3300000>;
28911+ regulator-boot-on;
28912+
28913+ gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
28914+ gpios-states = <0>;
28915+ states = <1800000 0x1
28916+ 3300000 0x0>;
28917+ enable-active-high;
28918+ };
28919 };
28920
28921 /* J9 */
28922@@ -71,6 +86,16 @@ &sata {
28923 status = "okay";
28924 };
28925
28926+/* J1 */
28927+&sdhci1 {
28928+ wp-inverted;
28929+ bus-width = <4>;
28930+ cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
28931+ marvell,pad-type = "sd";
28932+ vqmmc-supply = <&vcc_sd_reg1>;
28933+ status = "okay";
28934+};
28935+
28936 /* Exported on the micro USB connector J5 through an FTDI */
28937 &uart0 {
28938 status = "okay";
28939@@ -81,6 +106,11 @@ &usb3 {
28940 status = "okay";
28941 };
28942
28943+/* J8 */
28944+&usb2 {
28945+ status = "okay";
28946+};
28947+
28948 &mdio {
28949 switch0: switch0@1 {
28950 compatible = "marvell,mv88e6085";
28951diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
28952index 51763d674050..8c0cf7efac65 100644
28953--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
28954+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
28955@@ -81,6 +81,11 @@ timer {
28956 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
28957 };
28958
28959+ pmu {
28960+ compatible = "arm,armv8-pmuv3";
28961+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
28962+ };
28963+
28964 soc {
28965 compatible = "simple-bus";
28966 #address-cells = <2>;
28967@@ -322,7 +327,11 @@ gic: interrupt-controller@1d00000 {
28968 #interrupt-cells = <3>;
28969 interrupt-controller;
28970 reg = <0x1d00000 0x10000>, /* GICD */
28971- <0x1d40000 0x40000>; /* GICR */
28972+ <0x1d40000 0x40000>, /* GICR */
28973+ <0x1d80000 0x2000>, /* GICC */
28974+ <0x1d90000 0x2000>, /* GICH */
28975+ <0x1da0000 0x20000>; /* GICV */
28976+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
28977 };
28978 };
28979
28980diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
28981index 92c761c380d3..9c3bdf87e543 100644
28982--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
28983+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
28984@@ -44,6 +44,7 @@
28985 * Device Tree file for Marvell Armada 7040 Development board platform
28986 */
28987
28988+#include <dt-bindings/gpio/gpio.h>
28989 #include "armada-7040.dtsi"
28990
28991 / {
28992@@ -59,6 +60,34 @@ memory@00000000 {
28993 device_type = "memory";
28994 reg = <0x0 0x0 0x0 0x80000000>;
28995 };
28996+
28997+ cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
28998+ compatible = "regulator-fixed";
28999+ regulator-name = "usb3h0-vbus";
29000+ regulator-min-microvolt = <5000000>;
29001+ regulator-max-microvolt = <5000000>;
29002+ enable-active-high;
29003+ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
29004+ };
29005+
29006+ cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
29007+ compatible = "regulator-fixed";
29008+ regulator-name = "usb3h1-vbus";
29009+ regulator-min-microvolt = <5000000>;
29010+ regulator-max-microvolt = <5000000>;
29011+ enable-active-high;
29012+ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
29013+ };
29014+
29015+ cpm_usb3_0_phy: cpm-usb3-0-phy {
29016+ compatible = "usb-nop-xceiv";
29017+ vcc-supply = <&cpm_reg_usb3_0_vbus>;
29018+ };
29019+
29020+ cpm_usb3_1_phy: cpm-usb3-1-phy {
29021+ compatible = "usb-nop-xceiv";
29022+ vcc-supply = <&cpm_reg_usb3_1_vbus>;
29023+ };
29024 };
29025
29026 &i2c0 {
29027@@ -105,6 +134,14 @@ &cpm_pcie2 {
29028 &cpm_i2c0 {
29029 status = "okay";
29030 clock-frequency = <100000>;
29031+
29032+ expander0: pca9555@21 {
29033+ compatible = "nxp,pca9555";
29034+ pinctrl-names = "default";
29035+ gpio-controller;
29036+ #gpio-cells = <2>;
29037+ reg = <0x21>;
29038+ };
29039 };
29040
29041 &cpm_spi1 {
29042@@ -140,10 +177,12 @@ &cpm_sata0 {
29043 };
29044
29045 &cpm_usb3_0 {
29046+ usb-phy = <&cpm_usb3_0_phy>;
29047 status = "okay";
29048 };
29049
29050 &cpm_usb3_1 {
29051+ usb-phy = <&cpm_usb3_1_phy>;
29052 status = "okay";
29053 };
29054
29055diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
29056index 1e8f7242ed6f..0d7b2ae46610 100644
29057--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
29058+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
29059@@ -44,6 +44,7 @@
29060 * Device Tree file for Marvell Armada 8040 Development board platform
29061 */
29062
29063+#include <dt-bindings/gpio/gpio.h>
29064 #include "armada-8040.dtsi"
29065
29066 / {
29067@@ -59,6 +60,48 @@ memory@00000000 {
29068 device_type = "memory";
29069 reg = <0x0 0x0 0x0 0x80000000>;
29070 };
29071+
29072+ cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
29073+ compatible = "regulator-fixed";
29074+ regulator-name = "cpm-usb3h0-vbus";
29075+ regulator-min-microvolt = <5000000>;
29076+ regulator-max-microvolt = <5000000>;
29077+ enable-active-high;
29078+ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
29079+ };
29080+
29081+ cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
29082+ compatible = "regulator-fixed";
29083+ regulator-name = "cpm-usb3h1-vbus";
29084+ regulator-min-microvolt = <5000000>;
29085+ regulator-max-microvolt = <5000000>;
29086+ enable-active-high;
29087+ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
29088+ };
29089+
29090+ cpm_usb3_0_phy: cpm-usb3-0-phy {
29091+ compatible = "usb-nop-xceiv";
29092+ vcc-supply = <&cpm_reg_usb3_0_vbus>;
29093+ };
29094+
29095+ cpm_usb3_1_phy: cpm-usb3-1-phy {
29096+ compatible = "usb-nop-xceiv";
29097+ vcc-supply = <&cpm_reg_usb3_1_vbus>;
29098+ };
29099+
29100+ cps_reg_usb3_0_vbus: cps-usb3-0-vbus {
29101+ compatible = "regulator-fixed";
29102+ regulator-name = "cps-usb3h0-vbus";
29103+ regulator-min-microvolt = <5000000>;
29104+ regulator-max-microvolt = <5000000>;
29105+ enable-active-high;
29106+ gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
29107+ };
29108+
29109+ cps_usb3_0_phy: cps-usb3-0-phy {
29110+ compatible = "usb-nop-xceiv";
29111+ vcc-supply = <&cps_reg_usb3_0_vbus>;
29112+ };
29113 };
29114
29115 &i2c0 {
29116@@ -107,6 +150,25 @@ &cpm_pcie2 {
29117 &cpm_i2c0 {
29118 status = "okay";
29119 clock-frequency = <100000>;
29120+
29121+ /* U31 */
29122+ expander0: pca9555@21 {
29123+ compatible = "nxp,pca9555";
29124+ pinctrl-names = "default";
29125+ gpio-controller;
29126+ #gpio-cells = <2>;
29127+ reg = <0x21>;
29128+ };
29129+
29130+ /* U25 */
29131+ expander1: pca9555@25 {
29132+ compatible = "nxp,pca9555";
29133+ pinctrl-names = "default";
29134+ gpio-controller;
29135+ #gpio-cells = <2>;
29136+ reg = <0x25>;
29137+ };
29138+
29139 };
29140
29141 /* CON4 on CP0 expansion */
29142@@ -116,11 +178,13 @@ &cpm_sata0 {
29143
29144 /* CON9 on CP0 expansion */
29145 &cpm_usb3_0 {
29146+ usb-phy = <&cpm_usb3_0_phy>;
29147 status = "okay";
29148 };
29149
29150 /* CON10 on CP0 expansion */
29151 &cpm_usb3_1 {
29152+ usb-phy = <&cpm_usb3_1_phy>;
29153 status = "okay";
29154 };
29155
29156@@ -159,6 +223,7 @@ &cps_sata0 {
29157
29158 /* CON9 on CP1 expansion */
29159 &cps_usb3_0 {
29160+ usb-phy = <&cps_usb3_0_phy>;
29161 status = "okay";
29162 };
29163
29164diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
29165index 4968e731de61..acf5c7d16d79 100644
29166--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
29167+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
29168@@ -46,11 +46,17 @@
29169
29170 #include "armada-8040.dtsi"
29171
29172+#include <dt-bindings/gpio/gpio.h>
29173+
29174 / {
29175 model = "Marvell 8040 MACHIATOBin";
29176 compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
29177 "marvell,armada-ap806-quad", "marvell,armada-ap806";
29178
29179+ chosen {
29180+ stdout-path = "serial0:115200n8";
29181+ };
29182+
29183 memory@00000000 {
29184 device_type = "memory";
29185 reg = <0x0 0x0 0x0 0x80000000>;
29186@@ -77,11 +83,13 @@ v_vddo_h: regulator-1-8v {
29187
29188 v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
29189 compatible = "regulator-fixed";
29190+ enable-active-high;
29191+ gpio = <&cpm_gpio2 15 GPIO_ACTIVE_HIGH>;
29192+ pinctrl-names = "default";
29193+ pinctrl-0 = <&cpm_xhci_vbus_pins>;
29194 regulator-name = "v_5v0_usb3_hst_vbus";
29195 regulator-min-microvolt = <5000000>;
29196 regulator-max-microvolt = <5000000>;
29197- /* actually GPIO controlled, but 8k has no GPIO support yet */
29198- regulator-always-on;
29199 status = "okay";
29200 };
29201
29202@@ -112,10 +120,44 @@ &ap_sdhci0 {
29203
29204 &cpm_i2c0 {
29205 clock-frequency = <100000>;
29206+ pinctrl-names = "default";
29207+ pinctrl-0 = <&cpm_i2c0_pins>;
29208 status = "okay";
29209 };
29210
29211+&cpm_i2c1 {
29212+ clock-frequency = <100000>;
29213+ pinctrl-names = "default";
29214+ pinctrl-0 = <&cpm_i2c1_pins>;
29215+ status = "okay";
29216+
29217+ i2c-switch@70 {
29218+ compatible = "nxp,pca9548";
29219+ #address-cells = <1>;
29220+ #size-cells = <0>;
29221+ reg = <0x70>;
29222+
29223+ sfpp0_i2c: i2c@0 {
29224+ #address-cells = <1>;
29225+ #size-cells = <0>;
29226+ reg = <0>;
29227+ };
29228+ sfpp1_i2c: i2c@1 {
29229+ #address-cells = <1>;
29230+ #size-cells = <0>;
29231+ reg = <1>;
29232+ };
29233+ sfp_1g_i2c: i2c@2 {
29234+ #address-cells = <1>;
29235+ #size-cells = <0>;
29236+ reg = <2>;
29237+ };
29238+ };
29239+};
29240+
29241 &cpm_mdio {
29242+ pinctrl-names = "default";
29243+ pinctrl-0 = <&cpm_ge_mdio_pins>;
29244 status = "okay";
29245
29246 ge_phy: ethernet-phy@0 {
29247@@ -123,6 +165,67 @@ ge_phy: ethernet-phy@0 {
29248 };
29249 };
29250
29251+&cpm_pcie0 {
29252+ pinctrl-names = "default";
29253+ pinctrl-0 = <&cpm_pcie_pins>;
29254+ num-lanes = <4>;
29255+ num-viewport = <8>;
29256+ reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>;
29257+ status = "okay";
29258+};
29259+
29260+&cpm_pinctrl {
29261+ cpm_ge_mdio_pins: ge-mdio-pins {
29262+ marvell,pins = "mpp32", "mpp34";
29263+ marvell,function = "ge";
29264+ };
29265+ cpm_i2c1_pins: i2c1-pins {
29266+ marvell,pins = "mpp35", "mpp36";
29267+ marvell,function = "i2c1";
29268+ };
29269+ cpm_i2c0_pins: i2c0-pins {
29270+ marvell,pins = "mpp37", "mpp38";
29271+ marvell,function = "i2c0";
29272+ };
29273+ cpm_xhci_vbus_pins: xhci0-vbus-pins {
29274+ marvell,pins = "mpp47";
29275+ marvell,function = "gpio";
29276+ };
29277+ cpm_pcie_pins: pcie-pins {
29278+ marvell,pins = "mpp52";
29279+ marvell,function = "gpio";
29280+ };
29281+ cpm_sdhci_pins: sdhci-pins {
29282+ marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
29283+ "mpp60", "mpp61";
29284+ marvell,function = "sdio";
29285+ };
29286+};
29287+
29288+&cpm_xmdio {
29289+ status = "okay";
29290+
29291+ phy0: ethernet-phy@0 {
29292+ compatible = "ethernet-phy-ieee802.3-c45";
29293+ reg = <0>;
29294+ };
29295+
29296+ phy8: ethernet-phy@8 {
29297+ compatible = "ethernet-phy-ieee802.3-c45";
29298+ reg = <8>;
29299+ };
29300+};
29301+
29302+&cpm_ethernet {
29303+ status = "okay";
29304+};
29305+
29306+&cpm_eth0 {
29307+ status = "okay";
29308+ phy = <&phy0>;
29309+ phy-mode = "10gbase-kr";
29310+};
29311+
29312 &cpm_sata0 {
29313 /* CPM Lane 0 - U29 */
29314 status = "okay";
29315@@ -132,6 +235,8 @@ &cpm_sdhci0 {
29316 /* U6 */
29317 broken-cd;
29318 bus-width = <4>;
29319+ pinctrl-names = "default";
29320+ pinctrl-0 = <&cpm_sdhci_pins>;
29321 status = "okay";
29322 vqmmc-supply = <&v_3_3>;
29323 };
29324@@ -150,6 +255,12 @@ &cps_ethernet {
29325 status = "okay";
29326 };
29327
29328+&cps_eth0 {
29329+ status = "okay";
29330+ phy = <&phy8>;
29331+ phy-mode = "10gbase-kr";
29332+};
29333+
29334 &cps_eth1 {
29335 /* CPS Lane 0 - J5 (Gigabit RJ45) */
29336 status = "okay";
29337@@ -157,6 +268,13 @@ &cps_eth1 {
29338 phy-mode = "sgmii";
29339 };
29340
29341+&cps_pinctrl {
29342+ cps_spi1_pins: spi1-pins {
29343+ marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
29344+ marvell,function = "spi1";
29345+ };
29346+};
29347+
29348 &cps_sata0 {
29349 /* CPS Lane 1 - U32 */
29350 /* CPS Lane 3 - U31 */
29351@@ -164,6 +282,8 @@ &cps_sata0 {
29352 };
29353
29354 &cps_spi1 {
29355+ pinctrl-names = "default";
29356+ pinctrl-0 = <&cps_spi1_pins>;
29357 status = "okay";
29358
29359 spi-flash@0 {
29360diff --git a/arch/arm64/boot/dts/marvell/armada-8080-db.dts b/arch/arm64/boot/dts/marvell/armada-8080-db.dts
29361new file mode 100644
29362index 000000000000..707af833832b
29363--- /dev/null
29364+++ b/arch/arm64/boot/dts/marvell/armada-8080-db.dts
29365@@ -0,0 +1,67 @@
29366+/*
29367+ * Copyright (C) 2017 Marvell Technology Group Ltd.
29368+ *
29369+ * This file is dual-licensed: you can use it either under the terms
29370+ * of the GPLv2 or the X11 license, at your option. Note that this dual
29371+ * licensing only applies to this file, and not this project as a
29372+ * whole.
29373+ *
29374+ * a) This library is free software; you can redistribute it and/or
29375+ * modify it under the terms of the GNU General Public License as
29376+ * published by the Free Software Foundation; either version 2 of the
29377+ * License, or (at your option) any later version.
29378+ *
29379+ * This library is distributed in the hope that it will be useful,
29380+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
29381+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29382+ * GNU General Public License for more details.
29383+ *
29384+ * Or, alternatively,
29385+ *
29386+ * b) Permission is hereby granted, free of charge, to any person
29387+ * obtaining a copy of this software and associated documentation
29388+ * files (the "Software"), to deal in the Software without
29389+ * restriction, including without limitation the rights to use,
29390+ * copy, modify, merge, publish, distribute, sublicense, and/or
29391+ * sell copies of the Software, and to permit persons to whom the
29392+ * Software is furnished to do so, subject to the following
29393+ * conditions:
29394+ *
29395+ * The above copyright notice and this permission notice shall be
29396+ * included in all copies or substantial portions of the Software.
29397+ *
29398+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
29399+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
29400+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29401+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
29402+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
29403+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
29404+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29405+ * OTHER DEALINGS IN THE SOFTWARE.
29406+ */
29407+
29408+/*
29409+ * Device Tree file for Marvell Armada-8080 Development board platform
29410+ */
29411+
29412+#include "armada-8080.dtsi"
29413+
29414+/ {
29415+ model = "Marvell 8080 board";
29416+ compatible = "marvell,armada-8080-db", "marvell,armada-8080",
29417+ "marvell,armada-ap810-octa", "marvell,armada-ap810";
29418+
29419+ chosen {
29420+ stdout-path = "serial0:115200n8";
29421+ };
29422+
29423+ memory@00000000 {
29424+ device_type = "memory";
29425+ reg = <0x0 0x0 0x0 0x80000000>;
29426+ };
29427+};
29428+
29429+&uart0_ap0 {
29430+ clock-frequency = <384000>;
29431+ status = "okay";
29432+};
29433diff --git a/arch/arm64/boot/dts/marvell/armada-8080.dtsi b/arch/arm64/boot/dts/marvell/armada-8080.dtsi
29434new file mode 100644
29435index 000000000000..d5535b716735
29436--- /dev/null
29437+++ b/arch/arm64/boot/dts/marvell/armada-8080.dtsi
29438@@ -0,0 +1,53 @@
29439+/*
29440+ * Copyright (C) 2017 Marvell Technology Group Ltd.
29441+ *
29442+ * This file is dual-licensed: you can use it either under the terms
29443+ * of the GPLv2 or the X11 license, at your option. Note that this dual
29444+ * licensing only applies to this file, and not this project as a
29445+ * whole.
29446+ *
29447+ * a) This library is free software; you can redistribute it and/or
29448+ * modify it under the terms of the GNU General Public License as
29449+ * published by the Free Software Foundation; either version 2 of the
29450+ * License, or (at your option) any later version.
29451+ *
29452+ * This library is distributed in the hope that it will be useful,
29453+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
29454+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29455+ * GNU General Public License for more details.
29456+ *
29457+ * Or, alternatively,
29458+ *
29459+ * b) Permission is hereby granted, free of charge, to any person
29460+ * obtaining a copy of this software and associated documentation
29461+ * files (the "Software"), to deal in the Software without
29462+ * restriction, including without limitation the rights to use,
29463+ * copy, modify, merge, publish, distribute, sublicense, and/or
29464+ * sell copies of the Software, and to permit persons to whom the
29465+ * Software is furnished to do so, subject to the following
29466+ * conditions:
29467+ *
29468+ * The above copyright notice and this permission notice shall be
29469+ * included in all copies or substantial portions of the Software.
29470+ *
29471+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
29472+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
29473+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29474+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
29475+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
29476+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
29477+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29478+ * OTHER DEALINGS IN THE SOFTWARE.
29479+ */
29480+
29481+/*
29482+ * Device Tree file for Marvell Armada-8080 SoC, made of an AP810 OCTA.
29483+ */
29484+
29485+#include "armada-ap810-ap0-octa-core.dtsi"
29486+
29487+/ {
29488+ model = "Marvell 8080 board";
29489+ compatible = "marvell,armada-8080", "marvell,armada-ap810-octa",
29490+ "marvell,armada-ap810";
29491+};
29492diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
29493new file mode 100644
29494index 000000000000..bf1b22b70384
29495--- /dev/null
29496+++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
29497@@ -0,0 +1,104 @@
29498+/*
29499+ * Copyright (C) 2017 Marvell Technology Group Ltd.
29500+ *
29501+ * This file is dual-licensed: you can use it either under the terms
29502+ * of the GPLv2 or the X11 license, at your option. Note that this dual
29503+ * licensing only applies to this file, and not this project as a
29504+ * whole.
29505+ *
29506+ * a) This library is free software; you can redistribute it and/or
29507+ * modify it under the terms of the GNU General Public License as
29508+ * published by the Free Software Foundation; either version 2 of the
29509+ * License, or (at your option) any later version.
29510+ *
29511+ * This library is distributed in the hope that it will be useful,
29512+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
29513+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29514+ * GNU General Public License for more details.
29515+ *
29516+ * Or, alternatively,
29517+ *
29518+ * b) Permission is hereby granted, free of charge, to any person
29519+ * obtaining a copy of this software and associated documentation
29520+ * files (the "Software"), to deal in the Software without
29521+ * restriction, including without limitation the rights to use,
29522+ * copy, modify, merge, publish, distribute, sublicense, and/or
29523+ * sell copies of the Software, and to permit persons to whom the
29524+ * Software is furnished to do so, subject to the following
29525+ * conditions:
29526+ *
29527+ * The above copyright notice and this permission notice shall be
29528+ * included in all copies or substantial portions of the Software.
29529+ *
29530+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
29531+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
29532+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29533+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
29534+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
29535+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
29536+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29537+ * OTHER DEALINGS IN THE SOFTWARE.
29538+ */
29539+
29540+/*
29541+ * Device Tree file for Marvell Armada AP810 OCTA cores.
29542+ */
29543+
29544+#include "armada-ap810-ap0.dtsi"
29545+
29546+/ {
29547+ cpus {
29548+ #address-cells = <1>;
29549+ #size-cells = <0>;
29550+ compatible = "marvell,armada-ap810-octa";
29551+
29552+ cpu@000 {
29553+ device_type = "cpu";
29554+ compatible = "arm,cortex-a72", "arm,armv8";
29555+ reg = <0x000>;
29556+ enable-method = "psci";
29557+ };
29558+ cpu@001 {
29559+ device_type = "cpu";
29560+ compatible = "arm,cortex-a72", "arm,armv8";
29561+ reg = <0x001>;
29562+ enable-method = "psci";
29563+ };
29564+ cpu@100 {
29565+ device_type = "cpu";
29566+ compatible = "arm,cortex-a72", "arm,armv8";
29567+ reg = <0x100>;
29568+ enable-method = "psci";
29569+ };
29570+ cpu@101 {
29571+ device_type = "cpu";
29572+ compatible = "arm,cortex-a72", "arm,armv8";
29573+ reg = <0x101>;
29574+ enable-method = "psci";
29575+ };
29576+ cpu@200 {
29577+ device_type = "cpu";
29578+ compatible = "arm,cortex-a72", "arm,armv8";
29579+ reg = <0x200>;
29580+ enable-method = "psci";
29581+ };
29582+ cpu@201 {
29583+ device_type = "cpu";
29584+ compatible = "arm,cortex-a72", "arm,armv8";
29585+ reg = <0x201>;
29586+ enable-method = "psci";
29587+ };
29588+ cpu@300 {
29589+ device_type = "cpu";
29590+ compatible = "arm,cortex-a72", "arm,armv8";
29591+ reg = <0x300>;
29592+ enable-method = "psci";
29593+ };
29594+ cpu@301 {
29595+ device_type = "cpu";
29596+ compatible = "arm,cortex-a72", "arm,armv8";
29597+ reg = <0x301>;
29598+ enable-method = "psci";
29599+ };
29600+ };
29601+};
29602diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi
29603new file mode 100644
29604index 000000000000..7e6f039f0f80
29605--- /dev/null
29606+++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi
29607@@ -0,0 +1,163 @@
29608+/*
29609+ * Copyright (C) 2017 Marvell Technology Group Ltd.
29610+ *
29611+ * This file is dual-licensed: you can use it either under the terms
29612+ * of the GPLv2 or the X11 license, at your option. Note that this dual
29613+ * licensing only applies to this file, and not this project as a
29614+ * whole.
29615+ *
29616+ * a) This library is free software; you can redistribute it and/or
29617+ * modify it under the terms of the GNU General Public License as
29618+ * published by the Free Software Foundation; either version 2 of the
29619+ * License, or (at your option) any later version.
29620+ *
29621+ * This library is distributed in the hope that it will be useful,
29622+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
29623+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29624+ * GNU General Public License for more details.
29625+ *
29626+ * Or, alternatively,
29627+ *
29628+ * b) Permission is hereby granted, free of charge, to any person
29629+ * obtaining a copy of this software and associated documentation
29630+ * files (the "Software"), to deal in the Software without
29631+ * restriction, including without limitation the rights to use,
29632+ * copy, modify, merge, publish, distribute, sublicense, and/or
29633+ * sell copies of the Software, and to permit persons to whom the
29634+ * Software is furnished to do so, subject to the following
29635+ * conditions:
29636+ *
29637+ * The above copyright notice and this permission notice shall be
29638+ * included in all copies or substantial portions of the Software.
29639+ *
29640+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
29641+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
29642+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29643+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
29644+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
29645+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
29646+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29647+ * OTHER DEALINGS IN THE SOFTWARE.
29648+ */
29649+
29650+/*
29651+ * Device Tree file for Marvell Armada AP810.
29652+ */
29653+
29654+#include <dt-bindings/interrupt-controller/arm-gic.h>
29655+
29656+/dts-v1/;
29657+
29658+/ {
29659+ model = "Marvell Armada AP810";
29660+ compatible = "marvell,armada-ap810";
29661+ #address-cells = <2>;
29662+ #size-cells = <2>;
29663+
29664+ aliases {
29665+ serial0 = &uart0_ap0;
29666+ serial1 = &uart1_ap0;
29667+ };
29668+
29669+ psci {
29670+ compatible = "arm,psci-0.2";
29671+ method = "smc";
29672+ };
29673+
29674+ ap810-ap0 {
29675+ #address-cells = <2>;
29676+ #size-cells = <2>;
29677+ compatible = "simple-bus";
29678+ interrupt-parent = <&gic>;
29679+ ranges;
29680+
29681+ config-space@e8000000 {
29682+ #address-cells = <1>;
29683+ #size-cells = <1>;
29684+ compatible = "simple-bus";
29685+ ranges = <0x0 0x0 0xe8000000 0x4000000>;
29686+ interrupt-parent = <&gic>;
29687+
29688+ gic: interrupt-controller@3000000 {
29689+ compatible = "arm,gic-v3";
29690+ #interrupt-cells = <3>;
29691+ #address-cells = <1>;
29692+ #size-cells = <1>;
29693+ interrupt-controller;
29694+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
29695+ ranges;
29696+
29697+ reg = <0x3000000 0x10000>, /* GICD */
29698+ <0x3060000 0x100000>, /* GICR */
29699+ <0x00c0000 0x2000>, /* GICC */
29700+ <0x00d0000 0x1000>, /* GICH */
29701+ <0x00e0000 0x2000>; /* GICV */
29702+
29703+ gic_its_ap0: interrupt-controller@3040000 {
29704+ compatible = "arm,gic-v3-its";
29705+ msi-controller;
29706+ #msi-cells = <1>;
29707+ reg = <0x3040000 0x20000>;
29708+ };
29709+ };
29710+
29711+ timer {
29712+ compatible = "arm,armv8-timer";
29713+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
29714+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
29715+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
29716+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
29717+ };
29718+
29719+ xor@400000 {
29720+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
29721+ reg = <0x400000 0x1000>,
29722+ <0x410000 0x1000>;
29723+ msi-parent = <&gic_its_ap0 0xa0>;
29724+ dma-coherent;
29725+ };
29726+
29727+ xor@420000 {
29728+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
29729+ reg = <0x420000 0x1000>,
29730+ <0x430000 0x1000>;
29731+ msi-parent = <&gic_its_ap0 0xa1>;
29732+ dma-coherent;
29733+ };
29734+
29735+ xor@440000 {
29736+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
29737+ reg = <0x440000 0x1000>,
29738+ <0x450000 0x1000>;
29739+ msi-parent = <&gic_its_ap0 0xa2>;
29740+ dma-coherent;
29741+ };
29742+
29743+ xor@460000 {
29744+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
29745+ reg = <0x460000 0x1000>,
29746+ <0x470000 0x1000>;
29747+ msi-parent = <&gic_its_ap0 0xa3>;
29748+ dma-coherent;
29749+ };
29750+
29751+ uart0_ap0: serial@512000 {
29752+ compatible = "snps,dw-apb-uart";
29753+ reg = <0x512000 0x100>;
29754+ reg-shift = <2>;
29755+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
29756+ reg-io-width = <1>;
29757+ status = "disabled";
29758+ };
29759+
29760+ uart1_ap0: serial@512100 {
29761+ compatible = "snps,dw-apb-uart";
29762+ reg = <0x512100 0x100>;
29763+ reg-shift = <2>;
29764+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
29765+ reg-io-width = <1>;
29766+ status = "disabled";
29767+ };
29768+ };
29769+ };
29770+};
29771diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
29772index 4c68605675a8..8263a8a504a8 100644
29773--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
29774+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
29775@@ -65,25 +65,44 @@ cpm_ethernet: ethernet@0 {
29776 reg = <0x0 0x100000>, <0x129000 0xb000>;
29777 clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
29778 clock-names = "pp_clk", "gop_clk", "mg_clk";
29779+ marvell,system-controller = <&cpm_syscon0>;
29780 status = "disabled";
29781 dma-coherent;
29782
29783 cpm_eth0: eth0 {
29784- interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
29785+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
29786+ <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
29787+ <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
29788+ <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
29789+ <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
29790+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
29791+ "tx-cpu3", "rx-shared";
29792 port-id = <0>;
29793 gop-port-id = <0>;
29794 status = "disabled";
29795 };
29796
29797 cpm_eth1: eth1 {
29798- interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
29799+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
29800+ <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
29801+ <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
29802+ <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
29803+ <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
29804+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
29805+ "tx-cpu3", "rx-shared";
29806 port-id = <1>;
29807 gop-port-id = <2>;
29808 status = "disabled";
29809 };
29810
29811 cpm_eth2: eth2 {
29812- interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
29813+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
29814+ <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
29815+ <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
29816+ <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
29817+ <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
29818+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
29819+ "tx-cpu3", "rx-shared";
29820 port-id = <2>;
29821 gop-port-id = <3>;
29822 status = "disabled";
29823@@ -115,6 +134,13 @@ cpm_icu: interrupt-controller@1e0000 {
29824 msi-parent = <&gicp>;
29825 };
29826
29827+ cpm_rtc: rtc@284000 {
29828+ compatible = "marvell,armada-8k-rtc";
29829+ reg = <0x284000 0x20>, <0x284080 0x24>;
29830+ reg-names = "rtc", "rtc-soc";
29831+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
29832+ };
29833+
29834 cpm_syscon0: system-controller@440000 {
29835 compatible = "syscon", "simple-mfd";
29836 reg = <0x440000 0x1000>;
29837@@ -131,8 +157,12 @@ cpm_gpio1: gpio@100 {
29838 gpio-controller;
29839 #gpio-cells = <2>;
29840 gpio-ranges = <&cpm_pinctrl 0 0 32>;
29841+ interrupt-controller;
29842+ interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
29843+ <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
29844+ <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
29845+ <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
29846 status = "disabled";
29847-
29848 };
29849
29850 cpm_gpio2: gpio@140 {
29851@@ -142,26 +172,15 @@ cpm_gpio2: gpio@140 {
29852 gpio-controller;
29853 #gpio-cells = <2>;
29854 gpio-ranges = <&cpm_pinctrl 0 32 31>;
29855+ interrupt-controller;
29856+ interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
29857+ <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
29858+ <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
29859+ <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
29860 status = "disabled";
29861 };
29862 };
29863
29864- cpm_rtc: rtc@284000 {
29865- compatible = "marvell,armada-8k-rtc";
29866- reg = <0x284000 0x20>, <0x284080 0x24>;
29867- reg-names = "rtc", "rtc-soc";
29868- interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
29869- };
29870-
29871- cpm_sata0: sata@540000 {
29872- compatible = "marvell,armada-8k-ahci",
29873- "generic-ahci";
29874- reg = <0x540000 0x30000>;
29875- interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
29876- clocks = <&cpm_clk 1 15>;
29877- status = "disabled";
29878- };
29879-
29880 cpm_usb3_0: usb3@500000 {
29881 compatible = "marvell,armada-8k-xhci",
29882 "generic-xhci";
29883@@ -182,6 +201,15 @@ cpm_usb3_1: usb3@510000 {
29884 status = "disabled";
29885 };
29886
29887+ cpm_sata0: sata@540000 {
29888+ compatible = "marvell,armada-8k-ahci",
29889+ "generic-ahci";
29890+ reg = <0x540000 0x30000>;
29891+ interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
29892+ clocks = <&cpm_clk 1 15>;
29893+ status = "disabled";
29894+ };
29895+
29896 cpm_xor0: xor@6a0000 {
29897 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
29898 reg = <0x6a0000 0x1000>,
29899@@ -240,6 +268,21 @@ cpm_i2c1: i2c@701100 {
29900 status = "disabled";
29901 };
29902
29903+ cpm_nand: nand@720000 {
29904+ /*
29905+ * Due to the limiation of the pin available
29906+ * this controller is only usable on the CPM
29907+ * for A7K and on the CPS for A8K.
29908+ */
29909+ compatible = "marvell,armada370-nand";
29910+ reg = <0x720000 0x54>;
29911+ #address-cells = <1>;
29912+ #size-cells = <1>;
29913+ interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
29914+ clocks = <&cpm_clk 1 2>;
29915+ status = "disabled";
29916+ };
29917+
29918 cpm_trng: trng@760000 {
29919 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
29920 reg = <0x760000 0x7d>;
29921diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
29922index 923f354b02f0..b71ee6c83668 100644
29923--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
29924+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
29925@@ -60,37 +60,49 @@ config-space@f4000000 {
29926 compatible = "simple-bus";
29927 ranges = <0x0 0x0 0xf4000000 0x2000000>;
29928
29929- cps_rtc: rtc@284000 {
29930- compatible = "marvell,armada-8k-rtc";
29931- reg = <0x284000 0x20>, <0x284080 0x24>;
29932- reg-names = "rtc", "rtc-soc";
29933- interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
29934- };
29935-
29936 cps_ethernet: ethernet@0 {
29937 compatible = "marvell,armada-7k-pp22";
29938 reg = <0x0 0x100000>, <0x129000 0xb000>;
29939 clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
29940 clock-names = "pp_clk", "gop_clk", "mg_clk";
29941+ marvell,system-controller = <&cps_syscon0>;
29942 status = "disabled";
29943 dma-coherent;
29944
29945 cps_eth0: eth0 {
29946- interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
29947+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
29948+ <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
29949+ <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
29950+ <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
29951+ <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
29952+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
29953+ "tx-cpu3", "rx-shared";
29954 port-id = <0>;
29955 gop-port-id = <0>;
29956 status = "disabled";
29957 };
29958
29959 cps_eth1: eth1 {
29960- interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
29961+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
29962+ <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
29963+ <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
29964+ <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
29965+ <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
29966+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
29967+ "tx-cpu3", "rx-shared";
29968 port-id = <1>;
29969 gop-port-id = <2>;
29970 status = "disabled";
29971 };
29972
29973 cps_eth2: eth2 {
29974- interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
29975+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
29976+ <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
29977+ <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
29978+ <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
29979+ <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
29980+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
29981+ "tx-cpu3", "rx-shared";
29982 port-id = <2>;
29983 gop-port-id = <3>;
29984 status = "disabled";
29985@@ -122,6 +134,13 @@ cps_icu: interrupt-controller@1e0000 {
29986 msi-parent = <&gicp>;
29987 };
29988
29989+ cps_rtc: rtc@284000 {
29990+ compatible = "marvell,armada-8k-rtc";
29991+ reg = <0x284000 0x20>, <0x284080 0x24>;
29992+ reg-names = "rtc", "rtc-soc";
29993+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
29994+ };
29995+
29996 cps_syscon0: system-controller@440000 {
29997 compatible = "syscon", "simple-mfd";
29998 reg = <0x440000 0x1000>;
29999@@ -138,8 +157,12 @@ cps_gpio1: gpio@100 {
30000 gpio-controller;
30001 #gpio-cells = <2>;
30002 gpio-ranges = <&cps_pinctrl 0 0 32>;
30003+ interrupt-controller;
30004+ interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
30005+ <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
30006+ <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
30007+ <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
30008 status = "disabled";
30009-
30010 };
30011
30012 cps_gpio2: gpio@140 {
30013@@ -149,20 +172,16 @@ cps_gpio2: gpio@140 {
30014 gpio-controller;
30015 #gpio-cells = <2>;
30016 gpio-ranges = <&cps_pinctrl 0 32 31>;
30017+ interrupt-controller;
30018+ interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
30019+ <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
30020+ <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
30021+ <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
30022 status = "disabled";
30023 };
30024
30025 };
30026
30027- cps_sata0: sata@540000 {
30028- compatible = "marvell,armada-8k-ahci",
30029- "generic-ahci";
30030- reg = <0x540000 0x30000>;
30031- interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
30032- clocks = <&cps_clk 1 15>;
30033- status = "disabled";
30034- };
30035-
30036 cps_usb3_0: usb3@500000 {
30037 compatible = "marvell,armada-8k-xhci",
30038 "generic-xhci";
30039@@ -183,6 +202,15 @@ cps_usb3_1: usb3@510000 {
30040 status = "disabled";
30041 };
30042
30043+ cps_sata0: sata@540000 {
30044+ compatible = "marvell,armada-8k-ahci",
30045+ "generic-ahci";
30046+ reg = <0x540000 0x30000>;
30047+ interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
30048+ clocks = <&cps_clk 1 15>;
30049+ status = "disabled";
30050+ };
30051+
30052 cps_xor0: xor@6a0000 {
30053 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
30054 reg = <0x6a0000 0x1000>,
30055@@ -241,6 +269,21 @@ cps_i2c1: i2c@701100 {
30056 status = "disabled";
30057 };
30058
30059+ cps_nand: nand@720000 {
30060+ /*
30061+ * Due to the limiation of the pin available
30062+ * this controller is only usable on the CPM
30063+ * for A7K and on the CPS for A8K.
30064+ */
30065+ compatible = "marvell,armada370-nand";
30066+ reg = <0x720000 0x54>;
30067+ #address-cells = <1>;
30068+ #size-cells = <1>;
30069+ interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
30070+ clocks = <&cps_clk 1 2>;
30071+ status = "disabled";
30072+ };
30073+
30074 cps_trng: trng@760000 {
30075 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
30076 reg = <0x760000 0x7d>;
30077diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
30078index 015eb072ddef..151723b5c733 100644
30079--- a/arch/arm64/boot/dts/mediatek/Makefile
30080+++ b/arch/arm64/boot/dts/mediatek/Makefile
30081@@ -1,6 +1,8 @@
30082+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
30083 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
30084 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
30085 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
30086+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
30087 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
30088
30089 always := $(dtb-y)
30090diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
30091new file mode 100644
30092index 000000000000..8c804df3da4e
30093--- /dev/null
30094+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
30095@@ -0,0 +1,32 @@
30096+/*
30097+ * Copyright (c) 2017 MediaTek Inc.
30098+ * Author: YT Shen <yt.shen@mediatek.com>
30099+ *
30100+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
30101+ */
30102+
30103+/dts-v1/;
30104+#include "mt2712e.dtsi"
30105+
30106+/ {
30107+ model = "MediaTek MT2712 evaluation board";
30108+ compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
30109+
30110+ aliases {
30111+ serial0 = &uart0;
30112+ };
30113+
30114+ memory@40000000 {
30115+ device_type = "memory";
30116+ reg = <0 0x40000000 0 0x80000000>;
30117+ };
30118+
30119+ chosen {
30120+ stdout-path = "serial0:921600n8";
30121+ };
30122+};
30123+
30124+&uart0 {
30125+ status = "okay";
30126+};
30127+
30128diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
30129new file mode 100644
30130index 000000000000..57d0396b7faa
30131--- /dev/null
30132+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
30133@@ -0,0 +1,171 @@
30134+/*
30135+ * Copyright (c) 2017 MediaTek Inc.
30136+ * Author: YT Shen <yt.shen@mediatek.com>
30137+ *
30138+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
30139+ */
30140+
30141+#include <dt-bindings/interrupt-controller/irq.h>
30142+#include <dt-bindings/interrupt-controller/arm-gic.h>
30143+
30144+/ {
30145+ compatible = "mediatek,mt2712";
30146+ interrupt-parent = <&sysirq>;
30147+ #address-cells = <2>;
30148+ #size-cells = <2>;
30149+
30150+ cpus {
30151+ #address-cells = <1>;
30152+ #size-cells = <0>;
30153+
30154+ cpu-map {
30155+ cluster0 {
30156+ core0 {
30157+ cpu = <&cpu0>;
30158+ };
30159+ core1 {
30160+ cpu = <&cpu1>;
30161+ };
30162+ };
30163+
30164+ cluster1 {
30165+ core0 {
30166+ cpu = <&cpu2>;
30167+ };
30168+ };
30169+ };
30170+
30171+ cpu0: cpu@0 {
30172+ device_type = "cpu";
30173+ compatible = "arm,cortex-a35";
30174+ reg = <0x000>;
30175+ };
30176+
30177+ cpu1: cpu@1 {
30178+ device_type = "cpu";
30179+ compatible = "arm,cortex-a35";
30180+ reg = <0x001>;
30181+ enable-method = "psci";
30182+ };
30183+
30184+ cpu2: cpu@200 {
30185+ device_type = "cpu";
30186+ compatible = "arm,cortex-a72";
30187+ reg = <0x200>;
30188+ enable-method = "psci";
30189+ };
30190+ };
30191+
30192+ psci {
30193+ compatible = "arm,psci-0.2";
30194+ method = "smc";
30195+ };
30196+
30197+ baud_clk: dummy26m {
30198+ compatible = "fixed-clock";
30199+ clock-frequency = <26000000>;
30200+ #clock-cells = <0>;
30201+ };
30202+
30203+ sys_clk: dummyclk {
30204+ compatible = "fixed-clock";
30205+ clock-frequency = <26000000>;
30206+ #clock-cells = <0>;
30207+ };
30208+
30209+ timer {
30210+ compatible = "arm,armv8-timer";
30211+ interrupt-parent = <&gic>;
30212+ interrupts = <GIC_PPI 13
30213+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
30214+ <GIC_PPI 14
30215+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
30216+ <GIC_PPI 11
30217+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
30218+ <GIC_PPI 10
30219+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
30220+ };
30221+
30222+ uart5: serial@1000f000 {
30223+ compatible = "mediatek,mt2712-uart",
30224+ "mediatek,mt6577-uart";
30225+ reg = <0 0x1000f000 0 0x400>;
30226+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
30227+ clocks = <&baud_clk>, <&sys_clk>;
30228+ clock-names = "baud", "bus";
30229+ status = "disabled";
30230+ };
30231+
30232+ sysirq: interrupt-controller@10220a80 {
30233+ compatible = "mediatek,mt2712-sysirq",
30234+ "mediatek,mt6577-sysirq";
30235+ interrupt-controller;
30236+ #interrupt-cells = <3>;
30237+ interrupt-parent = <&gic>;
30238+ reg = <0 0x10220a80 0 0x40>;
30239+ };
30240+
30241+ gic: interrupt-controller@10510000 {
30242+ compatible = "arm,gic-400";
30243+ #interrupt-cells = <3>;
30244+ interrupt-parent = <&gic>;
30245+ interrupt-controller;
30246+ reg = <0 0x10510000 0 0x10000>,
30247+ <0 0x10520000 0 0x20000>,
30248+ <0 0x10540000 0 0x20000>,
30249+ <0 0x10560000 0 0x20000>;
30250+ interrupts = <GIC_PPI 9
30251+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
30252+ };
30253+
30254+ uart0: serial@11002000 {
30255+ compatible = "mediatek,mt2712-uart",
30256+ "mediatek,mt6577-uart";
30257+ reg = <0 0x11002000 0 0x400>;
30258+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
30259+ clocks = <&baud_clk>, <&sys_clk>;
30260+ clock-names = "baud", "bus";
30261+ status = "disabled";
30262+ };
30263+
30264+ uart1: serial@11003000 {
30265+ compatible = "mediatek,mt2712-uart",
30266+ "mediatek,mt6577-uart";
30267+ reg = <0 0x11003000 0 0x400>;
30268+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
30269+ clocks = <&baud_clk>, <&sys_clk>;
30270+ clock-names = "baud", "bus";
30271+ status = "disabled";
30272+ };
30273+
30274+ uart2: serial@11004000 {
30275+ compatible = "mediatek,mt2712-uart",
30276+ "mediatek,mt6577-uart";
30277+ reg = <0 0x11004000 0 0x400>;
30278+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
30279+ clocks = <&baud_clk>, <&sys_clk>;
30280+ clock-names = "baud", "bus";
30281+ status = "disabled";
30282+ };
30283+
30284+ uart3: serial@11005000 {
30285+ compatible = "mediatek,mt2712-uart",
30286+ "mediatek,mt6577-uart";
30287+ reg = <0 0x11005000 0 0x400>;
30288+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
30289+ clocks = <&baud_clk>, <&sys_clk>;
30290+ clock-names = "baud", "bus";
30291+ status = "disabled";
30292+ };
30293+
30294+ uart4: serial@11019000 {
30295+ compatible = "mediatek,mt2712-uart",
30296+ "mediatek,mt6577-uart";
30297+ reg = <0 0x11019000 0 0x400>;
30298+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
30299+ clocks = <&baud_clk>, <&sys_clk>;
30300+ clock-names = "baud", "bus";
30301+ status = "disabled";
30302+ };
30303+};
30304+
30305diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
30306index 31088a9f71de..4beaa71107d7 100644
30307--- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi
30308+++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
30309@@ -108,13 +108,6 @@ clk26m: oscillator@0 {
30310 clock-output-names = "clk26m";
30311 };
30312
30313- clk32k: oscillator@1 {
30314- compatible = "fixed-clock";
30315- #clock-cells = <0>;
30316- clock-frequency = <32000>;
30317- clock-output-names = "clk32k";
30318- };
30319-
30320 timer {
30321 compatible = "arm,armv8-timer";
30322 interrupt-parent = <&gic>;
30323@@ -147,6 +140,11 @@ scpsys: scpsys@10006000 {
30324 infracfg = <&infrasys>;
30325 };
30326
30327+ watchdog: watchdog@10007000 {
30328+ compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
30329+ reg = <0 0x10007000 0 0x100>;
30330+ };
30331+
30332 apmixedsys: apmixed@1000c000 {
30333 compatible = "mediatek,mt6797-apmixedsys";
30334 reg = <0 0x1000c000 0 0x1000>;
30335diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
30336new file mode 100644
30337index 000000000000..c08309df2cc7
30338--- /dev/null
30339+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
30340@@ -0,0 +1,27 @@
30341+/*
30342+ * Copyright (c) 2017 MediaTek Inc.
30343+ * Author: Ming Huang <ming.huang@mediatek.com>
30344+ * Sean Wang <sean.wang@mediatek.com>
30345+ *
30346+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
30347+ */
30348+
30349+/dts-v1/;
30350+#include "mt7622.dtsi"
30351+
30352+/ {
30353+ model = "MediaTek MT7622 RFB1 board";
30354+ compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
30355+
30356+ chosen {
30357+ bootargs = "console=ttyS0,115200n1";
30358+ };
30359+
30360+ memory {
30361+ reg = <0 0x40000000 0 0x3F000000>;
30362+ };
30363+};
30364+
30365+&uart0 {
30366+ status = "okay";
30367+};
30368diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
30369new file mode 100644
30370index 000000000000..b111fec2ed9d
30371--- /dev/null
30372+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
30373@@ -0,0 +1,110 @@
30374+/*
30375+ * Copyright (c) 2017 MediaTek Inc.
30376+ * Author: Ming Huang <ming.huang@mediatek.com>
30377+ * Sean Wang <sean.wang@mediatek.com>
30378+ *
30379+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
30380+ */
30381+
30382+#include <dt-bindings/interrupt-controller/irq.h>
30383+#include <dt-bindings/interrupt-controller/arm-gic.h>
30384+
30385+/ {
30386+ compatible = "mediatek,mt7622";
30387+ interrupt-parent = <&sysirq>;
30388+ #address-cells = <2>;
30389+ #size-cells = <2>;
30390+
30391+ cpus {
30392+ #address-cells = <2>;
30393+ #size-cells = <0>;
30394+
30395+ cpu0: cpu@0 {
30396+ device_type = "cpu";
30397+ compatible = "arm,cortex-a53", "arm,armv8";
30398+ reg = <0x0 0x0>;
30399+ enable-method = "psci";
30400+ clock-frequency = <1300000000>;
30401+ };
30402+
30403+ cpu1: cpu@1 {
30404+ device_type = "cpu";
30405+ compatible = "arm,cortex-a53", "arm,armv8";
30406+ reg = <0x0 0x1>;
30407+ enable-method = "psci";
30408+ clock-frequency = <1300000000>;
30409+ };
30410+ };
30411+
30412+ uart_clk: dummy25m {
30413+ compatible = "fixed-clock";
30414+ #clock-cells = <0>;
30415+ clock-frequency = <25000000>;
30416+ };
30417+
30418+ bus_clk: dummy280m {
30419+ compatible = "fixed-clock";
30420+ #clock-cells = <0>;
30421+ clock-frequency = <280000000>;
30422+ };
30423+
30424+ psci {
30425+ compatible = "arm,psci-0.2";
30426+ method = "smc";
30427+ };
30428+
30429+ reserved-memory {
30430+ #address-cells = <2>;
30431+ #size-cells = <2>;
30432+ ranges;
30433+
30434+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
30435+ secmon_reserved: secmon@43000000 {
30436+ reg = <0 0x43000000 0 0x30000>;
30437+ no-map;
30438+ };
30439+ };
30440+
30441+ timer {
30442+ compatible = "arm,armv8-timer";
30443+ interrupt-parent = <&gic>;
30444+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
30445+ IRQ_TYPE_LEVEL_HIGH)>,
30446+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
30447+ IRQ_TYPE_LEVEL_HIGH)>,
30448+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
30449+ IRQ_TYPE_LEVEL_HIGH)>,
30450+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
30451+ IRQ_TYPE_LEVEL_HIGH)>;
30452+ };
30453+
30454+ sysirq: interrupt-controller@10200620 {
30455+ compatible = "mediatek,mt7622-sysirq",
30456+ "mediatek,mt6577-sysirq";
30457+ interrupt-controller;
30458+ #interrupt-cells = <3>;
30459+ interrupt-parent = <&gic>;
30460+ reg = <0 0x10200620 0 0x20>;
30461+ };
30462+
30463+ gic: interrupt-controller@10300000 {
30464+ compatible = "arm,gic-400";
30465+ interrupt-controller;
30466+ #interrupt-cells = <3>;
30467+ interrupt-parent = <&gic>;
30468+ reg = <0 0x10310000 0 0x1000>,
30469+ <0 0x10320000 0 0x1000>,
30470+ <0 0x10340000 0 0x2000>,
30471+ <0 0x10360000 0 0x2000>;
30472+ };
30473+
30474+ uart0: serial@11002000 {
30475+ compatible = "mediatek,mt7622-uart",
30476+ "mediatek,mt6577-uart";
30477+ reg = <0 0x11002000 0 0x400>;
30478+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
30479+ clocks = <&uart_clk>, <&bus_clk>;
30480+ clock-names = "baud", "bus";
30481+ status = "disabled";
30482+ };
30483+};
30484diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
30485index cc0f02d9dd02..ff81d7e5805e 100644
30486--- a/arch/arm64/boot/dts/qcom/Makefile
30487+++ b/arch/arm64/boot/dts/qcom/Makefile
30488@@ -1,5 +1,6 @@
30489 dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
30490 dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
30491+dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
30492 dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
30493 dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
30494 dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
30495diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
30496index d94640812194..790b7775b901 100644
30497--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
30498+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
30499@@ -17,6 +17,7 @@ pinconf {
30500 function = PMIC_GPIO_FUNC_NORMAL;
30501 power-source = <PM8916_GPIO_VPH>;
30502 input-disable;
30503+ output-high;
30504 };
30505 };
30506
30507diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
30508index bd310ac1967a..1d63e6b879de 100644
30509--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
30510+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
30511@@ -88,6 +88,8 @@ adv_bridge: bridge@39 {
30512 interrupts = <31 2>;
30513
30514 adi,dsi-lanes = <4>;
30515+ clocks = <&rpmcc RPM_SMD_BB_CLK2>;
30516+ clock-names = "cec";
30517
30518 pd-gpios = <&msmgpio 32 0>;
30519
30520@@ -213,11 +215,14 @@ sdhci@07864000 {
30521 };
30522
30523 usb@78d9000 {
30524- extcon = <&usb_id>, <&usb_id>;
30525+ extcon = <&usb_id>;
30526 status = "okay";
30527 adp-disable;
30528 hnp-disable;
30529 srp-disable;
30530+ dr_mode = "host";
30531+ pinctrl-names = "default";
30532+ pinctrl-0 = <&usb_sw_sel_pm>;
30533 ulpi {
30534 phy {
30535 v1p8-supply = <&pm8916_l7>;
30536@@ -337,19 +342,11 @@ usb2513 {
30537
30538 usb_id: usb-id {
30539 compatible = "linux,extcon-usb-gpio";
30540- id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>;
30541+ vbus-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>;
30542 pinctrl-names = "default";
30543 pinctrl-0 = <&usb_id_default>;
30544 };
30545
30546- usb-switch {
30547- compatible = "toshiba,tc7usb40mu";
30548- switch-gpios = <&pm8916_gpios 4 GPIO_ACTIVE_HIGH>;
30549- extcon = <&usb_id>;
30550- pinctrl-names = "default";
30551- pinctrl-0 = <&usb_sw_sel_pm>;
30552- };
30553-
30554 hdmi-out {
30555 compatible = "hdmi-connector";
30556 type = "a";
30557diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
30558index b1142c45fdc9..8e379782597a 100644
30559--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
30560+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
30561@@ -24,4 +24,28 @@ pinconf {
30562 power-source = <PM8994_GPIO_S4>; // 1.8V
30563 };
30564 };
30565+
30566+ usb3_vbus_det_gpio: pm8996_gpio22 {
30567+ pinconf {
30568+ pins = "gpio22";
30569+ function = PMIC_GPIO_FUNC_NORMAL;
30570+ input-enable;
30571+ bias-pull-down;
30572+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
30573+ power-source = <PM8994_GPIO_S4>; // 1.8V
30574+ };
30575+ };
30576+};
30577+
30578+&pmi8994_gpios {
30579+ usb2_vbus_det_gpio: pmi8996_gpio6 {
30580+ pinconf {
30581+ pins = "gpio6";
30582+ function = PMIC_GPIO_FUNC_NORMAL;
30583+ input-enable;
30584+ bias-pull-down;
30585+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
30586+ power-source = <PM8994_GPIO_S4>; // 1.8V
30587+ };
30588+ };
30589 };
30590diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
30591index d2196fc6d739..789f3e87321e 100644
30592--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
30593+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
30594@@ -13,6 +13,7 @@
30595
30596 #include "msm8996.dtsi"
30597 #include "pm8994.dtsi"
30598+#include "pmi8994.dtsi"
30599 #include "apq8096-db820c-pins.dtsi"
30600 #include "apq8096-db820c-pmic-pins.dtsi"
30601 #include <dt-bindings/input/input.h>
30602@@ -88,6 +89,55 @@ sdhci@74a4900 {
30603 cd-gpios = <&msmgpio 38 0x1>;
30604 status = "okay";
30605 };
30606+
30607+ phy@34000 {
30608+ status = "okay";
30609+ };
30610+
30611+ phy@7410000 {
30612+ status = "okay";
30613+ };
30614+
30615+ phy@7411000 {
30616+ status = "okay";
30617+ };
30618+
30619+ phy@7412000 {
30620+ status = "okay";
30621+ };
30622+
30623+ usb@6a00000 {
30624+ status = "okay";
30625+
30626+ dwc3@6a00000 {
30627+ extcon = <&usb3_id>;
30628+ dr_mode = "otg";
30629+ };
30630+ };
30631+
30632+ usb3_id: usb3-id {
30633+ compatible = "linux,extcon-usb-gpio";
30634+ id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
30635+ pinctrl-names = "default";
30636+ pinctrl-0 = <&usb3_vbus_det_gpio>;
30637+ };
30638+
30639+ usb@7600000 {
30640+ status = "okay";
30641+
30642+ dwc3@7600000 {
30643+ extcon = <&usb2_id>;
30644+ dr_mode = "otg";
30645+ maximum-speed = "high-speed";
30646+ };
30647+ };
30648+
30649+ usb2_id: usb2-id {
30650+ compatible = "linux,extcon-usb-gpio";
30651+ id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
30652+ pinctrl-names = "default";
30653+ pinctrl-0 = <&usb2_vbus_det_gpio>;
30654+ };
30655 };
30656
30657
30658@@ -106,4 +156,152 @@ button@0 {
30659 gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
30660 };
30661 };
30662+
30663+ rpm-glink {
30664+ rpm_requests {
30665+ pm8994-regulators {
30666+ vdd_l1-supply = <&pm8994_s3>;
30667+ vdd_l2_l26_l28-supply = <&pm8994_s3>;
30668+ vdd_l3_l11-supply = <&pm8994_s3>;
30669+ vdd_l4_l27_l31-supply = <&pm8994_s3>;
30670+ vdd_l5_l7-supply = <&pm8994_s5>;
30671+ vdd_l14_l15-supply = <&pm8994_s5>;
30672+ vdd_l20_l21-supply = <&pm8994_s5>;
30673+ vdd_l25-supply = <&pm8994_s3>;
30674+
30675+ s3 {
30676+ regulator-min-microvolt = <1300000>;
30677+ regulator-max-microvolt = <1300000>;
30678+ };
30679+ s4 {
30680+ regulator-min-microvolt = <1800000>;
30681+ regulator-max-microvolt = <1800000>;
30682+ };
30683+ s5 {
30684+ regulator-min-microvolt = <2150000>;
30685+ regulator-max-microvolt = <2150000>;
30686+ };
30687+ s7 {
30688+ regulator-min-microvolt = <800000>;
30689+ regulator-max-microvolt = <800000>;
30690+ };
30691+
30692+ l1 {
30693+ regulator-min-microvolt = <1000000>;
30694+ regulator-max-microvolt = <1000000>;
30695+ };
30696+ l2 {
30697+ regulator-min-microvolt = <1250000>;
30698+ regulator-max-microvolt = <1250000>;
30699+ };
30700+ l3 {
30701+ regulator-min-microvolt = <850000>;
30702+ regulator-max-microvolt = <850000>;
30703+ };
30704+ l4 {
30705+ regulator-min-microvolt = <1225000>;
30706+ regulator-max-microvolt = <1225000>;
30707+ };
30708+ l6 {
30709+ regulator-min-microvolt = <1200000>;
30710+ regulator-max-microvolt = <1200000>;
30711+ };
30712+ l8 {
30713+ regulator-min-microvolt = <1800000>;
30714+ regulator-max-microvolt = <1800000>;
30715+ };
30716+ l9 {
30717+ regulator-min-microvolt = <1800000>;
30718+ regulator-max-microvolt = <1800000>;
30719+ };
30720+ l10 {
30721+ regulator-min-microvolt = <1800000>;
30722+ regulator-max-microvolt = <1800000>;
30723+ };
30724+ l11 {
30725+ regulator-min-microvolt = <1150000>;
30726+ regulator-max-microvolt = <1150000>;
30727+ };
30728+ l12 {
30729+ regulator-min-microvolt = <1800000>;
30730+ regulator-max-microvolt = <1800000>;
30731+ };
30732+ l13 {
30733+ regulator-min-microvolt = <1800000>;
30734+ regulator-max-microvolt = <2950000>;
30735+ };
30736+ l14 {
30737+ regulator-min-microvolt = <1800000>;
30738+ regulator-max-microvolt = <1800000>;
30739+ };
30740+ l15 {
30741+ regulator-min-microvolt = <1800000>;
30742+ regulator-max-microvolt = <1800000>;
30743+ };
30744+ l16 {
30745+ regulator-min-microvolt = <2700000>;
30746+ regulator-max-microvolt = <2700000>;
30747+ };
30748+ l17 {
30749+ regulator-min-microvolt = <2500000>;
30750+ regulator-max-microvolt = <2500000>;
30751+ };
30752+ l18 {
30753+ regulator-min-microvolt = <2700000>;
30754+ regulator-max-microvolt = <2900000>;
30755+ };
30756+ l19 {
30757+ regulator-min-microvolt = <3000000>;
30758+ regulator-max-microvolt = <3000000>;
30759+ };
30760+ l20 {
30761+ regulator-min-microvolt = <2950000>;
30762+ regulator-max-microvolt = <2950000>;
30763+ regulator-allow-set-load;
30764+ };
30765+ l21 {
30766+ regulator-min-microvolt = <2950000>;
30767+ regulator-max-microvolt = <2950000>;
30768+ };
30769+ l22 {
30770+ regulator-min-microvolt = <3300000>;
30771+ regulator-max-microvolt = <3300000>;
30772+ };
30773+ l23 {
30774+ regulator-min-microvolt = <2800000>;
30775+ regulator-max-microvolt = <2800000>;
30776+ };
30777+ l24 {
30778+ regulator-min-microvolt = <3075000>;
30779+ regulator-max-microvolt = <3075000>;
30780+ };
30781+ l25 {
30782+ regulator-min-microvolt = <1200000>;
30783+ regulator-max-microvolt = <1200000>;
30784+ regulator-allow-set-load;
30785+ };
30786+ l27 {
30787+ regulator-min-microvolt = <1000000>;
30788+ regulator-max-microvolt = <1000000>;
30789+ };
30790+ l28 {
30791+ regulator-min-microvolt = <925000>;
30792+ regulator-max-microvolt = <925000>;
30793+ regulator-allow-set-load;
30794+ };
30795+ l29 {
30796+ regulator-min-microvolt = <2800000>;
30797+ regulator-max-microvolt = <2800000>;
30798+ };
30799+ l30 {
30800+ regulator-min-microvolt = <1800000>;
30801+ regulator-max-microvolt = <1800000>;
30802+ };
30803+ l32 {
30804+ regulator-min-microvolt = <1800000>;
30805+ regulator-max-microvolt = <1800000>;
30806+ };
30807+ };
30808+ };
30809+ };
30810 };
30811diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
30812new file mode 100644
30813index 000000000000..6a838b5d321e
30814--- /dev/null
30815+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
30816@@ -0,0 +1,52 @@
30817+/dts-v1/;
30818+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
30819+ *
30820+ * This program is free software; you can redistribute it and/or modify
30821+ * it under the terms of the GNU General Public License version 2 and
30822+ * only version 2 as published by the Free Software Foundation.
30823+ *
30824+ * This program is distributed in the hope that it will be useful,
30825+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
30826+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30827+ * GNU General Public License for more details.
30828+ */
30829+#include "ipq8074.dtsi"
30830+
30831+/ {
30832+ #address-cells = <0x2>;
30833+ #size-cells = <0x2>;
30834+ model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
30835+ compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
30836+ interrupt-parent = <&intc>;
30837+
30838+ aliases {
30839+ serial0 = &blsp1_uart5;
30840+ };
30841+
30842+ chosen {
30843+ stdout-path = "serial0";
30844+ };
30845+
30846+ memory {
30847+ device_type = "memory";
30848+ reg = <0x0 0x40000000 0x0 0x20000000>;
30849+ };
30850+
30851+ soc {
30852+ pinctrl@1000000 {
30853+ serial_4_pins: serial4_pinmux {
30854+ mux {
30855+ pins = "gpio23", "gpio24";
30856+ function = "blsp4_uart1";
30857+ bias-disable;
30858+ };
30859+ };
30860+ };
30861+
30862+ serial@78b3000 {
30863+ pinctrl-0 = <&serial_4_pins>;
30864+ pinctrl-names = "default";
30865+ status = "ok";
30866+ };
30867+ };
30868+};
30869diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
30870new file mode 100644
30871index 000000000000..2bc5dec5614d
30872--- /dev/null
30873+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
30874@@ -0,0 +1,194 @@
30875+/*
30876+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
30877+ *
30878+ * This program is free software; you can redistribute it and/or modify
30879+ * it under the terms of the GNU General Public License version 2 and
30880+ * only version 2 as published by the Free Software Foundation.
30881+ *
30882+ * This program is distributed in the hope that it will be useful,
30883+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
30884+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30885+ * GNU General Public License for more details.
30886+ */
30887+
30888+#include <dt-bindings/interrupt-controller/arm-gic.h>
30889+#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
30890+
30891+/ {
30892+ model = "Qualcomm Technologies, Inc. IPQ8074";
30893+ compatible = "qcom,ipq8074";
30894+
30895+ soc: soc {
30896+ #address-cells = <0x1>;
30897+ #size-cells = <0x1>;
30898+ ranges = <0 0 0 0xffffffff>;
30899+ compatible = "simple-bus";
30900+
30901+ pinctrl@1000000 {
30902+ compatible = "qcom,ipq8074-pinctrl";
30903+ reg = <0x1000000 0x300000>;
30904+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
30905+ gpio-controller;
30906+ #gpio-cells = <0x2>;
30907+ interrupt-controller;
30908+ #interrupt-cells = <0x2>;
30909+ };
30910+
30911+ intc: interrupt-controller@b000000 {
30912+ compatible = "qcom,msm-qgic2";
30913+ interrupt-controller;
30914+ #interrupt-cells = <0x3>;
30915+ reg = <0xb000000 0x1000>, <0xb002000 0x1000>;
30916+ };
30917+
30918+ timer {
30919+ compatible = "arm,armv8-timer";
30920+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
30921+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
30922+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
30923+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
30924+ };
30925+
30926+ timer@b120000 {
30927+ #address-cells = <1>;
30928+ #size-cells = <1>;
30929+ ranges;
30930+ compatible = "arm,armv7-timer-mem";
30931+ reg = <0xb120000 0x1000>;
30932+ clock-frequency = <19200000>;
30933+
30934+ frame@b120000 {
30935+ frame-number = <0>;
30936+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
30937+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
30938+ reg = <0xb121000 0x1000>,
30939+ <0xb122000 0x1000>;
30940+ };
30941+
30942+ frame@b123000 {
30943+ frame-number = <1>;
30944+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
30945+ reg = <0xb123000 0x1000>;
30946+ status = "disabled";
30947+ };
30948+
30949+ frame@b124000 {
30950+ frame-number = <2>;
30951+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
30952+ reg = <0xb124000 0x1000>;
30953+ status = "disabled";
30954+ };
30955+
30956+ frame@b125000 {
30957+ frame-number = <3>;
30958+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
30959+ reg = <0xb125000 0x1000>;
30960+ status = "disabled";
30961+ };
30962+
30963+ frame@b126000 {
30964+ frame-number = <4>;
30965+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
30966+ reg = <0xb126000 0x1000>;
30967+ status = "disabled";
30968+ };
30969+
30970+ frame@b127000 {
30971+ frame-number = <5>;
30972+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
30973+ reg = <0xb127000 0x1000>;
30974+ status = "disabled";
30975+ };
30976+
30977+ frame@b128000 {
30978+ frame-number = <6>;
30979+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
30980+ reg = <0xb128000 0x1000>;
30981+ status = "disabled";
30982+ };
30983+ };
30984+
30985+ gcc: gcc@1800000 {
30986+ compatible = "qcom,gcc-ipq8074";
30987+ reg = <0x1800000 0x80000>;
30988+ #clock-cells = <0x1>;
30989+ #reset-cells = <0x1>;
30990+ };
30991+
30992+ blsp1_uart5: serial@78b3000 {
30993+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
30994+ reg = <0x78b3000 0x200>;
30995+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
30996+ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
30997+ <&gcc GCC_BLSP1_AHB_CLK>;
30998+ clock-names = "core", "iface";
30999+ status = "disabled";
31000+ };
31001+ };
31002+
31003+ cpus {
31004+ #address-cells = <0x1>;
31005+ #size-cells = <0x0>;
31006+
31007+ CPU0: cpu@0 {
31008+ device_type = "cpu";
31009+ compatible = "arm,cortex-a53", "arm,armv8";
31010+ reg = <0x0>;
31011+ next-level-cache = <&L2_0>;
31012+ enable-method = "psci";
31013+ };
31014+
31015+ CPU1: cpu@1 {
31016+ device_type = "cpu";
31017+ compatible = "arm,cortex-a53", "arm,armv8";
31018+ enable-method = "psci";
31019+ reg = <0x1>;
31020+ next-level-cache = <&L2_0>;
31021+ };
31022+
31023+ CPU2: cpu@2 {
31024+ device_type = "cpu";
31025+ compatible = "arm,cortex-a53", "arm,armv8";
31026+ enable-method = "psci";
31027+ reg = <0x2>;
31028+ next-level-cache = <&L2_0>;
31029+ };
31030+
31031+ CPU3: cpu@3 {
31032+ device_type = "cpu";
31033+ compatible = "arm,cortex-a53", "arm,armv8";
31034+ enable-method = "psci";
31035+ reg = <0x3>;
31036+ next-level-cache = <&L2_0>;
31037+ };
31038+
31039+ L2_0: l2-cache {
31040+ compatible = "cache";
31041+ cache-level = <0x2>;
31042+ };
31043+ };
31044+
31045+ psci {
31046+ compatible = "arm,psci-1.0";
31047+ method = "smc";
31048+ };
31049+
31050+ pmu {
31051+ compatible = "arm,armv8-pmuv3";
31052+ interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
31053+ };
31054+
31055+ clocks {
31056+ sleep_clk: sleep_clk {
31057+ compatible = "fixed-clock";
31058+ clock-frequency = <32000>;
31059+ #clock-cells = <0>;
31060+ };
31061+
31062+ xo: xo {
31063+ compatible = "fixed-clock";
31064+ clock-frequency = <19200000>;
31065+ #clock-cells = <0>;
31066+ };
31067+ };
31068+};
31069diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
31070index 039991f80831..dc3817593e14 100644
31071--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
31072+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
31073@@ -88,6 +88,11 @@ wcnss_mem: wcnss@89300000 {
31074 no-map;
31075 };
31076
31077+ venus_mem: venus@89900000 {
31078+ reg = <0x0 0x89900000 0x0 0x600000>;
31079+ no-map;
31080+ };
31081+
31082 mba_mem: mba@8ea00000 {
31083 no-map;
31084 reg = <0 0x8ea00000 0 0x100000>;
31085@@ -204,6 +209,17 @@ cpu_crit1: trip1 {
31086
31087 };
31088
31089+ gpu_opp_table: opp_table {
31090+ compatible = "operating-points-v2";
31091+
31092+ opp-400000000 {
31093+ opp-hz = /bits/ 64 <400000000>;
31094+ };
31095+ opp-19200000 {
31096+ opp-hz = /bits/ 64 <19200000>;
31097+ };
31098+ };
31099+
31100 timer {
31101 compatible = "arm,armv8-timer";
31102 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
31103@@ -694,6 +710,84 @@ tsens: thermal-sensor@4a8000 {
31104 #thermal-sensor-cells = <1>;
31105 };
31106
31107+ apps_iommu: iommu@1ef0000 {
31108+ #address-cells = <1>;
31109+ #size-cells = <1>;
31110+ #iommu-cells = <1>;
31111+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
31112+ ranges = <0 0x1e20000 0x40000>;
31113+ reg = <0x1ef0000 0x3000>;
31114+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
31115+ <&gcc GCC_APSS_TCU_CLK>;
31116+ clock-names = "iface", "bus";
31117+ qcom,iommu-secure-id = <17>;
31118+
31119+ // mdp_0:
31120+ iommu-ctx@4000 {
31121+ compatible = "qcom,msm-iommu-v1-ns";
31122+ reg = <0x4000 0x1000>;
31123+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
31124+ };
31125+
31126+ // venus_ns:
31127+ iommu-ctx@5000 {
31128+ compatible = "qcom,msm-iommu-v1-sec";
31129+ reg = <0x5000 0x1000>;
31130+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
31131+ };
31132+ };
31133+
31134+ gpu_iommu: iommu@1f08000 {
31135+ #address-cells = <1>;
31136+ #size-cells = <1>;
31137+ #iommu-cells = <1>;
31138+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
31139+ ranges = <0 0x1f08000 0x10000>;
31140+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
31141+ <&gcc GCC_GFX_TCU_CLK>;
31142+ clock-names = "iface", "bus";
31143+ qcom,iommu-secure-id = <18>;
31144+
31145+ // gfx3d_user:
31146+ iommu-ctx@1000 {
31147+ compatible = "qcom,msm-iommu-v1-ns";
31148+ reg = <0x1000 0x1000>;
31149+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
31150+ };
31151+
31152+ // gfx3d_priv:
31153+ iommu-ctx@2000 {
31154+ compatible = "qcom,msm-iommu-v1-ns";
31155+ reg = <0x2000 0x1000>;
31156+ interrupts = <GIC_SPI 242 0>;
31157+ };
31158+ };
31159+
31160+ gpu@1c00000 {
31161+ compatible = "qcom,adreno-306.0", "qcom,adreno";
31162+ reg = <0x01c00000 0x20000>;
31163+ reg-names = "kgsl_3d0_reg_memory";
31164+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
31165+ interrupt-names = "kgsl_3d0_irq";
31166+ clock-names =
31167+ "core",
31168+ "iface",
31169+ "mem",
31170+ "mem_iface",
31171+ "alt_mem_iface",
31172+ "gfx3d";
31173+ clocks =
31174+ <&gcc GCC_OXILI_GFX3D_CLK>,
31175+ <&gcc GCC_OXILI_AHB_CLK>,
31176+ <&gcc GCC_OXILI_GMEM_CLK>,
31177+ <&gcc GCC_BIMC_GFX_CLK>,
31178+ <&gcc GCC_BIMC_GPU_CLK>,
31179+ <&gcc GFX3D_CLK_SRC>;
31180+ power-domains = <&gcc OXILI_GDSC>;
31181+ operating-points-v2 = <&gpu_opp_table>;
31182+ iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
31183+ };
31184+
31185 mdss: mdss@1a00000 {
31186 compatible = "qcom,mdss";
31187 reg = <0x1a00000 0x1000>,
31188@@ -735,6 +829,8 @@ mdp: mdp@1a01000 {
31189 "core_clk",
31190 "vsync_clk";
31191
31192+ iommus = <&apps_iommu 4>;
31193+
31194 ports {
31195 #address-cells = <1>;
31196 #size-cells = <0>;
31197@@ -990,7 +1086,7 @@ funnel0_out: endpoint {
31198 };
31199
31200 replicator@824000 {
31201- compatible = "qcom,coresight-replicator1x", "arm,primecell";
31202+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
31203 reg = <0x824000 0x1000>;
31204
31205 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
31206@@ -1207,6 +1303,28 @@ etm3_out: endpoint {
31207 };
31208 };
31209 };
31210+
31211+ venus: video-codec@1d00000 {
31212+ compatible = "qcom,msm8916-venus";
31213+ reg = <0x01d00000 0xff000>;
31214+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
31215+ power-domains = <&gcc VENUS_GDSC>;
31216+ clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
31217+ <&gcc GCC_VENUS0_AHB_CLK>,
31218+ <&gcc GCC_VENUS0_AXI_CLK>;
31219+ clock-names = "core", "iface", "bus";
31220+ iommus = <&apps_iommu 5>;
31221+ memory-region = <&venus_mem>;
31222+ status = "okay";
31223+
31224+ video-decoder {
31225+ compatible = "venus-decoder";
31226+ };
31227+
31228+ video-encoder {
31229+ compatible = "venus-encoder";
31230+ };
31231+ };
31232 };
31233
31234 smd {
31235diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
31236index 8f085716e258..887b61c872dd 100644
31237--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
31238+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
31239@@ -276,12 +276,83 @@ smem {
31240 hwlocks = <&tcsr_mutex 3>;
31241 };
31242
31243+ rpm-glink {
31244+ compatible = "qcom,glink-rpm";
31245+
31246+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
31247+
31248+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
31249+
31250+ mboxes = <&apcs_glb 0>;
31251+
31252+ rpm_requests {
31253+ compatible = "qcom,rpm-msm8996";
31254+ qcom,glink-channels = "rpm_requests";
31255+
31256+ pm8994-regulators {
31257+ compatible = "qcom,rpm-pm8994-regulators";
31258+
31259+ pm8994_s1: s1 {};
31260+ pm8994_s2: s2 {};
31261+ pm8994_s3: s3 {};
31262+ pm8994_s4: s4 {};
31263+ pm8994_s5: s5 {};
31264+ pm8994_s6: s6 {};
31265+ pm8994_s7: s7 {};
31266+ pm8994_s8: s8 {};
31267+ pm8994_s9: s9 {};
31268+ pm8994_s10: s10 {};
31269+ pm8994_s11: s11 {};
31270+ pm8994_s12: s12 {};
31271+
31272+ pm8994_l1: l1 {};
31273+ pm8994_l2: l2 {};
31274+ pm8994_l3: l3 {};
31275+ pm8994_l4: l4 {};
31276+ pm8994_l5: l5 {};
31277+ pm8994_l6: l6 {};
31278+ pm8994_l7: l7 {};
31279+ pm8994_l8: l8 {};
31280+ pm8994_l9: l9 {};
31281+ pm8994_l10: l10 {};
31282+ pm8994_l11: l11 {};
31283+ pm8994_l12: l12 {};
31284+ pm8994_l13: l13 {};
31285+ pm8994_l14: l14 {};
31286+ pm8994_l15: l15 {};
31287+ pm8994_l16: l16 {};
31288+ pm8994_l17: l17 {};
31289+ pm8994_l18: l18 {};
31290+ pm8994_l19: l19 {};
31291+ pm8994_l20: l20 {};
31292+ pm8994_l21: l21 {};
31293+ pm8994_l22: l22 {};
31294+ pm8994_l23: l23 {};
31295+ pm8994_l24: l24 {};
31296+ pm8994_l25: l25 {};
31297+ pm8994_l26: l26 {};
31298+ pm8994_l27: l27 {};
31299+ pm8994_l28: l28 {};
31300+ pm8994_l29: l29 {};
31301+ pm8994_l30: l30 {};
31302+ pm8994_l31: l31 {};
31303+ pm8994_l32: l32 {};
31304+ };
31305+
31306+ };
31307+ };
31308+
31309 soc: soc {
31310 #address-cells = <1>;
31311 #size-cells = <1>;
31312 ranges = <0 0 0 0xffffffff>;
31313 compatible = "simple-bus";
31314
31315+ rpm_msg_ram: memory@68000 {
31316+ compatible = "qcom,rpm-msg-ram";
31317+ reg = <0x68000 0x6000>;
31318+ };
31319+
31320 tcsr_mutex_regs: syscon@740000 {
31321 compatible = "syscon";
31322 reg = <0x740000 0x20000>;
31323@@ -303,6 +374,13 @@ apcs: syscon@9820000 {
31324 reg = <0x9820000 0x1000>;
31325 };
31326
31327+ apcs_glb: mailbox@9820000 {
31328+ compatible = "qcom,msm8996-apcs-hmss-global";
31329+ reg = <0x9820000 0x1000>;
31330+
31331+ #mbox-cells = <1>;
31332+ };
31333+
31334 gcc: clock-controller@300000 {
31335 compatible = "qcom,gcc-msm8996";
31336 #clock-cells = <1>;
31337@@ -538,6 +616,209 @@ mmcc: clock-controller@8c0000 {
31338 <960000000>,
31339 <825000000>;
31340 };
31341+
31342+ qfprom@74000 {
31343+ compatible = "qcom,qfprom";
31344+ reg = <0x74000 0x8ff>;
31345+ #address-cells = <1>;
31346+ #size-cells = <1>;
31347+
31348+ qusb2p_hstx_trim: hstx_trim@24e {
31349+ reg = <0x24e 0x2>;
31350+ bits = <5 4>;
31351+ };
31352+
31353+ qusb2s_hstx_trim: hstx_trim@24f {
31354+ reg = <0x24f 0x1>;
31355+ bits = <1 4>;
31356+ };
31357+ };
31358+
31359+ phy@34000 {
31360+ compatible = "qcom,msm8996-qmp-pcie-phy";
31361+ reg = <0x34000 0x488>;
31362+ #clock-cells = <1>;
31363+ #address-cells = <1>;
31364+ #size-cells = <1>;
31365+ ranges;
31366+
31367+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
31368+ <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
31369+ <&gcc GCC_PCIE_CLKREF_CLK>;
31370+ clock-names = "aux", "cfg_ahb", "ref";
31371+
31372+ vdda-phy-supply = <&pm8994_l28>;
31373+ vdda-pll-supply = <&pm8994_l12>;
31374+
31375+ resets = <&gcc GCC_PCIE_PHY_BCR>,
31376+ <&gcc GCC_PCIE_PHY_COM_BCR>,
31377+ <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
31378+ reset-names = "phy", "common", "cfg";
31379+ status = "disabled";
31380+
31381+ pciephy_0: lane@35000 {
31382+ reg = <0x035000 0x130>,
31383+ <0x035200 0x200>,
31384+ <0x035400 0x1dc>;
31385+ #phy-cells = <0>;
31386+
31387+ clock-output-names = "pcie_0_pipe_clk_src";
31388+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
31389+ clock-names = "pipe0";
31390+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
31391+ reset-names = "lane0";
31392+ };
31393+
31394+ pciephy_1: lane@36000 {
31395+ reg = <0x036000 0x130>,
31396+ <0x036200 0x200>,
31397+ <0x036400 0x1dc>;
31398+ #phy-cells = <0>;
31399+
31400+ clock-output-names = "pcie_1_pipe_clk_src";
31401+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
31402+ clock-names = "pipe1";
31403+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
31404+ reset-names = "lane1";
31405+ };
31406+
31407+ pciephy_2: lane@37000 {
31408+ reg = <0x037000 0x130>,
31409+ <0x037200 0x200>,
31410+ <0x037400 0x1dc>;
31411+ #phy-cells = <0>;
31412+
31413+ clock-output-names = "pcie_2_pipe_clk_src";
31414+ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
31415+ clock-names = "pipe2";
31416+ resets = <&gcc GCC_PCIE_2_PHY_BCR>;
31417+ reset-names = "lane2";
31418+ };
31419+ };
31420+
31421+ phy@7410000 {
31422+ compatible = "qcom,msm8996-qmp-usb3-phy";
31423+ reg = <0x7410000 0x1c4>;
31424+ #clock-cells = <1>;
31425+ #address-cells = <1>;
31426+ #size-cells = <1>;
31427+ ranges;
31428+
31429+ clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
31430+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
31431+ <&gcc GCC_USB3_CLKREF_CLK>;
31432+ clock-names = "aux", "cfg_ahb", "ref";
31433+
31434+ vdda-phy-supply = <&pm8994_l28>;
31435+ vdda-pll-supply = <&pm8994_l12>;
31436+
31437+ resets = <&gcc GCC_USB3_PHY_BCR>,
31438+ <&gcc GCC_USB3PHY_PHY_BCR>;
31439+ reset-names = "phy", "common";
31440+ status = "disabled";
31441+
31442+ ssusb_phy_0: lane@7410200 {
31443+ reg = <0x7410200 0x200>,
31444+ <0x7410400 0x130>,
31445+ <0x7410600 0x1a8>;
31446+ #phy-cells = <0>;
31447+
31448+ clock-output-names = "usb3_phy_pipe_clk_src";
31449+ clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
31450+ clock-names = "pipe0";
31451+ };
31452+ };
31453+
31454+ hsusb_phy1: phy@7411000 {
31455+ compatible = "qcom,msm8996-qusb2-phy";
31456+ reg = <0x7411000 0x180>;
31457+ #phy-cells = <0>;
31458+
31459+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
31460+ <&gcc GCC_RX1_USB2_CLKREF_CLK>;
31461+ clock-names = "cfg_ahb", "ref";
31462+
31463+ vdda-pll-supply = <&pm8994_l12>;
31464+ vdda-phy-dpdm-supply = <&pm8994_l24>;
31465+
31466+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
31467+ nvmem-cells = <&qusb2p_hstx_trim>;
31468+ status = "disabled";
31469+ };
31470+
31471+ hsusb_phy2: phy@7412000 {
31472+ compatible = "qcom,msm8996-qusb2-phy";
31473+ reg = <0x7412000 0x180>;
31474+ #phy-cells = <0>;
31475+
31476+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
31477+ <&gcc GCC_RX2_USB2_CLKREF_CLK>;
31478+ clock-names = "cfg_ahb", "ref";
31479+
31480+ vdda-pll-supply = <&pm8994_l12>;
31481+ vdda-phy-dpdm-supply = <&pm8994_l24>;
31482+
31483+ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
31484+ nvmem-cells = <&qusb2s_hstx_trim>;
31485+ status = "disabled";
31486+ };
31487+
31488+ usb2: usb@7600000 {
31489+ compatible = "qcom,dwc3";
31490+ #address-cells = <1>;
31491+ #size-cells = <1>;
31492+ ranges;
31493+
31494+ clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
31495+ <&gcc GCC_USB20_MASTER_CLK>,
31496+ <&gcc GCC_USB20_MOCK_UTMI_CLK>,
31497+ <&gcc GCC_USB20_SLEEP_CLK>,
31498+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
31499+
31500+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
31501+ <&gcc GCC_USB20_MASTER_CLK>;
31502+ assigned-clock-rates = <19200000>, <60000000>;
31503+
31504+ power-domains = <&gcc USB30_GDSC>;
31505+ status = "disabled";
31506+
31507+ dwc3@7600000 {
31508+ compatible = "snps,dwc3";
31509+ reg = <0x7600000 0xcc00>;
31510+ interrupts = <0 138 0>;
31511+ phys = <&hsusb_phy2>;
31512+ phy-names = "usb2-phy";
31513+ };
31514+ };
31515+
31516+ usb3: usb@6a00000 {
31517+ compatible = "qcom,dwc3";
31518+ #address-cells = <1>;
31519+ #size-cells = <1>;
31520+ ranges;
31521+
31522+ clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
31523+ <&gcc GCC_USB30_MASTER_CLK>,
31524+ <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
31525+ <&gcc GCC_USB30_MOCK_UTMI_CLK>,
31526+ <&gcc GCC_USB30_SLEEP_CLK>,
31527+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
31528+
31529+ assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
31530+ <&gcc GCC_USB30_MASTER_CLK>;
31531+ assigned-clock-rates = <19200000>, <120000000>;
31532+
31533+ power-domains = <&gcc USB30_GDSC>;
31534+ status = "disabled";
31535+
31536+ dwc3@6a00000 {
31537+ compatible = "snps,dwc3";
31538+ reg = <0x6a00000 0xcc00>;
31539+ interrupts = <0 131 0>;
31540+ phys = <&hsusb_phy1>, <&ssusb_phy_0>;
31541+ phy-names = "usb2-phy", "usb3-phy";
31542+ };
31543+ };
31544 };
31545
31546 adsp-pil {
31547@@ -558,6 +839,15 @@ adsp-pil {
31548
31549 qcom,smem-states = <&adsp_smp2p_out 0>;
31550 qcom,smem-state-names = "stop";
31551+
31552+ smd-edge {
31553+ interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
31554+
31555+ label = "lpass";
31556+ qcom,ipc = <&apcs 16 8>;
31557+ qcom,smd-edge = <1>;
31558+ qcom,remote-pid = <2>;
31559+ };
31560 };
31561
31562 adsp-smp2p {
31563@@ -584,6 +874,30 @@ adsp_smp2p_in: slave-kernel {
31564 };
31565 };
31566
31567+ modem-smp2p {
31568+ compatible = "qcom,smp2p";
31569+ qcom,smem = <435>, <428>;
31570+
31571+ interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
31572+
31573+ qcom,ipc = <&apcs 16 14>;
31574+
31575+ qcom,local-pid = <0>;
31576+ qcom,remote-pid = <1>;
31577+
31578+ modem_smp2p_out: master-kernel {
31579+ qcom,entry-name = "master-kernel";
31580+ #qcom,smem-state-cells = <1>;
31581+ };
31582+
31583+ modem_smp2p_in: slave-kernel {
31584+ qcom,entry-name = "slave-kernel";
31585+
31586+ interrupt-controller;
31587+ #interrupt-cells = <2>;
31588+ };
31589+ };
31590+
31591 smp2p-slpi {
31592 compatible = "qcom,smp2p";
31593 qcom,smem = <481>, <430>;
31594diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi
31595index d3879a4e8076..57673f92805d 100644
31596--- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi
31597+++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi
31598@@ -8,6 +8,23 @@ pmic@2 {
31599 reg = <0x2 SPMI_USID>;
31600 #address-cells = <1>;
31601 #size-cells = <0>;
31602+
31603+ pmi8994_gpios: gpios@c000 {
31604+ compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio";
31605+ reg = <0xc000>;
31606+ gpio-controller;
31607+ #gpio-cells = <2>;
31608+ interrupts = <2 0xc0 0 IRQ_TYPE_NONE>,
31609+ <2 0xc1 0 IRQ_TYPE_NONE>,
31610+ <2 0xc2 0 IRQ_TYPE_NONE>,
31611+ <2 0xc3 0 IRQ_TYPE_NONE>,
31612+ <2 0xc4 0 IRQ_TYPE_NONE>,
31613+ <2 0xc5 0 IRQ_TYPE_NONE>,
31614+ <2 0xc6 0 IRQ_TYPE_NONE>,
31615+ <2 0xc7 0 IRQ_TYPE_NONE>,
31616+ <2 0xc8 0 IRQ_TYPE_NONE>,
31617+ <2 0xc9 0 IRQ_TYPE_NONE>;
31618+ };
31619 };
31620
31621 pmic@3 {
31622diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
31623index acc4bb30d485..381928bc1358 100644
31624--- a/arch/arm64/boot/dts/renesas/Makefile
31625+++ b/arch/arm64/boot/dts/renesas/Makefile
31626@@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
31627 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
31628 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb
31629 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
31630+dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
31631
31632 always := $(dtb-y)
31633 clean-files := *.dtb
31634diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts
31635index 95fe207cb6a3..dd4f9b6a4254 100644
31636--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts
31637+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts
31638@@ -9,8 +9,6 @@
31639 * kind, whether express or implied.
31640 */
31641
31642-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
31643-
31644 /dts-v1/;
31645 #include "r8a7795-es1.dtsi"
31646 #include "ulcb.dtsi"
31647diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
31648index b84c156ed696..3f7d5f51e428 100644
31649--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
31650+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
31651@@ -8,8 +8,6 @@
31652 * kind, whether express or implied.
31653 */
31654
31655-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
31656-
31657 /dts-v1/;
31658 #include "r8a7795-es1.dtsi"
31659 #include "salvator-x.dtsi"
31660diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
31661index a0ba7bd21ea3..aaa5e67a963e 100644
31662--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
31663+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
31664@@ -21,6 +21,14 @@ xhci1: usb@ee0400000 {
31665 status = "disabled";
31666 };
31667
31668+ /delete-node/ usb-phy@ee0e0200;
31669+ /delete-node/ usb@ee0e0100;
31670+ /delete-node/ usb@ee0e0000;
31671+ /delete-node/ usb@e659c000;
31672+
31673+ /delete-node/ dma-controller@e6460000;
31674+ /delete-node/ dma-controller@e6470000;
31675+
31676 fcpf2: fcp@fe952000 {
31677 compatible = "renesas,fcpf";
31678 reg = <0 0xfe952000 0 0x200>;
31679@@ -79,6 +87,5 @@ fdp1@fe948000 {
31680 };
31681
31682 &du {
31683- compatible = "renesas,du-r8a7795";
31684 vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
31685 };
31686diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
31687index 0426f41765f0..0afe777973de 100644
31688--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
31689+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
31690@@ -9,8 +9,6 @@
31691 * kind, whether express or implied.
31692 */
31693
31694-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
31695-
31696 /dts-v1/;
31697 #include "r8a7795.dtsi"
31698 #include "ulcb.dtsi"
31699@@ -40,3 +38,17 @@ memory@700000000 {
31700 reg = <0x7 0x00000000 0x0 0x40000000>;
31701 };
31702 };
31703+
31704+&du {
31705+ clocks = <&cpg CPG_MOD 724>,
31706+ <&cpg CPG_MOD 723>,
31707+ <&cpg CPG_MOD 722>,
31708+ <&cpg CPG_MOD 721>,
31709+ <&cpg CPG_MOD 727>,
31710+ <&versaclock5 1>,
31711+ <&versaclock5 3>,
31712+ <&versaclock5 4>,
31713+ <&versaclock5 2>;
31714+ clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
31715+ "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
31716+};
31717diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
31718index 684fb3b9d154..17953070f38d 100644
31719--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
31720+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
31721@@ -8,8 +8,6 @@
31722 * kind, whether express or implied.
31723 */
31724
31725-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
31726-
31727 /dts-v1/;
31728 #include "r8a7795.dtsi"
31729 #include "salvator-x.dtsi"
31730diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
31731index de354957144b..7675de5d4f2c 100644
31732--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
31733+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
31734@@ -8,8 +8,6 @@
31735 * kind, whether express or implied.
31736 */
31737
31738-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
31739-
31740 /dts-v1/;
31741 #include "r8a7795.dtsi"
31742 #include "salvator-xs.dtsi"
31743@@ -46,10 +44,12 @@ &du {
31744 <&cpg CPG_MOD 722>,
31745 <&cpg CPG_MOD 721>,
31746 <&cpg CPG_MOD 727>,
31747+ <&versaclock6 1>,
31748 <&x21_clk>,
31749- <&x22_clk>;
31750+ <&x22_clk>,
31751+ <&versaclock6 2>;
31752 clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
31753- "dclkin.1", "dclkin.2";
31754+ "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
31755 };
31756
31757 &ehci2 {
31758diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
31759index e31c1b660b3f..2938195b9571 100644
31760--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
31761+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
31762@@ -12,6 +12,8 @@
31763 #include <dt-bindings/interrupt-controller/arm-gic.h>
31764 #include <dt-bindings/power/r8a7795-sysc.h>
31765
31766+#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
31767+
31768 / {
31769 compatible = "renesas,r8a7795";
31770 #address-cells = <2>;
31771@@ -691,6 +693,126 @@ channel1 {
31772 };
31773 };
31774
31775+ drif00: rif@e6f40000 {
31776+ compatible = "renesas,r8a7795-drif",
31777+ "renesas,rcar-gen3-drif";
31778+ reg = <0 0xe6f40000 0 0x64>;
31779+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
31780+ clocks = <&cpg CPG_MOD 515>;
31781+ clock-names = "fck";
31782+ dmas = <&dmac1 0x20>, <&dmac2 0x20>;
31783+ dma-names = "rx", "rx";
31784+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
31785+ resets = <&cpg 515>;
31786+ renesas,bonding = <&drif01>;
31787+ status = "disabled";
31788+ };
31789+
31790+ drif01: rif@e6f50000 {
31791+ compatible = "renesas,r8a7795-drif",
31792+ "renesas,rcar-gen3-drif";
31793+ reg = <0 0xe6f50000 0 0x64>;
31794+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
31795+ clocks = <&cpg CPG_MOD 514>;
31796+ clock-names = "fck";
31797+ dmas = <&dmac1 0x22>, <&dmac2 0x22>;
31798+ dma-names = "rx", "rx";
31799+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
31800+ resets = <&cpg 514>;
31801+ renesas,bonding = <&drif00>;
31802+ status = "disabled";
31803+ };
31804+
31805+ drif10: rif@e6f60000 {
31806+ compatible = "renesas,r8a7795-drif",
31807+ "renesas,rcar-gen3-drif";
31808+ reg = <0 0xe6f60000 0 0x64>;
31809+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
31810+ clocks = <&cpg CPG_MOD 513>;
31811+ clock-names = "fck";
31812+ dmas = <&dmac1 0x24>, <&dmac2 0x24>;
31813+ dma-names = "rx", "rx";
31814+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
31815+ resets = <&cpg 513>;
31816+ renesas,bonding = <&drif11>;
31817+ status = "disabled";
31818+ };
31819+
31820+ drif11: rif@e6f70000 {
31821+ compatible = "renesas,r8a7795-drif",
31822+ "renesas,rcar-gen3-drif";
31823+ reg = <0 0xe6f70000 0 0x64>;
31824+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
31825+ clocks = <&cpg CPG_MOD 512>;
31826+ clock-names = "fck";
31827+ dmas = <&dmac1 0x26>, <&dmac2 0x26>;
31828+ dma-names = "rx", "rx";
31829+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
31830+ resets = <&cpg 512>;
31831+ renesas,bonding = <&drif10>;
31832+ status = "disabled";
31833+ };
31834+
31835+ drif20: rif@e6f80000 {
31836+ compatible = "renesas,r8a7795-drif",
31837+ "renesas,rcar-gen3-drif";
31838+ reg = <0 0xe6f80000 0 0x64>;
31839+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
31840+ clocks = <&cpg CPG_MOD 511>;
31841+ clock-names = "fck";
31842+ dmas = <&dmac1 0x28>, <&dmac2 0x28>;
31843+ dma-names = "rx", "rx";
31844+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
31845+ resets = <&cpg 511>;
31846+ renesas,bonding = <&drif21>;
31847+ status = "disabled";
31848+ };
31849+
31850+ drif21: rif@e6f90000 {
31851+ compatible = "renesas,r8a7795-drif",
31852+ "renesas,rcar-gen3-drif";
31853+ reg = <0 0xe6f90000 0 0x64>;
31854+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
31855+ clocks = <&cpg CPG_MOD 510>;
31856+ clock-names = "fck";
31857+ dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
31858+ dma-names = "rx", "rx";
31859+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
31860+ resets = <&cpg 510>;
31861+ renesas,bonding = <&drif20>;
31862+ status = "disabled";
31863+ };
31864+
31865+ drif30: rif@e6fa0000 {
31866+ compatible = "renesas,r8a7795-drif",
31867+ "renesas,rcar-gen3-drif";
31868+ reg = <0 0xe6fa0000 0 0x64>;
31869+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
31870+ clocks = <&cpg CPG_MOD 509>;
31871+ clock-names = "fck";
31872+ dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
31873+ dma-names = "rx", "rx";
31874+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
31875+ resets = <&cpg 509>;
31876+ renesas,bonding = <&drif31>;
31877+ status = "disabled";
31878+ };
31879+
31880+ drif31: rif@e6fb0000 {
31881+ compatible = "renesas,r8a7795-drif",
31882+ "renesas,rcar-gen3-drif";
31883+ reg = <0 0xe6fb0000 0 0x64>;
31884+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
31885+ clocks = <&cpg CPG_MOD 508>;
31886+ clock-names = "fck";
31887+ dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
31888+ dma-names = "rx", "rx";
31889+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
31890+ resets = <&cpg 508>;
31891+ renesas,bonding = <&drif30>;
31892+ status = "disabled";
31893+ };
31894+
31895 hscif0: serial@e6540000 {
31896 compatible = "renesas,hscif-r8a7795",
31897 "renesas,rcar-gen3-hscif",
31898@@ -776,6 +898,68 @@ hscif4: serial@e66b0000 {
31899 status = "disabled";
31900 };
31901
31902+ msiof0: spi@e6e90000 {
31903+ compatible = "renesas,msiof-r8a7795",
31904+ "renesas,rcar-gen3-msiof";
31905+ reg = <0 0xe6e90000 0 0x0064>;
31906+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
31907+ clocks = <&cpg CPG_MOD 211>;
31908+ dmas = <&dmac1 0x41>, <&dmac1 0x40>,
31909+ <&dmac2 0x41>, <&dmac2 0x40>;
31910+ dma-names = "tx", "rx", "tx", "rx";
31911+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
31912+ resets = <&cpg 211>;
31913+ #address-cells = <1>;
31914+ #size-cells = <0>;
31915+ status = "disabled";
31916+ };
31917+
31918+ msiof1: spi@e6ea0000 {
31919+ compatible = "renesas,msiof-r8a7795",
31920+ "renesas,rcar-gen3-msiof";
31921+ reg = <0 0xe6ea0000 0 0x0064>;
31922+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
31923+ clocks = <&cpg CPG_MOD 210>;
31924+ dmas = <&dmac1 0x43>, <&dmac1 0x42>,
31925+ <&dmac2 0x43>, <&dmac2 0x42>;
31926+ dma-names = "tx", "rx", "tx", "rx";
31927+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
31928+ resets = <&cpg 210>;
31929+ #address-cells = <1>;
31930+ #size-cells = <0>;
31931+ status = "disabled";
31932+ };
31933+
31934+ msiof2: spi@e6c00000 {
31935+ compatible = "renesas,msiof-r8a7795",
31936+ "renesas,rcar-gen3-msiof";
31937+ reg = <0 0xe6c00000 0 0x0064>;
31938+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
31939+ clocks = <&cpg CPG_MOD 209>;
31940+ dmas = <&dmac0 0x45>, <&dmac0 0x44>;
31941+ dma-names = "tx", "rx";
31942+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
31943+ resets = <&cpg 209>;
31944+ #address-cells = <1>;
31945+ #size-cells = <0>;
31946+ status = "disabled";
31947+ };
31948+
31949+ msiof3: spi@e6c10000 {
31950+ compatible = "renesas,msiof-r8a7795",
31951+ "renesas,rcar-gen3-msiof";
31952+ reg = <0 0xe6c10000 0 0x0064>;
31953+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
31954+ clocks = <&cpg CPG_MOD 208>;
31955+ dmas = <&dmac0 0x47>, <&dmac0 0x46>;
31956+ dma-names = "tx", "rx";
31957+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
31958+ resets = <&cpg 208>;
31959+ #address-cells = <1>;
31960+ #size-cells = <0>;
31961+ status = "disabled";
31962+ };
31963+
31964 scif0: serial@e6e60000 {
31965 compatible = "renesas,scif-r8a7795",
31966 "renesas,rcar-gen3-scif", "renesas,scif";
31967@@ -1267,7 +1451,8 @@ ssi9: ssi-9 {
31968 };
31969
31970 sata: sata@ee300000 {
31971- compatible = "renesas,sata-r8a7795";
31972+ compatible = "renesas,sata-r8a7795",
31973+ "renesas,rcar-gen3-sata";
31974 reg = <0 0xee300000 0 0x200000>;
31975 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
31976 clocks = <&cpg CPG_MOD 815>;
31977@@ -1314,6 +1499,34 @@ usb_dmac1: dma-controller@e65b0000 {
31978 dma-channels = <2>;
31979 };
31980
31981+ usb_dmac2: dma-controller@e6460000 {
31982+ compatible = "renesas,r8a7795-usb-dmac",
31983+ "renesas,usb-dmac";
31984+ reg = <0 0xe6460000 0 0x100>;
31985+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH
31986+ GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
31987+ interrupt-names = "ch0", "ch1";
31988+ clocks = <&cpg CPG_MOD 326>;
31989+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
31990+ resets = <&cpg 326>;
31991+ #dma-cells = <1>;
31992+ dma-channels = <2>;
31993+ };
31994+
31995+ usb_dmac3: dma-controller@e6470000 {
31996+ compatible = "renesas,r8a7795-usb-dmac",
31997+ "renesas,usb-dmac";
31998+ reg = <0 0xe6470000 0 0x100>;
31999+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH
32000+ GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
32001+ interrupt-names = "ch0", "ch1";
32002+ clocks = <&cpg CPG_MOD 329>;
32003+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
32004+ resets = <&cpg 329>;
32005+ #dma-cells = <1>;
32006+ dma-channels = <2>;
32007+ };
32008+
32009 sdhi0: sd@ee100000 {
32010 compatible = "renesas,sdhi-r8a7795";
32011 reg = <0 0xee100000 0 0x2000>;
32012@@ -1392,6 +1605,18 @@ usb2_phy2: usb-phy@ee0c0200 {
32013 status = "disabled";
32014 };
32015
32016+ usb2_phy3: usb-phy@ee0e0200 {
32017+ compatible = "renesas,usb2-phy-r8a7795",
32018+ "renesas,rcar-gen3-usb2-phy";
32019+ reg = <0 0xee0e0200 0 0x700>;
32020+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
32021+ clocks = <&cpg CPG_MOD 700>;
32022+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
32023+ resets = <&cpg 700>;
32024+ #phy-cells = <0>;
32025+ status = "disabled";
32026+ };
32027+
32028 ehci0: usb@ee080100 {
32029 compatible = "generic-ehci";
32030 reg = <0 0xee080100 0 0x100>;
32031@@ -1399,6 +1624,7 @@ ehci0: usb@ee080100 {
32032 clocks = <&cpg CPG_MOD 703>;
32033 phys = <&usb2_phy0>;
32034 phy-names = "usb";
32035+ companion = <&ohci0>;
32036 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
32037 resets = <&cpg 703>;
32038 status = "disabled";
32039@@ -1411,6 +1637,7 @@ ehci1: usb@ee0a0100 {
32040 clocks = <&cpg CPG_MOD 702>;
32041 phys = <&usb2_phy1>;
32042 phy-names = "usb";
32043+ companion = <&ohci1>;
32044 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
32045 resets = <&cpg 702>;
32046 status = "disabled";
32047@@ -1423,11 +1650,25 @@ ehci2: usb@ee0c0100 {
32048 clocks = <&cpg CPG_MOD 701>;
32049 phys = <&usb2_phy2>;
32050 phy-names = "usb";
32051+ companion = <&ohci2>;
32052 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
32053 resets = <&cpg 701>;
32054 status = "disabled";
32055 };
32056
32057+ ehci3: usb@ee0e0100 {
32058+ compatible = "generic-ehci";
32059+ reg = <0 0xee0e0100 0 0x100>;
32060+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
32061+ clocks = <&cpg CPG_MOD 700>;
32062+ phys = <&usb2_phy3>;
32063+ phy-names = "usb";
32064+ companion = <&ohci3>;
32065+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
32066+ resets = <&cpg 700>;
32067+ status = "disabled";
32068+ };
32069+
32070 ohci0: usb@ee080000 {
32071 compatible = "generic-ohci";
32072 reg = <0 0xee080000 0 0x100>;
32073@@ -1464,6 +1705,18 @@ ohci2: usb@ee0c0000 {
32074 status = "disabled";
32075 };
32076
32077+ ohci3: usb@ee0e0000 {
32078+ compatible = "generic-ohci";
32079+ reg = <0 0xee0e0000 0 0x100>;
32080+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
32081+ clocks = <&cpg CPG_MOD 700>;
32082+ phys = <&usb2_phy3>;
32083+ phy-names = "usb";
32084+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
32085+ resets = <&cpg 700>;
32086+ status = "disabled";
32087+ };
32088+
32089 hsusb: usb@e6590000 {
32090 compatible = "renesas,usbhs-r8a7795",
32091 "renesas,rcar-gen3-usbhs";
32092@@ -1481,6 +1734,23 @@ hsusb: usb@e6590000 {
32093 status = "disabled";
32094 };
32095
32096+ hsusb3: usb@e659c000 {
32097+ compatible = "renesas,usbhs-r8a7795",
32098+ "renesas,rcar-gen3-usbhs";
32099+ reg = <0 0xe659c000 0 0x100>;
32100+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
32101+ clocks = <&cpg CPG_MOD 705>;
32102+ dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
32103+ <&usb_dmac3 0>, <&usb_dmac3 1>;
32104+ dma-names = "ch0", "ch1", "ch2", "ch3";
32105+ renesas,buswait = <11>;
32106+ phys = <&usb2_phy3>;
32107+ phy-names = "usb";
32108+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
32109+ resets = <&cpg 705>;
32110+ status = "disabled";
32111+ };
32112+
32113 pciec0: pcie@fe000000 {
32114 compatible = "renesas,pcie-r8a7795",
32115 "renesas,pcie-rcar-gen3";
32116@@ -1535,6 +1805,46 @@ pciec1: pcie@ee800000 {
32117 status = "disabled";
32118 };
32119
32120+ imr-lx4@fe860000 {
32121+ compatible = "renesas,r8a7795-imr-lx4",
32122+ "renesas,imr-lx4";
32123+ reg = <0 0xfe860000 0 0x2000>;
32124+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
32125+ clocks = <&cpg CPG_MOD 823>;
32126+ power-domains = <&sysc R8A7795_PD_A3VC>;
32127+ resets = <&cpg 823>;
32128+ };
32129+
32130+ imr-lx4@fe870000 {
32131+ compatible = "renesas,r8a7795-imr-lx4",
32132+ "renesas,imr-lx4";
32133+ reg = <0 0xfe870000 0 0x2000>;
32134+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
32135+ clocks = <&cpg CPG_MOD 822>;
32136+ power-domains = <&sysc R8A7795_PD_A3VC>;
32137+ resets = <&cpg 822>;
32138+ };
32139+
32140+ imr-lx4@fe880000 {
32141+ compatible = "renesas,r8a7795-imr-lx4",
32142+ "renesas,imr-lx4";
32143+ reg = <0 0xfe880000 0 0x2000>;
32144+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
32145+ clocks = <&cpg CPG_MOD 821>;
32146+ power-domains = <&sysc R8A7795_PD_A3VC>;
32147+ resets = <&cpg 821>;
32148+ };
32149+
32150+ imr-lx4@fe890000 {
32151+ compatible = "renesas,r8a7795-imr-lx4",
32152+ "renesas,imr-lx4";
32153+ reg = <0 0xfe890000 0 0x2000>;
32154+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
32155+ clocks = <&cpg CPG_MOD 820>;
32156+ power-domains = <&sysc R8A7795_PD_A3VC>;
32157+ resets = <&cpg 820>;
32158+ };
32159+
32160 vspbc: vsp@fe920000 {
32161 compatible = "renesas,vsp2";
32162 reg = <0 0xfe920000 0 0x8000>;
32163@@ -1755,6 +2065,7 @@ port@1 {
32164 };
32165
32166 du: display@feb00000 {
32167+ compatible = "renesas,du-r8a7795";
32168 reg = <0 0xfeb00000 0 0x80000>,
32169 <0 0xfeb90000 0 0x14>;
32170 reg-names = "du", "lvds.0";
32171@@ -1768,6 +2079,7 @@ du: display@feb00000 {
32172 <&cpg CPG_MOD 721>,
32173 <&cpg CPG_MOD 727>;
32174 clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
32175+ vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
32176 status = "disabled";
32177
32178 ports {
32179diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
32180index 38b58b7fca4b..daee1f1a3f68 100644
32181--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
32182+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
32183@@ -9,8 +9,6 @@
32184 * kind, whether express or implied.
32185 */
32186
32187-#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
32188-
32189 /dts-v1/;
32190 #include "r8a7796.dtsi"
32191 #include "ulcb.dtsi"
32192@@ -30,3 +28,15 @@ memory@600000000 {
32193 reg = <0x6 0x00000000 0x0 0x40000000>;
32194 };
32195 };
32196+
32197+&du {
32198+ clocks = <&cpg CPG_MOD 724>,
32199+ <&cpg CPG_MOD 723>,
32200+ <&cpg CPG_MOD 722>,
32201+ <&cpg CPG_MOD 727>,
32202+ <&versaclock5 1>,
32203+ <&versaclock5 3>,
32204+ <&versaclock5 2>;
32205+ clock-names = "du.0", "du.1", "du.2", "lvds.0",
32206+ "dclkin.0", "dclkin.1", "dclkin.2";
32207+};
32208diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
32209index db4f162d6bdd..b317be03306e 100644
32210--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
32211+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
32212@@ -8,8 +8,6 @@
32213 * kind, whether express or implied.
32214 */
32215
32216-#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
32217-
32218 /dts-v1/;
32219 #include "r8a7796.dtsi"
32220 #include "salvator-x.dtsi"
32221@@ -29,3 +27,32 @@ memory@600000000 {
32222 reg = <0x6 0x00000000 0x0 0x80000000>;
32223 };
32224 };
32225+
32226+&du {
32227+ clocks = <&cpg CPG_MOD 724>,
32228+ <&cpg CPG_MOD 723>,
32229+ <&cpg CPG_MOD 722>,
32230+ <&cpg CPG_MOD 727>,
32231+ <&versaclock5 1>,
32232+ <&x21_clk>,
32233+ <&versaclock5 2>;
32234+ clock-names = "du.0", "du.1", "du.2", "lvds.0",
32235+ "dclkin.0", "dclkin.1", "dclkin.2";
32236+};
32237+
32238+&hdmi0 {
32239+ status = "okay";
32240+
32241+ ports {
32242+ port@1 {
32243+ reg = <1>;
32244+ rcar_dw_hdmi0_out: endpoint {
32245+ remote-endpoint = <&hdmi0_con>;
32246+ };
32247+ };
32248+ };
32249+};
32250+
32251+&hdmi0_con {
32252+ remote-endpoint = <&rcar_dw_hdmi0_out>;
32253+};
32254diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
32255index 1f6710912045..369092e17e34 100644
32256--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
32257+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
32258@@ -12,6 +12,8 @@
32259 #include <dt-bindings/interrupt-controller/arm-gic.h>
32260 #include <dt-bindings/power/r8a7796-sysc.h>
32261
32262+#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
32263+
32264 / {
32265 compatible = "renesas,r8a7796";
32266 #address-cells = <2>;
32267@@ -639,6 +641,126 @@ channel1 {
32268 };
32269 };
32270
32271+ drif00: rif@e6f40000 {
32272+ compatible = "renesas,r8a7796-drif",
32273+ "renesas,rcar-gen3-drif";
32274+ reg = <0 0xe6f40000 0 0x64>;
32275+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
32276+ clocks = <&cpg CPG_MOD 515>;
32277+ clock-names = "fck";
32278+ dmas = <&dmac1 0x20>, <&dmac2 0x20>;
32279+ dma-names = "rx", "rx";
32280+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32281+ resets = <&cpg 515>;
32282+ renesas,bonding = <&drif01>;
32283+ status = "disabled";
32284+ };
32285+
32286+ drif01: rif@e6f50000 {
32287+ compatible = "renesas,r8a7796-drif",
32288+ "renesas,rcar-gen3-drif";
32289+ reg = <0 0xe6f50000 0 0x64>;
32290+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
32291+ clocks = <&cpg CPG_MOD 514>;
32292+ clock-names = "fck";
32293+ dmas = <&dmac1 0x22>, <&dmac2 0x22>;
32294+ dma-names = "rx", "rx";
32295+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32296+ resets = <&cpg 514>;
32297+ renesas,bonding = <&drif00>;
32298+ status = "disabled";
32299+ };
32300+
32301+ drif10: rif@e6f60000 {
32302+ compatible = "renesas,r8a7796-drif",
32303+ "renesas,rcar-gen3-drif";
32304+ reg = <0 0xe6f60000 0 0x64>;
32305+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
32306+ clocks = <&cpg CPG_MOD 513>;
32307+ clock-names = "fck";
32308+ dmas = <&dmac1 0x24>, <&dmac2 0x24>;
32309+ dma-names = "rx", "rx";
32310+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32311+ resets = <&cpg 513>;
32312+ renesas,bonding = <&drif11>;
32313+ status = "disabled";
32314+ };
32315+
32316+ drif11: rif@e6f70000 {
32317+ compatible = "renesas,r8a7796-drif",
32318+ "renesas,rcar-gen3-drif";
32319+ reg = <0 0xe6f70000 0 0x64>;
32320+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
32321+ clocks = <&cpg CPG_MOD 512>;
32322+ clock-names = "fck";
32323+ dmas = <&dmac1 0x26>, <&dmac2 0x26>;
32324+ dma-names = "rx", "rx";
32325+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32326+ resets = <&cpg 512>;
32327+ renesas,bonding = <&drif10>;
32328+ status = "disabled";
32329+ };
32330+
32331+ drif20: rif@e6f80000 {
32332+ compatible = "renesas,r8a7796-drif",
32333+ "renesas,rcar-gen3-drif";
32334+ reg = <0 0xe6f80000 0 0x64>;
32335+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
32336+ clocks = <&cpg CPG_MOD 511>;
32337+ clock-names = "fck";
32338+ dmas = <&dmac1 0x28>, <&dmac2 0x28>;
32339+ dma-names = "rx", "rx";
32340+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32341+ resets = <&cpg 511>;
32342+ renesas,bonding = <&drif21>;
32343+ status = "disabled";
32344+ };
32345+
32346+ drif21: rif@e6f90000 {
32347+ compatible = "renesas,r8a7796-drif",
32348+ "renesas,rcar-gen3-drif";
32349+ reg = <0 0xe6f90000 0 0x64>;
32350+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
32351+ clocks = <&cpg CPG_MOD 510>;
32352+ clock-names = "fck";
32353+ dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
32354+ dma-names = "rx", "rx";
32355+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32356+ resets = <&cpg 510>;
32357+ renesas,bonding = <&drif20>;
32358+ status = "disabled";
32359+ };
32360+
32361+ drif30: rif@e6fa0000 {
32362+ compatible = "renesas,r8a7796-drif",
32363+ "renesas,rcar-gen3-drif";
32364+ reg = <0 0xe6fa0000 0 0x64>;
32365+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
32366+ clocks = <&cpg CPG_MOD 509>;
32367+ clock-names = "fck";
32368+ dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
32369+ dma-names = "rx", "rx";
32370+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32371+ resets = <&cpg 509>;
32372+ renesas,bonding = <&drif31>;
32373+ status = "disabled";
32374+ };
32375+
32376+ drif31: rif@e6fb0000 {
32377+ compatible = "renesas,r8a7796-drif",
32378+ "renesas,rcar-gen3-drif";
32379+ reg = <0 0xe6fb0000 0 0x64>;
32380+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
32381+ clocks = <&cpg CPG_MOD 508>;
32382+ clock-names = "fck";
32383+ dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
32384+ dma-names = "rx", "rx";
32385+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32386+ resets = <&cpg 508>;
32387+ renesas,bonding = <&drif30>;
32388+ status = "disabled";
32389+ };
32390+
32391 avb: ethernet@e6800000 {
32392 compatible = "renesas,etheravb-r8a7796",
32393 "renesas,etheravb-rcar-gen3";
32394@@ -877,7 +999,7 @@ msiof0: spi@e6e90000 {
32395 clocks = <&cpg CPG_MOD 211>;
32396 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
32397 <&dmac2 0x41>, <&dmac2 0x40>;
32398- dma-names = "tx", "rx";
32399+ dma-names = "tx", "rx", "tx", "rx";
32400 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32401 resets = <&cpg 211>;
32402 #address-cells = <1>;
32403@@ -893,7 +1015,7 @@ msiof1: spi@e6ea0000 {
32404 clocks = <&cpg CPG_MOD 210>;
32405 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
32406 <&dmac2 0x43>, <&dmac2 0x42>;
32407- dma-names = "tx", "rx";
32408+ dma-names = "tx", "rx", "tx", "rx";
32409 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32410 resets = <&cpg 210>;
32411 #address-cells = <1>;
32412@@ -1101,36 +1223,133 @@ GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
32413 dma-channels = <16>;
32414 };
32415
32416+ usb_dmac0: dma-controller@e65a0000 {
32417+ compatible = "renesas,r8a7796-usb-dmac",
32418+ "renesas,usb-dmac";
32419+ reg = <0 0xe65a0000 0 0x100>;
32420+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
32421+ GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
32422+ interrupt-names = "ch0", "ch1";
32423+ clocks = <&cpg CPG_MOD 330>;
32424+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32425+ resets = <&cpg 330>;
32426+ #dma-cells = <1>;
32427+ dma-channels = <2>;
32428+ };
32429+
32430+ usb_dmac1: dma-controller@e65b0000 {
32431+ compatible = "renesas,r8a7796-usb-dmac",
32432+ "renesas,usb-dmac";
32433+ reg = <0 0xe65b0000 0 0x100>;
32434+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
32435+ GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
32436+ interrupt-names = "ch0", "ch1";
32437+ clocks = <&cpg CPG_MOD 331>;
32438+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32439+ resets = <&cpg 331>;
32440+ #dma-cells = <1>;
32441+ dma-channels = <2>;
32442+ };
32443+
32444 hsusb: usb@e6590000 {
32445- /* placeholder */
32446+ compatible = "renesas,usbhs-r8a7796",
32447+ "renesas,rcar-gen3-usbhs";
32448+ reg = <0 0xe6590000 0 0x100>;
32449+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
32450+ clocks = <&cpg CPG_MOD 704>;
32451+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
32452+ <&usb_dmac1 0>, <&usb_dmac1 1>;
32453+ dma-names = "ch0", "ch1", "ch2", "ch3";
32454+ renesas,buswait = <11>;
32455+ phys = <&usb2_phy0>;
32456+ phy-names = "usb";
32457+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32458+ resets = <&cpg 704>;
32459+ status = "disabled";
32460 };
32461
32462 xhci0: usb@ee000000 {
32463- /* placeholder */
32464+ compatible = "renesas,xhci-r8a7796",
32465+ "renesas,rcar-gen3-xhci";
32466+ reg = <0 0xee000000 0 0xc00>;
32467+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
32468+ clocks = <&cpg CPG_MOD 328>;
32469+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32470+ resets = <&cpg 328>;
32471+ status = "disabled";
32472 };
32473
32474 ohci0: usb@ee080000 {
32475- /* placeholder */
32476+ compatible = "generic-ohci";
32477+ reg = <0 0xee080000 0 0x100>;
32478+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
32479+ clocks = <&cpg CPG_MOD 703>;
32480+ phys = <&usb2_phy0>;
32481+ phy-names = "usb";
32482+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32483+ resets = <&cpg 703>;
32484+ status = "disabled";
32485 };
32486
32487 ehci0: usb@ee080100 {
32488- /* placeholder */
32489+ compatible = "generic-ehci";
32490+ reg = <0 0xee080100 0 0x100>;
32491+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
32492+ clocks = <&cpg CPG_MOD 703>;
32493+ phys = <&usb2_phy0>;
32494+ phy-names = "usb";
32495+ companion= <&ohci0>;
32496+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32497+ resets = <&cpg 703>;
32498+ status = "disabled";
32499 };
32500
32501 usb2_phy0: usb-phy@ee080200 {
32502- /* placeholder */
32503+ compatible = "renesas,usb2-phy-r8a7796",
32504+ "renesas,rcar-gen3-usb2-phy";
32505+ reg = <0 0xee080200 0 0x700>;
32506+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
32507+ clocks = <&cpg CPG_MOD 703>;
32508+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32509+ resets = <&cpg 703>;
32510+ #phy-cells = <0>;
32511+ status = "disabled";
32512 };
32513
32514 ohci1: usb@ee0a0000 {
32515- /* placeholder */
32516+ compatible = "generic-ohci";
32517+ reg = <0 0xee0a0000 0 0x100>;
32518+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
32519+ clocks = <&cpg CPG_MOD 702>;
32520+ phys = <&usb2_phy1>;
32521+ phy-names = "usb";
32522+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32523+ resets = <&cpg 702>;
32524+ status = "disabled";
32525 };
32526
32527 ehci1: usb@ee0a0100 {
32528- /* placeholder */
32529+ compatible = "generic-ehci";
32530+ reg = <0 0xee0a0100 0 0x100>;
32531+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
32532+ clocks = <&cpg CPG_MOD 702>;
32533+ phys = <&usb2_phy1>;
32534+ phy-names = "usb";
32535+ companion= <&ohci1>;
32536+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32537+ resets = <&cpg 702>;
32538+ status = "disabled";
32539 };
32540
32541 usb2_phy1: usb-phy@ee0a0200 {
32542- /* placeholder */
32543+ compatible = "renesas,usb2-phy-r8a7796",
32544+ "renesas,rcar-gen3-usb2-phy";
32545+ reg = <0 0xee0a0200 0 0x700>;
32546+ clocks = <&cpg CPG_MOD 702>;
32547+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32548+ resets = <&cpg 702>;
32549+ #phy-cells = <0>;
32550+ status = "disabled";
32551 };
32552
32553 sdhi0: sd@ee100000 {
32554@@ -1440,8 +1659,150 @@ pciec1: pcie@ee800000 {
32555 /* placeholder */
32556 };
32557
32558+ fcpf0: fcp@fe950000 {
32559+ compatible = "renesas,fcpf";
32560+ reg = <0 0xfe950000 0 0x200>;
32561+ clocks = <&cpg CPG_MOD 615>;
32562+ power-domains = <&sysc R8A7796_PD_A3VC>;
32563+ resets = <&cpg 615>;
32564+ };
32565+
32566+ vspb: vsp@fe960000 {
32567+ compatible = "renesas,vsp2";
32568+ reg = <0 0xfe960000 0 0x8000>;
32569+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
32570+ clocks = <&cpg CPG_MOD 626>;
32571+ power-domains = <&sysc R8A7796_PD_A3VC>;
32572+ resets = <&cpg 626>;
32573+
32574+ renesas,fcp = <&fcpvb0>;
32575+ };
32576+
32577+ fcpvb0: fcp@fe96f000 {
32578+ compatible = "renesas,fcpv";
32579+ reg = <0 0xfe96f000 0 0x200>;
32580+ clocks = <&cpg CPG_MOD 607>;
32581+ power-domains = <&sysc R8A7796_PD_A3VC>;
32582+ resets = <&cpg 607>;
32583+ };
32584+
32585+ vspi0: vsp@fe9a0000 {
32586+ compatible = "renesas,vsp2";
32587+ reg = <0 0xfe9a0000 0 0x8000>;
32588+ interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
32589+ clocks = <&cpg CPG_MOD 631>;
32590+ power-domains = <&sysc R8A7796_PD_A3VC>;
32591+ resets = <&cpg 631>;
32592+
32593+ renesas,fcp = <&fcpvi0>;
32594+ };
32595+
32596+ fcpvi0: fcp@fe9af000 {
32597+ compatible = "renesas,fcpv";
32598+ reg = <0 0xfe9af000 0 0x200>;
32599+ clocks = <&cpg CPG_MOD 611>;
32600+ power-domains = <&sysc R8A7796_PD_A3VC>;
32601+ resets = <&cpg 611>;
32602+ };
32603+
32604+ vspd0: vsp@fea20000 {
32605+ compatible = "renesas,vsp2";
32606+ reg = <0 0xfea20000 0 0x4000>;
32607+ interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
32608+ clocks = <&cpg CPG_MOD 623>;
32609+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32610+ resets = <&cpg 623>;
32611+
32612+ renesas,fcp = <&fcpvd0>;
32613+ };
32614+
32615+ fcpvd0: fcp@fea27000 {
32616+ compatible = "renesas,fcpv";
32617+ reg = <0 0xfea27000 0 0x200>;
32618+ clocks = <&cpg CPG_MOD 603>;
32619+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32620+ resets = <&cpg 603>;
32621+ };
32622+
32623+ vspd1: vsp@fea28000 {
32624+ compatible = "renesas,vsp2";
32625+ reg = <0 0xfea28000 0 0x4000>;
32626+ interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
32627+ clocks = <&cpg CPG_MOD 622>;
32628+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32629+ resets = <&cpg 622>;
32630+
32631+ renesas,fcp = <&fcpvd1>;
32632+ };
32633+
32634+ fcpvd1: fcp@fea2f000 {
32635+ compatible = "renesas,fcpv";
32636+ reg = <0 0xfea2f000 0 0x200>;
32637+ clocks = <&cpg CPG_MOD 602>;
32638+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32639+ resets = <&cpg 602>;
32640+ };
32641+
32642+ vspd2: vsp@fea30000 {
32643+ compatible = "renesas,vsp2";
32644+ reg = <0 0xfea30000 0 0x4000>;
32645+ interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
32646+ clocks = <&cpg CPG_MOD 621>;
32647+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32648+ resets = <&cpg 621>;
32649+
32650+ renesas,fcp = <&fcpvd2>;
32651+ };
32652+
32653+ fcpvd2: fcp@fea37000 {
32654+ compatible = "renesas,fcpv";
32655+ reg = <0 0xfea37000 0 0x200>;
32656+ clocks = <&cpg CPG_MOD 601>;
32657+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32658+ resets = <&cpg 601>;
32659+ };
32660+
32661+ hdmi0: hdmi@fead0000 {
32662+ compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
32663+ reg = <0 0xfead0000 0 0x10000>;
32664+ interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
32665+ clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
32666+ clock-names = "iahb", "isfr";
32667+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
32668+ resets = <&cpg 729>;
32669+ status = "disabled";
32670+
32671+ ports {
32672+ #address-cells = <1>;
32673+ #size-cells = <0>;
32674+ port@0 {
32675+ reg = <0>;
32676+ dw_hdmi0_in: endpoint {
32677+ remote-endpoint = <&du_out_hdmi0>;
32678+ };
32679+ };
32680+ port@1 {
32681+ reg = <1>;
32682+ };
32683+ };
32684+ };
32685+
32686 du: display@feb00000 {
32687- /* placeholder */
32688+ compatible = "renesas,du-r8a7796";
32689+ reg = <0 0xfeb00000 0 0x70000>,
32690+ <0 0xfeb90000 0 0x14>;
32691+ reg-names = "du", "lvds.0";
32692+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
32693+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
32694+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
32695+ clocks = <&cpg CPG_MOD 724>,
32696+ <&cpg CPG_MOD 723>,
32697+ <&cpg CPG_MOD 722>,
32698+ <&cpg CPG_MOD 727>;
32699+ clock-names = "du.0", "du.1", "du.2", "lvds.0";
32700+ status = "disabled";
32701+
32702+ vsps = <&vspd0 &vspd1 &vspd2>;
32703
32704 ports {
32705 #address-cells = <1>;
32706@@ -1452,7 +1813,38 @@ port@0 {
32707 du_out_rgb: endpoint {
32708 };
32709 };
32710+ port@1 {
32711+ reg = <1>;
32712+ du_out_hdmi0: endpoint {
32713+ remote-endpoint = <&dw_hdmi0_in>;
32714+ };
32715+ };
32716+ port@2 {
32717+ reg = <2>;
32718+ du_out_lvds0: endpoint {
32719+ };
32720+ };
32721 };
32722 };
32723+
32724+ imr-lx4@fe860000 {
32725+ compatible = "renesas,r8a7796-imr-lx4",
32726+ "renesas,imr-lx4";
32727+ reg = <0 0xfe860000 0 0x2000>;
32728+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
32729+ clocks = <&cpg CPG_MOD 823>;
32730+ power-domains = <&sysc R8A7796_PD_A3VC>;
32731+ resets = <&cpg 823>;
32732+ };
32733+
32734+ imr-lx4@fe870000 {
32735+ compatible = "renesas,r8a7796-imr-lx4",
32736+ "renesas,imr-lx4";
32737+ reg = <0 0xfe870000 0 0x2000>;
32738+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
32739+ clocks = <&cpg CPG_MOD 822>;
32740+ power-domains = <&sysc R8A7796_PD_A3VC>;
32741+ resets = <&cpg 822>;
32742+ };
32743 };
32744 };
32745diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
32746new file mode 100644
32747index 000000000000..d144370051d5
32748--- /dev/null
32749+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
32750@@ -0,0 +1,46 @@
32751+/*
32752+ * Device Tree Source for the Draak board
32753+ *
32754+ * Copyright (C) 2016 Renesas Electronics Corp.
32755+ * Copyright (C) 2017 Glider bvba
32756+ *
32757+ * This file is licensed under the terms of the GNU General Public License
32758+ * version 2. This program is licensed "as is" without any warranty of any
32759+ * kind, whether express or implied.
32760+ */
32761+
32762+/dts-v1/;
32763+#include "r8a77995.dtsi"
32764+
32765+/ {
32766+ model = "Renesas Draak board based on r8a77995";
32767+ compatible = "renesas,draak", "renesas,r8a77995";
32768+
32769+ aliases {
32770+ serial0 = &scif2;
32771+ };
32772+
32773+ chosen {
32774+ bootargs = "ignore_loglevel";
32775+ stdout-path = "serial0:115200n8";
32776+ };
32777+
32778+ memory@48000000 {
32779+ device_type = "memory";
32780+ /* first 128MB is reserved for secure area. */
32781+ reg = <0x0 0x48000000 0x0 0x18000000>;
32782+ };
32783+};
32784+
32785+&extal_clk {
32786+ clock-frequency = <48000000>;
32787+};
32788+
32789+&scif2 {
32790+ status = "okay";
32791+};
32792+
32793+&rwdt {
32794+ timeout-sec = <60>;
32795+ status = "okay";
32796+};
32797diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
32798new file mode 100644
32799index 000000000000..d0f95b78c022
32800--- /dev/null
32801+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
32802@@ -0,0 +1,155 @@
32803+/*
32804+ * Device Tree Source for the r8a77995 SoC
32805+ *
32806+ * Copyright (C) 2016 Renesas Electronics Corp.
32807+ * Copyright (C) 2017 Glider bvba
32808+ *
32809+ * This file is licensed under the terms of the GNU General Public License
32810+ * version 2. This program is licensed "as is" without any warranty of any
32811+ * kind, whether express or implied.
32812+ */
32813+
32814+#include <dt-bindings/clock/renesas-cpg-mssr.h>
32815+#include <dt-bindings/interrupt-controller/arm-gic.h>
32816+
32817+/ {
32818+ compatible = "renesas,r8a77995";
32819+ #address-cells = <2>;
32820+ #size-cells = <2>;
32821+
32822+ psci {
32823+ compatible = "arm,psci-1.0", "arm,psci-0.2";
32824+ method = "smc";
32825+ };
32826+
32827+ cpus {
32828+ #address-cells = <1>;
32829+ #size-cells = <0>;
32830+
32831+ a53_0: cpu@0 {
32832+ compatible = "arm,cortex-a53", "arm,armv8";
32833+ reg = <0x0>;
32834+ device_type = "cpu";
32835+ power-domains = <&sysc 5>;
32836+ next-level-cache = <&L2_CA53>;
32837+ enable-method = "psci";
32838+ };
32839+
32840+ L2_CA53: cache-controller-1 {
32841+ compatible = "cache";
32842+ power-domains = <&sysc 21>;
32843+ cache-unified;
32844+ cache-level = <2>;
32845+ };
32846+ };
32847+
32848+ extal_clk: extal {
32849+ compatible = "fixed-clock";
32850+ #clock-cells = <0>;
32851+ /* This value must be overridden by the board */
32852+ clock-frequency = <0>;
32853+ };
32854+
32855+ scif_clk: scif {
32856+ compatible = "fixed-clock";
32857+ #clock-cells = <0>;
32858+ clock-frequency = <0>;
32859+ };
32860+
32861+ soc {
32862+ compatible = "simple-bus";
32863+ interrupt-parent = <&gic>;
32864+ #address-cells = <2>;
32865+ #size-cells = <2>;
32866+ ranges;
32867+
32868+ gic: interrupt-controller@f1010000 {
32869+ compatible = "arm,gic-400";
32870+ #interrupt-cells = <3>;
32871+ #address-cells = <0>;
32872+ interrupt-controller;
32873+ reg = <0x0 0xf1010000 0 0x1000>,
32874+ <0x0 0xf1020000 0 0x20000>,
32875+ <0x0 0xf1040000 0 0x20000>,
32876+ <0x0 0xf1060000 0 0x20000>;
32877+ interrupts = <GIC_PPI 9
32878+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
32879+ clocks = <&cpg CPG_MOD 408>;
32880+ clock-names = "clk";
32881+ power-domains = <&sysc 32>;
32882+ resets = <&cpg 408>;
32883+ };
32884+
32885+ timer {
32886+ compatible = "arm,armv8-timer";
32887+ interrupts = <GIC_PPI 13
32888+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
32889+ <GIC_PPI 14
32890+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
32891+ <GIC_PPI 11
32892+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
32893+ <GIC_PPI 10
32894+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
32895+ };
32896+
32897+ rwdt: watchdog@e6020000 {
32898+ compatible = "renesas,r8a77995-wdt",
32899+ "renesas,rcar-gen3-wdt";
32900+ reg = <0 0xe6020000 0 0x0c>;
32901+ clocks = <&cpg CPG_MOD 402>;
32902+ power-domains = <&sysc 32>;
32903+ resets = <&cpg 402>;
32904+ status = "disabled";
32905+ };
32906+
32907+ pmu_a53 {
32908+ compatible = "arm,cortex-a53-pmu";
32909+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
32910+ };
32911+
32912+ cpg: clock-controller@e6150000 {
32913+ compatible = "renesas,r8a77995-cpg-mssr";
32914+ reg = <0 0xe6150000 0 0x1000>;
32915+ clocks = <&extal_clk>;
32916+ clock-names = "extal";
32917+ #clock-cells = <2>;
32918+ #power-domain-cells = <0>;
32919+ #reset-cells = <1>;
32920+ };
32921+
32922+ rst: reset-controller@e6160000 {
32923+ compatible = "renesas,r8a77995-rst";
32924+ reg = <0 0xe6160000 0 0x0200>;
32925+ };
32926+
32927+ pfc: pfc@e6060000 {
32928+ compatible = "renesas,pfc-r8a77995";
32929+ reg = <0 0xe6060000 0 0x508>;
32930+ };
32931+
32932+ prr: chipid@fff00044 {
32933+ compatible = "renesas,prr";
32934+ reg = <0 0xfff00044 0 4>;
32935+ };
32936+
32937+ sysc: system-controller@e6180000 {
32938+ compatible = "renesas,r8a77995-sysc";
32939+ reg = <0 0xe6180000 0 0x0400>;
32940+ #power-domain-cells = <1>;
32941+ };
32942+
32943+ scif2: serial@e6e88000 {
32944+ compatible = "renesas,scif-r8a77995",
32945+ "renesas,rcar-gen3-scif", "renesas,scif";
32946+ reg = <0 0xe6e88000 0 64>;
32947+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
32948+ clocks = <&cpg CPG_MOD 310>,
32949+ <&cpg CPG_CORE 16>,
32950+ <&scif_clk>;
32951+ clock-names = "fck", "brg_int", "scif_clk";
32952+ power-domains = <&sysc 32>;
32953+ resets = <&cpg 310>;
32954+ status = "disabled";
32955+ };
32956+ };
32957+};
32958diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
32959index f903957da504..4786c67b5e65 100644
32960--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
32961+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
32962@@ -268,10 +268,6 @@ endpoint {
32963 remote-endpoint = <&adv7123_in>;
32964 };
32965 };
32966- port@3 {
32967- lvds_connector: endpoint {
32968- };
32969- };
32970 };
32971 };
32972
32973diff --git a/arch/arm64/boot/dts/renesas/salvator-xs.dtsi b/arch/arm64/boot/dts/renesas/salvator-xs.dtsi
32974index 81227e3c2c6f..bf4d200fb546 100644
32975--- a/arch/arm64/boot/dts/renesas/salvator-xs.dtsi
32976+++ b/arch/arm64/boot/dts/renesas/salvator-xs.dtsi
32977@@ -18,3 +18,13 @@ / {
32978 &extal_clk {
32979 clock-frequency = <16640000>;
32980 };
32981+
32982+&i2c4 {
32983+ versaclock6: clock-generator@6a {
32984+ compatible = "idt,5p49v6901";
32985+ reg = <0x6a>;
32986+ #clock-cells = <1>;
32987+ clocks = <&x23_clk>;
32988+ clock-names = "xin";
32989+ };
32990+};
32991diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
32992index d1a3f3b7a0ab..1b868df2393f 100644
32993--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
32994+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
32995@@ -34,6 +34,16 @@ audio_clkout: audio-clkout {
32996 clock-frequency = <11289600>;
32997 };
32998
32999+ hdmi0-out {
33000+ compatible = "hdmi-connector";
33001+ type = "a";
33002+
33003+ port {
33004+ hdmi0_con: endpoint {
33005+ };
33006+ };
33007+ };
33008+
33009 keyboard {
33010 compatible = "gpio-keys";
33011
33012@@ -120,6 +130,12 @@ x12_clk: x12 {
33013 #clock-cells = <0>;
33014 clock-frequency = <24576000>;
33015 };
33016+
33017+ x23_clk: x23-clock {
33018+ compatible = "fixed-clock";
33019+ #clock-cells = <0>;
33020+ clock-frequency = <25000000>;
33021+ };
33022 };
33023
33024 &audio_clk_a {
33025@@ -153,6 +169,23 @@ &extalr_clk {
33026 clock-frequency = <32768>;
33027 };
33028
33029+&hdmi0 {
33030+ status = "okay";
33031+
33032+ ports {
33033+ port@1 {
33034+ reg = <1>;
33035+ rcar_dw_hdmi0_out: endpoint {
33036+ remote-endpoint = <&hdmi0_con>;
33037+ };
33038+ };
33039+ };
33040+};
33041+
33042+&hdmi0_con {
33043+ remote-endpoint = <&rcar_dw_hdmi0_out>;
33044+};
33045+
33046 &i2c2 {
33047 pinctrl-0 = <&i2c2_pins>;
33048 pinctrl-names = "default";
33049@@ -189,6 +222,24 @@ cs2000: clk-multiplier@4f {
33050 };
33051 };
33052
33053+&i2c4 {
33054+ status = "okay";
33055+
33056+ clock-frequency = <400000>;
33057+
33058+ versaclock5: clock-generator@6a {
33059+ compatible = "idt,5p49v5925";
33060+ reg = <0x6a>;
33061+ #clock-cells = <1>;
33062+ clocks = <&x23_clk>;
33063+ clock-names = "xin";
33064+ };
33065+};
33066+
33067+&i2c_dvfs {
33068+ status = "okay";
33069+};
33070+
33071 &ohci1 {
33072 status = "okay";
33073 };
33074diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
33075index bcfa53b1e6b7..f1c9b13cea5c 100644
33076--- a/arch/arm64/boot/dts/rockchip/Makefile
33077+++ b/arch/arm64/boot/dts/rockchip/Makefile
33078@@ -1,4 +1,5 @@
33079 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
33080+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
33081 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
33082 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
33083 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
33084@@ -7,6 +8,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
33085 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
33086 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
33087 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
33088+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
33089+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
33090
33091 always := $(dtb-y)
33092 subdir-y := $(dts-dirs)
33093diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
33094index b9f36dad17e6..8e6a65431756 100644
33095--- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
33096+++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
33097@@ -51,6 +51,25 @@ chosen {
33098 stdout-path = "serial2:1500000n8";
33099 };
33100
33101+ dc_12v: dc-12v {
33102+ compatible = "regulator-fixed";
33103+ regulator-name = "dc_12v";
33104+ regulator-always-on;
33105+ regulator-boot-on;
33106+ regulator-min-microvolt = <12000000>;
33107+ regulator-max-microvolt = <12000000>;
33108+ };
33109+
33110+ vcc_sys: vcc-sys {
33111+ compatible = "regulator-fixed";
33112+ regulator-name = "vcc_sys";
33113+ regulator-always-on;
33114+ regulator-boot-on;
33115+ regulator-min-microvolt = <5000000>;
33116+ regulator-max-microvolt = <5000000>;
33117+ vin-supply = <&dc_12v>;
33118+ };
33119+
33120 vcc_phy: vcc-phy-regulator {
33121 compatible = "regulator-fixed";
33122 regulator-name = "vcc_phy";
33123@@ -69,6 +88,151 @@ &gmac2phy {
33124 status = "okay";
33125 };
33126
33127+&i2c1 {
33128+ status = "okay";
33129+
33130+ rk805: rk805@18 {
33131+ compatible = "rockchip,rk805";
33132+ reg = <0x18>;
33133+ interrupt-parent = <&gpio2>;
33134+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
33135+ #clock-cells = <1>;
33136+ clock-output-names = "xin32k", "rk805-clkout2";
33137+ gpio-controller;
33138+ #gpio-cells = <2>;
33139+ pinctrl-names = "default";
33140+ pinctrl-0 = <&pmic_int_l>;
33141+ rockchip,system-power-controller;
33142+ wakeup-source;
33143+
33144+ vcc1-supply = <&vcc_sys>;
33145+ vcc2-supply = <&vcc_sys>;
33146+ vcc3-supply = <&vcc_sys>;
33147+ vcc4-supply = <&vcc_sys>;
33148+ vcc5-supply = <&vcc_io>;
33149+ vcc6-supply = <&vcc_io>;
33150+
33151+ regulators {
33152+ vdd_logic: DCDC_REG1 {
33153+ regulator-name = "vdd_logic";
33154+ regulator-min-microvolt = <712500>;
33155+ regulator-max-microvolt = <1450000>;
33156+ regulator-always-on;
33157+ regulator-boot-on;
33158+ regulator-state-mem {
33159+ regulator-on-in-suspend;
33160+ regulator-suspend-microvolt = <1000000>;
33161+ };
33162+ };
33163+
33164+ vdd_arm: DCDC_REG2 {
33165+ regulator-name = "vdd_arm";
33166+ regulator-min-microvolt = <712500>;
33167+ regulator-max-microvolt = <1450000>;
33168+ regulator-always-on;
33169+ regulator-boot-on;
33170+ regulator-state-mem {
33171+ regulator-on-in-suspend;
33172+ regulator-suspend-microvolt = <950000>;
33173+ };
33174+ };
33175+
33176+ vcc_ddr: DCDC_REG3 {
33177+ regulator-name = "vcc_ddr";
33178+ regulator-always-on;
33179+ regulator-boot-on;
33180+ regulator-state-mem {
33181+ regulator-on-in-suspend;
33182+ };
33183+ };
33184+
33185+ vcc_io: DCDC_REG4 {
33186+ regulator-name = "vcc_io";
33187+ regulator-min-microvolt = <3300000>;
33188+ regulator-max-microvolt = <3300000>;
33189+ regulator-always-on;
33190+ regulator-boot-on;
33191+ regulator-state-mem {
33192+ regulator-on-in-suspend;
33193+ regulator-suspend-microvolt = <3300000>;
33194+ };
33195+ };
33196+
33197+ vcc_18: LDO_REG1 {
33198+ regulator-name = "vcc_18";
33199+ regulator-min-microvolt = <1800000>;
33200+ regulator-max-microvolt = <1800000>;
33201+ regulator-always-on;
33202+ regulator-boot-on;
33203+ regulator-state-mem {
33204+ regulator-on-in-suspend;
33205+ regulator-suspend-microvolt = <1800000>;
33206+ };
33207+ };
33208+
33209+ vcc18_emmc: LDO_REG2 {
33210+ regulator-name = "vcc18_emmc";
33211+ regulator-min-microvolt = <1800000>;
33212+ regulator-max-microvolt = <1800000>;
33213+ regulator-always-on;
33214+ regulator-boot-on;
33215+ regulator-state-mem {
33216+ regulator-on-in-suspend;
33217+ regulator-suspend-microvolt = <1800000>;
33218+ };
33219+ };
33220+
33221+ vdd_10: LDO_REG3 {
33222+ regulator-name = "vdd_10";
33223+ regulator-min-microvolt = <1000000>;
33224+ regulator-max-microvolt = <1000000>;
33225+ regulator-always-on;
33226+ regulator-boot-on;
33227+ regulator-state-mem {
33228+ regulator-on-in-suspend;
33229+ regulator-suspend-microvolt = <1000000>;
33230+ };
33231+ };
33232+ };
33233+ };
33234+};
33235+
33236+&pinctrl {
33237+ pmic {
33238+ pmic_int_l: pmic-int-l {
33239+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
33240+ };
33241+ };
33242+};
33243+
33244+&tsadc {
33245+ status = "okay";
33246+};
33247+
33248 &uart2 {
33249 status = "okay";
33250 };
33251+
33252+&u2phy {
33253+ status = "okay";
33254+};
33255+
33256+&u2phy_host {
33257+ status = "okay";
33258+};
33259+
33260+&u2phy_otg {
33261+ status = "okay";
33262+};
33263+
33264+&usb20_otg {
33265+ status = "okay";
33266+};
33267+
33268+&usb_host0_ehci {
33269+ status = "okay";
33270+};
33271+
33272+&usb_host0_ohci {
33273+ status = "okay";
33274+};
33275diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
33276new file mode 100644
33277index 000000000000..d4f80786e7c2
33278--- /dev/null
33279+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
33280@@ -0,0 +1,333 @@
33281+/*
33282+ * Copyright (c) 2017 PINE64
33283+ *
33284+ * This file is dual-licensed: you can use it either under the terms
33285+ * of the GPL or the X11 license, at your option. Note that this dual
33286+ * licensing only applies to this file, and not this project as a
33287+ * whole.
33288+ *
33289+ * a) This library is free software; you can redistribute it and/or
33290+ * modify it under the terms of the GNU General Public License as
33291+ * published by the Free Software Foundation; either version 2 of the
33292+ * License, or (at your option) any later version.
33293+ *
33294+ * This library is distributed in the hope that it will be useful,
33295+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
33296+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33297+ * GNU General Public License for more details.
33298+ *
33299+ * Or, alternatively,
33300+ *
33301+ * b) Permission is hereby granted, free of charge, to any person
33302+ * obtaining a copy of this software and associated documentation
33303+ * files (the "Software"), to deal in the Software without
33304+ * restriction, including without limitation the rights to use,
33305+ * copy, modify, merge, publish, distribute, sublicense, and/or
33306+ * sell copies of the Software, and to permit persons to whom the
33307+ * Software is furnished to do so, subject to the following
33308+ * conditions:
33309+ *
33310+ * The above copyright notice and this permission notice shall be
33311+ * included in all copies or substantial portions of the Software.
33312+ *
33313+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33314+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33315+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
33316+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
33317+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
33318+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
33319+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33320+ * OTHER DEALINGS IN THE SOFTWARE.
33321+ */
33322+
33323+/dts-v1/;
33324+#include "rk3328.dtsi"
33325+
33326+/ {
33327+ model = "Pine64 Rock64";
33328+ compatible = "pine64,rock64", "rockchip,rk3328";
33329+
33330+ chosen {
33331+ stdout-path = "serial2:1500000n8";
33332+ };
33333+
33334+ gmac_clkin: external-gmac-clock {
33335+ compatible = "fixed-clock";
33336+ clock-frequency = <125000000>;
33337+ clock-output-names = "gmac_clkin";
33338+ #clock-cells = <0>;
33339+ };
33340+
33341+ vcc_sd: sdmmc-regulator {
33342+ compatible = "regulator-fixed";
33343+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
33344+ pinctrl-names = "default";
33345+ pinctrl-0 = <&sdmmc0m1_gpio>;
33346+ regulator-name = "vcc_sd";
33347+ regulator-min-microvolt = <3300000>;
33348+ regulator-max-microvolt = <3300000>;
33349+ vin-supply = <&vcc_io>;
33350+ };
33351+
33352+ vcc_host_5v: vcc-host-5v-regulator {
33353+ compatible = "regulator-fixed";
33354+ enable-active-high;
33355+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
33356+ pinctrl-names = "default";
33357+ pinctrl-0 = <&usb30_host_drv>;
33358+ regulator-name = "vcc_host_5v";
33359+ regulator-always-on;
33360+ vin-supply = <&vcc_sys>;
33361+ };
33362+
33363+ vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
33364+ compatible = "regulator-fixed";
33365+ enable-active-high;
33366+ gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
33367+ pinctrl-names = "default";
33368+ pinctrl-0 = <&usb20_host_drv>;
33369+ regulator-name = "vcc_host1_5v";
33370+ regulator-always-on;
33371+ vin-supply = <&vcc_sys>;
33372+ };
33373+
33374+ vcc_sys: vcc-sys {
33375+ compatible = "regulator-fixed";
33376+ regulator-name = "vcc_sys";
33377+ regulator-always-on;
33378+ regulator-boot-on;
33379+ regulator-min-microvolt = <5000000>;
33380+ regulator-max-microvolt = <5000000>;
33381+ };
33382+};
33383+
33384+&cpu0 {
33385+ cpu-supply = <&vdd_arm>;
33386+};
33387+
33388+&cpu1 {
33389+ cpu-supply = <&vdd_arm>;
33390+};
33391+
33392+&cpu2 {
33393+ cpu-supply = <&vdd_arm>;
33394+};
33395+
33396+&cpu3 {
33397+ cpu-supply = <&vdd_arm>;
33398+};
33399+
33400+&emmc {
33401+ bus-width = <8>;
33402+ cap-mmc-highspeed;
33403+ non-removable;
33404+ pinctrl-names = "default";
33405+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
33406+ vmmc-supply = <&vcc_io>;
33407+ vqmmc-supply = <&vcc18_emmc>;
33408+ status = "okay";
33409+};
33410+
33411+&gmac2io {
33412+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
33413+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
33414+ clock_in_out = "input";
33415+ phy-supply = <&vcc_io>;
33416+ phy-mode = "rgmii";
33417+ pinctrl-names = "default";
33418+ pinctrl-0 = <&rgmiim1_pins>;
33419+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
33420+ snps,reset-active-low;
33421+ snps,reset-delays-us = <0 10000 50000>;
33422+ tx_delay = <0x26>;
33423+ rx_delay = <0x11>;
33424+ status = "okay";
33425+};
33426+
33427+&i2c1 {
33428+ status = "okay";
33429+
33430+ rk805: rk805@18 {
33431+ compatible = "rockchip,rk805";
33432+ reg = <0x18>;
33433+ interrupt-parent = <&gpio2>;
33434+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
33435+ #clock-cells = <1>;
33436+ clock-output-names = "xin32k", "rk805-clkout2";
33437+ pinctrl-names = "default";
33438+ pinctrl-0 = <&pmic_int_l>;
33439+ rockchip,system-power-controller;
33440+ wakeup-source;
33441+
33442+ vcc1-supply = <&vcc_sys>;
33443+ vcc2-supply = <&vcc_sys>;
33444+ vcc3-supply = <&vcc_sys>;
33445+ vcc4-supply = <&vcc_sys>;
33446+ vcc5-supply = <&vcc_io>;
33447+ vcc6-supply = <&vcc_sys>;
33448+
33449+ regulators {
33450+ vdd_logic: DCDC_REG1 {
33451+ regulator-name = "vdd_logic";
33452+ regulator-min-microvolt = <712500>;
33453+ regulator-max-microvolt = <1450000>;
33454+ regulator-ramp-delay = <12500>;
33455+ regulator-always-on;
33456+ regulator-boot-on;
33457+ regulator-state-mem {
33458+ regulator-on-in-suspend;
33459+ regulator-suspend-microvolt = <1000000>;
33460+ };
33461+ };
33462+
33463+ vdd_arm: DCDC_REG2 {
33464+ regulator-name = "vdd_arm";
33465+ regulator-min-microvolt = <712500>;
33466+ regulator-max-microvolt = <1450000>;
33467+ regulator-ramp-delay = <12500>;
33468+ regulator-always-on;
33469+ regulator-boot-on;
33470+ regulator-state-mem {
33471+ regulator-on-in-suspend;
33472+ regulator-suspend-microvolt = <950000>;
33473+ };
33474+ };
33475+
33476+ vcc_ddr: DCDC_REG3 {
33477+ regulator-name = "vcc_ddr";
33478+ regulator-always-on;
33479+ regulator-boot-on;
33480+ regulator-state-mem {
33481+ regulator-on-in-suspend;
33482+ };
33483+ };
33484+
33485+ vcc_io: DCDC_REG4 {
33486+ regulator-name = "vcc_io";
33487+ regulator-min-microvolt = <3300000>;
33488+ regulator-max-microvolt = <3300000>;
33489+ regulator-always-on;
33490+ regulator-boot-on;
33491+ regulator-state-mem {
33492+ regulator-on-in-suspend;
33493+ regulator-suspend-microvolt = <3300000>;
33494+ };
33495+ };
33496+
33497+ vcc_18: LDO_REG1 {
33498+ regulator-name = "vdd_18";
33499+ regulator-min-microvolt = <1800000>;
33500+ regulator-max-microvolt = <1800000>;
33501+ regulator-always-on;
33502+ regulator-boot-on;
33503+ regulator-state-mem {
33504+ regulator-on-in-suspend;
33505+ regulator-suspend-microvolt = <1800000>;
33506+ };
33507+ };
33508+
33509+ vcc18_emmc: LDO_REG2 {
33510+ regulator-name = "vcc_18emmc";
33511+ regulator-min-microvolt = <1800000>;
33512+ regulator-max-microvolt = <1800000>;
33513+ regulator-always-on;
33514+ regulator-boot-on;
33515+ regulator-state-mem {
33516+ regulator-on-in-suspend;
33517+ regulator-suspend-microvolt = <1800000>;
33518+ };
33519+ };
33520+
33521+ vdd_10: LDO_REG3 {
33522+ regulator-name = "vdd_10";
33523+ regulator-min-microvolt = <1000000>;
33524+ regulator-max-microvolt = <1000000>;
33525+ regulator-always-on;
33526+ regulator-boot-on;
33527+ regulator-state-mem {
33528+ regulator-on-in-suspend;
33529+ regulator-suspend-microvolt = <1000000>;
33530+ };
33531+ };
33532+ };
33533+ };
33534+};
33535+
33536+&io_domains {
33537+ status = "okay";
33538+
33539+ vccio1-supply = <&vcc_io>;
33540+ vccio2-supply = <&vcc18_emmc>;
33541+ vccio3-supply = <&vcc_io>;
33542+ vccio4-supply = <&vcc_18>;
33543+ vccio5-supply = <&vcc_io>;
33544+ vccio6-supply = <&vcc_io>;
33545+ pmuio-supply = <&vcc_io>;
33546+};
33547+
33548+&pinctrl {
33549+ pmic {
33550+ pmic_int_l: pmic-int-l {
33551+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
33552+ };
33553+ };
33554+
33555+ usb2 {
33556+ usb20_host_drv: usb20-host-drv {
33557+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
33558+ };
33559+ };
33560+
33561+ usb3 {
33562+ usb30_host_drv: usb30-host-drv {
33563+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
33564+ };
33565+ };
33566+};
33567+
33568+&sdmmc {
33569+ bus-width = <4>;
33570+ cap-mmc-highspeed;
33571+ cap-sd-highspeed;
33572+ disable-wp;
33573+ max-frequency = <150000000>;
33574+ pinctrl-names = "default";
33575+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
33576+ vmmc-supply = <&vcc_sd>;
33577+ status = "okay";
33578+};
33579+
33580+&tsadc {
33581+ rockchip,hw-tshut-mode = <0>;
33582+ rockchip,hw-tshut-polarity = <0>;
33583+ status = "okay";
33584+};
33585+
33586+&uart2 {
33587+ status = "okay";
33588+};
33589+
33590+&u2phy {
33591+ status = "okay";
33592+
33593+ u2phy_host: host-port {
33594+ status = "okay";
33595+ };
33596+
33597+ u2phy_otg: otg-port {
33598+ status = "okay";
33599+ };
33600+};
33601+
33602+&usb20_otg {
33603+ dr_mode = "host";
33604+ status = "okay";
33605+};
33606+
33607+&usb_host0_ehci {
33608+ status = "okay";
33609+};
33610+
33611+&usb_host0_ohci {
33612+ status = "okay";
33613+};
33614diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
33615index d48bf5d9f8bd..6d615cb6e64d 100644
33616--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
33617+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
33618@@ -47,6 +47,7 @@
33619 #include <dt-bindings/pinctrl/rockchip.h>
33620 #include <dt-bindings/power/rk3328-power.h>
33621 #include <dt-bindings/soc/rockchip,boot-mode.h>
33622+#include <dt-bindings/thermal/thermal.h>
33623
33624 / {
33625 compatible = "rockchip,rk3328";
33626@@ -76,8 +77,11 @@ cpu0: cpu@0 {
33627 compatible = "arm,cortex-a53", "arm,armv8";
33628 reg = <0x0 0x0>;
33629 clocks = <&cru ARMCLK>;
33630+ #cooling-cells = <2>;
33631+ dynamic-power-coefficient = <120>;
33632 enable-method = "psci";
33633 next-level-cache = <&l2>;
33634+ operating-points-v2 = <&cpu0_opp_table>;
33635 };
33636
33637 cpu1: cpu@1 {
33638@@ -85,8 +89,10 @@ cpu1: cpu@1 {
33639 compatible = "arm,cortex-a53", "arm,armv8";
33640 reg = <0x0 0x1>;
33641 clocks = <&cru ARMCLK>;
33642+ dynamic-power-coefficient = <120>;
33643 enable-method = "psci";
33644 next-level-cache = <&l2>;
33645+ operating-points-v2 = <&cpu0_opp_table>;
33646 };
33647
33648 cpu2: cpu@2 {
33649@@ -94,8 +100,10 @@ cpu2: cpu@2 {
33650 compatible = "arm,cortex-a53", "arm,armv8";
33651 reg = <0x0 0x2>;
33652 clocks = <&cru ARMCLK>;
33653+ dynamic-power-coefficient = <120>;
33654 enable-method = "psci";
33655 next-level-cache = <&l2>;
33656+ operating-points-v2 = <&cpu0_opp_table>;
33657 };
33658
33659 cpu3: cpu@3 {
33660@@ -103,8 +111,10 @@ cpu3: cpu@3 {
33661 compatible = "arm,cortex-a53", "arm,armv8";
33662 reg = <0x0 0x3>;
33663 clocks = <&cru ARMCLK>;
33664+ dynamic-power-coefficient = <120>;
33665 enable-method = "psci";
33666 next-level-cache = <&l2>;
33667+ operating-points-v2 = <&cpu0_opp_table>;
33668 };
33669
33670 l2: l2-cache0 {
33671@@ -112,6 +122,43 @@ l2: l2-cache0 {
33672 };
33673 };
33674
33675+ cpu0_opp_table: opp_table0 {
33676+ compatible = "operating-points-v2";
33677+ opp-shared;
33678+
33679+ opp-408000000 {
33680+ opp-hz = /bits/ 64 <408000000>;
33681+ opp-microvolt = <950000>;
33682+ clock-latency-ns = <40000>;
33683+ opp-suspend;
33684+ };
33685+ opp-600000000 {
33686+ opp-hz = /bits/ 64 <600000000>;
33687+ opp-microvolt = <950000>;
33688+ clock-latency-ns = <40000>;
33689+ };
33690+ opp-816000000 {
33691+ opp-hz = /bits/ 64 <816000000>;
33692+ opp-microvolt = <1000000>;
33693+ clock-latency-ns = <40000>;
33694+ };
33695+ opp-1008000000 {
33696+ opp-hz = /bits/ 64 <1008000000>;
33697+ opp-microvolt = <1100000>;
33698+ clock-latency-ns = <40000>;
33699+ };
33700+ opp-1200000000 {
33701+ opp-hz = /bits/ 64 <1200000000>;
33702+ opp-microvolt = <1225000>;
33703+ clock-latency-ns = <40000>;
33704+ };
33705+ opp-1296000000 {
33706+ opp-hz = /bits/ 64 <1296000000>;
33707+ opp-microvolt = <1300000>;
33708+ clock-latency-ns = <40000>;
33709+ };
33710+ };
33711+
33712 amba {
33713 compatible = "simple-bus";
33714 #address-cells = <2>;
33715@@ -158,12 +205,84 @@ xin24m: xin24m {
33716 clock-output-names = "xin24m";
33717 };
33718
33719+ i2s0: i2s@ff000000 {
33720+ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
33721+ reg = <0x0 0xff000000 0x0 0x1000>;
33722+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
33723+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
33724+ clock-names = "i2s_clk", "i2s_hclk";
33725+ dmas = <&dmac 11>, <&dmac 12>;
33726+ dma-names = "tx", "rx";
33727+ status = "disabled";
33728+ };
33729+
33730+ i2s1: i2s@ff010000 {
33731+ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
33732+ reg = <0x0 0xff010000 0x0 0x1000>;
33733+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
33734+ clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
33735+ clock-names = "i2s_clk", "i2s_hclk";
33736+ dmas = <&dmac 14>, <&dmac 15>;
33737+ dma-names = "tx", "rx";
33738+ status = "disabled";
33739+ };
33740+
33741+ i2s2: i2s@ff020000 {
33742+ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
33743+ reg = <0x0 0xff020000 0x0 0x1000>;
33744+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
33745+ clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
33746+ clock-names = "i2s_clk", "i2s_hclk";
33747+ dmas = <&dmac 0>, <&dmac 1>;
33748+ dma-names = "tx", "rx";
33749+ status = "disabled";
33750+ };
33751+
33752+ spdif: spdif@ff030000 {
33753+ compatible = "rockchip,rk3328-spdif";
33754+ reg = <0x0 0xff030000 0x0 0x1000>;
33755+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
33756+ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
33757+ clock-names = "mclk", "hclk";
33758+ dmas = <&dmac 10>;
33759+ dma-names = "tx";
33760+ pinctrl-names = "default";
33761+ pinctrl-0 = <&spdifm2_tx>;
33762+ status = "disabled";
33763+ };
33764+
33765+ pdm: pdm@ff040000 {
33766+ compatible = "rockchip,pdm";
33767+ reg = <0x0 0xff040000 0x0 0x1000>;
33768+ clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
33769+ clock-names = "pdm_clk", "pdm_hclk";
33770+ dmas = <&dmac 16>;
33771+ dma-names = "rx";
33772+ pinctrl-names = "default", "sleep";
33773+ pinctrl-0 = <&pdmm0_clk
33774+ &pdmm0_sdi0
33775+ &pdmm0_sdi1
33776+ &pdmm0_sdi2
33777+ &pdmm0_sdi3>;
33778+ pinctrl-1 = <&pdmm0_clk_sleep
33779+ &pdmm0_sdi0_sleep
33780+ &pdmm0_sdi1_sleep
33781+ &pdmm0_sdi2_sleep
33782+ &pdmm0_sdi3_sleep>;
33783+ status = "disabled";
33784+ };
33785+
33786 grf: syscon@ff100000 {
33787 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
33788 reg = <0x0 0xff100000 0x0 0x1000>;
33789 #address-cells = <1>;
33790 #size-cells = <1>;
33791
33792+ io_domains: io-domains {
33793+ compatible = "rockchip,rk3328-io-voltage-domain";
33794+ status = "disabled";
33795+ };
33796+
33797 power: power-controller {
33798 compatible = "rockchip,rk3328-power-controller";
33799 #power-domain-cells = <1>;
33800@@ -310,6 +429,108 @@ wdt: watchdog@ff1a0000 {
33801 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
33802 };
33803
33804+ pwm0: pwm@ff1b0000 {
33805+ compatible = "rockchip,rk3328-pwm";
33806+ reg = <0x0 0xff1b0000 0x0 0x10>;
33807+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
33808+ clock-names = "pwm", "pclk";
33809+ pinctrl-names = "default";
33810+ pinctrl-0 = <&pwm0_pin>;
33811+ #pwm-cells = <3>;
33812+ status = "disabled";
33813+ };
33814+
33815+ pwm1: pwm@ff1b0010 {
33816+ compatible = "rockchip,rk3328-pwm";
33817+ reg = <0x0 0xff1b0010 0x0 0x10>;
33818+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
33819+ clock-names = "pwm", "pclk";
33820+ pinctrl-names = "default";
33821+ pinctrl-0 = <&pwm1_pin>;
33822+ #pwm-cells = <3>;
33823+ status = "disabled";
33824+ };
33825+
33826+ pwm2: pwm@ff1b0020 {
33827+ compatible = "rockchip,rk3328-pwm";
33828+ reg = <0x0 0xff1b0020 0x0 0x10>;
33829+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
33830+ clock-names = "pwm", "pclk";
33831+ pinctrl-names = "default";
33832+ pinctrl-0 = <&pwm2_pin>;
33833+ #pwm-cells = <3>;
33834+ status = "disabled";
33835+ };
33836+
33837+ pwm3: pwm@ff1b0030 {
33838+ compatible = "rockchip,rk3328-pwm";
33839+ reg = <0x0 0xff1b0030 0x0 0x10>;
33840+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
33841+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
33842+ clock-names = "pwm", "pclk";
33843+ pinctrl-names = "default";
33844+ pinctrl-0 = <&pwmir_pin>;
33845+ #pwm-cells = <3>;
33846+ status = "disabled";
33847+ };
33848+
33849+ thermal-zones {
33850+ soc_thermal: soc-thermal {
33851+ polling-delay-passive = <20>;
33852+ polling-delay = <1000>;
33853+ sustainable-power = <1000>;
33854+
33855+ thermal-sensors = <&tsadc 0>;
33856+
33857+ trips {
33858+ threshold: trip-point0 {
33859+ temperature = <70000>;
33860+ hysteresis = <2000>;
33861+ type = "passive";
33862+ };
33863+ target: trip-point1 {
33864+ temperature = <85000>;
33865+ hysteresis = <2000>;
33866+ type = "passive";
33867+ };
33868+ soc_crit: soc-crit {
33869+ temperature = <95000>;
33870+ hysteresis = <2000>;
33871+ type = "critical";
33872+ };
33873+ };
33874+
33875+ cooling-maps {
33876+ map0 {
33877+ trip = <&target>;
33878+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
33879+ contribution = <4096>;
33880+ };
33881+ };
33882+ };
33883+
33884+ };
33885+
33886+ tsadc: tsadc@ff250000 {
33887+ compatible = "rockchip,rk3328-tsadc";
33888+ reg = <0x0 0xff250000 0x0 0x100>;
33889+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
33890+ assigned-clocks = <&cru SCLK_TSADC>;
33891+ assigned-clock-rates = <50000>;
33892+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
33893+ clock-names = "tsadc", "apb_pclk";
33894+ pinctrl-names = "init", "default", "sleep";
33895+ pinctrl-0 = <&otp_gpio>;
33896+ pinctrl-1 = <&otp_out>;
33897+ pinctrl-2 = <&otp_gpio>;
33898+ resets = <&cru SRST_TSADC>;
33899+ reset-names = "tsadc-apb";
33900+ rockchip,grf = <&grf>;
33901+ rockchip,hw-tshut-temp = <100000>;
33902+ #thermal-sensor-cells = <1>;
33903+ status = "disabled";
33904+ };
33905+
33906 saradc: adc@ff280000 {
33907 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
33908 reg = <0x0 0xff280000 0x0 0x100>;
33909@@ -322,6 +543,51 @@ saradc: adc@ff280000 {
33910 status = "disabled";
33911 };
33912
33913+ h265e_mmu: iommu@ff330200 {
33914+ compatible = "rockchip,iommu";
33915+ reg = <0x0 0xff330200 0 0x100>;
33916+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
33917+ interrupt-names = "h265e_mmu";
33918+ #iommu-cells = <0>;
33919+ status = "disabled";
33920+ };
33921+
33922+ vepu_mmu: iommu@ff340800 {
33923+ compatible = "rockchip,iommu";
33924+ reg = <0x0 0xff340800 0x0 0x40>;
33925+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33926+ interrupt-names = "vepu_mmu";
33927+ #iommu-cells = <0>;
33928+ status = "disabled";
33929+ };
33930+
33931+ vpu_mmu: iommu@ff350800 {
33932+ compatible = "rockchip,iommu";
33933+ reg = <0x0 0xff350800 0x0 0x40>;
33934+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
33935+ interrupt-names = "vpu_mmu";
33936+ #iommu-cells = <0>;
33937+ status = "disabled";
33938+ };
33939+
33940+ rkvdec_mmu: iommu@ff360480 {
33941+ compatible = "rockchip,iommu";
33942+ reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
33943+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
33944+ interrupt-names = "rkvdec_mmu";
33945+ #iommu-cells = <0>;
33946+ status = "disabled";
33947+ };
33948+
33949+ vop_mmu: iommu@ff373f00 {
33950+ compatible = "rockchip,iommu";
33951+ reg = <0x0 0xff373f00 0x0 0x100>;
33952+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
33953+ interrupt-names = "vop_mmu";
33954+ #iommu-cells = <0>;
33955+ status = "disabled";
33956+ };
33957+
33958 cru: clock-controller@ff440000 {
33959 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
33960 reg = <0x0 0xff440000 0x0 0x1000>;
33961@@ -374,6 +640,43 @@ cru: clock-controller@ff440000 {
33962 <32768>;
33963 };
33964
33965+ usb2phy_grf: syscon@ff450000 {
33966+ compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
33967+ "simple-mfd";
33968+ reg = <0x0 0xff450000 0x0 0x10000>;
33969+ #address-cells = <1>;
33970+ #size-cells = <1>;
33971+
33972+ u2phy: usb2-phy@100 {
33973+ compatible = "rockchip,rk3328-usb2phy";
33974+ reg = <0x100 0x10>;
33975+ clocks = <&xin24m>;
33976+ clock-names = "phyclk";
33977+ clock-output-names = "usb480m_phy";
33978+ #clock-cells = <0>;
33979+ assigned-clocks = <&cru USB480M>;
33980+ assigned-clock-parents = <&u2phy>;
33981+ status = "disabled";
33982+
33983+ u2phy_otg: otg-port {
33984+ #phy-cells = <0>;
33985+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
33986+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
33987+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
33988+ interrupt-names = "otg-bvalid", "otg-id",
33989+ "linestate";
33990+ status = "disabled";
33991+ };
33992+
33993+ u2phy_host: host-port {
33994+ #phy-cells = <0>;
33995+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
33996+ interrupt-names = "linestate";
33997+ status = "disabled";
33998+ };
33999+ };
34000+ };
34001+
34002 sdmmc: dwmmc@ff500000 {
34003 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
34004 reg = <0x0 0xff500000 0x0 0x4000>;
34005@@ -463,6 +766,45 @@ phy: phy@0 {
34006 };
34007 };
34008
34009+ usb20_otg: usb@ff580000 {
34010+ compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
34011+ "snps,dwc2";
34012+ reg = <0x0 0xff580000 0x0 0x40000>;
34013+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
34014+ clocks = <&cru HCLK_OTG>;
34015+ clock-names = "otg";
34016+ dr_mode = "otg";
34017+ g-np-tx-fifo-size = <16>;
34018+ g-rx-fifo-size = <280>;
34019+ g-tx-fifo-size = <256 128 128 64 32 16>;
34020+ g-use-dma;
34021+ phys = <&u2phy_otg>;
34022+ phy-names = "usb2-phy";
34023+ status = "disabled";
34024+ };
34025+
34026+ usb_host0_ehci: usb@ff5c0000 {
34027+ compatible = "generic-ehci";
34028+ reg = <0x0 0xff5c0000 0x0 0x10000>;
34029+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
34030+ clocks = <&cru HCLK_HOST0>, <&u2phy>;
34031+ clock-names = "usbhost", "utmi";
34032+ phys = <&u2phy_host>;
34033+ phy-names = "usb";
34034+ status = "disabled";
34035+ };
34036+
34037+ usb_host0_ohci: usb@ff5d0000 {
34038+ compatible = "generic-ohci";
34039+ reg = <0x0 0xff5d0000 0x0 0x10000>;
34040+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
34041+ clocks = <&cru HCLK_HOST0>, <&u2phy>;
34042+ clock-names = "usbhost", "utmi";
34043+ phys = <&u2phy_host>;
34044+ phy-names = "usb";
34045+ status = "disabled";
34046+ };
34047+
34048 gic: interrupt-controller@ff811000 {
34049 compatible = "arm,gic-400";
34050 #interrupt-cells = <3>;
34051@@ -649,6 +991,62 @@ hdmii2c_xfer: hdmii2c-xfer {
34052 };
34053 };
34054
34055+ pdm-0 {
34056+ pdmm0_clk: pdmm0-clk {
34057+ rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
34058+ };
34059+
34060+ pdmm0_fsync: pdmm0-fsync {
34061+ rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
34062+ };
34063+
34064+ pdmm0_sdi0: pdmm0-sdi0 {
34065+ rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
34066+ };
34067+
34068+ pdmm0_sdi1: pdmm0-sdi1 {
34069+ rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
34070+ };
34071+
34072+ pdmm0_sdi2: pdmm0-sdi2 {
34073+ rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
34074+ };
34075+
34076+ pdmm0_sdi3: pdmm0-sdi3 {
34077+ rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
34078+ };
34079+
34080+ pdmm0_clk_sleep: pdmm0-clk-sleep {
34081+ rockchip,pins =
34082+ <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
34083+ };
34084+
34085+ pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
34086+ rockchip,pins =
34087+ <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
34088+ };
34089+
34090+ pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
34091+ rockchip,pins =
34092+ <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
34093+ };
34094+
34095+ pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
34096+ rockchip,pins =
34097+ <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
34098+ };
34099+
34100+ pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
34101+ rockchip,pins =
34102+ <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
34103+ };
34104+
34105+ pdmm0_fsync_sleep: pdmm0-fsync-sleep {
34106+ rockchip,pins =
34107+ <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
34108+ };
34109+ };
34110+
34111 tsadc {
34112 otp_gpio: otp-gpio {
34113 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
34114diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
34115index 4772917c5f7e..a37220a9387c 100644
34116--- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
34117+++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
34118@@ -156,7 +156,6 @@ &emmc {
34119 disable-wp;
34120 mmc-pwrseq = <&emmc_pwrseq>;
34121 non-removable;
34122- num-slots = <1>;
34123 pinctrl-names = "default";
34124 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
34125 status = "okay";
34126diff --git a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
34127index e631d424f08e..5e4d3a7015f5 100644
34128--- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
34129+++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
34130@@ -117,7 +117,6 @@ &emmc {
34131 clock-frequency = <150000000>;
34132 disable-wp;
34133 non-removable;
34134- num-slots = <1>;
34135 vmmc-supply = <&vcc_io>;
34136 vqmmc-supply = <&vcc18_flash>;
34137 pinctrl-names = "default";
34138diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
34139index fac116acc12f..d3f6c8e0d206 100644
34140--- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
34141+++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
34142@@ -203,7 +203,6 @@ &emmc {
34143 mmc-hs200-1_2v;
34144 mmc-hs200-1_8v;
34145 non-removable;
34146- num-slots = <1>;
34147 pinctrl-names = "default";
34148 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
34149 status = "okay";
34150@@ -347,7 +346,6 @@ &sdmmc {
34151 max-frequency = <50000000>;
34152 cap-sd-highspeed;
34153 card-detect-delay = <200>;
34154- num-slots = <1>;
34155 pinctrl-names = "default";
34156 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
34157 vmmc-supply = <&vcc_sd>;
34158diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
34159index ff48edd8e348..13a9e22f5d2d 100644
34160--- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
34161+++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
34162@@ -86,12 +86,10 @@ &emmc {
34163 cap-mmc-highspeed;
34164 clock-frequency = <150000000>;
34165 disable-wp;
34166- keep-power-in-suspend;
34167 mmc-hs200-1_8v;
34168 no-sdio;
34169 no-sd;
34170 non-removable;
34171- num-slots = <1>;
34172 pinctrl-names = "default";
34173 pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
34174 vmmc-supply = <&vcc_io>;
34175@@ -281,7 +279,6 @@ &sdmmc {
34176 card-detect-delay = <200>;
34177 no-emmc;
34178 no-sdio;
34179- num-slots = <1>;
34180 sd-uhs-sdr12;
34181 sd-uhs-sdr25;
34182 pinctrl-names = "default";
34183diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
34184index 7134181f1dc2..b3510d56517a 100644
34185--- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
34186+++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
34187@@ -189,7 +189,6 @@ &emmc {
34188 disable-wp;
34189 mmc-pwrseq = <&emmc_pwrseq>;
34190 non-removable;
34191- num-slots = <1>;
34192 pinctrl-names = "default";
34193 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
34194 status = "okay";
34195@@ -254,7 +253,6 @@ &sdio0 {
34196 keep-power-in-suspend;
34197 mmc-pwrseq = <&sdio_pwrseq>;
34198 non-removable;
34199- num-slots = <1>;
34200 pinctrl-names = "default";
34201 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
34202 vmmc-supply = <&vcc_io>;
34203diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
34204index 6d5dc0587e59..e0518b4bc6c2 100644
34205--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
34206+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
34207@@ -113,7 +113,8 @@ cpu_l0: cpu@0 {
34208 compatible = "arm,cortex-a53", "arm,armv8";
34209 reg = <0x0 0x0>;
34210 enable-method = "psci";
34211-
34212+ clocks = <&cru ARMCLKL>;
34213+ operating-points-v2 = <&cluster0_opp>;
34214 #cooling-cells = <2>; /* min followed by max */
34215 };
34216
34217@@ -122,6 +123,8 @@ cpu_l1: cpu@1 {
34218 compatible = "arm,cortex-a53", "arm,armv8";
34219 reg = <0x0 0x1>;
34220 enable-method = "psci";
34221+ clocks = <&cru ARMCLKL>;
34222+ operating-points-v2 = <&cluster0_opp>;
34223 };
34224
34225 cpu_l2: cpu@2 {
34226@@ -129,6 +132,8 @@ cpu_l2: cpu@2 {
34227 compatible = "arm,cortex-a53", "arm,armv8";
34228 reg = <0x0 0x2>;
34229 enable-method = "psci";
34230+ clocks = <&cru ARMCLKL>;
34231+ operating-points-v2 = <&cluster0_opp>;
34232 };
34233
34234 cpu_l3: cpu@3 {
34235@@ -136,6 +141,8 @@ cpu_l3: cpu@3 {
34236 compatible = "arm,cortex-a53", "arm,armv8";
34237 reg = <0x0 0x3>;
34238 enable-method = "psci";
34239+ clocks = <&cru ARMCLKL>;
34240+ operating-points-v2 = <&cluster0_opp>;
34241 };
34242
34243 cpu_b0: cpu@100 {
34244@@ -143,7 +150,8 @@ cpu_b0: cpu@100 {
34245 compatible = "arm,cortex-a53", "arm,armv8";
34246 reg = <0x0 0x100>;
34247 enable-method = "psci";
34248-
34249+ clocks = <&cru ARMCLKB>;
34250+ operating-points-v2 = <&cluster1_opp>;
34251 #cooling-cells = <2>; /* min followed by max */
34252 };
34253
34254@@ -152,6 +160,8 @@ cpu_b1: cpu@101 {
34255 compatible = "arm,cortex-a53", "arm,armv8";
34256 reg = <0x0 0x101>;
34257 enable-method = "psci";
34258+ clocks = <&cru ARMCLKB>;
34259+ operating-points-v2 = <&cluster1_opp>;
34260 };
34261
34262 cpu_b2: cpu@102 {
34263@@ -159,6 +169,8 @@ cpu_b2: cpu@102 {
34264 compatible = "arm,cortex-a53", "arm,armv8";
34265 reg = <0x0 0x102>;
34266 enable-method = "psci";
34267+ clocks = <&cru ARMCLKB>;
34268+ operating-points-v2 = <&cluster1_opp>;
34269 };
34270
34271 cpu_b3: cpu@103 {
34272@@ -166,6 +178,62 @@ cpu_b3: cpu@103 {
34273 compatible = "arm,cortex-a53", "arm,armv8";
34274 reg = <0x0 0x103>;
34275 enable-method = "psci";
34276+ clocks = <&cru ARMCLKB>;
34277+ operating-points-v2 = <&cluster1_opp>;
34278+ };
34279+ };
34280+
34281+ cluster0_opp: opp-table0 {
34282+ compatible = "operating-points-v2";
34283+ opp-shared;
34284+
34285+ opp00 {
34286+ opp-hz = /bits/ 64 <312000000>;
34287+ opp-microvolt = <950000>;
34288+ clock-latency-ns = <40000>;
34289+ };
34290+ opp01 {
34291+ opp-hz = /bits/ 64 <408000000>;
34292+ opp-microvolt = <950000>;
34293+ };
34294+ opp02 {
34295+ opp-hz = /bits/ 64 <600000000>;
34296+ opp-microvolt = <950000>;
34297+ };
34298+ opp03 {
34299+ opp-hz = /bits/ 64 <816000000>;
34300+ opp-microvolt = <1025000>;
34301+ };
34302+ opp04 {
34303+ opp-hz = /bits/ 64 <1008000000>;
34304+ opp-microvolt = <1125000>;
34305+ };
34306+ };
34307+
34308+ cluster1_opp: opp-table1 {
34309+ compatible = "operating-points-v2";
34310+ opp-shared;
34311+
34312+ opp00 {
34313+ opp-hz = /bits/ 64 <312000000>;
34314+ opp-microvolt = <950000>;
34315+ clock-latency-ns = <40000>;
34316+ };
34317+ opp01 {
34318+ opp-hz = /bits/ 64 <408000000>;
34319+ opp-microvolt = <950000>;
34320+ };
34321+ opp02 {
34322+ opp-hz = /bits/ 64 <600000000>;
34323+ opp-microvolt = <950000>;
34324+ };
34325+ opp03 {
34326+ opp-hz = /bits/ 64 <816000000>;
34327+ opp-microvolt = <975000>;
34328+ };
34329+ opp04 {
34330+ opp-hz = /bits/ 64 <1008000000>;
34331+ opp-microvolt = <1050000>;
34332 };
34333 };
34334
34335@@ -700,6 +768,19 @@ timer@ff810000 {
34336 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
34337 };
34338
34339+ spdif: spdif@ff880000 {
34340+ compatible = "rockchip,rk3368-spdif";
34341+ reg = <0x0 0xff880000 0x0 0x1000>;
34342+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
34343+ clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
34344+ clock-names = "mclk", "hclk";
34345+ dmas = <&dmac_bus 3>;
34346+ dma-names = "tx";
34347+ pinctrl-names = "default";
34348+ pinctrl-0 = <&spdif_tx>;
34349+ status = "disabled";
34350+ };
34351+
34352 i2s_2ch: i2s-2ch@ff890000 {
34353 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
34354 reg = <0x0 0xff890000 0x0 0x1000>;
34355@@ -724,6 +805,55 @@ i2s_8ch: i2s-8ch@ff898000 {
34356 status = "disabled";
34357 };
34358
34359+ iep_mmu: iommu@ff900800 {
34360+ compatible = "rockchip,iommu";
34361+ reg = <0x0 0xff900800 0x0 0x100>;
34362+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
34363+ interrupt-names = "iep_mmu";
34364+ #iommu-cells = <0>;
34365+ status = "disabled";
34366+ };
34367+
34368+ isp_mmu: iommu@ff914000 {
34369+ compatible = "rockchip,iommu";
34370+ reg = <0x0 0xff914000 0x0 0x100>,
34371+ <0x0 0xff915000 0x0 0x100>;
34372+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
34373+ interrupt-names = "isp_mmu";
34374+ #iommu-cells = <0>;
34375+ rockchip,disable-mmu-reset;
34376+ status = "disabled";
34377+ };
34378+
34379+ vop_mmu: iommu@ff930300 {
34380+ compatible = "rockchip,iommu";
34381+ reg = <0x0 0xff930300 0x0 0x100>;
34382+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
34383+ interrupt-names = "vop_mmu";
34384+ #iommu-cells = <0>;
34385+ status = "disabled";
34386+ };
34387+
34388+ hevc_mmu: iommu@ff9a0440 {
34389+ compatible = "rockchip,iommu";
34390+ reg = <0x0 0xff9a0440 0x0 0x40>,
34391+ <0x0 0xff9a0480 0x0 0x40>;
34392+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
34393+ interrupt-names = "hevc_mmu";
34394+ #iommu-cells = <0>;
34395+ status = "disabled";
34396+ };
34397+
34398+ vpu_mmu: iommu@ff9a0800 {
34399+ compatible = "rockchip,iommu";
34400+ reg = <0x0 0xff9a0800 0x0 0x100>;
34401+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
34402+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
34403+ interrupt-names = "vepu_mmu", "vdpu_mmu";
34404+ #iommu-cells = <0>;
34405+ status = "disabled";
34406+ };
34407+
34408 gic: interrupt-controller@ffb71000 {
34409 compatible = "arm,gic-400";
34410 interrupt-controller;
34411@@ -1024,6 +1154,12 @@ sdmmc_bus4: sdmmc-bus4 {
34412 };
34413 };
34414
34415+ spdif {
34416+ spdif_tx: spdif-tx {
34417+ rockchip,pins = <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
34418+ };
34419+ };
34420+
34421 spi0 {
34422 spi0_clk: spi0-clk {
34423 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
34424diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
34425index 42033bcc614c..56533c344ef2 100644
34426--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
34427+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
34428@@ -199,7 +199,7 @@ &pcie0 {
34429 ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
34430 num-lanes = <4>;
34431 pinctrl-names = "default";
34432- pinctrl-0 = <&pcie_clkreqn>;
34433+ pinctrl-0 = <&pcie_clkreqn_cpm>;
34434 status = "disabled";
34435 };
34436
34437diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
34438index ba1d9810ad1e..7fd4bfcaa38e 100644
34439--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
34440+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
34441@@ -43,6 +43,7 @@
34442 /dts-v1/;
34443 #include <dt-bindings/pwm/pwm.h>
34444 #include "rk3399.dtsi"
34445+#include "rk3399-opp.dtsi"
34446
34447 / {
34448 model = "Firefly-RK3399 Board";
34449@@ -550,7 +551,7 @@ &pcie0 {
34450 ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
34451 num-lanes = <4>;
34452 pinctrl-names = "default";
34453- pinctrl-0 = <&pcie_clkreqn>;
34454+ pinctrl-0 = <&pcie_clkreqn_cpm>;
34455 status = "okay";
34456 };
34457
34458@@ -630,9 +631,20 @@ &saradc {
34459 status = "okay";
34460 };
34461
34462+&sdmmc {
34463+ bus-width = <4>;
34464+ cap-mmc-highspeed;
34465+ cap-sd-highspeed;
34466+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
34467+ disable-wp;
34468+ max-frequency = <150000000>;
34469+ pinctrl-names = "default";
34470+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
34471+ status = "okay";
34472+};
34473+
34474 &sdhci {
34475 bus-width = <8>;
34476- keep-power-in-suspend;
34477 mmc-hs400-1_8v;
34478 mmc-hs400-enhanced-strobe;
34479 non-removable;
34480diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
34481index 7bd31066399b..a3d3cea7dc4f 100644
34482--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
34483+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
34484@@ -264,6 +264,50 @@ touchscreen@4b {
34485 };
34486 };
34487
34488+&ppvar_bigcpu_pwm {
34489+ regulator-min-microvolt = <798674>;
34490+ regulator-max-microvolt = <1302172>;
34491+};
34492+
34493+&ppvar_bigcpu {
34494+ regulator-min-microvolt = <798674>;
34495+ regulator-max-microvolt = <1302172>;
34496+ ctrl-voltage-range = <798674 1302172>;
34497+};
34498+
34499+&ppvar_litcpu_pwm {
34500+ regulator-min-microvolt = <799065>;
34501+ regulator-max-microvolt = <1303738>;
34502+};
34503+
34504+&ppvar_litcpu {
34505+ regulator-min-microvolt = <799065>;
34506+ regulator-max-microvolt = <1303738>;
34507+ ctrl-voltage-range = <799065 1303738>;
34508+};
34509+
34510+&ppvar_gpu_pwm {
34511+ regulator-min-microvolt = <785782>;
34512+ regulator-max-microvolt = <1217729>;
34513+};
34514+
34515+&ppvar_gpu {
34516+ regulator-min-microvolt = <785782>;
34517+ regulator-max-microvolt = <1217729>;
34518+ ctrl-voltage-range = <785782 1217729>;
34519+};
34520+
34521+&ppvar_centerlogic_pwm {
34522+ regulator-min-microvolt = <800069>;
34523+ regulator-max-microvolt = <1049692>;
34524+};
34525+
34526+&ppvar_centerlogic {
34527+ regulator-min-microvolt = <800069>;
34528+ regulator-max-microvolt = <1049692>;
34529+ ctrl-voltage-range = <800069 1049692>;
34530+};
34531+
34532 &saradc {
34533 status = "okay";
34534 vref-supply = <&pp1800_ap_io>;
34535diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
34536index eb5059344023..199a5118b20d 100644
34537--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
34538+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
34539@@ -164,14 +164,9 @@ pp5000: pp5000 {
34540 vin-supply = <&ppvar_sys>;
34541 };
34542
34543- ppvar_bigcpu: ppvar-bigcpu {
34544+ ppvar_bigcpu_pwm: ppvar-bigcpu-pwm {
34545 compatible = "pwm-regulator";
34546- regulator-name = "ppvar_bigcpu";
34547- /*
34548- * OVP circuit requires special handling which is not yet
34549- * represented. Keep disabled for now.
34550- */
34551- status = "disabled";
34552+ regulator-name = "ppvar_bigcpu_pwm";
34553
34554 pwms = <&pwm1 0 3337 0>;
34555 pwm-supply = <&ppvar_sys>;
34556@@ -181,18 +176,28 @@ ppvar_bigcpu: ppvar-bigcpu {
34557 /* EC turns on w/ ap_core_en; always on for AP */
34558 regulator-always-on;
34559 regulator-boot-on;
34560- regulator-min-microvolt = <798674>;
34561- regulator-max-microvolt = <1302172>;
34562+ regulator-min-microvolt = <800107>;
34563+ regulator-max-microvolt = <1302232>;
34564 };
34565
34566- ppvar_litcpu: ppvar-litcpu {
34567+ ppvar_bigcpu: ppvar-bigcpu {
34568+ compatible = "vctrl-regulator";
34569+ regulator-name = "ppvar_bigcpu";
34570+
34571+ regulator-min-microvolt = <800107>;
34572+ regulator-max-microvolt = <1302232>;
34573+
34574+ ctrl-supply = <&ppvar_bigcpu_pwm>;
34575+ ctrl-voltage-range = <800107 1302232>;
34576+
34577+ regulator-settling-time-up-us = <322>;
34578+ min-slew-down-rate = <225>;
34579+ ovp-threshold-percent = <16>;
34580+ };
34581+
34582+ ppvar_litcpu_pwm: ppvar-litcpu-pwm {
34583 compatible = "pwm-regulator";
34584- regulator-name = "ppvar_litcpu";
34585- /*
34586- * OVP circuit requires special handling which is not yet
34587- * represented. Keep disabled for now.
34588- */
34589- status = "disabled";
34590+ regulator-name = "ppvar_litcpu_pwm";
34591
34592 pwms = <&pwm2 0 3337 0>;
34593 pwm-supply = <&ppvar_sys>;
34594@@ -202,18 +207,28 @@ ppvar_litcpu: ppvar-litcpu {
34595 /* EC turns on w/ ap_core_en; always on for AP */
34596 regulator-always-on;
34597 regulator-boot-on;
34598- regulator-min-microvolt = <799065>;
34599- regulator-max-microvolt = <1303738>;
34600+ regulator-min-microvolt = <797743>;
34601+ regulator-max-microvolt = <1307837>;
34602 };
34603
34604- ppvar_gpu: ppvar-gpu {
34605+ ppvar_litcpu: ppvar-litcpu {
34606+ compatible = "vctrl-regulator";
34607+ regulator-name = "ppvar_litcpu";
34608+
34609+ regulator-min-microvolt = <797743>;
34610+ regulator-max-microvolt = <1307837>;
34611+
34612+ ctrl-supply = <&ppvar_litcpu_pwm>;
34613+ ctrl-voltage-range = <797743 1307837>;
34614+
34615+ regulator-settling-time-up-us = <384>;
34616+ min-slew-down-rate = <225>;
34617+ ovp-threshold-percent = <16>;
34618+ };
34619+
34620+ ppvar_gpu_pwm: ppvar-gpu-pwm {
34621 compatible = "pwm-regulator";
34622- regulator-name = "ppvar_gpu";
34623- /*
34624- * OVP circuit requires special handling which is not yet
34625- * represented. Keep disabled for now.
34626- */
34627- status = "disabled";
34628+ regulator-name = "ppvar_gpu_pwm";
34629
34630 pwms = <&pwm0 0 3337 0>;
34631 pwm-supply = <&ppvar_sys>;
34632@@ -223,18 +238,28 @@ ppvar_gpu: ppvar-gpu {
34633 /* EC turns on w/ ap_core_en; always on for AP */
34634 regulator-always-on;
34635 regulator-boot-on;
34636- regulator-min-microvolt = <785782>;
34637- regulator-max-microvolt = <1217729>;
34638+ regulator-min-microvolt = <786384>;
34639+ regulator-max-microvolt = <1217747>;
34640 };
34641
34642- ppvar_centerlogic: ppvar-centerlogic {
34643+ ppvar_gpu: ppvar-gpu {
34644+ compatible = "vctrl-regulator";
34645+ regulator-name = "ppvar_gpu";
34646+
34647+ regulator-min-microvolt = <786384>;
34648+ regulator-max-microvolt = <1217747>;
34649+
34650+ ctrl-supply = <&ppvar_gpu_pwm>;
34651+ ctrl-voltage-range = <786384 1217747>;
34652+
34653+ regulator-settling-time-up-us = <390>;
34654+ min-slew-down-rate = <225>;
34655+ ovp-threshold-percent = <16>;
34656+ };
34657+
34658+ ppvar_centerlogic_pwm: ppvar-centerlogic-pwm {
34659 compatible = "pwm-regulator";
34660- regulator-name = "ppvar_centerlogic";
34661- /*
34662- * OVP circuit requires special handling which is not yet
34663- * represented. Keep disabled for now.
34664- */
34665- status = "disabled";
34666+ regulator-name = "ppvar_centerlogic_pwm";
34667
34668 pwms = <&pwm3 0 3337 0>;
34669 pwm-supply = <&ppvar_sys>;
34670@@ -244,8 +269,23 @@ ppvar_centerlogic: ppvar-centerlogic {
34671 /* EC turns on w/ ppvar_centerlogic_en; always on for AP */
34672 regulator-always-on;
34673 regulator-boot-on;
34674- regulator-min-microvolt = <800069>;
34675- regulator-max-microvolt = <1049692>;
34676+ regulator-min-microvolt = <799434>;
34677+ regulator-max-microvolt = <1049925>;
34678+ };
34679+
34680+ ppvar_centerlogic: ppvar-centerlogic {
34681+ compatible = "vctrl-regulator";
34682+ regulator-name = "ppvar_centerlogic";
34683+
34684+ regulator-min-microvolt = <799434>;
34685+ regulator-max-microvolt = <1049925>;
34686+
34687+ ctrl-supply = <&ppvar_centerlogic_pwm>;
34688+ ctrl-voltage-range = <799434 1049925>;
34689+
34690+ regulator-settling-time-up-us = <378>;
34691+ min-slew-down-rate = <225>;
34692+ ovp-threshold-percent = <16>;
34693 };
34694
34695 /* Schematics call this PPVAR even though it's fixed */
34696@@ -555,6 +595,11 @@ &emmc_phy {
34697 status = "okay";
34698 };
34699
34700+&gpu {
34701+ mali-supply = <&ppvar_gpu>;
34702+ status = "okay";
34703+};
34704+
34705 ap_i2c_mic: &i2c1 {
34706 status = "okay";
34707
34708@@ -567,12 +612,7 @@ ap_i2c_mic: &i2c1 {
34709 headsetcodec: rt5514@57 {
34710 compatible = "realtek,rt5514";
34711 reg = <0x57>;
34712- interrupt-parent = <&gpio1>;
34713- interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
34714- pinctrl-names = "default";
34715- pinctrl-0 = <&mic_int>;
34716- realtek,dmic-init-delay = <20>;
34717- wakeup-source;
34718+ realtek,dmic-init-delay-ms = <20>;
34719 };
34720 };
34721
34722@@ -781,9 +821,13 @@ &spi2 {
34723 wacky_spi_audio: spi2@0 {
34724 compatible = "realtek,rt5514";
34725 reg = <0>;
34726-
34727+ interrupt-parent = <&gpio1>;
34728+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
34729+ pinctrl-names = "default";
34730+ pinctrl-0 = <&mic_int>;
34731 /* May run faster once verified. */
34732 spi-max-frequency = <10000000>;
34733+ wakeup-source;
34734 };
34735 };
34736
34737@@ -1031,7 +1075,7 @@ sdmmc_cmd: sdmmc-cmd {
34738 * hurt and dw_mmc will ignore it. We make sure to disable
34739 * the pull though so we don't burn needless power.
34740 */
34741- sdmmc_cd: sdmcc-cd {
34742+ sdmmc_cd: sdmmc-cd {
34743 rockchip,pins =
34744 <0 7 RK_FUNC_1 &pcfg_pull_none>;
34745 };
34746diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
34747index be7fe635f7c1..d8a120f945c8 100644
34748--- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
34749+++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
34750@@ -118,6 +118,35 @@ opp08 {
34751 opp-microvolt = <1250000>;
34752 };
34753 };
34754+
34755+ gpu_opp_table: opp-table2 {
34756+ compatible = "operating-points-v2";
34757+
34758+ opp00 {
34759+ opp-hz = /bits/ 64 <200000000>;
34760+ opp-microvolt = <800000>;
34761+ };
34762+ opp01 {
34763+ opp-hz = /bits/ 64 <297000000>;
34764+ opp-microvolt = <800000>;
34765+ };
34766+ opp02 {
34767+ opp-hz = /bits/ 64 <400000000>;
34768+ opp-microvolt = <825000>;
34769+ };
34770+ opp03 {
34771+ opp-hz = /bits/ 64 <500000000>;
34772+ opp-microvolt = <850000>;
34773+ };
34774+ opp04 {
34775+ opp-hz = /bits/ 64 <600000000>;
34776+ opp-microvolt = <925000>;
34777+ };
34778+ opp05 {
34779+ opp-hz = /bits/ 64 <800000000>;
34780+ opp-microvolt = <1075000>;
34781+ };
34782+ };
34783 };
34784
34785 &cpu_l0 {
34786@@ -143,3 +172,7 @@ &cpu_b0 {
34787 &cpu_b1 {
34788 operating-points-v2 = <&cluster1_opp>;
34789 };
34790+
34791+&gpu {
34792+ operating-points-v2 = <&gpu_opp_table>;
34793+};
34794diff --git a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
34795index c83460db130a..81617bcf2522 100644
34796--- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
34797+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
34798@@ -110,6 +110,35 @@ opp07 {
34799 opp-microvolt = <1200000>;
34800 };
34801 };
34802+
34803+ gpu_opp_table: opp-table2 {
34804+ compatible = "operating-points-v2";
34805+
34806+ opp00 {
34807+ opp-hz = /bits/ 64 <200000000>;
34808+ opp-microvolt = <800000>;
34809+ };
34810+ opp01 {
34811+ opp-hz = /bits/ 64 <297000000>;
34812+ opp-microvolt = <800000>;
34813+ };
34814+ opp02 {
34815+ opp-hz = /bits/ 64 <400000000>;
34816+ opp-microvolt = <825000>;
34817+ };
34818+ opp03 {
34819+ opp-hz = /bits/ 64 <500000000>;
34820+ opp-microvolt = <875000>;
34821+ };
34822+ opp04 {
34823+ opp-hz = /bits/ 64 <600000000>;
34824+ opp-microvolt = <925000>;
34825+ };
34826+ opp05 {
34827+ opp-hz = /bits/ 64 <800000000>;
34828+ opp-microvolt = <1100000>;
34829+ };
34830+ };
34831 };
34832
34833 &cpu_l0 {
34834@@ -135,3 +164,7 @@ &cpu_b0 {
34835 &cpu_b1 {
34836 operating-points-v2 = <&cluster1_opp>;
34837 };
34838+
34839+&gpu {
34840+ operating-points-v2 = <&gpu_opp_table>;
34841+};
34842diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
34843new file mode 100644
34844index 000000000000..9a7486058455
34845--- /dev/null
34846+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
34847@@ -0,0 +1,228 @@
34848+/*
34849+ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
34850+ *
34851+ * This file is dual-licensed: you can use it either under the terms
34852+ * of the GPL or the X11 license, at your option. Note that this dual
34853+ * licensing only applies to this file, and not this project as a
34854+ * whole.
34855+ *
34856+ * a) This file is free software; you can redistribute it and/or
34857+ * modify it under the terms of the GNU General Public License as
34858+ * published by the Free Software Foundation; either version 2 of the
34859+ * License, or (at your option) any later version.
34860+ *
34861+ * This file is distributed in the hope that it will be useful,
34862+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
34863+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34864+ * GNU General Public License for more details.
34865+ *
34866+ * Or, alternatively,
34867+ *
34868+ * b) Permission is hereby granted, free of charge, to any person
34869+ * obtaining a copy of this software and associated documentation
34870+ * files (the "Software"), to deal in the Software without
34871+ * restriction, including without limitation the rights to use,
34872+ * copy, modify, merge, publish, distribute, sublicense, and/or
34873+ * sell copies of the Software, and to permit persons to whom the
34874+ * Software is furnished to do so, subject to the following
34875+ * conditions:
34876+ *
34877+ * The above copyright notice and this permission notice shall be
34878+ * included in all copies or substantial portions of the Software.
34879+ *
34880+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34881+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34882+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34883+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
34884+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
34885+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
34886+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
34887+ * OTHER DEALINGS IN THE SOFTWARE.
34888+ */
34889+
34890+/dts-v1/;
34891+#include "rk3399-puma.dtsi"
34892+
34893+/ {
34894+ model = "Theobroma Systems RK3399-Q7 SoM";
34895+ compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399";
34896+
34897+ chosen {
34898+ stdout-path = "serial0:115200n8";
34899+ };
34900+
34901+ leds {
34902+ pinctrl-0 = <&led_pin_module>, <&led_sd_haikou>;
34903+
34904+ sd-card-led {
34905+ label = "sd_card_led";
34906+ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
34907+ linux,default-trigger = "mmc0";
34908+ };
34909+ };
34910+
34911+ dc_12v: dc-12v {
34912+ compatible = "regulator-fixed";
34913+ regulator-name = "dc_12v";
34914+ regulator-always-on;
34915+ regulator-boot-on;
34916+ regulator-min-microvolt = <12000000>;
34917+ regulator-max-microvolt = <12000000>;
34918+ };
34919+
34920+ vcc3v3_baseboard: vcc3v3-baseboard {
34921+ compatible = "regulator-fixed";
34922+ regulator-name = "vcc3v3_baseboard";
34923+ regulator-always-on;
34924+ regulator-boot-on;
34925+ regulator-min-microvolt = <3300000>;
34926+ regulator-max-microvolt = <3300000>;
34927+ vin-supply = <&dc_12v>;
34928+ };
34929+
34930+ vcc5v0_otg: vcc5v0-otg-regulator {
34931+ compatible = "regulator-fixed";
34932+ enable-active-high;
34933+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
34934+ pinctrl-names = "default";
34935+ pinctrl-0 = <&otg_vbus_drv>;
34936+ regulator-name = "vcc5v0_otg";
34937+ regulator-always-on;
34938+ };
34939+};
34940+
34941+&i2c1 {
34942+ status = "okay";
34943+ clock-frequency = <400000>;
34944+};
34945+
34946+&i2c2 {
34947+ status = "okay";
34948+ clock-frequency = <400000>;
34949+};
34950+
34951+&i2c3 {
34952+ i2c-scl-rising-time-ns = <450>;
34953+ i2c-scl-falling-time-ns = <15>;
34954+ status = "okay";
34955+};
34956+
34957+&i2c4 {
34958+ status = "okay";
34959+ clock-frequency = <400000>;
34960+};
34961+
34962+&i2c6 {
34963+ status = "okay";
34964+ clock-frequency = <400000>;
34965+};
34966+
34967+&i2s0 {
34968+ status = "okay";
34969+ rockchip,playback-channels = <8>;
34970+ rockchip,capture-channels = <8>;
34971+ #sound-dai-cells = <0>;
34972+ status = "okay";
34973+};
34974+
34975+&pcie_phy {
34976+ status = "okay";
34977+};
34978+
34979+&pcie0 {
34980+ ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
34981+ num-lanes = <4>;
34982+ pinctrl-names = "default";
34983+ pinctrl-0 = <&pcie_clkreqn_cpm>;
34984+ status = "okay";
34985+};
34986+
34987+&pinctrl {
34988+ pinctrl-names = "default";
34989+ pinctrl-0 = <&haikou_pin_hog>;
34990+
34991+ hog {
34992+ haikou_pin_hog: haikou-pin-hog {
34993+ rockchip,pins =
34994+ /* LID_BTN */
34995+ <RK_GPIO0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
34996+ /* BATLOW# */
34997+ <RK_GPIO0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
34998+ /* SLP_BTN# */
34999+ <RK_GPIO0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
35000+ /* BIOS_DISABLE# */
35001+ <RK_GPIO0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
35002+ };
35003+ };
35004+
35005+ leds {
35006+ led_sd_haikou: led-sd-gpio {
35007+ rockchip,pins =
35008+ <RK_GPIO1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
35009+ };
35010+ };
35011+
35012+ usb2 {
35013+ otg_vbus_drv: otg-vbus-drv {
35014+ rockchip,pins =
35015+ <RK_GPIO0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
35016+ };
35017+ };
35018+};
35019+
35020+&pwm0 {
35021+ status = "okay";
35022+};
35023+
35024+&sdmmc {
35025+ bus-width = <4>;
35026+ cap-mmc-highspeed;
35027+ cap-sd-highspeed;
35028+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
35029+ disable-wp;
35030+ max-frequency = <150000000>;
35031+ pinctrl-names = "default";
35032+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
35033+ vmmc-supply = <&vcc3v3_baseboard>;
35034+ status = "okay";
35035+};
35036+
35037+&spi5 {
35038+ status = "okay";
35039+};
35040+
35041+&u2phy0 {
35042+ status = "okay";
35043+};
35044+
35045+&usbdrd3_0 {
35046+ status = "okay";
35047+};
35048+
35049+&usbdrd_dwc3_0 {
35050+ dr_mode = "otg";
35051+ status = "okay";
35052+};
35053+
35054+&u2phy0_host {
35055+ phy-supply = <&vcc5v0_otg>;
35056+ status = "okay";
35057+};
35058+
35059+&uart0 {
35060+ pinctrl-names = "default";
35061+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
35062+ status = "okay";
35063+};
35064+
35065+&uart2 {
35066+ status = "okay";
35067+};
35068+
35069+&usb_host0_ehci {
35070+ status = "okay";
35071+};
35072+
35073+&usb_host0_ohci {
35074+ status = "okay";
35075+};
35076diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
35077new file mode 100644
35078index 000000000000..53ff3d191a1d
35079--- /dev/null
35080+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
35081@@ -0,0 +1,547 @@
35082+/*
35083+ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
35084+ *
35085+ * This file is dual-licensed: you can use it either under the terms
35086+ * of the GPL or the X11 license, at your option. Note that this dual
35087+ * licensing only applies to this file, and not this project as a
35088+ * whole.
35089+ *
35090+ * a) This file is free software; you can redistribute it and/or
35091+ * modify it under the terms of the GNU General Public License as
35092+ * published by the Free Software Foundation; either version 2 of the
35093+ * License, or (at your option) any later version.
35094+ *
35095+ * This file is distributed in the hope that it will be useful,
35096+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
35097+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35098+ * GNU General Public License for more details.
35099+ *
35100+ * Or, alternatively,
35101+ *
35102+ * b) Permission is hereby granted, free of charge, to any person
35103+ * obtaining a copy of this software and associated documentation
35104+ * files (the "Software"), to deal in the Software without
35105+ * restriction, including without limitation the rights to use,
35106+ * copy, modify, merge, publish, distribute, sublicense, and/or
35107+ * sell copies of the Software, and to permit persons to whom the
35108+ * Software is furnished to do so, subject to the following
35109+ * conditions:
35110+ *
35111+ * The above copyright notice and this permission notice shall be
35112+ * included in all copies or substantial portions of the Software.
35113+ *
35114+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35115+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35116+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35117+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35118+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
35119+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
35120+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
35121+ * OTHER DEALINGS IN THE SOFTWARE.
35122+ */
35123+
35124+#include <dt-bindings/pwm/pwm.h>
35125+#include "rk3399.dtsi"
35126+#include "rk3399-opp.dtsi"
35127+
35128+/ {
35129+ leds {
35130+ compatible = "gpio-leds";
35131+ pinctrl-names = "default";
35132+ pinctrl-0 = <&led_pin_module>;
35133+
35134+ module-led {
35135+ label = "module_led";
35136+ gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
35137+ linux,default-trigger = "heartbeat";
35138+ panic-indicator;
35139+ };
35140+ };
35141+
35142+ /*
35143+ * Overwrite the opp-table for CPUB as this board uses a different
35144+ * regulator (FAN53555) that only allows 10mV steps and therefore
35145+ * can't reach the operation point target voltages from rk3399-opp.dtsi
35146+ */
35147+ /delete-node/ opp-table1;
35148+ cluster1_opp: opp-table1 {
35149+ compatible = "operating-points-v2";
35150+ opp-shared;
35151+
35152+ opp00 {
35153+ opp-hz = /bits/ 64 <408000000>;
35154+ opp-microvolt = <800000>;
35155+ clock-latency-ns = <40000>;
35156+ };
35157+ opp01 {
35158+ opp-hz = /bits/ 64 <600000000>;
35159+ opp-microvolt = <800000>;
35160+ };
35161+ opp02 {
35162+ opp-hz = /bits/ 64 <816000000>;
35163+ opp-microvolt = <830000>;
35164+ opp-suspend;
35165+ };
35166+ opp03 {
35167+ opp-hz = /bits/ 64 <1008000000>;
35168+ opp-microvolt = <880000>;
35169+ };
35170+ opp04 {
35171+ opp-hz = /bits/ 64 <1200000000>;
35172+ opp-microvolt = <950000>;
35173+ };
35174+ opp05 {
35175+ opp-hz = /bits/ 64 <1416000000>;
35176+ opp-microvolt = <1030000>;
35177+ };
35178+ opp06 {
35179+ opp-hz = /bits/ 64 <1608000000>;
35180+ opp-microvolt = <1100000>;
35181+ };
35182+ opp07 {
35183+ opp-hz = /bits/ 64 <1800000000>;
35184+ opp-microvolt = <1200000>;
35185+ };
35186+ opp08 {
35187+ opp-hz = /bits/ 64 <1992000000>;
35188+ opp-microvolt = <1230000>;
35189+ turbo-mode;
35190+ };
35191+ };
35192+
35193+ clkin_gmac: external-gmac-clock {
35194+ compatible = "fixed-clock";
35195+ clock-frequency = <125000000>;
35196+ clock-output-names = "clkin_gmac";
35197+ #clock-cells = <0>;
35198+ };
35199+
35200+ vcc1v2_phy: vcc1v2-phy {
35201+ compatible = "regulator-fixed";
35202+ regulator-name = "vcc1v2_phy";
35203+ regulator-always-on;
35204+ regulator-boot-on;
35205+ regulator-min-microvolt = <1200000>;
35206+ regulator-max-microvolt = <1200000>;
35207+ vin-supply = <&vcc5v0_sys>;
35208+ };
35209+
35210+ vcc3v3_sys: vcc3v3-sys {
35211+ compatible = "regulator-fixed";
35212+ regulator-name = "vcc3v3_sys";
35213+ regulator-always-on;
35214+ regulator-boot-on;
35215+ regulator-min-microvolt = <3300000>;
35216+ regulator-max-microvolt = <3300000>;
35217+ vin-supply = <&vcc5v0_sys>;
35218+ };
35219+
35220+ vcc5v0_host: vcc5v0-host-regulator {
35221+ compatible = "regulator-fixed";
35222+ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
35223+ enable-active-low;
35224+ pinctrl-names = "default";
35225+ pinctrl-0 = <&vcc5v0_host_en>;
35226+ regulator-name = "vcc5v0_host";
35227+ regulator-always-on;
35228+ vin-supply = <&vcc5v0_sys>;
35229+ };
35230+
35231+ vcc5v0_sys: vcc5v0-sys {
35232+ compatible = "regulator-fixed";
35233+ regulator-name = "vcc5v0_sys";
35234+ regulator-always-on;
35235+ regulator-boot-on;
35236+ regulator-min-microvolt = <5000000>;
35237+ regulator-max-microvolt = <5000000>;
35238+ };
35239+
35240+ vdd_log: vdd-log {
35241+ compatible = "pwm-regulator";
35242+ pwms = <&pwm2 0 25000 0>;
35243+ regulator-name = "vdd_log";
35244+ regulator-min-microvolt = <800000>;
35245+ regulator-max-microvolt = <1400000>;
35246+ regulator-always-on;
35247+ regulator-boot-on;
35248+ status = "okay";
35249+ };
35250+};
35251+
35252+&cpu_b0 {
35253+ cpu-supply = <&vdd_cpu_b>;
35254+};
35255+
35256+&cpu_b1 {
35257+ cpu-supply = <&vdd_cpu_b>;
35258+};
35259+
35260+&cpu_l0 {
35261+ cpu-supply = <&vdd_cpu_l>;
35262+};
35263+
35264+&cpu_l1 {
35265+ cpu-supply = <&vdd_cpu_l>;
35266+};
35267+
35268+&cpu_l2 {
35269+ cpu-supply = <&vdd_cpu_l>;
35270+};
35271+
35272+&cpu_l3 {
35273+ cpu-supply = <&vdd_cpu_l>;
35274+};
35275+
35276+&emmc_phy {
35277+ status = "okay";
35278+};
35279+
35280+&gmac {
35281+ assigned-clocks = <&cru SCLK_RMII_SRC>;
35282+ assigned-clock-parents = <&clkin_gmac>;
35283+ clock_in_out = "input";
35284+ phy-supply = <&vcc1v2_phy>;
35285+ phy-mode = "rgmii";
35286+ pinctrl-names = "default";
35287+ pinctrl-0 = <&rgmii_pins>;
35288+ snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
35289+ snps,reset-active-low;
35290+ snps,reset-delays-us = <0 10000 50000>;
35291+ tx_delay = <0x10>;
35292+ rx_delay = <0x10>;
35293+ status = "okay";
35294+};
35295+
35296+&i2c0 {
35297+ status = "okay";
35298+ i2c-scl-rising-time-ns = <168>;
35299+ i2c-scl-falling-time-ns = <4>;
35300+ clock-frequency = <400000>;
35301+
35302+ rk808: pmic@1b {
35303+ compatible = "rockchip,rk808";
35304+ reg = <0x1b>;
35305+ interrupt-parent = <&gpio1>;
35306+ interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
35307+ #clock-cells = <1>;
35308+ clock-output-names = "xin32k", "rk808-clkout2";
35309+ pinctrl-names = "default";
35310+ pinctrl-0 = <&pmic_int_l>;
35311+ rockchip,system-power-controller;
35312+ wakeup-source;
35313+
35314+ vcc1-supply = <&vcc5v0_sys>;
35315+ vcc2-supply = <&vcc5v0_sys>;
35316+ vcc3-supply = <&vcc5v0_sys>;
35317+ vcc4-supply = <&vcc5v0_sys>;
35318+ vcc6-supply = <&vcc5v0_sys>;
35319+ vcc7-supply = <&vcc5v0_sys>;
35320+ vcc8-supply = <&vcc3v3_sys>;
35321+ vcc9-supply = <&vcc5v0_sys>;
35322+ vcc10-supply = <&vcc5v0_sys>;
35323+ vcc11-supply = <&vcc5v0_sys>;
35324+ vcc12-supply = <&vcc3v3_sys>;
35325+ vddio-supply = <&vcc1v8_pmu>;
35326+
35327+ regulators {
35328+ vdd_center: DCDC_REG1 {
35329+ regulator-name = "vdd_center";
35330+ regulator-min-microvolt = <750000>;
35331+ regulator-max-microvolt = <1350000>;
35332+ regulator-ramp-delay = <6001>;
35333+ regulator-always-on;
35334+ regulator-boot-on;
35335+ regulator-state-mem {
35336+ regulator-off-in-suspend;
35337+ };
35338+ };
35339+
35340+ vdd_cpu_l: DCDC_REG2 {
35341+ regulator-name = "vdd_cpu_l";
35342+ regulator-min-microvolt = <750000>;
35343+ regulator-max-microvolt = <1350000>;
35344+ regulator-ramp-delay = <6001>;
35345+ regulator-always-on;
35346+ regulator-boot-on;
35347+ regulator-state-mem {
35348+ regulator-off-in-suspend;
35349+ };
35350+ };
35351+
35352+ vcc_ddr: DCDC_REG3 {
35353+ regulator-name = "vcc_ddr";
35354+ regulator-always-on;
35355+ regulator-boot-on;
35356+ regulator-state-mem {
35357+ regulator-on-in-suspend;
35358+ };
35359+ };
35360+
35361+ vcc_1v8: DCDC_REG4 {
35362+ regulator-name = "vcc_1v8";
35363+ regulator-min-microvolt = <1800000>;
35364+ regulator-max-microvolt = <1800000>;
35365+ regulator-always-on;
35366+ regulator-boot-on;
35367+ regulator-state-mem {
35368+ regulator-on-in-suspend;
35369+ regulator-suspend-microvolt = <1800000>;
35370+ };
35371+ };
35372+
35373+ vcc_ldo1: LDO_REG1 {
35374+ regulator-name = "vcc_ldo1";
35375+ regulator-min-microvolt = <1800000>;
35376+ regulator-max-microvolt = <1800000>;
35377+ regulator-boot-on;
35378+ regulator-state-mem {
35379+ regulator-off-in-suspend;
35380+ };
35381+ };
35382+
35383+ vcc1v8_hdmi: LDO_REG2 {
35384+ regulator-name = "vcc1v8_hdmi";
35385+ regulator-min-microvolt = <1800000>;
35386+ regulator-max-microvolt = <1800000>;
35387+ regulator-always-on;
35388+ regulator-boot-on;
35389+ regulator-state-mem {
35390+ regulator-off-in-suspend;
35391+ };
35392+ };
35393+
35394+ vcc1v8_pmu: LDO_REG3 {
35395+ regulator-name = "vcc1v8_pmu";
35396+ regulator-min-microvolt = <1800000>;
35397+ regulator-max-microvolt = <1800000>;
35398+ regulator-always-on;
35399+ regulator-boot-on;
35400+ regulator-state-mem {
35401+ regulator-on-in-suspend;
35402+ regulator-suspend-microvolt = <1800000>;
35403+ };
35404+ };
35405+
35406+ vcc_sd: LDO_REG4 {
35407+ regulator-name = "vcc_sd";
35408+ regulator-min-microvolt = <1800000>;
35409+ regulator-max-microvolt = <3300000>;
35410+ regulator-always-on;
35411+ regulator-boot-on;
35412+ regulator-state-mem {
35413+ regulator-on-in-suspend;
35414+ regulator-suspend-microvolt = <3300000>;
35415+ };
35416+ };
35417+
35418+ vcc_ldo5: LDO_REG5 {
35419+ regulator-name = "vcc_ldo5";
35420+ regulator-min-microvolt = <3000000>;
35421+ regulator-max-microvolt = <3000000>;
35422+ regulator-boot-on;
35423+ regulator-state-mem {
35424+ regulator-off-in-suspend;
35425+ };
35426+ };
35427+
35428+ vcc_ldo6: LDO_REG6 {
35429+ regulator-name = "vcc_ldo6";
35430+ regulator-min-microvolt = <1500000>;
35431+ regulator-max-microvolt = <1500000>;
35432+ regulator-boot-on;
35433+ regulator-state-mem {
35434+ regulator-off-in-suspend;
35435+ };
35436+ };
35437+
35438+ vcc0v9_hdmi: LDO_REG7 {
35439+ regulator-name = "vcc0v9_hdmi";
35440+ regulator-min-microvolt = <900000>;
35441+ regulator-max-microvolt = <900000>;
35442+ regulator-always-on;
35443+ regulator-boot-on;
35444+ regulator-state-mem {
35445+ regulator-off-in-suspend;
35446+ };
35447+ };
35448+
35449+ vcc_efuse: LDO_REG8 {
35450+ regulator-name = "vcc_efuse";
35451+ regulator-min-microvolt = <1800000>;
35452+ regulator-max-microvolt = <1800000>;
35453+ regulator-always-on;
35454+ regulator-boot-on;
35455+ regulator-state-mem {
35456+ regulator-off-in-suspend;
35457+ };
35458+ };
35459+
35460+ vcc3v3_s3: SWITCH_REG1 {
35461+ regulator-name = "vcc3v3_s3";
35462+ regulator-always-on;
35463+ regulator-boot-on;
35464+ regulator-state-mem {
35465+ regulator-off-in-suspend;
35466+ };
35467+ };
35468+
35469+ vcc3v3_s0: SWITCH_REG2 {
35470+ regulator-name = "vcc3v3_s0";
35471+ regulator-always-on;
35472+ regulator-boot-on;
35473+ regulator-state-mem {
35474+ regulator-off-in-suspend;
35475+ };
35476+ };
35477+ };
35478+ };
35479+
35480+ vdd_gpu: regulator@60 {
35481+ compatible = "fcs,fan53555";
35482+ reg = <0x60>;
35483+ fcs,suspend-voltage-selector = <1>;
35484+ regulator-name = "vdd_gpu";
35485+ regulator-min-microvolt = <600000>;
35486+ regulator-max-microvolt = <1230000>;
35487+ regulator-ramp-delay = <1000>;
35488+ regulator-always-on;
35489+ regulator-boot-on;
35490+ vin-supply = <&vcc5v0_sys>;
35491+ };
35492+};
35493+
35494+&i2c7 {
35495+ status = "okay";
35496+ clock-frequency = <400000>;
35497+
35498+ fan: fan@18 {
35499+ compatible = "ti,amc6821";
35500+ reg = <0x18>;
35501+ cooling-min-state = <0>;
35502+ cooling-max-state = <9>;
35503+ #cooling-cells = <2>;
35504+ };
35505+
35506+ rtc_twi: rtc@6f {
35507+ compatible = "isil,isl1208";
35508+ reg = <0x6f>;
35509+ };
35510+};
35511+
35512+&i2c8 {
35513+ status = "okay";
35514+ clock-frequency = <400000>;
35515+
35516+ vdd_cpu_b: regulator@60 {
35517+ compatible = "fcs,fan53555";
35518+ reg = <0x60>;
35519+ vin-supply = <&vcc5v0_sys>;
35520+ regulator-name = "vdd_cpu_b";
35521+ regulator-min-microvolt = <600000>;
35522+ regulator-max-microvolt = <1230000>;
35523+ regulator-ramp-delay = <1000>;
35524+ fcs,suspend-voltage-selector = <1>;
35525+ regulator-always-on;
35526+ regulator-boot-on;
35527+ };
35528+};
35529+
35530+&io_domains {
35531+ status = "okay";
35532+ bt656-supply = <&vcc_1v8>;
35533+ audio-supply = <&vcc_1v8>;
35534+ sdmmc-supply = <&vcc_sd>;
35535+ gpio1830-supply = <&vcc_1v8>;
35536+};
35537+
35538+&pmu_io_domains {
35539+ status = "okay";
35540+ pmu1830-supply = <&vcc_1v8>;
35541+};
35542+
35543+&pwm2 {
35544+ status = "okay";
35545+};
35546+
35547+&pinctrl {
35548+ i2c8 {
35549+ i2c8_xfer_a: i2c8-xfer {
35550+ rockchip,pins =
35551+ <RK_GPIO1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
35552+ <RK_GPIO1 RK_PC5 RK_FUNC_1 &pcfg_pull_up>;
35553+ };
35554+ };
35555+
35556+ leds {
35557+ led_pin_module: led-module-gpio {
35558+ rockchip,pins =
35559+ <RK_GPIO2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
35560+ };
35561+ };
35562+
35563+ pmic {
35564+ pmic_int_l: pmic-int-l {
35565+ rockchip,pins =
35566+ <RK_GPIO1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
35567+ };
35568+ };
35569+
35570+ usb2 {
35571+ vcc5v0_host_en: vcc5v0-host-en {
35572+ rockchip,pins =
35573+ <RK_GPIO4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
35574+ };
35575+ };
35576+};
35577+
35578+&sdhci {
35579+ bus-width = <8>;
35580+ mmc-hs400-1_8v;
35581+ mmc-hs400-enhanced-strobe;
35582+ non-removable;
35583+ status = "okay";
35584+};
35585+
35586+&sdmmc {
35587+ vqmmc = <&vcc_sd>;
35588+};
35589+
35590+&spi1 {
35591+ status = "okay";
35592+
35593+ norflash: flash@0 {
35594+ compatible = "jedec,spi-nor";
35595+ reg = <0>;
35596+ spi-max-frequency = <50000000>;
35597+ };
35598+};
35599+
35600+&u2phy1 {
35601+ status = "okay";
35602+
35603+ u2phy1_otg: otg-port {
35604+ status = "okay";
35605+ };
35606+
35607+ u2phy1_host: host-port {
35608+ phy-supply = <&vcc5v0_host>;
35609+ status = "okay";
35610+ };
35611+};
35612+
35613+&usbdrd3_1 {
35614+ status = "okay";
35615+};
35616+
35617+&usbdrd_dwc3_1 {
35618+ status = "okay";
35619+ dr_mode = "host";
35620+};
35621+
35622+&usb_host1_ehci {
35623+ status = "okay";
35624+};
35625+
35626+&usb_host1_ohci {
35627+ status = "okay";
35628+};
35629diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
35630new file mode 100644
35631index 000000000000..b7bd88fb3ae3
35632--- /dev/null
35633+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
35634@@ -0,0 +1,240 @@
35635+/*
35636+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
35637+ *
35638+ * This file is dual-licensed: you can use it either under the terms
35639+ * of the GPL or the X11 license, at your option. Note that this dual
35640+ * licensing only applies to this file, and not this project as a
35641+ * whole.
35642+ *
35643+ * a) This file is free software; you can redistribute it and/or
35644+ * modify it under the terms of the GNU General Public License as
35645+ * published by the Free Software Foundation; either version 2 of the
35646+ * License, or (at your option) any later version.
35647+ *
35648+ * This file is distributed in the hope that it will be useful,
35649+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
35650+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35651+ * GNU General Public License for more details.
35652+ *
35653+ * Or, alternatively,
35654+ *
35655+ * b) Permission is hereby granted, free of charge, to any person
35656+ * obtaining a copy of this software and associated documentation
35657+ * files (the "Software"), to deal in the Software without
35658+ * restriction, including without limitation the rights to use,
35659+ * copy, modify, merge, publish, distribute, sublicense, and/or
35660+ * sell copies of the Software, and to permit persons to whom the
35661+ * Software is furnished to do so, subject to the following
35662+ * conditions:
35663+ *
35664+ * The above copyright notice and this permission notice shall be
35665+ * included in all copies or substantial portions of the Software.
35666+ *
35667+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35668+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35669+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35670+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35671+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
35672+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
35673+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
35674+ * OTHER DEALINGS IN THE SOFTWARE.
35675+ */
35676+
35677+/dts-v1/;
35678+#include <dt-bindings/input/input.h>
35679+#include "rk3399-sapphire.dtsi"
35680+
35681+/ {
35682+ model = "Excavator-RK3399 Board";
35683+ compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
35684+
35685+ adc-keys {
35686+ compatible = "adc-keys";
35687+ io-channels = <&saradc 1>;
35688+ io-channel-names = "buttons";
35689+ keyup-threshold-microvolt = <1800000>;
35690+ poll-interval = <100>;
35691+
35692+ button-up {
35693+ label = "Volume Up";
35694+ linux,code = <KEY_VOLUMEUP>;
35695+ press-threshold-microvolt = <100000>;
35696+ };
35697+
35698+ button-down {
35699+ label = "Volume Down";
35700+ linux,code = <KEY_VOLUMEDOWN>;
35701+ press-threshold-microvolt = <300000>;
35702+ };
35703+
35704+ back {
35705+ label = "Back";
35706+ linux,code = <KEY_BACK>;
35707+ press-threshold-microvolt = <985000>;
35708+ };
35709+
35710+ menu {
35711+ label = "Menu";
35712+ linux,code = <KEY_MENU>;
35713+ press-threshold-microvolt = <1314000>;
35714+ };
35715+ };
35716+
35717+ edp_panel: edp-panel {
35718+ compatible ="lg,lp079qx1-sp0v", "simple-panel";
35719+ backlight = <&backlight>;
35720+ enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
35721+ pinctrl-names = "default";
35722+ pinctrl-0 = <&lcd_panel_reset>;
35723+ power-supply = <&vcc3v3_s0>;
35724+
35725+ ports {
35726+ panel_in_edp: endpoint {
35727+ remote-endpoint = <&edp_out_panel>;
35728+ };
35729+ };
35730+ };
35731+
35732+ keys: gpio-keys {
35733+ compatible = "gpio-keys";
35734+ autorepeat;
35735+
35736+ power {
35737+ debounce-interval = <100>;
35738+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
35739+ label = "GPIO Power";
35740+ linux,code = <KEY_POWER>;
35741+ linux,input-type = <1>;
35742+ pinctrl-names = "default";
35743+ pinctrl-0 = <&pwr_btn>;
35744+ wakeup-source;
35745+ };
35746+ };
35747+
35748+ rt5651-sound {
35749+ compatible = "simple-audio-card";
35750+ simple-audio-card,name = "realtek,rt5651-codec";
35751+ simple-audio-card,format = "i2s";
35752+ simple-audio-card,mclk-fs = <256>;
35753+ simple-audio-card,widgets =
35754+ "Microphone", "Mic Jack",
35755+ "Headphone", "Headphone Jack";
35756+ simple-audio-card,routing =
35757+ "Mic Jack", "MICBIAS1",
35758+ "IN1P", "Mic Jack",
35759+ "Headphone Jack", "HPOL",
35760+ "Headphone Jack", "HPOR";
35761+ simple-audio-card,cpu {
35762+ sound-dai = <&i2s0>;
35763+ };
35764+ simple-audio-card,codec {
35765+ sound-dai = <&rt5651>;
35766+ };
35767+ };
35768+
35769+ sdio_pwrseq: sdio-pwrseq {
35770+ compatible = "mmc-pwrseq-simple";
35771+ clocks = <&rk808 1>;
35772+ clock-names = "ext_clock";
35773+ pinctrl-names = "default";
35774+ pinctrl-0 = <&wifi_enable_h>;
35775+
35776+ /*
35777+ * On the module itself this is one of these (depending
35778+ * on the actual card populated):
35779+ * - SDIO_RESET_L_WL_REG_ON
35780+ * - PDN (power down when low)
35781+ */
35782+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
35783+ };
35784+};
35785+
35786+&backlight {
35787+ enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
35788+ status = "okay";
35789+};
35790+
35791+&edp {
35792+ status = "okay";
35793+
35794+ ports {
35795+ edp_out: port@1 {
35796+ reg = <1>;
35797+ #address-cells = <1>;
35798+ #size-cells = <0>;
35799+
35800+ edp_out_panel: endpoint@0 {
35801+ reg = <0>;
35802+ remote-endpoint = <&panel_in_edp>;
35803+ };
35804+ };
35805+ };
35806+};
35807+
35808+&i2c1 {
35809+ i2c-scl-rising-time-ns = <300>;
35810+ i2c-scl-falling-time-ns = <15>;
35811+ status = "okay";
35812+
35813+ rt5651: rt5651@1a {
35814+ compatible = "rockchip,rt5651";
35815+ reg = <0x1a>;
35816+ clocks = <&cru SCLK_I2S_8CH_OUT>;
35817+ clock-names = "mclk";
35818+ hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
35819+ spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
35820+ #sound-dai-cells = <0>;
35821+ };
35822+};
35823+
35824+&i2c4 {
35825+ i2c-scl-rising-time-ns = <600>;
35826+ i2c-scl-falling-time-ns = <20>;
35827+ status = "okay";
35828+
35829+ accelerometer@68 {
35830+ compatible = "invensense,mpu6500";
35831+ reg = <0x68>;
35832+ interrupt-parent = <&gpio1>;
35833+ interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
35834+ };
35835+};
35836+
35837+&i2s0 {
35838+ rockchip,playback-channels = <8>;
35839+ rockchip,capture-channels = <8>;
35840+ #sound-dai-cells = <0>;
35841+ status = "okay";
35842+};
35843+
35844+&i2s2 {
35845+ #sound-dai-cells = <0>;
35846+ status = "okay";
35847+};
35848+
35849+&pinctrl {
35850+ buttons {
35851+ pwr_btn: pwr-btn {
35852+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
35853+ };
35854+ };
35855+
35856+ sdio-pwrseq {
35857+ wifi_enable_h: wifi-enable-h {
35858+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
35859+ };
35860+ };
35861+
35862+ lcd-panel {
35863+ lcd_panel_reset: lcd-panel-reset {
35864+ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
35865+ };
35866+ };
35867+};
35868+
35869+&spdif {
35870+ i2c-scl-rising-time-ns = <450>;
35871+ i2c-scl-falling-time-ns = <15>;
35872+ #sound-dai-cells = <0>;
35873+ status = "okay";
35874+};
35875diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
35876new file mode 100644
35877index 000000000000..6c30bb02210d
35878--- /dev/null
35879+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
35880@@ -0,0 +1,644 @@
35881+/*
35882+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
35883+ *
35884+ * This file is dual-licensed: you can use it either under the terms
35885+ * of the GPL or the X11 license, at your option. Note that this dual
35886+ * licensing only applies to this file, and not this project as a
35887+ * whole.
35888+ *
35889+ * a) This file is free software; you can redistribute it and/or
35890+ * modify it under the terms of the GNU General Public License as
35891+ * published by the Free Software Foundation; either version 2 of the
35892+ * License, or (at your option) any later version.
35893+ *
35894+ * This file is distributed in the hope that it will be useful,
35895+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
35896+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35897+ * GNU General Public License for more details.
35898+ *
35899+ * Or, alternatively,
35900+ *
35901+ * b) Permission is hereby granted, free of charge, to any person
35902+ * obtaining a copy of this software and associated documentation
35903+ * files (the "Software"), to deal in the Software without
35904+ * restriction, including without limitation the rights to use,
35905+ * copy, modify, merge, publish, distribute, sublicense, and/or
35906+ * sell copies of the Software, and to permit persons to whom the
35907+ * Software is furnished to do so, subject to the following
35908+ * conditions:
35909+ *
35910+ * The above copyright notice and this permission notice shall be
35911+ * included in all copies or substantial portions of the Software.
35912+ *
35913+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35914+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35915+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35916+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35917+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
35918+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
35919+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
35920+ * OTHER DEALINGS IN THE SOFTWARE.
35921+ */
35922+
35923+#include "dt-bindings/pwm/pwm.h"
35924+#include "rk3399.dtsi"
35925+#include "rk3399-opp.dtsi"
35926+
35927+/ {
35928+ compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
35929+
35930+ backlight: backlight {
35931+ compatible = "pwm-backlight";
35932+ brightness-levels = <
35933+ 0 1 2 3 4 5 6 7
35934+ 8 9 10 11 12 13 14 15
35935+ 16 17 18 19 20 21 22 23
35936+ 24 25 26 27 28 29 30 31
35937+ 32 33 34 35 36 37 38 39
35938+ 40 41 42 43 44 45 46 47
35939+ 48 49 50 51 52 53 54 55
35940+ 56 57 58 59 60 61 62 63
35941+ 64 65 66 67 68 69 70 71
35942+ 72 73 74 75 76 77 78 79
35943+ 80 81 82 83 84 85 86 87
35944+ 88 89 90 91 92 93 94 95
35945+ 96 97 98 99 100 101 102 103
35946+ 104 105 106 107 108 109 110 111
35947+ 112 113 114 115 116 117 118 119
35948+ 120 121 122 123 124 125 126 127
35949+ 128 129 130 131 132 133 134 135
35950+ 136 137 138 139 140 141 142 143
35951+ 144 145 146 147 148 149 150 151
35952+ 152 153 154 155 156 157 158 159
35953+ 160 161 162 163 164 165 166 167
35954+ 168 169 170 171 172 173 174 175
35955+ 176 177 178 179 180 181 182 183
35956+ 184 185 186 187 188 189 190 191
35957+ 192 193 194 195 196 197 198 199
35958+ 200 201 202 203 204 205 206 207
35959+ 208 209 210 211 212 213 214 215
35960+ 216 217 218 219 220 221 222 223
35961+ 224 225 226 227 228 229 230 231
35962+ 232 233 234 235 236 237 238 239
35963+ 240 241 242 243 244 245 246 247
35964+ 248 249 250 251 252 253 254 255>;
35965+ default-brightness-level = <200>;
35966+ pwms = <&pwm0 0 25000 0>;
35967+ };
35968+
35969+ clkin_gmac: external-gmac-clock {
35970+ compatible = "fixed-clock";
35971+ clock-frequency = <125000000>;
35972+ clock-output-names = "clkin_gmac";
35973+ #clock-cells = <0>;
35974+ };
35975+
35976+ dc_12v: dc-12v {
35977+ compatible = "regulator-fixed";
35978+ regulator-name = "dc_12v";
35979+ regulator-always-on;
35980+ regulator-boot-on;
35981+ regulator-min-microvolt = <12000000>;
35982+ regulator-max-microvolt = <12000000>;
35983+ };
35984+
35985+ /* switched by pmic_sleep */
35986+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
35987+ compatible = "regulator-fixed";
35988+ regulator-name = "vcc1v8_s3";
35989+ regulator-always-on;
35990+ regulator-boot-on;
35991+ regulator-min-microvolt = <1800000>;
35992+ regulator-max-microvolt = <1800000>;
35993+ vin-supply = <&vcc_1v8>;
35994+ };
35995+
35996+ vcc3v3_sys: vcc3v3-sys {
35997+ compatible = "regulator-fixed";
35998+ regulator-name = "vcc3v3_sys";
35999+ regulator-always-on;
36000+ regulator-boot-on;
36001+ regulator-min-microvolt = <3300000>;
36002+ regulator-max-microvolt = <3300000>;
36003+ vin-supply = <&vcc_sys>;
36004+ };
36005+
36006+ vcc_sys: vcc-sys {
36007+ compatible = "regulator-fixed";
36008+ regulator-name = "vcc_sys";
36009+ regulator-always-on;
36010+ regulator-boot-on;
36011+ regulator-min-microvolt = <5000000>;
36012+ regulator-max-microvolt = <5000000>;
36013+ vin-supply = <&dc_12v>;
36014+ };
36015+
36016+ vcc5v0_host: vcc5v0-host-regulator {
36017+ compatible = "regulator-fixed";
36018+ enable-active-high;
36019+ gpio = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
36020+ pinctrl-names = "default";
36021+ pinctrl-0 = <&vcc5v0_host_en>;
36022+ regulator-name = "vcc5v0_host";
36023+ regulator-always-on;
36024+ vin-supply = <&vcc_sys>;
36025+ };
36026+};
36027+
36028+&cpu_l0 {
36029+ cpu-supply = <&vdd_cpu_l>;
36030+};
36031+
36032+&cpu_l1 {
36033+ cpu-supply = <&vdd_cpu_l>;
36034+};
36035+
36036+&cpu_l2 {
36037+ cpu-supply = <&vdd_cpu_l>;
36038+};
36039+
36040+&cpu_l3 {
36041+ cpu-supply = <&vdd_cpu_l>;
36042+};
36043+
36044+&cpu_b0 {
36045+ cpu-supply = <&vdd_cpu_b>;
36046+};
36047+
36048+&cpu_b1 {
36049+ cpu-supply = <&vdd_cpu_b>;
36050+};
36051+
36052+&emmc_phy {
36053+ status = "okay";
36054+};
36055+
36056+&gmac {
36057+ assigned-clocks = <&cru SCLK_RMII_SRC>;
36058+ assigned-clock-parents = <&clkin_gmac>;
36059+ clock_in_out = "input";
36060+ phy-supply = <&vcc_lan>;
36061+ phy-mode = "rgmii";
36062+ pinctrl-names = "default";
36063+ pinctrl-0 = <&rgmii_pins>;
36064+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
36065+ snps,reset-active-low;
36066+ snps,reset-delays-us = <0 10000 50000>;
36067+ tx_delay = <0x28>;
36068+ rx_delay = <0x11>;
36069+ status = "okay";
36070+};
36071+
36072+&gpu {
36073+ mali-supply = <&vdd_gpu>;
36074+ status = "okay";
36075+};
36076+
36077+&hdmi {
36078+ ddc-i2c-bus = <&i2c3>;
36079+ status = "okay";
36080+};
36081+
36082+&i2c0 {
36083+ clock-frequency = <400000>;
36084+ i2c-scl-rising-time-ns = <168>;
36085+ i2c-scl-falling-time-ns = <4>;
36086+ status = "okay";
36087+
36088+ rk808: pmic@1b {
36089+ compatible = "rockchip,rk808";
36090+ reg = <0x1b>;
36091+ interrupt-parent = <&gpio1>;
36092+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
36093+ #clock-cells = <1>;
36094+ clock-output-names = "xin32k", "rk808-clkout2";
36095+ pinctrl-names = "default";
36096+ pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
36097+ rockchip,system-power-controller;
36098+ wakeup-source;
36099+
36100+ vcc1-supply = <&vcc_sys>;
36101+ vcc2-supply = <&vcc_sys>;
36102+ vcc3-supply = <&vcc_sys>;
36103+ vcc4-supply = <&vcc_sys>;
36104+ vcc6-supply = <&vcc_sys>;
36105+ vcc7-supply = <&vcc_sys>;
36106+ vcc8-supply = <&vcc3v3_sys>;
36107+ vcc9-supply = <&vcc_sys>;
36108+ vcc10-supply = <&vcc_sys>;
36109+ vcc11-supply = <&vcc_sys>;
36110+ vcc12-supply = <&vcc3v3_sys>;
36111+ vddio-supply = <&vcc1v8_pmu>;
36112+
36113+ regulators {
36114+ vdd_center: DCDC_REG1 {
36115+ regulator-name = "vdd_center";
36116+ regulator-always-on;
36117+ regulator-boot-on;
36118+ regulator-min-microvolt = <750000>;
36119+ regulator-max-microvolt = <1350000>;
36120+ regulator-ramp-delay = <6001>;
36121+ regulator-state-mem {
36122+ regulator-off-in-suspend;
36123+ };
36124+ };
36125+
36126+ vdd_cpu_l: DCDC_REG2 {
36127+ regulator-name = "vdd_cpu_l";
36128+ regulator-always-on;
36129+ regulator-boot-on;
36130+ regulator-min-microvolt = <750000>;
36131+ regulator-max-microvolt = <1350000>;
36132+ regulator-ramp-delay = <6001>;
36133+ regulator-state-mem {
36134+ regulator-off-in-suspend;
36135+ };
36136+ };
36137+
36138+ vcc_ddr: DCDC_REG3 {
36139+ regulator-name = "vcc_ddr";
36140+ regulator-always-on;
36141+ regulator-boot-on;
36142+ regulator-state-mem {
36143+ regulator-on-in-suspend;
36144+ };
36145+ };
36146+
36147+ vcc_1v8: DCDC_REG4 {
36148+ regulator-name = "vcc_1v8";
36149+ regulator-always-on;
36150+ regulator-boot-on;
36151+ regulator-min-microvolt = <1800000>;
36152+ regulator-max-microvolt = <1800000>;
36153+ regulator-state-mem {
36154+ regulator-on-in-suspend;
36155+ regulator-suspend-microvolt = <1800000>;
36156+ };
36157+ };
36158+
36159+ vcc1v8_dvp: LDO_REG1 {
36160+ regulator-name = "vcc1v8_dvp";
36161+ regulator-always-on;
36162+ regulator-boot-on;
36163+ regulator-min-microvolt = <1800000>;
36164+ regulator-max-microvolt = <1800000>;
36165+ regulator-state-mem {
36166+ regulator-off-in-suspend;
36167+ };
36168+ };
36169+
36170+ vcc3v0_tp: LDO_REG2 {
36171+ regulator-name = "vcc3v0_tp";
36172+ regulator-always-on;
36173+ regulator-boot-on;
36174+ regulator-min-microvolt = <3000000>;
36175+ regulator-max-microvolt = <3000000>;
36176+ regulator-state-mem {
36177+ regulator-off-in-suspend;
36178+ };
36179+ };
36180+
36181+ vcc1v8_pmu: LDO_REG3 {
36182+ regulator-name = "vcc1v8_pmu";
36183+ regulator-always-on;
36184+ regulator-boot-on;
36185+ regulator-min-microvolt = <1800000>;
36186+ regulator-max-microvolt = <1800000>;
36187+ regulator-state-mem {
36188+ regulator-on-in-suspend;
36189+ regulator-suspend-microvolt = <1800000>;
36190+ };
36191+ };
36192+
36193+ vcc_sdio: LDO_REG4 {
36194+ regulator-name = "vcc_sdio";
36195+ regulator-always-on;
36196+ regulator-boot-on;
36197+ regulator-min-microvolt = <1800000>;
36198+ regulator-max-microvolt = <3300000>;
36199+ regulator-state-mem {
36200+ regulator-on-in-suspend;
36201+ regulator-suspend-microvolt = <3300000>;
36202+ };
36203+ };
36204+
36205+ vcca3v0_codec: LDO_REG5 {
36206+ regulator-name = "vcca3v0_codec";
36207+ regulator-always-on;
36208+ regulator-boot-on;
36209+ regulator-min-microvolt = <3000000>;
36210+ regulator-max-microvolt = <3000000>;
36211+ regulator-state-mem {
36212+ regulator-off-in-suspend;
36213+ };
36214+ };
36215+
36216+ vcc_1v5: LDO_REG6 {
36217+ regulator-name = "vcc_1v5";
36218+ regulator-always-on;
36219+ regulator-boot-on;
36220+ regulator-min-microvolt = <1500000>;
36221+ regulator-max-microvolt = <1500000>;
36222+ regulator-state-mem {
36223+ regulator-on-in-suspend;
36224+ regulator-suspend-microvolt = <1500000>;
36225+ };
36226+ };
36227+
36228+ vcca1v8_codec: LDO_REG7 {
36229+ regulator-name = "vcca1v8_codec";
36230+ regulator-always-on;
36231+ regulator-boot-on;
36232+ regulator-min-microvolt = <1800000>;
36233+ regulator-max-microvolt = <1800000>;
36234+ regulator-state-mem {
36235+ regulator-off-in-suspend;
36236+ };
36237+ };
36238+
36239+ vcc_3v0: LDO_REG8 {
36240+ regulator-name = "vcc_3v0";
36241+ regulator-always-on;
36242+ regulator-boot-on;
36243+ regulator-min-microvolt = <3000000>;
36244+ regulator-max-microvolt = <3000000>;
36245+ regulator-state-mem {
36246+ regulator-on-in-suspend;
36247+ regulator-suspend-microvolt = <3000000>;
36248+ };
36249+ };
36250+
36251+ vcc3v3_s3: vcc_lan: SWITCH_REG1 {
36252+ regulator-name = "vcc3v3_s3";
36253+ regulator-always-on;
36254+ regulator-boot-on;
36255+ regulator-state-mem {
36256+ regulator-off-in-suspend;
36257+ };
36258+ };
36259+
36260+ vcc3v3_s0: SWITCH_REG2 {
36261+ regulator-name = "vcc3v3_s0";
36262+ regulator-always-on;
36263+ regulator-boot-on;
36264+ regulator-state-mem {
36265+ regulator-off-in-suspend;
36266+ };
36267+ };
36268+ };
36269+ };
36270+
36271+ vdd_cpu_b: regulator@40 {
36272+ compatible = "silergy,syr827";
36273+ reg = <0x40>;
36274+ fcs,suspend-voltage-selector = <1>;
36275+ regulator-name = "vdd_cpu_b";
36276+ regulator-min-microvolt = <712500>;
36277+ regulator-max-microvolt = <1500000>;
36278+ regulator-ramp-delay = <1000>;
36279+ regulator-always-on;
36280+ regulator-boot-on;
36281+ vin-supply = <&vcc_sys>;
36282+
36283+ regulator-state-mem {
36284+ regulator-off-in-suspend;
36285+ };
36286+ };
36287+
36288+ vdd_gpu: regulator@41 {
36289+ compatible = "silergy,syr828";
36290+ reg = <0x41>;
36291+ fcs,suspend-voltage-selector = <1>;
36292+ regulator-name = "vdd_gpu";
36293+ regulator-min-microvolt = <712500>;
36294+ regulator-max-microvolt = <1500000>;
36295+ regulator-ramp-delay = <1000>;
36296+ regulator-always-on;
36297+ regulator-boot-on;
36298+ vin-supply = <&vcc_sys>;
36299+
36300+ regulator-state-mem {
36301+ regulator-off-in-suspend;
36302+ };
36303+ };
36304+
36305+ vdd_log: vdd-log {
36306+ compatible = "pwm-regulator";
36307+ pwms = <&pwm2 0 25000 1>;
36308+ regulator-name = "vdd_log";
36309+ regulator-always-on;
36310+ regulator-boot-on;
36311+ regulator-min-microvolt = <800000>;
36312+ regulator-max-microvolt = <1400000>;
36313+ vin-supply = <&vcc_sys>;
36314+ };
36315+};
36316+
36317+&i2c3 {
36318+ i2c-scl-rising-time-ns = <450>;
36319+ i2c-scl-falling-time-ns = <15>;
36320+ status = "okay";
36321+};
36322+
36323+&io_domains {
36324+ status = "okay";
36325+
36326+ bt656-supply = <&vcc_3v0>;
36327+ audio-supply = <&vcca1v8_codec>;
36328+ sdmmc-supply = <&vcc_sdio>;
36329+ gpio1830-supply = <&vcc_3v0>;
36330+};
36331+
36332+&pcie_phy {
36333+ status = "okay";
36334+};
36335+
36336+&pcie0 {
36337+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
36338+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
36339+ assigned-clock-rates = <100000000>;
36340+ ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
36341+ num-lanes = <4>;
36342+ pinctrl-names = "default";
36343+ pinctrl-0 = <&pcie_clkreqn_cpm>;
36344+ status = "okay";
36345+};
36346+
36347+&pmu_io_domains {
36348+ pmu1830-supply = <&vcc_3v0>;
36349+ status = "okay";
36350+};
36351+
36352+&pinctrl {
36353+ pmic {
36354+ pmic_int_l: pmic-int-l {
36355+ rockchip,pins =
36356+ <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
36357+ };
36358+
36359+ pmic_dvs2: pmic-dvs2 {
36360+ rockchip,pins =
36361+ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
36362+ };
36363+
36364+ vsel1_gpio: vsel1-gpio {
36365+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
36366+ };
36367+
36368+ vsel2_gpio: vsel2-gpio {
36369+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
36370+ };
36371+ };
36372+
36373+ usb2 {
36374+ vcc5v0_host_en: vcc5v0-host-en {
36375+ rockchip,pins =
36376+ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
36377+ };
36378+ };
36379+};
36380+
36381+&pwm0 {
36382+ status = "okay";
36383+};
36384+
36385+&pwm2 {
36386+ status = "okay";
36387+};
36388+
36389+&saradc {
36390+ vref-supply = <&vcca1v8_s3>;
36391+ status = "okay";
36392+};
36393+
36394+&sdhci {
36395+ bus-width = <8>;
36396+ keep-power-in-suspend;
36397+ mmc-hs400-1_8v;
36398+ mmc-hs400-enhanced-strobe;
36399+ non-removable;
36400+ status = "okay";
36401+};
36402+
36403+&sdio0 {
36404+ bus-width = <4>;
36405+ cap-sd-highspeed;
36406+ cap-sdio-irq;
36407+ clock-frequency = <50000000>;
36408+ disable-wp;
36409+ keep-power-in-suspend;
36410+ max-frequency = <50000000>;
36411+ mmc-pwrseq = <&sdio_pwrseq>;
36412+ non-removable;
36413+ pinctrl-names = "default";
36414+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
36415+ sd-uhs-sdr104;
36416+ status = "okay";
36417+};
36418+
36419+&sdmmc {
36420+ bus-width = <4>;
36421+ cap-mmc-highspeed;
36422+ cap-sd-highspeed;
36423+ clock-frequency = <150000000>;
36424+ disable-wp;
36425+ max-frequency = <150000000>;
36426+ pinctrl-names = "default";
36427+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
36428+ vqmmc-supply = <&vcc_sdio>;
36429+ status = "okay";
36430+};
36431+
36432+&tsadc {
36433+ /* tshut mode 0:CRU 1:GPIO */
36434+ rockchip,hw-tshut-mode = <1>;
36435+ /* tshut polarity 0:LOW 1:HIGH */
36436+ rockchip,hw-tshut-polarity = <1>;
36437+ status = "okay";
36438+};
36439+
36440+&u2phy0 {
36441+ status = "okay";
36442+
36443+ u2phy0_otg: otg-port {
36444+ status = "okay";
36445+ };
36446+
36447+ u2phy0_host: host-port {
36448+ phy-supply = <&vcc5v0_host>;
36449+ status = "okay";
36450+ };
36451+};
36452+
36453+&u2phy1 {
36454+ status = "okay";
36455+
36456+ u2phy1_otg: otg-port {
36457+ status = "okay";
36458+ };
36459+
36460+ u2phy1_host: host-port {
36461+ phy-supply = <&vcc5v0_host>;
36462+ status = "okay";
36463+ };
36464+};
36465+
36466+&uart0 {
36467+ pinctrl-names = "default";
36468+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
36469+ status = "okay";
36470+};
36471+
36472+&uart2 {
36473+ status = "okay";
36474+};
36475+
36476+&usb_host0_ehci {
36477+ status = "okay";
36478+};
36479+
36480+&usb_host0_ohci {
36481+ status = "okay";
36482+};
36483+
36484+&usb_host1_ehci {
36485+ status = "okay";
36486+};
36487+
36488+&usb_host1_ohci {
36489+ status = "okay";
36490+};
36491+
36492+&usbdrd3_0 {
36493+ status = "okay";
36494+};
36495+
36496+&usbdrd_dwc3_0 {
36497+ status = "okay";
36498+ dr_mode = "otg";
36499+};
36500+
36501+&usbdrd3_1 {
36502+ status = "okay";
36503+};
36504+
36505+&usbdrd_dwc3_1 {
36506+ status = "okay";
36507+ dr_mode = "host";
36508+};
36509+
36510+&vopb {
36511+ status = "okay";
36512+};
36513+
36514+&vopb_mmu {
36515+ status = "okay";
36516+};
36517+
36518+&vopl {
36519+ status = "okay";
36520+};
36521+
36522+&vopl_mmu {
36523+ status = "okay";
36524+};
36525diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
36526index 5b78ce16a87e..d79e9b3265b9 100644
36527--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
36528+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
36529@@ -110,6 +110,7 @@ cpu_l0: cpu@0 {
36530 enable-method = "psci";
36531 #cooling-cells = <2>; /* min followed by max */
36532 clocks = <&cru ARMCLKL>;
36533+ dynamic-power-coefficient = <100>;
36534 };
36535
36536 cpu_l1: cpu@1 {
36537@@ -118,6 +119,7 @@ cpu_l1: cpu@1 {
36538 reg = <0x0 0x1>;
36539 enable-method = "psci";
36540 clocks = <&cru ARMCLKL>;
36541+ dynamic-power-coefficient = <100>;
36542 };
36543
36544 cpu_l2: cpu@2 {
36545@@ -126,6 +128,7 @@ cpu_l2: cpu@2 {
36546 reg = <0x0 0x2>;
36547 enable-method = "psci";
36548 clocks = <&cru ARMCLKL>;
36549+ dynamic-power-coefficient = <100>;
36550 };
36551
36552 cpu_l3: cpu@3 {
36553@@ -134,6 +137,7 @@ cpu_l3: cpu@3 {
36554 reg = <0x0 0x3>;
36555 enable-method = "psci";
36556 clocks = <&cru ARMCLKL>;
36557+ dynamic-power-coefficient = <100>;
36558 };
36559
36560 cpu_b0: cpu@100 {
36561@@ -143,6 +147,7 @@ cpu_b0: cpu@100 {
36562 enable-method = "psci";
36563 #cooling-cells = <2>; /* min followed by max */
36564 clocks = <&cru ARMCLKB>;
36565+ dynamic-power-coefficient = <436>;
36566 };
36567
36568 cpu_b1: cpu@101 {
36569@@ -151,9 +156,15 @@ cpu_b1: cpu@101 {
36570 reg = <0x0 0x101>;
36571 enable-method = "psci";
36572 clocks = <&cru ARMCLKB>;
36573+ dynamic-power-coefficient = <436>;
36574 };
36575 };
36576
36577+ display-subsystem {
36578+ compatible = "rockchip,display-subsystem";
36579+ ports = <&vopl_out>, <&vopb_out>;
36580+ };
36581+
36582 pmu_a53 {
36583 compatible = "arm,cortex-a53-pmu";
36584 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
36585@@ -289,6 +300,7 @@ sdio0: dwmmc@fe310000 {
36586 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
36587 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
36588 fifo-depth = <0x100>;
36589+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
36590 resets = <&cru SRST_SDIO0>;
36591 reset-names = "reset";
36592 status = "disabled";
36593@@ -402,6 +414,7 @@ usbdrd_dwc3_0: dwc3 {
36594 snps,dis-u2-freeclk-exists-quirk;
36595 snps,dis_u2_susphy_quirk;
36596 snps,dis-del-phy-power-chg-quirk;
36597+ snps,dis-tx-ipgap-linecheck-quirk;
36598 status = "disabled";
36599 };
36600 };
36601@@ -429,6 +442,7 @@ usbdrd_dwc3_1: dwc3 {
36602 snps,dis-u2-freeclk-exists-quirk;
36603 snps,dis_u2_susphy_quirk;
36604 snps,dis-del-phy-power-chg-quirk;
36605+ snps,dis-tx-ipgap-linecheck-quirk;
36606 status = "disabled";
36607 };
36608 };
36609@@ -678,6 +692,7 @@ spi5: spi@ff200000 {
36610 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
36611 pinctrl-names = "default";
36612 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
36613+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
36614 #address-cells = <1>;
36615 #size-cells = <0>;
36616 status = "disabled";
36617@@ -950,6 +965,10 @@ pd_gpu@RK3399_PD_GPU {
36618 };
36619
36620 /* These power domains are grouped by VD_LOGIC */
36621+ pd_edp@RK3399_PD_EDP {
36622+ reg = <RK3399_PD_EDP>;
36623+ clocks = <&cru PCLK_EDP_CTRL>;
36624+ };
36625 pd_emmc@RK3399_PD_EMMC {
36626 reg = <RK3399_PD_EMMC>;
36627 clocks = <&cru ACLK_EMMC>;
36628@@ -967,6 +986,11 @@ pd_sd@RK3399_PD_SD {
36629 <&cru SCLK_SDMMC>;
36630 pm_qos = <&qos_sd>;
36631 };
36632+ pd_sdioaudio@RK3399_PD_SDIOAUDIO {
36633+ reg = <RK3399_PD_SDIOAUDIO>;
36634+ clocks = <&cru HCLK_SDIO>;
36635+ pm_qos = <&qos_sdioaudio>;
36636+ };
36637 pd_vio@RK3399_PD_VIO {
36638 reg = <RK3399_PD_VIO>;
36639 #address-cells = <1>;
36640@@ -1153,6 +1177,33 @@ pwm3: pwm@ff420030 {
36641 status = "disabled";
36642 };
36643
36644+ vpu_mmu: iommu@ff650800 {
36645+ compatible = "rockchip,iommu";
36646+ reg = <0x0 0xff650800 0x0 0x40>;
36647+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
36648+ interrupt-names = "vpu_mmu";
36649+ #iommu-cells = <0>;
36650+ status = "disabled";
36651+ };
36652+
36653+ vdec_mmu: iommu@ff660480 {
36654+ compatible = "rockchip,iommu";
36655+ reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
36656+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
36657+ interrupt-names = "vdec_mmu";
36658+ #iommu-cells = <0>;
36659+ status = "disabled";
36660+ };
36661+
36662+ iep_mmu: iommu@ff670800 {
36663+ compatible = "rockchip,iommu";
36664+ reg = <0x0 0xff670800 0x0 0x40>;
36665+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
36666+ interrupt-names = "iep_mmu";
36667+ #iommu-cells = <0>;
36668+ status = "disabled";
36669+ };
36670+
36671 efuse0: efuse@ff690000 {
36672 compatible = "rockchip,rk3399-efuse";
36673 reg = <0x0 0xff690000 0x0 0x80>;
36674@@ -1387,6 +1438,7 @@ spdif: spdif@ff870000 {
36675 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
36676 pinctrl-names = "default";
36677 pinctrl-0 = <&spdif_bus>;
36678+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
36679 status = "disabled";
36680 };
36681
36682@@ -1401,6 +1453,7 @@ i2s0: i2s@ff880000 {
36683 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
36684 pinctrl-names = "default";
36685 pinctrl-0 = <&i2s0_8ch_bus>;
36686+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
36687 status = "disabled";
36688 };
36689
36690@@ -1414,6 +1467,7 @@ i2s1: i2s@ff890000 {
36691 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
36692 pinctrl-names = "default";
36693 pinctrl-0 = <&i2s1_2ch_bus>;
36694+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
36695 status = "disabled";
36696 };
36697
36698@@ -1425,6 +1479,224 @@ i2s2: i2s@ff8a0000 {
36699 dma-names = "tx", "rx";
36700 clock-names = "i2s_clk", "i2s_hclk";
36701 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
36702+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
36703+ status = "disabled";
36704+ };
36705+
36706+ vopl: vop@ff8f0000 {
36707+ compatible = "rockchip,rk3399-vop-lit";
36708+ reg = <0x0 0xff8f0000 0x0 0x3efc>;
36709+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
36710+ assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
36711+ assigned-clock-rates = <400000000>, <100000000>;
36712+ clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
36713+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
36714+ iommus = <&vopl_mmu>;
36715+ power-domains = <&power RK3399_PD_VOPL>;
36716+ resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
36717+ reset-names = "axi", "ahb", "dclk";
36718+ status = "disabled";
36719+
36720+ vopl_out: port {
36721+ #address-cells = <1>;
36722+ #size-cells = <0>;
36723+
36724+ vopl_out_mipi: endpoint@0 {
36725+ reg = <0>;
36726+ remote-endpoint = <&mipi_in_vopl>;
36727+ };
36728+
36729+ vopl_out_edp: endpoint@1 {
36730+ reg = <1>;
36731+ remote-endpoint = <&edp_in_vopl>;
36732+ };
36733+
36734+ vopl_out_hdmi: endpoint@2 {
36735+ reg = <2>;
36736+ remote-endpoint = <&hdmi_in_vopl>;
36737+ };
36738+ };
36739+ };
36740+
36741+ vopl_mmu: iommu@ff8f3f00 {
36742+ compatible = "rockchip,iommu";
36743+ reg = <0x0 0xff8f3f00 0x0 0x100>;
36744+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
36745+ interrupt-names = "vopl_mmu";
36746+ clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
36747+ clock-names = "aclk", "hclk";
36748+ power-domains = <&power RK3399_PD_VOPL>;
36749+ #iommu-cells = <0>;
36750+ status = "disabled";
36751+ };
36752+
36753+ vopb: vop@ff900000 {
36754+ compatible = "rockchip,rk3399-vop-big";
36755+ reg = <0x0 0xff900000 0x0 0x3efc>;
36756+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
36757+ assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
36758+ assigned-clock-rates = <400000000>, <100000000>;
36759+ clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
36760+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
36761+ iommus = <&vopb_mmu>;
36762+ power-domains = <&power RK3399_PD_VOPB>;
36763+ resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
36764+ reset-names = "axi", "ahb", "dclk";
36765+ status = "disabled";
36766+
36767+ vopb_out: port {
36768+ #address-cells = <1>;
36769+ #size-cells = <0>;
36770+
36771+ vopb_out_edp: endpoint@0 {
36772+ reg = <0>;
36773+ remote-endpoint = <&edp_in_vopb>;
36774+ };
36775+
36776+ vopb_out_mipi: endpoint@1 {
36777+ reg = <1>;
36778+ remote-endpoint = <&mipi_in_vopb>;
36779+ };
36780+
36781+ vopb_out_hdmi: endpoint@2 {
36782+ reg = <2>;
36783+ remote-endpoint = <&hdmi_in_vopb>;
36784+ };
36785+ };
36786+ };
36787+
36788+ vopb_mmu: iommu@ff903f00 {
36789+ compatible = "rockchip,iommu";
36790+ reg = <0x0 0xff903f00 0x0 0x100>;
36791+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
36792+ interrupt-names = "vopb_mmu";
36793+ clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
36794+ clock-names = "aclk", "hclk";
36795+ power-domains = <&power RK3399_PD_VOPB>;
36796+ #iommu-cells = <0>;
36797+ status = "disabled";
36798+ };
36799+
36800+ isp0_mmu: iommu@ff914000 {
36801+ compatible = "rockchip,iommu";
36802+ reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
36803+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
36804+ interrupt-names = "isp0_mmu";
36805+ #iommu-cells = <0>;
36806+ rockchip,disable-mmu-reset;
36807+ status = "disabled";
36808+ };
36809+
36810+ isp1_mmu: iommu@ff924000 {
36811+ compatible = "rockchip,iommu";
36812+ reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
36813+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
36814+ interrupt-names = "isp1_mmu";
36815+ #iommu-cells = <0>;
36816+ rockchip,disable-mmu-reset;
36817+ status = "disabled";
36818+ };
36819+
36820+ hdmi: hdmi@ff940000 {
36821+ compatible = "rockchip,rk3399-dw-hdmi";
36822+ reg = <0x0 0xff940000 0x0 0x20000>;
36823+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
36824+ clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
36825+ clock-names = "iahb", "isfr", "vpll", "grf";
36826+ power-domains = <&power RK3399_PD_HDCP>;
36827+ reg-io-width = <4>;
36828+ rockchip,grf = <&grf>;
36829+ status = "disabled";
36830+
36831+ ports {
36832+ hdmi_in: port {
36833+ #address-cells = <1>;
36834+ #size-cells = <0>;
36835+
36836+ hdmi_in_vopb: endpoint@0 {
36837+ reg = <0>;
36838+ remote-endpoint = <&vopb_out_hdmi>;
36839+ };
36840+ hdmi_in_vopl: endpoint@1 {
36841+ reg = <1>;
36842+ remote-endpoint = <&vopl_out_hdmi>;
36843+ };
36844+ };
36845+ };
36846+ };
36847+
36848+ mipi_dsi: mipi@ff960000 {
36849+ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
36850+ reg = <0x0 0xff960000 0x0 0x8000>;
36851+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
36852+ clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
36853+ <&cru SCLK_DPHY_TX0_CFG>;
36854+ clock-names = "ref", "pclk", "phy_cfg";
36855+ power-domains = <&power RK3399_PD_VIO>;
36856+ rockchip,grf = <&grf>;
36857+ status = "disabled";
36858+
36859+ ports {
36860+ mipi_in: port {
36861+ #address-cells = <1>;
36862+ #size-cells = <0>;
36863+
36864+ mipi_in_vopb: endpoint@0 {
36865+ reg = <0>;
36866+ remote-endpoint = <&vopb_out_mipi>;
36867+ };
36868+ mipi_in_vopl: endpoint@1 {
36869+ reg = <1>;
36870+ remote-endpoint = <&vopl_out_mipi>;
36871+ };
36872+ };
36873+ };
36874+ };
36875+
36876+ edp: edp@ff970000 {
36877+ compatible = "rockchip,rk3399-edp";
36878+ reg = <0x0 0xff970000 0x0 0x8000>;
36879+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
36880+ clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
36881+ clock-names = "dp", "pclk";
36882+ pinctrl-names = "default";
36883+ pinctrl-0 = <&edp_hpd>;
36884+ power-domains = <&power RK3399_PD_EDP>;
36885+ resets = <&cru SRST_P_EDP_CTRL>;
36886+ reset-names = "dp";
36887+ rockchip,grf = <&grf>;
36888+ status = "disabled";
36889+
36890+ ports {
36891+ #address-cells = <1>;
36892+ #size-cells = <0>;
36893+ edp_in: port@0 {
36894+ reg = <0>;
36895+ #address-cells = <1>;
36896+ #size-cells = <0>;
36897+
36898+ edp_in_vopb: endpoint@0 {
36899+ reg = <0>;
36900+ remote-endpoint = <&vopb_out_edp>;
36901+ };
36902+
36903+ edp_in_vopl: endpoint@1 {
36904+ reg = <1>;
36905+ remote-endpoint = <&vopl_out_edp>;
36906+ };
36907+ };
36908+ };
36909+ };
36910+
36911+ gpu: gpu@ff9a0000 {
36912+ compatible = "rockchip,rk3399-mali", "arm,mali-t860";
36913+ reg = <0x0 0xff9a0000 0x0 0x10000>;
36914+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
36915+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
36916+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
36917+ interrupt-names = "gpu", "job", "mmu";
36918+ clocks = <&cru ACLK_GPU>;
36919+ power-domains = <&power RK3399_PD_GPU>;
36920 status = "disabled";
36921 };
36922
36923@@ -1788,7 +2060,7 @@ sdmmc_cmd: sdmmc-cmd {
36924 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
36925 };
36926
36927- sdmmc_cd: sdmcc-cd {
36928+ sdmmc_cd: sdmmc-cd {
36929 rockchip,pins =
36930 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
36931 };
36932@@ -2092,16 +2364,6 @@ hdmi_cec: hdmi-cec {
36933 };
36934
36935 pcie {
36936- pcie_clkreqn: pci-clkreqn {
36937- rockchip,pins =
36938- <2 26 RK_FUNC_2 &pcfg_pull_none>;
36939- };
36940-
36941- pcie_clkreqnb: pci-clkreqnb {
36942- rockchip,pins =
36943- <4 24 RK_FUNC_1 &pcfg_pull_none>;
36944- };
36945-
36946 pcie_clkreqn_cpm: pci-clkreqn-cpm {
36947 rockchip,pins =
36948 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
36949diff --git a/arch/arm64/boot/dts/socionext/Makefile b/arch/arm64/boot/dts/socionext/Makefile
36950index 4a13a3a97101..4bc091b365fd 100644
36951--- a/arch/arm64/boot/dts/socionext/Makefile
36952+++ b/arch/arm64/boot/dts/socionext/Makefile
36953@@ -2,7 +2,8 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
36954 uniphier-ld11-global.dtb \
36955 uniphier-ld11-ref.dtb \
36956 uniphier-ld20-global.dtb \
36957- uniphier-ld20-ref.dtb
36958+ uniphier-ld20-ref.dtb \
36959+ uniphier-pxs3-ref.dtb
36960
36961 always := $(dtb-y)
36962 clean-files := *.dtb
36963diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts
36964index 115357018ef7..2452b2243f42 100644
36965--- a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts
36966+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts
36967@@ -9,7 +9,7 @@
36968 */
36969
36970 /dts-v1/;
36971-/include/ "uniphier-ld11.dtsi"
36972+#include "uniphier-ld11.dtsi"
36973
36974 / {
36975 model = "UniPhier LD11 Global Board (REF_LD11_GP)";
36976@@ -68,3 +68,7 @@ &usb1 {
36977 &usb2 {
36978 status = "okay";
36979 };
36980+
36981+&nand {
36982+ status = "okay";
36983+};
36984diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
36985index cc8ebe34c27c..ffb473ad2e0f 100644
36986--- a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
36987+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
36988@@ -8,9 +8,9 @@
36989 */
36990
36991 /dts-v1/;
36992-/include/ "uniphier-ld11.dtsi"
36993-/include/ "uniphier-ref-daughter.dtsi"
36994-/include/ "uniphier-support-card.dtsi"
36995+#include "uniphier-ld11.dtsi"
36996+#include "uniphier-ref-daughter.dtsi"
36997+#include "uniphier-support-card.dtsi"
36998
36999 / {
37000 model = "UniPhier LD11 Reference Board";
37001diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
37002index bdce5b89baec..ee4aff53a5f5 100644
37003--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
37004+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
37005@@ -150,6 +150,17 @@ serial3: serial@54006b00 {
37006 clocks = <&peri_clk 3>;
37007 };
37008
37009+ adamv@57920000 {
37010+ compatible = "socionext,uniphier-ld11-adamv",
37011+ "simple-mfd", "syscon";
37012+ reg = <0x57920000 0x1000>;
37013+
37014+ adamv_rst: reset {
37015+ compatible = "socionext,uniphier-ld11-adamv-reset";
37016+ #reset-cells = <1>;
37017+ };
37018+ };
37019+
37020 i2c0: i2c@58780000 {
37021 compatible = "socionext,uniphier-fi2c";
37022 status = "disabled";
37023@@ -344,6 +355,13 @@ pinctrl: pinctrl {
37024 };
37025 };
37026
37027+ aidet: aidet@5fc20000 {
37028+ compatible = "socionext,uniphier-ld11-aidet";
37029+ reg = <0x5fc20000 0x200>;
37030+ interrupt-controller;
37031+ #interrupt-cells = <2>;
37032+ };
37033+
37034 gic: interrupt-controller@5fe00000 {
37035 compatible = "arm,gic-v3";
37036 reg = <0x5fe00000 0x10000>, /* GICD */
37037@@ -367,8 +385,23 @@ sys_rst: reset {
37038 compatible = "socionext,uniphier-ld11-reset";
37039 #reset-cells = <1>;
37040 };
37041+
37042+ watchdog {
37043+ compatible = "socionext,uniphier-wdt";
37044+ };
37045+ };
37046+
37047+ nand: nand@68000000 {
37048+ compatible = "socionext,uniphier-denali-nand-v5b";
37049+ status = "disabled";
37050+ reg-names = "nand_data", "denali_reg";
37051+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
37052+ interrupts = <0 65 4>;
37053+ pinctrl-names = "default";
37054+ pinctrl-0 = <&pinctrl_nand>;
37055+ clocks = <&sys_clk 2>;
37056 };
37057 };
37058 };
37059
37060-/include/ "uniphier-pinctrl.dtsi"
37061+#include "uniphier-pinctrl.dtsi"
37062diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
37063index 9f620d4101b5..fc2bc9d75d35 100644
37064--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
37065+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
37066@@ -9,7 +9,7 @@
37067 */
37068
37069 /dts-v1/;
37070-/include/ "uniphier-ld20.dtsi"
37071+#include "uniphier-ld20.dtsi"
37072
37073 / {
37074 model = "UniPhier LD20 Global Board (REF_LD20_GP)";
37075@@ -50,3 +50,7 @@ &serial1 {
37076 &i2c0 {
37077 status = "okay";
37078 };
37079+
37080+&nand {
37081+ status = "okay";
37082+};
37083diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
37084index 494166aee24c..1ca0c8620dc5 100644
37085--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
37086+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
37087@@ -8,9 +8,9 @@
37088 */
37089
37090 /dts-v1/;
37091-/include/ "uniphier-ld20.dtsi"
37092-/include/ "uniphier-ref-daughter.dtsi"
37093-/include/ "uniphier-support-card.dtsi"
37094+#include "uniphier-ld20.dtsi"
37095+#include "uniphier-ref-daughter.dtsi"
37096+#include "uniphier-support-card.dtsi"
37097
37098 / {
37099 model = "UniPhier LD20 Reference Board";
37100diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
37101index de1e75362817..a29c279b6e8e 100644
37102--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
37103+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
37104@@ -219,6 +219,17 @@ serial3: serial@54006b00 {
37105 clocks = <&peri_clk 3>;
37106 };
37107
37108+ adamv@57920000 {
37109+ compatible = "socionext,uniphier-ld20-adamv",
37110+ "simple-mfd", "syscon";
37111+ reg = <0x57920000 0x1000>;
37112+
37113+ adamv_rst: reset {
37114+ compatible = "socionext,uniphier-ld20-adamv-reset";
37115+ #reset-cells = <1>;
37116+ };
37117+ };
37118+
37119 i2c0: i2c@58780000 {
37120 compatible = "socionext,uniphier-fi2c";
37121 status = "disabled";
37122@@ -309,7 +320,7 @@ smpctrl@59801000 {
37123 sdctrl@59810000 {
37124 compatible = "socionext,uniphier-ld20-sdctrl",
37125 "simple-mfd", "syscon";
37126- reg = <0x59810000 0x800>;
37127+ reg = <0x59810000 0x400>;
37128
37129 sd_clk: clock {
37130 compatible = "socionext,uniphier-ld20-sd-clock";
37131@@ -365,6 +376,13 @@ pinctrl: pinctrl {
37132 };
37133 };
37134
37135+ aidet: aidet@5fc20000 {
37136+ compatible = "socionext,uniphier-ld20-aidet";
37137+ reg = <0x5fc20000 0x200>;
37138+ interrupt-controller;
37139+ #interrupt-cells = <2>;
37140+ };
37141+
37142 gic: interrupt-controller@5fe00000 {
37143 compatible = "arm,gic-v3";
37144 reg = <0x5fe00000 0x10000>, /* GICD */
37145@@ -388,8 +406,23 @@ sys_rst: reset {
37146 compatible = "socionext,uniphier-ld20-reset";
37147 #reset-cells = <1>;
37148 };
37149+
37150+ watchdog {
37151+ compatible = "socionext,uniphier-wdt";
37152+ };
37153+ };
37154+
37155+ nand: nand@68000000 {
37156+ compatible = "socionext,uniphier-denali-nand-v5b";
37157+ status = "disabled";
37158+ reg-names = "nand_data", "denali_reg";
37159+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
37160+ interrupts = <0 65 4>;
37161+ pinctrl-names = "default";
37162+ pinctrl-0 = <&pinctrl_nand>;
37163+ clocks = <&sys_clk 2>;
37164 };
37165 };
37166 };
37167
37168-/include/ "uniphier-pinctrl.dtsi"
37169+#include "uniphier-pinctrl.dtsi"
37170diff --git a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi
37171deleted file mode 120000
37172index f42fb6f38bd3..000000000000
37173--- a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi
37174+++ /dev/null
37175@@ -1 +0,0 @@
37176-../../../../arm/boot/dts/uniphier-pinctrl.dtsi
37177\ No newline at end of file
37178diff --git a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi
37179new file mode 100644
37180index 000000000000..9caabbb8bae3
37181--- /dev/null
37182+++ b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi
37183@@ -0,0 +1 @@
37184+#include <arm/uniphier-pinctrl.dtsi>
37185diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
37186new file mode 100644
37187index 000000000000..d65f746a3f9d
37188--- /dev/null
37189+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
37190@@ -0,0 +1,62 @@
37191+/*
37192+ * Device Tree Source for UniPhier PXs3 Reference Board
37193+ *
37194+ * Copyright (C) 2017 Socionext Inc.
37195+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
37196+ *
37197+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
37198+ */
37199+
37200+/dts-v1/;
37201+#include "uniphier-pxs3.dtsi"
37202+#include "uniphier-support-card.dtsi"
37203+
37204+/ {
37205+ model = "UniPhier PXs3 Reference Board";
37206+ compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
37207+
37208+ chosen {
37209+ stdout-path = "serial0:115200n8";
37210+ };
37211+
37212+ aliases {
37213+ serial0 = &serial0;
37214+ serial1 = &serial1;
37215+ serial2 = &serial2;
37216+ serial3 = &serial3;
37217+ i2c0 = &i2c0;
37218+ i2c1 = &i2c1;
37219+ i2c2 = &i2c2;
37220+ i2c3 = &i2c3;
37221+ i2c6 = &i2c6;
37222+ };
37223+
37224+ memory@80000000 {
37225+ device_type = "memory";
37226+ reg = <0 0x80000000 0 0xa0000000>;
37227+ };
37228+};
37229+
37230+&ethsc {
37231+ interrupts = <0 52 4>;
37232+};
37233+
37234+&serial0 {
37235+ status = "okay";
37236+};
37237+
37238+&i2c0 {
37239+ status = "okay";
37240+};
37241+
37242+&i2c1 {
37243+ status = "okay";
37244+};
37245+
37246+&i2c2 {
37247+ status = "okay";
37248+};
37249+
37250+&i2c3 {
37251+ status = "okay";
37252+};
37253diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
37254new file mode 100644
37255index 000000000000..384729fa740f
37256--- /dev/null
37257+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
37258@@ -0,0 +1,367 @@
37259+/*
37260+ * Device Tree Source for UniPhier PXs3 SoC
37261+ *
37262+ * Copyright (C) 2017 Socionext Inc.
37263+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
37264+ *
37265+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
37266+ */
37267+
37268+/memreserve/ 0x80000000 0x02000000;
37269+
37270+/ {
37271+ compatible = "socionext,uniphier-pxs3";
37272+ #address-cells = <2>;
37273+ #size-cells = <2>;
37274+ interrupt-parent = <&gic>;
37275+
37276+ cpus {
37277+ #address-cells = <2>;
37278+ #size-cells = <0>;
37279+
37280+ cpu-map {
37281+ cluster0 {
37282+ core0 {
37283+ cpu = <&cpu0>;
37284+ };
37285+ core1 {
37286+ cpu = <&cpu1>;
37287+ };
37288+ core2 {
37289+ cpu = <&cpu2>;
37290+ };
37291+ core3 {
37292+ cpu = <&cpu3>;
37293+ };
37294+ };
37295+ };
37296+
37297+ cpu0: cpu@0 {
37298+ device_type = "cpu";
37299+ compatible = "arm,cortex-a53", "arm,armv8";
37300+ reg = <0 0x000>;
37301+ clocks = <&sys_clk 33>;
37302+ enable-method = "psci";
37303+ operating-points-v2 = <&cluster0_opp>;
37304+ };
37305+
37306+ cpu1: cpu@1 {
37307+ device_type = "cpu";
37308+ compatible = "arm,cortex-a53", "arm,armv8";
37309+ reg = <0 0x001>;
37310+ clocks = <&sys_clk 33>;
37311+ enable-method = "psci";
37312+ operating-points-v2 = <&cluster0_opp>;
37313+ };
37314+
37315+ cpu2: cpu@2 {
37316+ device_type = "cpu";
37317+ compatible = "arm,cortex-a53", "arm,armv8";
37318+ reg = <0 0x002>;
37319+ clocks = <&sys_clk 33>;
37320+ enable-method = "psci";
37321+ operating-points-v2 = <&cluster0_opp>;
37322+ };
37323+
37324+ cpu3: cpu@3 {
37325+ device_type = "cpu";
37326+ compatible = "arm,cortex-a53", "arm,armv8";
37327+ reg = <0 0x003>;
37328+ clocks = <&sys_clk 33>;
37329+ enable-method = "psci";
37330+ operating-points-v2 = <&cluster0_opp>;
37331+ };
37332+ };
37333+
37334+ cluster0_opp: opp_table {
37335+ compatible = "operating-points-v2";
37336+ opp-shared;
37337+
37338+ opp-250000000 {
37339+ opp-hz = /bits/ 64 <250000000>;
37340+ clock-latency-ns = <300>;
37341+ };
37342+ opp-325000000 {
37343+ opp-hz = /bits/ 64 <325000000>;
37344+ clock-latency-ns = <300>;
37345+ };
37346+ opp-500000000 {
37347+ opp-hz = /bits/ 64 <500000000>;
37348+ clock-latency-ns = <300>;
37349+ };
37350+ opp-650000000 {
37351+ opp-hz = /bits/ 64 <650000000>;
37352+ clock-latency-ns = <300>;
37353+ };
37354+ opp-666667000 {
37355+ opp-hz = /bits/ 64 <666667000>;
37356+ clock-latency-ns = <300>;
37357+ };
37358+ opp-866667000 {
37359+ opp-hz = /bits/ 64 <866667000>;
37360+ clock-latency-ns = <300>;
37361+ };
37362+ opp-1000000000 {
37363+ opp-hz = /bits/ 64 <1000000000>;
37364+ clock-latency-ns = <300>;
37365+ };
37366+ opp-1300000000 {
37367+ opp-hz = /bits/ 64 <1300000000>;
37368+ clock-latency-ns = <300>;
37369+ };
37370+ };
37371+
37372+ psci {
37373+ compatible = "arm,psci-1.0";
37374+ method = "smc";
37375+ };
37376+
37377+ clocks {
37378+ refclk: ref {
37379+ compatible = "fixed-clock";
37380+ #clock-cells = <0>;
37381+ clock-frequency = <25000000>;
37382+ };
37383+ };
37384+
37385+ timer {
37386+ compatible = "arm,armv8-timer";
37387+ interrupts = <1 13 4>,
37388+ <1 14 4>,
37389+ <1 11 4>,
37390+ <1 10 4>;
37391+ };
37392+
37393+ soc@0 {
37394+ compatible = "simple-bus";
37395+ #address-cells = <1>;
37396+ #size-cells = <1>;
37397+ ranges = <0 0 0 0xffffffff>;
37398+
37399+ serial0: serial@54006800 {
37400+ compatible = "socionext,uniphier-uart";
37401+ status = "disabled";
37402+ reg = <0x54006800 0x40>;
37403+ interrupts = <0 33 4>;
37404+ pinctrl-names = "default";
37405+ pinctrl-0 = <&pinctrl_uart0>;
37406+ clocks = <&peri_clk 0>;
37407+ };
37408+
37409+ serial1: serial@54006900 {
37410+ compatible = "socionext,uniphier-uart";
37411+ status = "disabled";
37412+ reg = <0x54006900 0x40>;
37413+ interrupts = <0 35 4>;
37414+ pinctrl-names = "default";
37415+ pinctrl-0 = <&pinctrl_uart1>;
37416+ clocks = <&peri_clk 1>;
37417+ };
37418+
37419+ serial2: serial@54006a00 {
37420+ compatible = "socionext,uniphier-uart";
37421+ status = "disabled";
37422+ reg = <0x54006a00 0x40>;
37423+ interrupts = <0 37 4>;
37424+ pinctrl-names = "default";
37425+ pinctrl-0 = <&pinctrl_uart2>;
37426+ clocks = <&peri_clk 2>;
37427+ };
37428+
37429+ serial3: serial@54006b00 {
37430+ compatible = "socionext,uniphier-uart";
37431+ status = "disabled";
37432+ reg = <0x54006b00 0x40>;
37433+ interrupts = <0 177 4>;
37434+ pinctrl-names = "default";
37435+ pinctrl-0 = <&pinctrl_uart3>;
37436+ clocks = <&peri_clk 3>;
37437+ };
37438+
37439+ i2c0: i2c@58780000 {
37440+ compatible = "socionext,uniphier-fi2c";
37441+ status = "disabled";
37442+ reg = <0x58780000 0x80>;
37443+ #address-cells = <1>;
37444+ #size-cells = <0>;
37445+ interrupts = <0 41 4>;
37446+ pinctrl-names = "default";
37447+ pinctrl-0 = <&pinctrl_i2c0>;
37448+ clocks = <&peri_clk 4>;
37449+ clock-frequency = <100000>;
37450+ };
37451+
37452+ i2c1: i2c@58781000 {
37453+ compatible = "socionext,uniphier-fi2c";
37454+ status = "disabled";
37455+ reg = <0x58781000 0x80>;
37456+ #address-cells = <1>;
37457+ #size-cells = <0>;
37458+ interrupts = <0 42 4>;
37459+ pinctrl-names = "default";
37460+ pinctrl-0 = <&pinctrl_i2c1>;
37461+ clocks = <&peri_clk 5>;
37462+ clock-frequency = <100000>;
37463+ };
37464+
37465+ i2c2: i2c@58782000 {
37466+ compatible = "socionext,uniphier-fi2c";
37467+ status = "disabled";
37468+ reg = <0x58782000 0x80>;
37469+ #address-cells = <1>;
37470+ #size-cells = <0>;
37471+ interrupts = <0 43 4>;
37472+ pinctrl-names = "default";
37473+ pinctrl-0 = <&pinctrl_i2c2>;
37474+ clocks = <&peri_clk 6>;
37475+ clock-frequency = <100000>;
37476+ };
37477+
37478+ i2c3: i2c@58783000 {
37479+ compatible = "socionext,uniphier-fi2c";
37480+ status = "disabled";
37481+ reg = <0x58783000 0x80>;
37482+ #address-cells = <1>;
37483+ #size-cells = <0>;
37484+ interrupts = <0 44 4>;
37485+ pinctrl-names = "default";
37486+ pinctrl-0 = <&pinctrl_i2c3>;
37487+ clocks = <&peri_clk 7>;
37488+ clock-frequency = <100000>;
37489+ };
37490+
37491+ /* chip-internal connection for HDMI */
37492+ i2c6: i2c@58786000 {
37493+ compatible = "socionext,uniphier-fi2c";
37494+ reg = <0x58786000 0x80>;
37495+ #address-cells = <1>;
37496+ #size-cells = <0>;
37497+ interrupts = <0 26 4>;
37498+ clocks = <&peri_clk 10>;
37499+ clock-frequency = <400000>;
37500+ };
37501+
37502+ system_bus: system-bus@58c00000 {
37503+ compatible = "socionext,uniphier-system-bus";
37504+ status = "disabled";
37505+ reg = <0x58c00000 0x400>;
37506+ #address-cells = <2>;
37507+ #size-cells = <1>;
37508+ pinctrl-names = "default";
37509+ pinctrl-0 = <&pinctrl_system_bus>;
37510+ };
37511+
37512+ smpctrl@59801000 {
37513+ compatible = "socionext,uniphier-smpctrl";
37514+ reg = <0x59801000 0x400>;
37515+ };
37516+
37517+ sdctrl@59810000 {
37518+ compatible = "socionext,uniphier-pxs3-sdctrl",
37519+ "simple-mfd", "syscon";
37520+ reg = <0x59810000 0x400>;
37521+
37522+ sd_clk: clock {
37523+ compatible = "socionext,uniphier-pxs3-sd-clock";
37524+ #clock-cells = <1>;
37525+ };
37526+
37527+ sd_rst: reset {
37528+ compatible = "socionext,uniphier-pxs3-sd-reset";
37529+ #reset-cells = <1>;
37530+ };
37531+ };
37532+
37533+ perictrl@59820000 {
37534+ compatible = "socionext,uniphier-pxs3-perictrl",
37535+ "simple-mfd", "syscon";
37536+ reg = <0x59820000 0x200>;
37537+
37538+ peri_clk: clock {
37539+ compatible = "socionext,uniphier-pxs3-peri-clock";
37540+ #clock-cells = <1>;
37541+ };
37542+
37543+ peri_rst: reset {
37544+ compatible = "socionext,uniphier-pxs3-peri-reset";
37545+ #reset-cells = <1>;
37546+ };
37547+ };
37548+
37549+ emmc: sdhc@5a000000 {
37550+ compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
37551+ reg = <0x5a000000 0x400>;
37552+ interrupts = <0 78 4>;
37553+ pinctrl-names = "default";
37554+ pinctrl-0 = <&pinctrl_emmc>;
37555+ clocks = <&sys_clk 4>;
37556+ bus-width = <8>;
37557+ mmc-ddr-1_8v;
37558+ mmc-hs200-1_8v;
37559+ cdns,phy-input-delay-legacy = <4>;
37560+ cdns,phy-input-delay-mmc-highspeed = <2>;
37561+ cdns,phy-input-delay-mmc-ddr = <3>;
37562+ cdns,phy-dll-delay-sdclk = <21>;
37563+ cdns,phy-dll-delay-sdclk-hsmmc = <21>;
37564+ };
37565+
37566+ soc-glue@5f800000 {
37567+ compatible = "socionext,uniphier-pxs3-soc-glue",
37568+ "simple-mfd", "syscon";
37569+ reg = <0x5f800000 0x2000>;
37570+
37571+ pinctrl: pinctrl {
37572+ compatible = "socionext,uniphier-pxs3-pinctrl";
37573+ };
37574+ };
37575+
37576+ aidet: aidet@5fc20000 {
37577+ compatible = "socionext,uniphier-pxs3-aidet";
37578+ reg = <0x5fc20000 0x200>;
37579+ interrupt-controller;
37580+ #interrupt-cells = <2>;
37581+ };
37582+
37583+ gic: interrupt-controller@5fe00000 {
37584+ compatible = "arm,gic-v3";
37585+ reg = <0x5fe00000 0x10000>, /* GICD */
37586+ <0x5fe80000 0x80000>; /* GICR */
37587+ interrupt-controller;
37588+ #interrupt-cells = <3>;
37589+ interrupts = <1 9 4>;
37590+ };
37591+
37592+ sysctrl@61840000 {
37593+ compatible = "socionext,uniphier-pxs3-sysctrl",
37594+ "simple-mfd", "syscon";
37595+ reg = <0x61840000 0x10000>;
37596+
37597+ sys_clk: clock {
37598+ compatible = "socionext,uniphier-pxs3-clock";
37599+ #clock-cells = <1>;
37600+ };
37601+
37602+ sys_rst: reset {
37603+ compatible = "socionext,uniphier-pxs3-reset";
37604+ #reset-cells = <1>;
37605+ };
37606+
37607+ watchdog {
37608+ compatible = "socionext,uniphier-wdt";
37609+ };
37610+ };
37611+
37612+ nand: nand@68000000 {
37613+ compatible = "socionext,uniphier-denali-nand-v5b";
37614+ status = "disabled";
37615+ reg-names = "nand_data", "denali_reg";
37616+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
37617+ interrupts = <0 65 4>;
37618+ pinctrl-names = "default";
37619+ pinctrl-0 = <&pinctrl_nand>;
37620+ clocks = <&sys_clk 2>;
37621+ };
37622+ };
37623+};
37624+
37625+#include "uniphier-pinctrl.dtsi"
37626diff --git a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi
37627deleted file mode 120000
37628index 4685a8d89cba..000000000000
37629--- a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi
37630+++ /dev/null
37631@@ -1 +0,0 @@
37632-../../../../arm/boot/dts/uniphier-ref-daughter.dtsi
37633\ No newline at end of file
37634diff --git a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi
37635new file mode 100644
37636index 000000000000..e66d999d9f5d
37637--- /dev/null
37638+++ b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi
37639@@ -0,0 +1 @@
37640+#include <arm/uniphier-ref-daughter.dtsi>
37641diff --git a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi
37642deleted file mode 120000
37643index 1246db9be2a1..000000000000
37644--- a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi
37645+++ /dev/null
37646@@ -1 +0,0 @@
37647-../../../../arm/boot/dts/uniphier-support-card.dtsi
37648\ No newline at end of file
37649diff --git a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi
37650new file mode 100644
37651index 000000000000..28c5b4ed1d95
37652--- /dev/null
37653+++ b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi
37654@@ -0,0 +1 @@
37655+#include <arm/uniphier-support-card.dtsi>
37656diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
37657index cdc6a437dcc7..b87b8316f4ac 100644
37658--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
37659+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
37660@@ -11,7 +11,7 @@
37661 * the License, or (at your option) any later version.
37662 */
37663
37664-&amba {
37665+/ {
37666 misc_clk: misc_clk {
37667 compatible = "fixed-clock";
37668 #clock-cells = <0>;
37669@@ -29,12 +29,60 @@ sata_clk: sata_clk {
37670 #clock-cells = <0>;
37671 clock-frequency = <75000000>;
37672 };
37673+
37674+ clk100: clk100 {
37675+ compatible = "fixed-clock";
37676+ #clock-cells = <0>;
37677+ clock-frequency = <100000000>;
37678+ };
37679+
37680+ clk600: clk600 {
37681+ compatible = "fixed-clock";
37682+ #clock-cells = <0>;
37683+ clock-frequency = <600000000>;
37684+ };
37685 };
37686
37687 &can0 {
37688 clocks = <&misc_clk &misc_clk>;
37689 };
37690
37691+&can1 {
37692+ clocks = <&misc_clk &misc_clk>;
37693+};
37694+
37695+&fpd_dma_chan1 {
37696+ clocks = <&clk600>, <&clk100>;
37697+};
37698+
37699+&fpd_dma_chan2 {
37700+ clocks = <&clk600>, <&clk100>;
37701+};
37702+
37703+&fpd_dma_chan3 {
37704+ clocks = <&clk600>, <&clk100>;
37705+};
37706+
37707+&fpd_dma_chan4 {
37708+ clocks = <&clk600>, <&clk100>;
37709+};
37710+
37711+&fpd_dma_chan5 {
37712+ clocks = <&clk600>, <&clk100>;
37713+};
37714+
37715+&fpd_dma_chan6 {
37716+ clocks = <&clk600>, <&clk100>;
37717+};
37718+
37719+&fpd_dma_chan7 {
37720+ clocks = <&clk600>, <&clk100>;
37721+};
37722+
37723+&fpd_dma_chan8 {
37724+ clocks = <&clk600>, <&clk100>;
37725+};
37726+
37727 &gem0 {
37728 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
37729 };
37730diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
37731index ef1b9e573af0..bf552674a834 100644
37732--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
37733+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
37734@@ -13,13 +13,15 @@
37735
37736 /dts-v1/;
37737
37738-/include/ "zynqmp.dtsi"
37739-/include/ "zynqmp-ep108-clk.dtsi"
37740+#include "zynqmp.dtsi"
37741+#include "zynqmp-ep108-clk.dtsi"
37742
37743 / {
37744 model = "ZynqMP EP108";
37745
37746 aliases {
37747+ mmc0 = &sdhci0;
37748+ mmc1 = &sdhci1;
37749 serial0 = &uart0;
37750 };
37751
37752@@ -37,6 +39,10 @@ &can0 {
37753 status = "okay";
37754 };
37755
37756+&can1 {
37757+ status = "okay";
37758+};
37759+
37760 &gem0 {
37761 status = "okay";
37762 phy-handle = <&phy0>;
37763@@ -55,7 +61,7 @@ &i2c0 {
37764 status = "okay";
37765 clock-frequency = <400000>;
37766 eeprom@54 {
37767- compatible = "at,24c64";
37768+ compatible = "atmel,24c64";
37769 reg = <0x54>;
37770 };
37771 };
37772@@ -64,7 +70,7 @@ &i2c1 {
37773 status = "okay";
37774 clock-frequency = <400000>;
37775 eeprom@55 {
37776- compatible = "at,24c64";
37777+ compatible = "atmel,24c64";
37778 reg = <0x55>;
37779 };
37780 };
37781@@ -92,7 +98,7 @@ spi0_flash0: spi0_flash0@0 {
37782 spi-max-frequency = <50000000>;
37783 reg = <0>;
37784
37785- spi0_flash0@00000000 {
37786+ spi0_flash0@0 {
37787 label = "spi0_flash0";
37788 reg = <0x0 0x100000>;
37789 };
37790@@ -109,7 +115,7 @@ spi1_flash0: spi1_flash0@0 {
37791 spi-max-frequency = <50000000>;
37792 reg = <0>;
37793
37794- spi1_flash0@00000000 {
37795+ spi1_flash0@0 {
37796 label = "spi1_flash0";
37797 reg = <0x0 0x100000>;
37798 };
37799diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
37800index 54dc28351c8c..7665fbddff28 100644
37801--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
37802+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
37803@@ -20,33 +20,84 @@ cpus {
37804 #address-cells = <1>;
37805 #size-cells = <0>;
37806
37807- cpu@0 {
37808+ cpu0: cpu@0 {
37809 compatible = "arm,cortex-a53", "arm,armv8";
37810 device_type = "cpu";
37811 enable-method = "psci";
37812+ operating-points-v2 = <&cpu_opp_table>;
37813 reg = <0x0>;
37814+ cpu-idle-states = <&CPU_SLEEP_0>;
37815 };
37816
37817- cpu@1 {
37818+ cpu1: cpu@1 {
37819 compatible = "arm,cortex-a53", "arm,armv8";
37820 device_type = "cpu";
37821 enable-method = "psci";
37822 reg = <0x1>;
37823+ operating-points-v2 = <&cpu_opp_table>;
37824+ cpu-idle-states = <&CPU_SLEEP_0>;
37825 };
37826
37827- cpu@2 {
37828+ cpu2: cpu@2 {
37829 compatible = "arm,cortex-a53", "arm,armv8";
37830 device_type = "cpu";
37831 enable-method = "psci";
37832 reg = <0x2>;
37833+ operating-points-v2 = <&cpu_opp_table>;
37834+ cpu-idle-states = <&CPU_SLEEP_0>;
37835 };
37836
37837- cpu@3 {
37838+ cpu3: cpu@3 {
37839 compatible = "arm,cortex-a53", "arm,armv8";
37840 device_type = "cpu";
37841 enable-method = "psci";
37842 reg = <0x3>;
37843+ operating-points-v2 = <&cpu_opp_table>;
37844+ cpu-idle-states = <&CPU_SLEEP_0>;
37845 };
37846+
37847+ idle-states {
37848+ entry-method = "arm,psci";
37849+
37850+ CPU_SLEEP_0: cpu-sleep-0 {
37851+ compatible = "arm,idle-state";
37852+ arm,psci-suspend-param = <0x40000000>;
37853+ local-timer-stop;
37854+ entry-latency-us = <300>;
37855+ exit-latency-us = <600>;
37856+ min-residency-us = <10000>;
37857+ };
37858+ };
37859+ };
37860+
37861+ cpu_opp_table: cpu_opp_table {
37862+ compatible = "operating-points-v2";
37863+ opp-shared;
37864+ opp00 {
37865+ opp-hz = /bits/ 64 <1199999988>;
37866+ opp-microvolt = <1000000>;
37867+ clock-latency-ns = <500000>;
37868+ };
37869+ opp01 {
37870+ opp-hz = /bits/ 64 <599999994>;
37871+ opp-microvolt = <1000000>;
37872+ clock-latency-ns = <500000>;
37873+ };
37874+ opp02 {
37875+ opp-hz = /bits/ 64 <399999996>;
37876+ opp-microvolt = <1000000>;
37877+ clock-latency-ns = <500000>;
37878+ };
37879+ opp03 {
37880+ opp-hz = /bits/ 64 <299999997>;
37881+ opp-microvolt = <1000000>;
37882+ clock-latency-ns = <500000>;
37883+ };
37884+ };
37885+
37886+ dcc: dcc {
37887+ compatible = "arm,dcc";
37888+ status = "disabled";
37889 };
37890
37891 pmu {
37892@@ -119,6 +170,190 @@ can1: can@ff070000 {
37893 rx-fifo-depth = <0x40>;
37894 };
37895
37896+ cci: cci@fd6e0000 {
37897+ compatible = "arm,cci-400";
37898+ reg = <0x0 0xfd6e0000 0x0 0x9000>;
37899+ ranges = <0x0 0x0 0xfd6e0000 0x10000>;
37900+ #address-cells = <1>;
37901+ #size-cells = <1>;
37902+
37903+ pmu@9000 {
37904+ compatible = "arm,cci-400-pmu,r1";
37905+ reg = <0x9000 0x5000>;
37906+ interrupt-parent = <&gic>;
37907+ interrupts = <0 123 4>,
37908+ <0 123 4>,
37909+ <0 123 4>,
37910+ <0 123 4>,
37911+ <0 123 4>;
37912+ };
37913+ };
37914+
37915+ /* GDMA */
37916+ fpd_dma_chan1: dma@fd500000 {
37917+ status = "disabled";
37918+ compatible = "xlnx,zynqmp-dma-1.0";
37919+ reg = <0x0 0xfd500000 0x0 0x1000>;
37920+ interrupt-parent = <&gic>;
37921+ interrupts = <0 124 4>;
37922+ clock-names = "clk_main", "clk_apb";
37923+ xlnx,bus-width = <128>;
37924+ };
37925+
37926+ fpd_dma_chan2: dma@fd510000 {
37927+ status = "disabled";
37928+ compatible = "xlnx,zynqmp-dma-1.0";
37929+ reg = <0x0 0xfd510000 0x0 0x1000>;
37930+ interrupt-parent = <&gic>;
37931+ interrupts = <0 125 4>;
37932+ clock-names = "clk_main", "clk_apb";
37933+ xlnx,bus-width = <128>;
37934+ };
37935+
37936+ fpd_dma_chan3: dma@fd520000 {
37937+ status = "disabled";
37938+ compatible = "xlnx,zynqmp-dma-1.0";
37939+ reg = <0x0 0xfd520000 0x0 0x1000>;
37940+ interrupt-parent = <&gic>;
37941+ interrupts = <0 126 4>;
37942+ clock-names = "clk_main", "clk_apb";
37943+ xlnx,bus-width = <128>;
37944+ };
37945+
37946+ fpd_dma_chan4: dma@fd530000 {
37947+ status = "disabled";
37948+ compatible = "xlnx,zynqmp-dma-1.0";
37949+ reg = <0x0 0xfd530000 0x0 0x1000>;
37950+ interrupt-parent = <&gic>;
37951+ interrupts = <0 127 4>;
37952+ clock-names = "clk_main", "clk_apb";
37953+ xlnx,bus-width = <128>;
37954+ };
37955+
37956+ fpd_dma_chan5: dma@fd540000 {
37957+ status = "disabled";
37958+ compatible = "xlnx,zynqmp-dma-1.0";
37959+ reg = <0x0 0xfd540000 0x0 0x1000>;
37960+ interrupt-parent = <&gic>;
37961+ interrupts = <0 128 4>;
37962+ clock-names = "clk_main", "clk_apb";
37963+ xlnx,bus-width = <128>;
37964+ };
37965+
37966+ fpd_dma_chan6: dma@fd550000 {
37967+ status = "disabled";
37968+ compatible = "xlnx,zynqmp-dma-1.0";
37969+ reg = <0x0 0xfd550000 0x0 0x1000>;
37970+ interrupt-parent = <&gic>;
37971+ interrupts = <0 129 4>;
37972+ clock-names = "clk_main", "clk_apb";
37973+ xlnx,bus-width = <128>;
37974+ };
37975+
37976+ fpd_dma_chan7: dma@fd560000 {
37977+ status = "disabled";
37978+ compatible = "xlnx,zynqmp-dma-1.0";
37979+ reg = <0x0 0xfd560000 0x0 0x1000>;
37980+ interrupt-parent = <&gic>;
37981+ interrupts = <0 130 4>;
37982+ clock-names = "clk_main", "clk_apb";
37983+ xlnx,bus-width = <128>;
37984+ };
37985+
37986+ fpd_dma_chan8: dma@fd570000 {
37987+ status = "disabled";
37988+ compatible = "xlnx,zynqmp-dma-1.0";
37989+ reg = <0x0 0xfd570000 0x0 0x1000>;
37990+ interrupt-parent = <&gic>;
37991+ interrupts = <0 131 4>;
37992+ clock-names = "clk_main", "clk_apb";
37993+ xlnx,bus-width = <128>;
37994+ };
37995+
37996+ /* LPDDMA default allows only secured access. inorder to enable
37997+ * These dma channels, Users should ensure that these dma
37998+ * Channels are allowed for non secure access.
37999+ */
38000+ lpd_dma_chan1: dma@ffa80000 {
38001+ status = "disabled";
38002+ compatible = "xlnx,zynqmp-dma-1.0";
38003+ reg = <0x0 0xffa80000 0x0 0x1000>;
38004+ interrupt-parent = <&gic>;
38005+ interrupts = <0 77 4>;
38006+ clock-names = "clk_main", "clk_apb";
38007+ xlnx,bus-width = <64>;
38008+ };
38009+
38010+ lpd_dma_chan2: dma@ffa90000 {
38011+ status = "disabled";
38012+ compatible = "xlnx,zynqmp-dma-1.0";
38013+ reg = <0x0 0xffa90000 0x0 0x1000>;
38014+ interrupt-parent = <&gic>;
38015+ interrupts = <0 78 4>;
38016+ clock-names = "clk_main", "clk_apb";
38017+ xlnx,bus-width = <64>;
38018+ };
38019+
38020+ lpd_dma_chan3: dma@ffaa0000 {
38021+ status = "disabled";
38022+ compatible = "xlnx,zynqmp-dma-1.0";
38023+ reg = <0x0 0xffaa0000 0x0 0x1000>;
38024+ interrupt-parent = <&gic>;
38025+ interrupts = <0 79 4>;
38026+ clock-names = "clk_main", "clk_apb";
38027+ xlnx,bus-width = <64>;
38028+ };
38029+
38030+ lpd_dma_chan4: dma@ffab0000 {
38031+ status = "disabled";
38032+ compatible = "xlnx,zynqmp-dma-1.0";
38033+ reg = <0x0 0xffab0000 0x0 0x1000>;
38034+ interrupt-parent = <&gic>;
38035+ interrupts = <0 80 4>;
38036+ clock-names = "clk_main", "clk_apb";
38037+ xlnx,bus-width = <64>;
38038+ };
38039+
38040+ lpd_dma_chan5: dma@ffac0000 {
38041+ status = "disabled";
38042+ compatible = "xlnx,zynqmp-dma-1.0";
38043+ reg = <0x0 0xffac0000 0x0 0x1000>;
38044+ interrupt-parent = <&gic>;
38045+ interrupts = <0 81 4>;
38046+ clock-names = "clk_main", "clk_apb";
38047+ xlnx,bus-width = <64>;
38048+ };
38049+
38050+ lpd_dma_chan6: dma@ffad0000 {
38051+ status = "disabled";
38052+ compatible = "xlnx,zynqmp-dma-1.0";
38053+ reg = <0x0 0xffad0000 0x0 0x1000>;
38054+ interrupt-parent = <&gic>;
38055+ interrupts = <0 82 4>;
38056+ clock-names = "clk_main", "clk_apb";
38057+ xlnx,bus-width = <64>;
38058+ };
38059+
38060+ lpd_dma_chan7: dma@ffae0000 {
38061+ status = "disabled";
38062+ compatible = "xlnx,zynqmp-dma-1.0";
38063+ reg = <0x0 0xffae0000 0x0 0x1000>;
38064+ interrupt-parent = <&gic>;
38065+ interrupts = <0 83 4>;
38066+ clock-names = "clk_main", "clk_apb";
38067+ xlnx,bus-width = <64>;
38068+ };
38069+
38070+ lpd_dma_chan8: dma@ffaf0000 {
38071+ status = "disabled";
38072+ compatible = "xlnx,zynqmp-dma-1.0";
38073+ reg = <0x0 0xffaf0000 0x0 0x1000>;
38074+ interrupt-parent = <&gic>;
38075+ interrupts = <0 84 4>;
38076+ clock-names = "clk_main", "clk_apb";
38077+ xlnx,bus-width = <64>;
38078+ };
38079+
38080 gem0: ethernet@ff0b0000 {
38081 compatible = "cdns,gem";
38082 status = "disabled";
38083@@ -215,12 +450,9 @@ pcie: pcie@fd0e0000 {
38084 <0x0 0xfd480000 0x0 0x1000>,
38085 <0x80 0x00000000 0x0 0x1000000>;
38086 reg-names = "breg", "pcireg", "cfg";
38087- ranges = <0x02000000 0x00000000 0xe0000000 0x00000000
38088- 0xe0000000 0x00000000 0x10000000
38089- /* non-prefetchable memory */
38090- 0x43000000 0x00000006 0x00000000 0x00000006
38091- 0x00000000 0x00000002 0x00000000>;
38092- /* prefetchable memory */
38093+ ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
38094+ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
38095+ bus-range = <0x00 0xff>;
38096 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
38097 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
38098 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
38099@@ -233,6 +465,16 @@ pcie_intc: legacy-interrupt-controller {
38100 };
38101 };
38102
38103+ rtc: rtc@ffa60000 {
38104+ compatible = "xlnx,zynqmp-rtc";
38105+ status = "disabled";
38106+ reg = <0x0 0xffa60000 0x0 0x100>;
38107+ interrupt-parent = <&gic>;
38108+ interrupts = <0 26 4>, <0 27 4>;
38109+ interrupt-names = "alarm", "sec";
38110+ calibration = <0x8000>;
38111+ };
38112+
38113 sata: ahci@fd0c0000 {
38114 compatible = "ceva,ahci-1v84";
38115 status = "disabled";
38116@@ -262,13 +504,14 @@ sdhci1: sdhci@ff170000 {
38117 smmu: smmu@fd800000 {
38118 compatible = "arm,mmu-500";
38119 reg = <0x0 0xfd800000 0x0 0x20000>;
38120+ status = "disabled";
38121 #global-interrupts = <1>;
38122 interrupt-parent = <&gic>;
38123- interrupts = <0 157 4>,
38124- <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
38125- <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
38126- <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
38127- <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
38128+ interrupts = <0 155 4>,
38129+ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
38130+ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
38131+ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
38132+ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
38133 };
38134
38135 spi0: spi@ff040000 {
38136@@ -330,7 +573,7 @@ ttc3: timer@ff140000 {
38137 };
38138
38139 uart0: serial@ff000000 {
38140- compatible = "cdns,uart-r1p8";
38141+ compatible = "cdns,uart-r1p12", "xlnx,xuartps";
38142 status = "disabled";
38143 interrupt-parent = <&gic>;
38144 interrupts = <0 21 4>;
38145@@ -339,7 +582,7 @@ uart0: serial@ff000000 {
38146 };
38147
38148 uart1: serial@ff010000 {
38149- compatible = "cdns,uart-r1p8";
38150+ compatible = "cdns,uart-r1p12", "xlnx,xuartps";
38151 status = "disabled";
38152 interrupt-parent = <&gic>;
38153 interrupts = <0 22 4>;
38154diff --git a/arch/arm64/boot/dts/zte/Makefile b/arch/arm64/boot/dts/zte/Makefile
38155index 667806620f59..d86c4def6bc9 100644
38156--- a/arch/arm64/boot/dts/zte/Makefile
38157+++ b/arch/arm64/boot/dts/zte/Makefile
38158@@ -1,4 +1,5 @@
38159 dtb-$(CONFIG_ARCH_ZX) += zx296718-evb.dtb
38160+dtb-$(CONFIG_ARCH_ZX) += zx296718-pcbox.dtb
38161
38162 always := $(dtb-y)
38163 subdir-y := $(dts-dirs)
38164diff --git a/arch/arm64/boot/dts/zte/zx296718-evb.dts b/arch/arm64/boot/dts/zte/zx296718-evb.dts
38165index bb900d2bbcfb..cb2519ecd724 100644
38166--- a/arch/arm64/boot/dts/zte/zx296718-evb.dts
38167+++ b/arch/arm64/boot/dts/zte/zx296718-evb.dts
38168@@ -57,16 +57,28 @@ memory@40000000 {
38169 reg = <0x40000000 0x40000000>;
38170 };
38171
38172- sound0 {
38173- compatible = "simple-audio-card";
38174- simple-audio-card,name = "zx_snd_spdif0";
38175+ sound-spdif0 {
38176+ compatible = "audio-graph-card";
38177+ dais = <&spdif0_port>;
38178+ };
38179
38180- simple-audio-card,cpu {
38181- sound-dai = <&spdif0>;
38182- };
38183+ sound-i2s0 {
38184+ compatible = "audio-graph-card";
38185+ dais = <&i2s0_port>;
38186+ pinctrl-names = "default";
38187+ pinctrl-0 = <&amplifier_pins>;
38188+ pa-gpios = <&bgpio4 0 GPIO_ACTIVE_HIGH>;
38189+ widgets = "Line", "Line Out Jack";
38190+ routing = "Amplifier", "LINEOUTL",
38191+ "Amplifier", "LINEOUTR",
38192+ "Line Out Jack", "Amplifier";
38193+ };
38194+};
38195
38196- simple-audio-card,codec {
38197- sound-dai = <&hdmi>;
38198+&aud96p22 {
38199+ port {
38200+ aud96p22_endpoint: endpoint {
38201+ remote-endpoint = <&i2s0_endpoint>;
38202 };
38203 };
38204 };
38205@@ -77,6 +89,36 @@ &emmc {
38206
38207 &hdmi {
38208 status = "okay";
38209+
38210+ port {
38211+ hdmi_endpoint: endpoint {
38212+ remote-endpoint = <&spdif0_endpoint>;
38213+ };
38214+ };
38215+};
38216+
38217+&i2c0 {
38218+ status = "okay";
38219+};
38220+
38221+&i2s0 {
38222+ status = "okay";
38223+
38224+ i2s0_port: port {
38225+ i2s0_endpoint: endpoint {
38226+ remote-endpoint = <&aud96p22_endpoint>;
38227+ dai-format = "i2s";
38228+ frame-master;
38229+ bitclock-master;
38230+ };
38231+ };
38232+};
38233+
38234+&pmm {
38235+ amplifier_pins: amplifier {
38236+ pins = "TSI3_DATA";
38237+ function = "BGPIO";
38238+ };
38239 };
38240
38241 &sd1 {
38242@@ -85,6 +127,16 @@ &sd1 {
38243
38244 &spdif0 {
38245 status = "okay";
38246+
38247+ spdif0_port: port {
38248+ spdif0_endpoint: endpoint {
38249+ remote-endpoint = <&hdmi_endpoint>;
38250+ };
38251+ };
38252+};
38253+
38254+&tvenc {
38255+ status = "okay";
38256 };
38257
38258 &uart0 {
38259diff --git a/arch/arm64/boot/dts/zte/zx296718-pcbox.dts b/arch/arm64/boot/dts/zte/zx296718-pcbox.dts
38260new file mode 100644
38261index 000000000000..e02509f7082b
38262--- /dev/null
38263+++ b/arch/arm64/boot/dts/zte/zx296718-pcbox.dts
38264@@ -0,0 +1,143 @@
38265+/*
38266+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
38267+ * Copyright 2017 Linaro Ltd.
38268+ *
38269+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
38270+ */
38271+
38272+/dts-v1/;
38273+#include "zx296718.dtsi"
38274+#include <dt-bindings/pwm/pwm.h>
38275+
38276+/ {
38277+ model = "ZTE ZX296718 PCBOX Board";
38278+ compatible = "zte,zx296718-pcbox", "zte,zx296718";
38279+
38280+ chosen {
38281+ stdout-path = "serial0:115200n8";
38282+ };
38283+
38284+ memory@80000000 {
38285+ device_type = "memory";
38286+ reg = <0x80000000 0x80000000>;
38287+ };
38288+
38289+ a53_vdd0v9: regulator-a53 {
38290+ compatible = "pwm-regulator";
38291+ pwms = <&pwm 3 1250 PWM_POLARITY_INVERTED>;
38292+ regulator-name = "A53_VDD0V9";
38293+ regulator-min-microvolt = <855000>;
38294+ regulator-max-microvolt = <1183000>;
38295+ pwm-dutycycle-unit = <100>;
38296+ pwm-dutycycle-range = <0 100>;
38297+ regulator-always-on;
38298+ regulator-boot-on;
38299+ };
38300+
38301+ sound-spdif0 {
38302+ compatible = "audio-graph-card";
38303+ dais = <&spdif0_port>;
38304+ };
38305+
38306+ sound-i2s0 {
38307+ compatible = "audio-graph-card";
38308+ dais = <&i2s0_port>;
38309+ };
38310+};
38311+
38312+&aud96p22 {
38313+ port {
38314+ aud96p22_endpoint: endpoint {
38315+ remote-endpoint = <&i2s0_endpoint>;
38316+ };
38317+ };
38318+};
38319+
38320+&cpu0 {
38321+ cpu-supply = <&a53_vdd0v9>;
38322+};
38323+
38324+&emmc {
38325+ status = "okay";
38326+};
38327+
38328+&hdmi {
38329+ status = "disabled";
38330+
38331+ port {
38332+ hdmi_endpoint: endpoint {
38333+ remote-endpoint = <&spdif0_endpoint>;
38334+ };
38335+ };
38336+};
38337+
38338+&i2c0 {
38339+ status = "okay";
38340+};
38341+
38342+&i2s0 {
38343+ status = "okay";
38344+
38345+ i2s0_port: port {
38346+ i2s0_endpoint: endpoint {
38347+ remote-endpoint = <&aud96p22_endpoint>;
38348+ dai-format = "i2s";
38349+ frame-master;
38350+ bitclock-master;
38351+ };
38352+ };
38353+};
38354+
38355+&irdec {
38356+ status = "okay";
38357+};
38358+
38359+&pmm {
38360+ pwm3_pins: pwm3 {
38361+ pins = "KEY_ROW2";
38362+ function = "PWM";
38363+ };
38364+
38365+ vga_pins: vga {
38366+ pins = "KEY_COL1", "KEY_COL2", "VGA_HS", "VGA_VS";
38367+ function = "VGA";
38368+ };
38369+};
38370+
38371+&pwm {
38372+ pinctrl-names = "default";
38373+ pinctrl-0 = <&pwm3_pins>;
38374+ status = "okay";
38375+};
38376+
38377+&sd0 {
38378+ status = "okay";
38379+};
38380+
38381+&sd1 {
38382+ status = "okay";
38383+};
38384+
38385+&spdif0 {
38386+ status = "okay";
38387+
38388+ spdif0_port: port {
38389+ spdif0_endpoint: endpoint {
38390+ remote-endpoint = <&hdmi_endpoint>;
38391+ };
38392+ };
38393+};
38394+
38395+&tvenc {
38396+ status = "disabled";
38397+};
38398+
38399+&uart0 {
38400+ status = "okay";
38401+};
38402+
38403+&vga {
38404+ pinctrl-names = "default";
38405+ pinctrl-0 = <&vga_pins>;
38406+ status = "okay";
38407+};
38408diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
38409index d83bf789c864..6eef64761009 100644
38410--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
38411+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
38412@@ -53,6 +53,13 @@ / {
38413 interrupt-parent = <&gic>;
38414
38415 aliases {
38416+ gpio0 = &bgpio0;
38417+ gpio1 = &bgpio1;
38418+ gpio2 = &bgpio2;
38419+ gpio3 = &bgpio3;
38420+ gpio4 = &bgpio4;
38421+ gpio5 = &bgpio5;
38422+ gpio6 = &bgpio6;
38423 serial0 = &uart0;
38424 };
38425
38426@@ -120,26 +127,31 @@ cluster0_opp: opp-table0 {
38427
38428 opp-500000000 {
38429 opp-hz = /bits/ 64 <500000000>;
38430+ opp-microvolt = <866000>;
38431 clock-latency-ns = <500000>;
38432 };
38433
38434 opp-648000000 {
38435 opp-hz = /bits/ 64 <648000000>;
38436+ opp-microvolt = <866000>;
38437 clock-latency-ns = <500000>;
38438 };
38439
38440 opp-800000000 {
38441 opp-hz = /bits/ 64 <800000000>;
38442+ opp-microvolt = <888000>;
38443 clock-latency-ns = <500000>;
38444 };
38445
38446 opp-1000000000 {
38447 opp-hz = /bits/ 64 <1000000000>;
38448+ opp-microvolt = <898000>;
38449 clock-latency-ns = <500000>;
38450 };
38451
38452 opp-1188000000 {
38453 opp-hz = /bits/ 64 <1188000000>;
38454+ opp-microvolt = <1015000>;
38455 clock-latency-ns = <500000>;
38456 };
38457 };
38458@@ -283,11 +295,23 @@ soc {
38459 compatible = "simple-bus";
38460 ranges;
38461
38462+ irdec: ir-decoder@111000 {
38463+ compatible = "zte,zx296718-irdec";
38464+ reg = <0x111000 0x1000>;
38465+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
38466+ status = "disabled";
38467+ };
38468+
38469 aon_sysctrl: aon-sysctrl@116000 {
38470 compatible = "zte,zx296718-aon-sysctrl", "syscon";
38471 reg = <0x116000 0x1000>;
38472 };
38473
38474+ iocfg: pin-controller@119000 {
38475+ compatible = "zte,zx296718-iocfg";
38476+ reg = <0x119000 0x1000>;
38477+ };
38478+
38479 uart0: uart@11f000 {
38480 compatible = "arm,pl011", "arm,primecell";
38481 arm,primecell-periphid = <0x001feffe>;
38482@@ -311,7 +335,6 @@ sd0: mmc@1110000 {
38483 clock-frequency = <50000000>;
38484 clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
38485 clock-names = "biu", "ciu";
38486- num-slots = <1>;
38487 max-frequency = <50000000>;
38488 cap-sdio-irq;
38489 cap-sd-highspeed;
38490@@ -336,7 +359,6 @@ sd1: mmc@1111000 {
38491 clock-frequency = <167000000>;
38492 clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>;
38493 clock-names = "biu", "ciu";
38494- num-slots = <1>;
38495 max-frequency = <167000000>;
38496 cap-sdio-irq;
38497 cap-sd-highspeed;
38498@@ -360,12 +382,109 @@ lsp0crm: clock-controller@1420000 {
38499 #clock-cells = <1>;
38500 };
38501
38502+ bgpio0: gpio@142d000 {
38503+ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
38504+ reg = <0x142d000 0x40>;
38505+ gpio-controller;
38506+ #gpio-cells = <2>;
38507+ gpio-ranges = <&pmm 0 48 16>;
38508+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
38509+ interrupt-parent = <&gic>;
38510+ interrupt-controller;
38511+ #interrupt-cells = <2>;
38512+ };
38513+
38514+ bgpio1: gpio@142d040 {
38515+ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
38516+ reg = <0x142d040 0x40>;
38517+ gpio-controller;
38518+ #gpio-cells = <2>;
38519+ gpio-ranges = <&pmm 0 80 16>;
38520+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
38521+ interrupt-parent = <&gic>;
38522+ interrupt-controller;
38523+ #interrupt-cells = <2>;
38524+ };
38525+
38526+ bgpio2: gpio@142d080 {
38527+ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
38528+ reg = <0x142d080 0x40>;
38529+ gpio-controller;
38530+ #gpio-cells = <2>;
38531+ gpio-ranges = <&pmm 0 80 3
38532+ &pmm 3 32 4
38533+ &pmm 7 83 9>;
38534+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
38535+ interrupt-parent = <&gic>;
38536+ interrupt-controller;
38537+ #interrupt-cells = <2>;
38538+ };
38539+
38540+ bgpio3: gpio@142d0c0 {
38541+ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
38542+ reg = <0x142d0c0 0x40>;
38543+ gpio-controller;
38544+ #gpio-cells = <2>;
38545+ gpio-ranges = <&pmm 0 92 16>;
38546+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
38547+ interrupt-parent = <&gic>;
38548+ interrupt-controller;
38549+ #interrupt-cells = <2>;
38550+ };
38551+
38552+ bgpio4: gpio@142d100 {
38553+ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
38554+ reg = <0x142d100 0x40>;
38555+ gpio-controller;
38556+ #gpio-cells = <2>;
38557+ gpio-ranges = <&pmm 0 108 12
38558+ &pmm 12 121 4>;
38559+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
38560+ interrupt-parent = <&gic>;
38561+ interrupt-controller;
38562+ #interrupt-cells = <2>;
38563+ };
38564+
38565+ bgpio5: gpio@142d140 {
38566+ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
38567+ reg = <0x142d140 0x40>;
38568+ gpio-controller;
38569+ #gpio-cells = <2>;
38570+ gpio-ranges = <&pmm 0 125 16>;
38571+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
38572+ interrupt-parent = <&gic>;
38573+ interrupt-controller;
38574+ #interrupt-cells = <2>;
38575+ };
38576+
38577+ bgpio6: gpio@142d180 {
38578+ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
38579+ reg = <0x142d180 0x40>;
38580+ gpio-controller;
38581+ #gpio-cells = <2>;
38582+ gpio-ranges = <&pmm 0 141 2>;
38583+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
38584+ interrupt-parent = <&gic>;
38585+ interrupt-controller;
38586+ #interrupt-cells = <2>;
38587+ };
38588+
38589 lsp1crm: clock-controller@1430000 {
38590 compatible = "zte,zx296718-lsp1crm";
38591 reg = <0x01430000 0x1000>;
38592 #clock-cells = <1>;
38593 };
38594
38595+ pwm: pwm@1439000 {
38596+ compatible = "zte,zx296718-pwm";
38597+ reg = <0x1439000 0x1000>;
38598+ clocks = <&lsp1crm LSP1_PWM_PCLK>,
38599+ <&lsp1crm LSP1_PWM_WCLK>;
38600+ clock-names = "pclk", "wclk";
38601+ #pwm-cells = <3>;
38602+ status = "disabled";
38603+ };
38604+
38605 vou: vou@1440000 {
38606 compatible = "zte,zx296718-vou";
38607 #address-cells = <1>;
38608@@ -387,6 +506,16 @@ dpc: dpc@0 {
38609 "main_wclk", "aux_wclk";
38610 };
38611
38612+ vga: vga@8000 {
38613+ compatible = "zte,zx296718-vga";
38614+ reg = <0x8000 0x1000>;
38615+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
38616+ clocks = <&topcrm VGA_I2C_WCLK>;
38617+ clock-names = "i2c_wclk";
38618+ zte,vga-power-control = <&sysctrl 0x170 0xe0>;
38619+ status = "disabled";
38620+ };
38621+
38622 hdmi: hdmi@c000 {
38623 compatible = "zte,zx296718-hdmi";
38624 reg = <0xc000 0x4000>;
38625@@ -413,6 +542,12 @@ topcrm: clock-controller@1461000 {
38626 #clock-cells = <1>;
38627 };
38628
38629+ pmm: pin-controller@1462000 {
38630+ compatible = "zte,zx296718-pmm";
38631+ reg = <0x1462000 0x1000>;
38632+ zte,auxiliary-controller = <&iocfg>;
38633+ };
38634+
38635 sysctrl: sysctrl@1463000 {
38636 compatible = "zte,zx296718-sysctrl", "syscon";
38637 reg = <0x1463000 0x1000>;
38638@@ -445,6 +580,38 @@ audiocrm: clock-controller@1480000 {
38639 #clock-cells = <1>;
38640 };
38641
38642+ i2s0: i2s@1482000 {
38643+ compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
38644+ reg = <0x01482000 0x1000>;
38645+ clocks = <&audiocrm AUDIO_I2S0_WCLK>,
38646+ <&audiocrm AUDIO_I2S0_PCLK>;
38647+ clock-names = "wclk", "pclk";
38648+ assigned-clocks = <&audiocrm I2S0_WCLK_MUX>;
38649+ assigned-clock-parents = <&topcrm AUDIO_99M>;
38650+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
38651+ dmas = <&dma 22>, <&dma 23>;
38652+ dma-names = "tx", "rx";
38653+ #sound-dai-cells = <0>;
38654+ status = "disabled";
38655+ };
38656+
38657+ i2c0: i2c@1486000 {
38658+ compatible = "zte,zx296718-i2c";
38659+ reg = <0x01486000 0x1000>;
38660+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
38661+ #address-cells = <1>;
38662+ #size-cells = <0>;
38663+ clocks = <&audiocrm AUDIO_I2C0_WCLK>;
38664+ clock-frequency = <1600000>;
38665+ status = "disabled";
38666+
38667+ aud96p22: codec@22 {
38668+ compatible = "zte,zx-aud96p22";
38669+ #sound-dai-cells = <0>;
38670+ reg = <0x22>;
38671+ };
38672+ };
38673+
38674 spdif0: spdif@1488000 {
38675 compatible = "zte,zx296702-spdif";
38676 reg = <0x1488000 0x1000>;
38677diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
38678index a7ea5f3da89d..964489b39f6a 100644
38679--- a/drivers/clk/meson/gxbb.c
38680+++ b/drivers/clk/meson/gxbb.c
38681@@ -1188,6 +1188,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
38682 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
38683 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
38684 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
38685+ [NR_CLKS] = NULL,
38686 },
38687 .num = NR_CLKS,
38688 };
38689@@ -1310,6 +1311,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
38690 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
38691 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
38692 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
38693+ [NR_CLKS] = NULL,
38694 },
38695 .num = NR_CLKS,
38696 };
38697diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
38698index d63e77e8433d..5b1d4b374d1c 100644
38699--- a/drivers/clk/meson/gxbb.h
38700+++ b/drivers/clk/meson/gxbb.h
38701@@ -167,130 +167,33 @@
38702 * CLKID index values
38703 *
38704 * These indices are entirely contrived and do not map onto the hardware.
38705- * Migrate them out of this header and into the DT header file when they need
38706- * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h
38707+ * It has now been decided to expose everything by default in the DT header:
38708+ * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
38709+ * to expose, such as the internal muxes and dividers of composite clocks,
38710+ * will remain defined here.
38711 */
38712-#define CLKID_SYS_PLL 0
38713 /* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
38714-/* CLKID_HDMI_PLL */
38715-#define CLKID_FIXED_PLL 3
38716-/* CLKID_FCLK_DIV2 */
38717-/* CLKID_FCLK_DIV3 */
38718-/* CLKID_FCLK_DIV4 */
38719-#define CLKID_FCLK_DIV5 7
38720-#define CLKID_FCLK_DIV7 8
38721-/* CLKID_GP0_PLL */
38722 #define CLKID_MPEG_SEL 10
38723 #define CLKID_MPEG_DIV 11
38724-/* CLKID_CLK81 */
38725-#define CLKID_MPLL0 13
38726-#define CLKID_MPLL1 14
38727-/* CLKID_MPLL2 */
38728-#define CLKID_DDR 16
38729-#define CLKID_DOS 17
38730-#define CLKID_ISA 18
38731-#define CLKID_PL301 19
38732-#define CLKID_PERIPHS 20
38733-/* CLKID_SPICC */
38734-/* CLKID_I2C */
38735-/* #define CLKID_SAR_ADC */
38736-#define CLKID_SMART_CARD 24
38737-/* CLKID_RNG0 */
38738-/* CLKID_UART0 */
38739-#define CLKID_SDHC 27
38740-#define CLKID_STREAM 28
38741-#define CLKID_ASYNC_FIFO 29
38742-#define CLKID_SDIO 30
38743-#define CLKID_ABUF 31
38744-#define CLKID_HIU_IFACE 32
38745-#define CLKID_ASSIST_MISC 33
38746-/* CLKID_SPI */
38747-#define CLKID_I2S_SPDIF 35
38748-/* CLKID_ETH */
38749-#define CLKID_DEMUX 37
38750-/* CLKID_AIU_GLUE */
38751-/* CLKID_IEC958 */
38752-/* CLKID_I2S_OUT */
38753-#define CLKID_AMCLK 41
38754-#define CLKID_AIFIFO2 42
38755-#define CLKID_MIXER 43
38756-/* CLKID_MIXER_IFACE */
38757-#define CLKID_ADC 45
38758-#define CLKID_BLKMV 46
38759-/* CLKID_AIU */
38760-/* CLKID_UART1 */
38761-#define CLKID_G2D 49
38762-/* CLKID_USB0 */
38763-/* CLKID_USB1 */
38764-#define CLKID_RESET 52
38765-#define CLKID_NAND 53
38766-#define CLKID_DOS_PARSER 54
38767-/* CLKID_USB */
38768-#define CLKID_VDIN1 56
38769-#define CLKID_AHB_ARB0 57
38770-#define CLKID_EFUSE 58
38771-#define CLKID_BOOT_ROM 59
38772-#define CLKID_AHB_DATA_BUS 60
38773-#define CLKID_AHB_CTRL_BUS 61
38774-#define CLKID_HDMI_INTR_SYNC 62
38775-/* CLKID_HDMI_PCLK */
38776-/* CLKID_USB1_DDR_BRIDGE */
38777-/* CLKID_USB0_DDR_BRIDGE */
38778-#define CLKID_MMC_PCLK 66
38779-#define CLKID_DVIN 67
38780-/* CLKID_UART2 */
38781-/* #define CLKID_SANA */
38782-#define CLKID_VPU_INTR 70
38783-#define CLKID_SEC_AHB_AHB3_BRIDGE 71
38784-#define CLKID_CLK81_A53 72
38785-#define CLKID_VCLK2_VENCI0 73
38786-#define CLKID_VCLK2_VENCI1 74
38787-#define CLKID_VCLK2_VENCP0 75
38788-#define CLKID_VCLK2_VENCP1 76
38789-/* CLKID_GCLK_VENCI_INT0 */
38790-#define CLKID_GCLK_VENCI_INT 78
38791-#define CLKID_DAC_CLK 79
38792-/* CLKID_AOCLK_GATE */
38793-/* CLKID_IEC958_GATE */
38794-#define CLKID_ENC480P 82
38795-#define CLKID_RNG1 83
38796-#define CLKID_GCLK_VENCI_INT1 84
38797-#define CLKID_VCLK2_VENCLMCC 85
38798-#define CLKID_VCLK2_VENCL 86
38799-#define CLKID_VCLK_OTHER 87
38800-#define CLKID_EDP 88
38801-#define CLKID_AO_MEDIA_CPU 89
38802-#define CLKID_AO_AHB_SRAM 90
38803-#define CLKID_AO_AHB_BUS 91
38804-#define CLKID_AO_IFACE 92
38805-/* CLKID_AO_I2C */
38806-/* CLKID_SD_EMMC_A */
38807-/* CLKID_SD_EMMC_B */
38808-/* CLKID_SD_EMMC_C */
38809-/* CLKID_SAR_ADC_CLK */
38810-/* CLKID_SAR_ADC_SEL */
38811 #define CLKID_SAR_ADC_DIV 99
38812-/* CLKID_MALI_0_SEL */
38813-#define CLKID_MALI_0_DIV 101
38814-/* CLKID_MALI_0 */
38815-/* CLKID_MALI_1_SEL */
38816-#define CLKID_MALI_1_DIV 104
38817-/* CLKID_MALI_1 */
38818-/* CLKID_MALI */
38819-/* CLKID_CTS_AMCLK */
38820+#define CLKID_MALI_0_DIV 101
38821+#define CLKID_MALI_1_DIV 104
38822 #define CLKID_CTS_AMCLK_SEL 108
38823 #define CLKID_CTS_AMCLK_DIV 109
38824-/* CLKID_CTS_MCLK_I958 */
38825 #define CLKID_CTS_MCLK_I958_SEL 111
38826 #define CLKID_CTS_MCLK_I958_DIV 112
38827-/* CLKID_CTS_I958 */
38828-#define CLKID_32K_CLK 114
38829 #define CLKID_32K_CLK_SEL 115
38830 #define CLKID_32K_CLK_DIV 116
38831+#define CLKID_SD_EMMC_A_CLK0_SEL 117
38832+#define CLKID_SD_EMMC_A_CLK0_DIV 118
38833+#define CLKID_SD_EMMC_B_CLK0_SEL 120
38834+#define CLKID_SD_EMMC_B_CLK0_DIV 121
38835+#define CLKID_SD_EMMC_C_CLK0_SEL 123
38836+#define CLKID_SD_EMMC_C_CLK0_DIV 124
38837
38838-#define NR_CLKS 117
38839+#define NR_CLKS 126
38840
38841-/* include the CLKIDs that have been made part of the stable DT binding */
38842+/* include the CLKIDs that have been made part of the DT binding */
38843 #include <dt-bindings/clock/gxbb-clkc.h>
38844
38845 #endif /* __GXBB_H */
38846diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
38847index 6ec512ad2598..cb60a516ca82 100644
38848--- a/drivers/clk/meson/meson8b.c
38849+++ b/drivers/clk/meson/meson8b.c
38850@@ -590,6 +590,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
38851 [CLKID_MPLL0] = &meson8b_mpll0.hw,
38852 [CLKID_MPLL1] = &meson8b_mpll1.hw,
38853 [CLKID_MPLL2] = &meson8b_mpll2.hw,
38854+ [CLK_NR_CLKS] = NULL,
38855 },
38856 .num = CLK_NR_CLKS,
38857 };
38858diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
38859index a687e02547dc..c139bb3273ca 100644
38860--- a/drivers/clk/meson/meson8b.h
38861+++ b/drivers/clk/meson/meson8b.h
38862@@ -60,107 +60,12 @@
38863 * CLKID index values
38864 *
38865 * These indices are entirely contrived and do not map onto the hardware.
38866- * Migrate them out of this header and into the DT header file when they need
38867- * to be exposed to client nodes in DT: include/dt-bindings/clock/meson8b-clkc.h
38868+ * It has now been decided to expose everything by default in the DT header:
38869+ * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
38870+ * to expose, such as the internal muxes and dividers of composite clocks,
38871+ * will remain defined here.
38872 */
38873
38874-/* CLKID_UNUSED */
38875-/* CLKID_XTAL */
38876-/* CLKID_PLL_FIXED */
38877-/* CLKID_PLL_VID */
38878-/* CLKID_PLL_SYS */
38879-/* CLKID_FCLK_DIV2 */
38880-/* CLKID_FCLK_DIV3 */
38881-/* CLKID_FCLK_DIV4 */
38882-/* CLKID_FCLK_DIV5 */
38883-/* CLKID_FCLK_DIV7 */
38884-/* CLKID_CLK81 */
38885-/* CLKID_MALI */
38886-/* CLKID_CPUCLK */
38887-/* CLKID_ZERO */
38888-/* CLKID_MPEG_SEL */
38889-/* CLKID_MPEG_DIV */
38890-#define CLKID_DDR 16
38891-#define CLKID_DOS 17
38892-#define CLKID_ISA 18
38893-#define CLKID_PL301 19
38894-#define CLKID_PERIPHS 20
38895-#define CLKID_SPICC 21
38896-#define CLKID_I2C 22
38897-/* #define CLKID_SAR_ADC */
38898-#define CLKID_SMART_CARD 24
38899-/* #define CLKID_RNG0 */
38900-#define CLKID_UART0 26
38901-#define CLKID_SDHC 27
38902-#define CLKID_STREAM 28
38903-#define CLKID_ASYNC_FIFO 29
38904-/* #define CLKID_SDIO */
38905-#define CLKID_ABUF 31
38906-#define CLKID_HIU_IFACE 32
38907-#define CLKID_ASSIST_MISC 33
38908-#define CLKID_SPI 34
38909-#define CLKID_I2S_SPDIF 35
38910-/* #define CLKID_ETH */
38911-#define CLKID_DEMUX 37
38912-#define CLKID_AIU_GLUE 38
38913-#define CLKID_IEC958 39
38914-#define CLKID_I2S_OUT 40
38915-#define CLKID_AMCLK 41
38916-#define CLKID_AIFIFO2 42
38917-#define CLKID_MIXER 43
38918-#define CLKID_MIXER_IFACE 44
38919-#define CLKID_ADC 45
38920-#define CLKID_BLKMV 46
38921-#define CLKID_AIU 47
38922-#define CLKID_UART1 48
38923-#define CLKID_G2D 49
38924-/* #define CLKID_USB0 */
38925-/* #define CLKID_USB1 */
38926-#define CLKID_RESET 52
38927-#define CLKID_NAND 53
38928-#define CLKID_DOS_PARSER 54
38929-/* #define CLKID_USB */
38930-#define CLKID_VDIN1 56
38931-#define CLKID_AHB_ARB0 57
38932-#define CLKID_EFUSE 58
38933-#define CLKID_BOOT_ROM 59
38934-#define CLKID_AHB_DATA_BUS 60
38935-#define CLKID_AHB_CTRL_BUS 61
38936-#define CLKID_HDMI_INTR_SYNC 62
38937-#define CLKID_HDMI_PCLK 63
38938-/* CLKID_USB1_DDR_BRIDGE */
38939-/* CLKID_USB0_DDR_BRIDGE */
38940-#define CLKID_MMC_PCLK 66
38941-#define CLKID_DVIN 67
38942-#define CLKID_UART2 68
38943-/* #define CLKID_SANA */
38944-#define CLKID_VPU_INTR 70
38945-#define CLKID_SEC_AHB_AHB3_BRIDGE 71
38946-#define CLKID_CLK81_A9 72
38947-#define CLKID_VCLK2_VENCI0 73
38948-#define CLKID_VCLK2_VENCI1 74
38949-#define CLKID_VCLK2_VENCP0 75
38950-#define CLKID_VCLK2_VENCP1 76
38951-#define CLKID_GCLK_VENCI_INT 77
38952-#define CLKID_GCLK_VENCP_INT 78
38953-#define CLKID_DAC_CLK 79
38954-#define CLKID_AOCLK_GATE 80
38955-#define CLKID_IEC958_GATE 81
38956-#define CLKID_ENC480P 82
38957-#define CLKID_RNG1 83
38958-#define CLKID_GCLK_VENCL_INT 84
38959-#define CLKID_VCLK2_VENCLMCC 85
38960-#define CLKID_VCLK2_VENCL 86
38961-#define CLKID_VCLK2_OTHER 87
38962-#define CLKID_EDP 88
38963-#define CLKID_AO_MEDIA_CPU 89
38964-#define CLKID_AO_AHB_SRAM 90
38965-#define CLKID_AO_AHB_BUS 91
38966-#define CLKID_AO_IFACE 92
38967-#define CLKID_MPLL0 93
38968-#define CLKID_MPLL1 94
38969-#define CLKID_MPLL2 95
38970-
38971 #define CLK_NR_CLKS 96
38972
38973 /* include the CLKIDs that have been made part of the stable DT binding */
38974diff --git a/include/dt-bindings/clock/gxbb-aoclkc.h b/include/dt-bindings/clock/gxbb-aoclkc.h
38975index 31751482d13c..9d15e2221fdb 100644
38976--- a/include/dt-bindings/clock/gxbb-aoclkc.h
38977+++ b/include/dt-bindings/clock/gxbb-aoclkc.h
38978@@ -62,5 +62,6 @@
38979 #define CLKID_AO_UART1 3
38980 #define CLKID_AO_UART2 4
38981 #define CLKID_AO_IR_BLASTER 5
38982+#define CLKID_AO_CEC_32K 6
38983
38984 #endif
38985diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
38986index e3e9f7919c31..c04a76d8facf 100644
38987--- a/include/dt-bindings/clock/gxbb-clkc.h
38988+++ b/include/dt-bindings/clock/gxbb-clkc.h
38989@@ -5,37 +5,96 @@
38990 #ifndef __GXBB_CLKC_H
38991 #define __GXBB_CLKC_H
38992
38993+#define CLKID_SYS_PLL 0
38994 #define CLKID_HDMI_PLL 2
38995+#define CLKID_FIXED_PLL 3
38996 #define CLKID_FCLK_DIV2 4
38997 #define CLKID_FCLK_DIV3 5
38998 #define CLKID_FCLK_DIV4 6
38999+#define CLKID_FCLK_DIV5 7
39000+#define CLKID_FCLK_DIV7 8
39001 #define CLKID_GP0_PLL 9
39002 #define CLKID_CLK81 12
39003+#define CLKID_MPLL0 13
39004+#define CLKID_MPLL1 14
39005 #define CLKID_MPLL2 15
39006+#define CLKID_DDR 16
39007+#define CLKID_DOS 17
39008+#define CLKID_ISA 18
39009+#define CLKID_PL301 19
39010+#define CLKID_PERIPHS 20
39011 #define CLKID_SPICC 21
39012 #define CLKID_I2C 22
39013 #define CLKID_SAR_ADC 23
39014+#define CLKID_SMART_CARD 24
39015 #define CLKID_RNG0 25
39016 #define CLKID_UART0 26
39017+#define CLKID_SDHC 27
39018+#define CLKID_STREAM 28
39019+#define CLKID_ASYNC_FIFO 29
39020+#define CLKID_SDIO 30
39021+#define CLKID_ABUF 31
39022+#define CLKID_HIU_IFACE 32
39023+#define CLKID_ASSIST_MISC 33
39024 #define CLKID_SPI 34
39025 #define CLKID_ETH 36
39026+#define CLKID_I2S_SPDIF 35
39027+#define CLKID_DEMUX 37
39028 #define CLKID_AIU_GLUE 38
39029 #define CLKID_IEC958 39
39030 #define CLKID_I2S_OUT 40
39031+#define CLKID_AMCLK 41
39032+#define CLKID_AIFIFO2 42
39033+#define CLKID_MIXER 43
39034 #define CLKID_MIXER_IFACE 44
39035+#define CLKID_ADC 45
39036+#define CLKID_BLKMV 46
39037 #define CLKID_AIU 47
39038 #define CLKID_UART1 48
39039+#define CLKID_G2D 49
39040 #define CLKID_USB0 50
39041 #define CLKID_USB1 51
39042+#define CLKID_RESET 52
39043+#define CLKID_NAND 53
39044+#define CLKID_DOS_PARSER 54
39045 #define CLKID_USB 55
39046+#define CLKID_VDIN1 56
39047+#define CLKID_AHB_ARB0 57
39048+#define CLKID_EFUSE 58
39049+#define CLKID_BOOT_ROM 59
39050+#define CLKID_AHB_DATA_BUS 60
39051+#define CLKID_AHB_CTRL_BUS 61
39052+#define CLKID_HDMI_INTR_SYNC 62
39053 #define CLKID_HDMI_PCLK 63
39054 #define CLKID_USB1_DDR_BRIDGE 64
39055 #define CLKID_USB0_DDR_BRIDGE 65
39056+#define CLKID_MMC_PCLK 66
39057+#define CLKID_DVIN 67
39058 #define CLKID_UART2 68
39059 #define CLKID_SANA 69
39060+#define CLKID_VPU_INTR 70
39061+#define CLKID_SEC_AHB_AHB3_BRIDGE 71
39062+#define CLKID_CLK81_A53 72
39063+#define CLKID_VCLK2_VENCI0 73
39064+#define CLKID_VCLK2_VENCI1 74
39065+#define CLKID_VCLK2_VENCP0 75
39066+#define CLKID_VCLK2_VENCP1 76
39067 #define CLKID_GCLK_VENCI_INT0 77
39068+#define CLKID_GCLK_VENCI_INT 78
39069+#define CLKID_DAC_CLK 79
39070 #define CLKID_AOCLK_GATE 80
39071 #define CLKID_IEC958_GATE 81
39072+#define CLKID_ENC480P 82
39073+#define CLKID_RNG1 83
39074+#define CLKID_GCLK_VENCI_INT1 84
39075+#define CLKID_VCLK2_VENCLMCC 85
39076+#define CLKID_VCLK2_VENCL 86
39077+#define CLKID_VCLK_OTHER 87
39078+#define CLKID_EDP 88
39079+#define CLKID_AO_MEDIA_CPU 89
39080+#define CLKID_AO_AHB_SRAM 90
39081+#define CLKID_AO_AHB_BUS 91
39082+#define CLKID_AO_IFACE 92
39083 #define CLKID_AO_I2C 93
39084 #define CLKID_SD_EMMC_A 94
39085 #define CLKID_SD_EMMC_B 95
39086@@ -50,5 +109,9 @@
39087 #define CLKID_CTS_AMCLK 107
39088 #define CLKID_CTS_MCLK_I958 110
39089 #define CLKID_CTS_I958 113
39090+#define CLKID_32K_CLK 114
39091+#define CLKID_SD_EMMC_A_CLK0 119
39092+#define CLKID_SD_EMMC_B_CLK0 122
39093+#define CLKID_SD_EMMC_C_CLK0 125
39094
39095 #endif /* __GXBB_CLKC_H */
39096diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
39097index e29227fb52a1..a9c0306330b6 100644
39098--- a/include/dt-bindings/clock/meson8b-clkc.h
39099+++ b/include/dt-bindings/clock/meson8b-clkc.h
39100@@ -21,15 +21,85 @@
39101 #define CLKID_ZERO 13
39102 #define CLKID_MPEG_SEL 14
39103 #define CLKID_MPEG_DIV 15
39104+#define CLKID_DDR 16
39105+#define CLKID_DOS 17
39106+#define CLKID_ISA 18
39107+#define CLKID_PL301 19
39108+#define CLKID_PERIPHS 20
39109+#define CLKID_SPICC 21
39110+#define CLKID_I2C 22
39111 #define CLKID_SAR_ADC 23
39112+#define CLKID_SMART_CARD 24
39113 #define CLKID_RNG0 25
39114+#define CLKID_UART0 26
39115+#define CLKID_SDHC 27
39116+#define CLKID_STREAM 28
39117+#define CLKID_ASYNC_FIFO 29
39118 #define CLKID_SDIO 30
39119+#define CLKID_ABUF 31
39120+#define CLKID_HIU_IFACE 32
39121+#define CLKID_ASSIST_MISC 33
39122+#define CLKID_SPI 34
39123+#define CLKID_I2S_SPDIF 35
39124 #define CLKID_ETH 36
39125+#define CLKID_DEMUX 37
39126+#define CLKID_AIU_GLUE 38
39127+#define CLKID_IEC958 39
39128+#define CLKID_I2S_OUT 40
39129+#define CLKID_AMCLK 41
39130+#define CLKID_AIFIFO2 42
39131+#define CLKID_MIXER 43
39132+#define CLKID_MIXER_IFACE 44
39133+#define CLKID_ADC 45
39134+#define CLKID_BLKMV 46
39135+#define CLKID_AIU 47
39136+#define CLKID_UART1 48
39137+#define CLKID_G2D 49
39138 #define CLKID_USB0 50
39139 #define CLKID_USB1 51
39140+#define CLKID_RESET 52
39141+#define CLKID_NAND 53
39142+#define CLKID_DOS_PARSER 54
39143 #define CLKID_USB 55
39144+#define CLKID_VDIN1 56
39145+#define CLKID_AHB_ARB0 57
39146+#define CLKID_EFUSE 58
39147+#define CLKID_BOOT_ROM 59
39148+#define CLKID_AHB_DATA_BUS 60
39149+#define CLKID_AHB_CTRL_BUS 61
39150+#define CLKID_HDMI_INTR_SYNC 62
39151+#define CLKID_HDMI_PCLK 63
39152 #define CLKID_USB1_DDR_BRIDGE 64
39153 #define CLKID_USB0_DDR_BRIDGE 65
39154+#define CLKID_MMC_PCLK 66
39155+#define CLKID_DVIN 67
39156+#define CLKID_UART2 68
39157 #define CLKID_SANA 69
39158+#define CLKID_VPU_INTR 70
39159+#define CLKID_SEC_AHB_AHB3_BRIDGE 71
39160+#define CLKID_CLK81_A9 72
39161+#define CLKID_VCLK2_VENCI0 73
39162+#define CLKID_VCLK2_VENCI1 74
39163+#define CLKID_VCLK2_VENCP0 75
39164+#define CLKID_VCLK2_VENCP1 76
39165+#define CLKID_GCLK_VENCI_INT 77
39166+#define CLKID_GCLK_VENCP_INT 78
39167+#define CLKID_DAC_CLK 79
39168+#define CLKID_AOCLK_GATE 80
39169+#define CLKID_IEC958_GATE 81
39170+#define CLKID_ENC480P 82
39171+#define CLKID_RNG1 83
39172+#define CLKID_GCLK_VENCL_INT 84
39173+#define CLKID_VCLK2_VENCLMCC 85
39174+#define CLKID_VCLK2_VENCL 86
39175+#define CLKID_VCLK2_OTHER 87
39176+#define CLKID_EDP 88
39177+#define CLKID_AO_MEDIA_CPU 89
39178+#define CLKID_AO_AHB_SRAM 90
39179+#define CLKID_AO_AHB_BUS 91
39180+#define CLKID_AO_IFACE 92
39181+#define CLKID_MPLL0 93
39182+#define CLKID_MPLL1 94
39183+#define CLKID_MPLL2 95
39184
39185 #endif /* __MESON8B_CLKC_H */
39186diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h
39187index ae26f8105914..f269d833e41a 100644
39188--- a/include/dt-bindings/clock/rv1108-cru.h
39189+++ b/include/dt-bindings/clock/rv1108-cru.h
39190@@ -43,12 +43,73 @@
39191 #define SCLK_SDMMC_SAMPLE 84
39192 #define SCLK_SDIO_SAMPLE 85
39193 #define SCLK_EMMC_SAMPLE 86
39194+#define SCLK_VENC_CORE 87
39195+#define SCLK_HEVC_CORE 88
39196+#define SCLK_HEVC_CABAC 89
39197+#define SCLK_PWM0_PMU 90
39198+#define SCLK_I2C0_PMU 91
39199+#define SCLK_WIFI 92
39200+#define SCLK_CIFOUT 93
39201+#define SCLK_MIPI_CSI_OUT 94
39202+#define SCLK_CIF0 95
39203+#define SCLK_CIF1 96
39204+#define SCLK_CIF2 97
39205+#define SCLK_CIF3 98
39206+#define SCLK_DSP 99
39207+#define SCLK_DSP_IOP 100
39208+#define SCLK_DSP_EPP 101
39209+#define SCLK_DSP_EDP 102
39210+#define SCLK_DSP_EDAP 103
39211+#define SCLK_CVBS_HOST 104
39212+#define SCLK_HDMI_SFR 105
39213+#define SCLK_HDMI_CEC 106
39214+#define SCLK_CRYPTO 107
39215+#define SCLK_SPI 108
39216+#define SCLK_SARADC 109
39217+#define SCLK_TSADC 110
39218+#define SCLK_MACPHY_PRE 111
39219+#define SCLK_MACPHY 112
39220+#define SCLK_MACPHY_RX 113
39221+#define SCLK_MAC_REF 114
39222+#define SCLK_MAC_REFOUT 115
39223+#define SCLK_DSP_PFM 116
39224+#define SCLK_RGA 117
39225+#define SCLK_I2C1 118
39226+#define SCLK_I2C2 119
39227+#define SCLK_I2C3 120
39228+#define SCLK_PWM 121
39229+#define SCLK_ISP 122
39230+#define SCLK_USBPHY 123
39231+#define SCLK_I2S0_SRC 124
39232+#define SCLK_I2S1_SRC 125
39233+#define SCLK_I2S2_SRC 126
39234+#define SCLK_UART0_SRC 127
39235+#define SCLK_UART1_SRC 128
39236+#define SCLK_UART2_SRC 129
39237+
39238+#define DCLK_VOP_SRC 185
39239+#define DCLK_HDMIPHY 186
39240+#define DCLK_VOP 187
39241
39242 /* aclk gates */
39243 #define ACLK_DMAC 192
39244 #define ACLK_PRE 193
39245 #define ACLK_CORE 194
39246 #define ACLK_ENMCORE 195
39247+#define ACLK_RKVENC 196
39248+#define ACLK_RKVDEC 197
39249+#define ACLK_VPU 198
39250+#define ACLK_CIF0 199
39251+#define ACLK_VIO0 200
39252+#define ACLK_VIO1 201
39253+#define ACLK_VOP 202
39254+#define ACLK_IEP 203
39255+#define ACLK_RGA 204
39256+#define ACLK_ISP 205
39257+#define ACLK_CIF1 206
39258+#define ACLK_CIF2 207
39259+#define ACLK_CIF3 208
39260+#define ACLK_PERI 209
39261
39262 /* pclk gates */
39263 #define PCLK_GPIO1 256
39264@@ -67,10 +128,23 @@
39265 #define PCLK_PWM 269
39266 #define PCLK_TIMER 270
39267 #define PCLK_PERI 271
39268+#define PCLK_GPIO0_PMU 272
39269+#define PCLK_I2C0_PMU 273
39270+#define PCLK_PWM0_PMU 274
39271+#define PCLK_ISP 275
39272+#define PCLK_VIO 276
39273+#define PCLK_MIPI_DSI 277
39274+#define PCLK_HDMI_CTRL 278
39275+#define PCLK_SARADC 279
39276+#define PCLK_DSP_CFG 280
39277+#define PCLK_BUS 281
39278+#define PCLK_EFUSE0 282
39279+#define PCLK_EFUSE1 283
39280+#define PCLK_WDT 284
39281
39282 /* hclk gates */
39283 #define HCLK_I2S0_8CH 320
39284-#define HCLK_I2S1_8CH 321
39285+#define HCLK_I2S1_2CH 321
39286 #define HCLK_I2S2_2CH 322
39287 #define HCLK_NANDC 323
39288 #define HCLK_SDMMC 324
39289@@ -78,20 +152,37 @@
39290 #define HCLK_EMMC 326
39291 #define HCLK_PERI 327
39292 #define HCLK_SFC 328
39293+#define HCLK_RKVENC 329
39294+#define HCLK_RKVDEC 330
39295+#define HCLK_CIF0 331
39296+#define HCLK_VIO 332
39297+#define HCLK_VOP 333
39298+#define HCLK_IEP 334
39299+#define HCLK_RGA 335
39300+#define HCLK_ISP 336
39301+#define HCLK_CRYPTO_MST 337
39302+#define HCLK_CRYPTO_SLV 338
39303+#define HCLK_HOST0 339
39304+#define HCLK_OTG 340
39305+#define HCLK_CIF1 341
39306+#define HCLK_CIF2 342
39307+#define HCLK_CIF3 343
39308+#define HCLK_BUS 344
39309+#define HCLK_VPU 345
39310
39311-#define CLK_NR_CLKS (HCLK_SFC + 1)
39312+#define CLK_NR_CLKS (HCLK_VPU + 1)
39313
39314 /* reset id */
39315-#define SRST_CORE_PO_AD 0
39316+#define SRST_CORE_PO_AD 0
39317 #define SRST_CORE_AD 1
39318 #define SRST_L2_AD 2
39319-#define SRST_CPU_NIU_AD 3
39320+#define SRST_CPU_NIU_AD 3
39321 #define SRST_CORE_PO 4
39322 #define SRST_CORE 5
39323-#define SRST_L2 6
39324+#define SRST_L2 6
39325 #define SRST_CORE_DBG 8
39326 #define PRST_DBG 9
39327-#define RST_DAP 10
39328+#define RST_DAP 10
39329 #define PRST_DBG_NIU 11
39330 #define ARST_STRC_SYS_AD 15
39331
39332@@ -158,9 +249,9 @@
39333 #define HRST_SYSBUS 75
39334 #define PRST_USBGRF 76
39335
39336-#define ARST_PERIPH_NIU 80
39337-#define HRST_PERIPH_NIU 81
39338-#define PRST_PERIPH_NIU 82
39339+#define ARST_PERIPH_NIU 80
39340+#define HRST_PERIPH_NIU 81
39341+#define PRST_PERIPH_NIU 82
39342 #define HRST_PERIPH 83
39343 #define HRST_SDMMC 84
39344 #define HRST_SDIO 85
39345@@ -178,7 +269,7 @@
39346 #define HRST_HOST0_AUX 96
39347 #define HRST_HOST0_ARB 97
39348 #define SRST_HOST0_EHCIPHY 98
39349-#define SRST_HOST0_UTMI 99
39350+#define SRST_HOST0_UTMI 99
39351 #define SRST_USBPOR 100
39352 #define SRST_UTMI0 101
39353 #define SRST_UTMI1 102
39354@@ -225,21 +316,21 @@
39355 #define HRST_VPU_NIU 141
39356 #define ARST_VPU 142
39357 #define HRST_VPU 143
39358-#define ARST_RKVDEC_NIU 144
39359-#define HRST_RKVDEC_NIU 145
39360+#define ARST_RKVDEC_NIU 144
39361+#define HRST_RKVDEC_NIU 145
39362 #define ARST_RKVDEC 146
39363 #define HRST_RKVDEC 147
39364 #define SRST_RKVDEC_CABAC 148
39365 #define SRST_RKVDEC_CORE 149
39366-#define ARST_RKVENC_NIU 150
39367-#define HRST_RKVENC_NIU 151
39368+#define ARST_RKVENC_NIU 150
39369+#define HRST_RKVENC_NIU 151
39370 #define ARST_RKVENC 152
39371 #define HRST_RKVENC 153
39372 #define SRST_RKVENC_CORE 154
39373
39374 #define SRST_DSP_CORE 156
39375 #define SRST_DSP_SYS 157
39376-#define SRST_DSP_GLOBAL 158
39377+#define SRST_DSP_GLOBAL 158
39378 #define SRST_DSP_OECM 159
39379 #define PRST_DSP_IOP_NIU 160
39380 #define ARST_DSP_EPP_NIU 161
39381@@ -257,7 +348,7 @@
39382 #define SRST_PMU_I2C0 173
39383 #define PRST_PMU_I2C0 174
39384 #define PRST_PMU_GPIO0 175
39385-#define PRST_PMU_INTMEM 176
39386+#define PRST_PMU_INTMEM 176
39387 #define PRST_PMU_PWM0 177
39388 #define SRST_PMU_PWM0 178
39389 #define PRST_PMU_GRF 179
39390diff --git a/include/dt-bindings/genpd/k2g.h b/include/dt-bindings/genpd/k2g.h
39391deleted file mode 100644
39392index 1f31f17e19eb..000000000000
39393--- a/include/dt-bindings/genpd/k2g.h
39394+++ /dev/null
39395@@ -1,90 +0,0 @@
39396-/*
39397- * TI K2G SoC Device definitions
39398- *
39399- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
39400- *
39401- * This program is free software; you can redistribute it and/or modify
39402- * it under the terms of the GNU General Public License as published by
39403- * the Free Software Foundation; either version 2 of the License, or
39404- * (at your option) any later version.
39405- *
39406- * This program is distributed in the hope that it will be useful,
39407- * but WITHOUT ANY WARRANTY; without even the implied warranty of
39408- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
39409- * GNU General Public License for more details.
39410- */
39411-
39412-#ifndef _DT_BINDINGS_GENPD_K2G_H
39413-#define _DT_BINDINGS_GENPD_K2G_H
39414-
39415-/* Documented in http://processors.wiki.ti.com/index.php/TISCI */
39416-
39417-#define K2G_DEV_PMMC0 0x0000
39418-#define K2G_DEV_MLB0 0x0001
39419-#define K2G_DEV_DSS0 0x0002
39420-#define K2G_DEV_MCBSP0 0x0003
39421-#define K2G_DEV_MCASP0 0x0004
39422-#define K2G_DEV_MCASP1 0x0005
39423-#define K2G_DEV_MCASP2 0x0006
39424-#define K2G_DEV_DCAN0 0x0008
39425-#define K2G_DEV_DCAN1 0x0009
39426-#define K2G_DEV_EMIF0 0x000a
39427-#define K2G_DEV_MMCHS0 0x000b
39428-#define K2G_DEV_MMCHS1 0x000c
39429-#define K2G_DEV_GPMC0 0x000d
39430-#define K2G_DEV_ELM0 0x000e
39431-#define K2G_DEV_SPI0 0x0010
39432-#define K2G_DEV_SPI1 0x0011
39433-#define K2G_DEV_SPI2 0x0012
39434-#define K2G_DEV_SPI3 0x0013
39435-#define K2G_DEV_ICSS0 0x0014
39436-#define K2G_DEV_ICSS1 0x0015
39437-#define K2G_DEV_USB0 0x0016
39438-#define K2G_DEV_USB1 0x0017
39439-#define K2G_DEV_NSS0 0x0018
39440-#define K2G_DEV_PCIE0 0x0019
39441-#define K2G_DEV_GPIO0 0x001b
39442-#define K2G_DEV_GPIO1 0x001c
39443-#define K2G_DEV_TIMER64_0 0x001d
39444-#define K2G_DEV_TIMER64_1 0x001e
39445-#define K2G_DEV_TIMER64_2 0x001f
39446-#define K2G_DEV_TIMER64_3 0x0020
39447-#define K2G_DEV_TIMER64_4 0x0021
39448-#define K2G_DEV_TIMER64_5 0x0022
39449-#define K2G_DEV_TIMER64_6 0x0023
39450-#define K2G_DEV_MSGMGR0 0x0025
39451-#define K2G_DEV_BOOTCFG0 0x0026
39452-#define K2G_DEV_ARM_BOOTROM0 0x0027
39453-#define K2G_DEV_DSP_BOOTROM0 0x0029
39454-#define K2G_DEV_DEBUGSS0 0x002b
39455-#define K2G_DEV_UART0 0x002c
39456-#define K2G_DEV_UART1 0x002d
39457-#define K2G_DEV_UART2 0x002e
39458-#define K2G_DEV_EHRPWM0 0x002f
39459-#define K2G_DEV_EHRPWM1 0x0030
39460-#define K2G_DEV_EHRPWM2 0x0031
39461-#define K2G_DEV_EHRPWM3 0x0032
39462-#define K2G_DEV_EHRPWM4 0x0033
39463-#define K2G_DEV_EHRPWM5 0x0034
39464-#define K2G_DEV_EQEP0 0x0035
39465-#define K2G_DEV_EQEP1 0x0036
39466-#define K2G_DEV_EQEP2 0x0037
39467-#define K2G_DEV_ECAP0 0x0038
39468-#define K2G_DEV_ECAP1 0x0039
39469-#define K2G_DEV_I2C0 0x003a
39470-#define K2G_DEV_I2C1 0x003b
39471-#define K2G_DEV_I2C2 0x003c
39472-#define K2G_DEV_EDMA0 0x003f
39473-#define K2G_DEV_SEMAPHORE0 0x0040
39474-#define K2G_DEV_INTC0 0x0041
39475-#define K2G_DEV_GIC0 0x0042
39476-#define K2G_DEV_QSPI0 0x0043
39477-#define K2G_DEV_ARM_64B_COUNTER0 0x0044
39478-#define K2G_DEV_TETRIS0 0x0045
39479-#define K2G_DEV_CGEM0 0x0046
39480-#define K2G_DEV_MSMC0 0x0047
39481-#define K2G_DEV_CBASS0 0x0049
39482-#define K2G_DEV_BOARD0 0x004c
39483-#define K2G_DEV_EDMA1 0x004f
39484-
39485-#endif
39486diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
39487index 5c75e80915fc..18ec5df5a581 100644
39488--- a/include/dt-bindings/pinctrl/dra.h
39489+++ b/include/dt-bindings/pinctrl/dra.h
39490@@ -73,5 +73,8 @@
39491 */
39492 #define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val)
39493
39494+/* DRA7 IODELAY configuration parameters */
39495+#define A_DELAY_PS(val) ((val) & 0xffff)
39496+#define G_DELAY_PS(val) ((val) & 0xffff)
39497 #endif
39498
39499diff --git a/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h b/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
39500new file mode 100644
39501index 000000000000..1f1b56e57346
39502--- /dev/null
39503+++ b/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
39504@@ -0,0 +1,27 @@
39505+/*
39506+ * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
39507+ *
39508+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
39509+ */
39510+
39511+#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
39512+#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
39513+
39514+#define CLKC_RESET_L2_CACHE_SOFT_RESET 0
39515+#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET 1
39516+#define CLKC_RESET_SCU_SOFT_RESET 2
39517+#define CLKC_RESET_CPU0_SOFT_RESET 3
39518+#define CLKC_RESET_CPU1_SOFT_RESET 4
39519+#define CLKC_RESET_CPU2_SOFT_RESET 5
39520+#define CLKC_RESET_CPU3_SOFT_RESET 6
39521+#define CLKC_RESET_A5_GLOBAL_RESET 7
39522+#define CLKC_RESET_A5_AXI_SOFT_RESET 8
39523+#define CLKC_RESET_A5_ABP_SOFT_RESET 9
39524+#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET 10
39525+#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET 11
39526+#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST 12
39527+#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE 13
39528+#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST 14
39529+#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE 15
39530+
39531+#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */