From fb15bf5eb1ac5d4ced4717558401b27b481fa9a8 Mon Sep 17 00:00:00 2001 From: Meghan Denny Date: Sat, 14 Mar 2026 03:42:03 -0700 Subject: [PATCH] fix another linux commit --- git.zig | 3 +- test.zig | 6 + ...f-e90937e756938f03d37d4cae7c82316a3a425944 | 39531 ++++++++++++++++ 3 files changed, 39539 insertions(+), 1 deletion(-) create mode 100644 testdata/diff-e90937e756938f03d37d4cae7c82316a3a425944 diff --git a/git.zig b/git.zig index a9dfce042132e437ddebf86cede06012098e3f21..4eb31725e45c3b3bcf63c9a215d1fac115cfe9ba 100644 --- a/git.zig +++ b/git.zig @@ -624,7 +624,8 @@ pub fn parseTreeDiff(alloc: std.mem.Allocator, input: string) !TreeDiff { const first_line = lineiter.next().?; std.debug.assert(std.mem.startsWith(u8, first_line, "diff --git")); var i = diffs.items.len; - for (overview.items[0..i]) |o| i -= @intFromBool(o.action == .T); + var n: usize = 0; + while (n < i) : (n += 1) i -= @intFromBool(overview.items[n].action == .T); try diffs.append(.{ .index = .{ "", "" }, .before_path = overview.items[i].sub_path, diff --git a/test.zig b/test.zig index 27924b878b0c6b55aa92e165605396f2d7a189c4..a479b10f14d9e8764ab789173466a3f0e2da2a05 100644 --- a/test.zig +++ b/test.zig @@ -256,3 +256,9 @@ test { const alloc = arena.allocator(); _ = try git.parseTreeDiff(alloc, @embedFile("./testdata/diff-a0482e3446cea426bf16571e0000423ed5b25af0")); // linux } +test { + var arena = std.heap.ArenaAllocator.init(std.testing.allocator); + defer arena.deinit(); + const alloc = arena.allocator(); + _ = try git.parseTreeDiff(alloc, @embedFile("./testdata/diff-e90937e756938f03d37d4cae7c82316a3a425944")); // linux +} diff --git a/testdata/diff-e90937e756938f03d37d4cae7c82316a3a425944 b/testdata/diff-e90937e756938f03d37d4cae7c82316a3a425944 new file mode 100644 index 0000000000000000000000000000000000000000..e826de21032a223dc7d04ab65d855d894c7e5b35 --- /dev/null +++ b/testdata/diff-e90937e756938f03d37d4cae7c82316a3a425944 @@ -0,0 +1,39531 @@ +:100644 100644 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arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi +:000000 100644 0000000000000000000000000000000000000000 d65f746a3f9d7843761f057840786236fc8a3abd A arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts +:000000 100644 0000000000000000000000000000000000000000 384729fa740f0b3b8863e1c7c47ddfe50fb9160c A arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +:120000 100644 4685a8d89cba2b56bcdc24e399c79a850d799491 e66d999d9f5d3a1ab87fc398ef611ef4cf048be2 T arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi +:120000 100644 1246db9be2a1914221d74871b1e6f303884731c6 28c5b4ed1d9500fb283876ba766d826a81c44a8d T arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi +:100644 100644 cdc6a437dcc73d33c0aaedb28df523cda333891a b87b8316f4acaecab6e5a243f2cce8ae2f1c7d31 M arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi +:100644 100644 ef1b9e573af0f5bd2ed6792ba5c9450a64ecaa45 bf552674a834140c0d574fe8b2fd3b0613c17798 M arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts +:100644 100644 54dc28351c8cb85a0abbd4bbad554d56dbcbac79 7665fbddff280fcb4be412470e551d9409d1575e M arch/arm64/boot/dts/xilinx/zynqmp.dtsi +:100644 100644 667806620f59273bf0720e121cc033bc2fc235c7 d86c4def6bc98ebac49c49b23d7294b59cf9da07 M arch/arm64/boot/dts/zte/Makefile +:100644 100644 bb900d2bbcfb5e6b9ca88187fc491142f359ed31 cb2519ecd724b526ff7f342b385d026f4c5808c0 M arch/arm64/boot/dts/zte/zx296718-evb.dts +:000000 100644 0000000000000000000000000000000000000000 e02509f7082b1d69ac918e4145b43c6dc598523d A arch/arm64/boot/dts/zte/zx296718-pcbox.dts +:100644 100644 d83bf789c8641b73f9c973e7aa0e1bdb41a62017 6eef64761009491ba768fa69919497e24d14f384 M arch/arm64/boot/dts/zte/zx296718.dtsi +:100644 100644 a7ea5f3da89d5357c2332f8a7fe4afa609cb9997 964489b39f6a0ed6e1a98ed28f26c676db52d0d8 M drivers/clk/meson/gxbb.c +:100644 100644 d63e77e8433d1f73fbcf52ce0122b6350c0dd15d 5b1d4b374d1c21dfa9ded8167b5e9d32bad95b77 M drivers/clk/meson/gxbb.h +:100644 100644 6ec512ad259805c34b57be3ee96eddef149599ee cb60a516ca82bcf85d3b8334306696531ab6a597 M drivers/clk/meson/meson8b.c +:100644 100644 a687e02547dcc9280d7bdf3bee07efd2db110e8f c139bb3273ca74a557605c987694e53980a5fb62 M drivers/clk/meson/meson8b.h +:100644 100644 31751482d13cb498fb4989a41cb336e8c7e92e13 9d15e2221fdb7fd5f732eaa5a800f7b66112f8a5 M include/dt-bindings/clock/gxbb-aoclkc.h +:100644 100644 e3e9f7919c318baed4063fc7199def1a6d684018 c04a76d8facff42319d708830c985bf342427627 M include/dt-bindings/clock/gxbb-clkc.h +:100644 100644 e29227fb52a18c66b6aba5773f38fc0c872ea97d a9c0306330b6a78e910fb5b1fb9fd3dfd107b01e M include/dt-bindings/clock/meson8b-clkc.h +:100644 100644 ae26f81059142867a009197e1c37c8e00d3dbd21 f269d833e41a32851af31a81cf09a9ff8c2ae1b8 M include/dt-bindings/clock/rv1108-cru.h +:100644 000000 1f31f17e19ebca5e528ad9498047ec9bd973d3c4 0000000000000000000000000000000000000000 D include/dt-bindings/genpd/k2g.h +:100644 100644 5c75e80915fcdc5b4411984cd57b8308eb388bfb 18ec5df5a5812a9f037247b6c95de1d15fba2546 M include/dt-bindings/pinctrl/dra.h +:000000 100644 0000000000000000000000000000000000000000 1f1b56e57346e3b939a4597b9242d2aacbcbc33d A include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h + +diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt +index 520cdd2127cf..4e4bc0bae597 100644 +--- a/Documentation/devicetree/bindings/arm/amlogic.txt ++++ b/Documentation/devicetree/bindings/arm/amlogic.txt +@@ -1,6 +1,18 @@ + Amlogic MesonX device tree bindings + ------------------------------------------- + ++Work in progress statement: ++ ++Device tree files and bindings applying to Amlogic SoCs and boards are ++considered "unstable". Any Amlogic device tree binding may change at ++any time. Be sure to use a device tree binary and a kernel image ++generated from the same source tree. ++ ++Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a ++stable binding/ABI. ++ ++--------------------------------------------------------------- ++ + Boards with the Amlogic Meson6 SoC shall have the following properties: + Required root node property: + compatible: "amlogic,meson6" +diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt +index 9c97de23919a..3e3efa046ac5 100644 +--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt ++++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt +@@ -42,6 +42,10 @@ Raspberry Pi Zero + Required root node properties: + compatible = "raspberrypi,model-zero", "brcm,bcm2835"; + ++Raspberry Pi Zero W ++Required root node properties: ++compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; ++ + Generic BCM2835 board + Required root node properties: + compatible = "brcm,bcm2835"; +diff --git a/Documentation/devicetree/bindings/arm/bhf.txt b/Documentation/devicetree/bindings/arm/bhf.txt +new file mode 100644 +index 000000000000..886b503caf9c +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/bhf.txt +@@ -0,0 +1,6 @@ ++Beckhoff Automation Platforms Device Tree Bindings ++-------------------------------------------------- ++ ++CX9020 Embedded PC ++Required root node properties: ++ - compatible = "bhf,cx9020", "fsl,imx53"; +diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt +index a44253cad269..b92f12bd5244 100644 +--- a/Documentation/devicetree/bindings/arm/cpus.txt ++++ b/Documentation/devicetree/bindings/arm/cpus.txt +@@ -200,6 +200,7 @@ described below. + "arm,realview-smp" + "brcm,bcm11351-cpu-method" + "brcm,bcm23550" ++ "brcm,bcm2836-smp" + "brcm,bcm-nsp-smp" + "brcm,brahma-b15" + "marvell,armada-375-smp" +diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt b/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt +new file mode 100644 +index 000000000000..f3e9624534c6 +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt +@@ -0,0 +1,15 @@ ++Marvell Armada 8KPlus Platforms Device Tree Bindings ++---------------------------------------------------- ++ ++Boards using a SoC of the Marvell Armada 8KP families must carry ++the following root node property: ++ ++ - compatible, with one of the following values: ++ ++ - "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810" ++ when the SoC being used is the Armada 8080 ++ ++Example: ++ ++compatible = "marvell,armada-8080-db", "marvell,armada-8080", ++ "marvell,armada-ap810-octa", "marvell,armada-ap810" +diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt +index da7bd138e6f2..91d517849483 100644 +--- a/Documentation/devicetree/bindings/arm/mediatek.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek.txt +@@ -1,12 +1,12 @@ +-MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings ++MediaTek SoC based Platforms Device Tree Bindings + +-Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the +-following property: ++Boards with a MediaTek SoC shall have the following property: + + Required root node property: + + compatible: Must contain one of + "mediatek,mt2701" ++ "mediatek,mt2712" + "mediatek,mt6580" + "mediatek,mt6589" + "mediatek,mt6592" +@@ -14,7 +14,8 @@ compatible: Must contain one of + "mediatek,mt6795" + "mediatek,mt6797" + "mediatek,mt7622" +- "mediatek,mt7623" ++ "mediatek,mt7623" which is referred to MT7623N SoC ++ "mediatek,mt7623a" + "mediatek,mt8127" + "mediatek,mt8135" + "mediatek,mt8173" +@@ -25,6 +26,9 @@ Supported boards: + - Evaluation board for MT2701: + Required root node properties: + - compatible = "mediatek,mt2701-evb", "mediatek,mt2701"; ++- Evaluation board for MT2712: ++ Required root node properties: ++ - compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; + - Evaluation board for MT6580: + Required root node properties: + - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580"; +@@ -46,9 +50,11 @@ Supported boards: + - Reference board variant 1 for MT7622: + Required root node properties: + - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; +-- Evaluation board for MT7623: ++- Reference board for MT7623n with NAND: + Required root node properties: +- - compatible = "mediatek,mt7623-evb", "mediatek,mt7623"; ++ - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623"; ++- Bananapi BPI-R2 board: ++ - compatible = "bananapi,bpi-r2", "mediatek,mt7623"; + - MTK mt8127 tablet moose EVB: + Required root node properties: + - compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; +diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt +index 9c6bebe43449..2ecc712bf707 100644 +--- a/Documentation/devicetree/bindings/arm/omap/omap.txt ++++ b/Documentation/devicetree/bindings/arm/omap/omap.txt +@@ -157,6 +157,9 @@ Boards: + - AM335X phyCORE-AM335x: Development kit + compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx" + ++- AM335X UC-8100-ME-T: Communication-centric industrial computing platform ++ compatible = "moxa,uc-8100-me-t", "ti,am33xx"; ++ + - OMAP5 EVM : Evaluation Module + compatible = "ti,omap5-evm", "ti,omap5" + +@@ -187,6 +190,9 @@ Boards: + - AM5718 IDK + compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7" + ++- DRA762 EVM: Software Development Board for DRA762 ++ compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7" ++ + - DRA742 EVM: Software Development Board for DRA742 + compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7" + +diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt +index 028d16e72186..0ed4d39d7fe1 100644 +--- a/Documentation/devicetree/bindings/arm/qcom.txt ++++ b/Documentation/devicetree/bindings/arm/qcom.txt +@@ -25,6 +25,7 @@ The 'SoC' element must be one of the following strings: + msm8994 + msm8996 + mdm9615 ++ ipq8074 + + The 'board' element must be one of the following strings: + +@@ -33,6 +34,7 @@ The 'board' element must be one of the following strings: + dragonboard + mtp + sbc ++ hk01 + + The 'soc_version' and 'board_version' elements take the form of v. + where the minor number may be omitted when it's zero, i.e. v1.0 is the same +diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt +index 11c0ac4a2d56..b003148e2945 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.txt ++++ b/Documentation/devicetree/bindings/arm/rockchip.txt +@@ -134,6 +134,10 @@ Rockchip platforms device tree bindings + Required root node properties: + - compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288"; + ++- Pine64 Rock64 board: ++ Required root node properties: ++ - compatible = "pine64,rock64", "rockchip,rk3328"; ++ + - Rockchip PX3 Evaluation board: + Required root node properties: + - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; +@@ -173,6 +177,14 @@ Rockchip platforms device tree bindings + Required root node properties: + - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; + ++- Rockchip RK3399 Sapphire Excavator board: ++ Required root node properties: ++ - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; ++ ++- Theobroma Systems RK3399-Q7 Haikou Baseboard: ++ Required root node properties: ++ - compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399"; ++ + - Tronsmart Orion R68 Meta + Required root node properties: + - compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368"; +diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt +index 1a671e329864..ae75cb3b1331 100644 +--- a/Documentation/devicetree/bindings/arm/shmobile.txt ++++ b/Documentation/devicetree/bindings/arm/shmobile.txt +@@ -39,6 +39,8 @@ SoCs: + compatible = "renesas,r8a7795" + - R-Car M3-W (R8A77960) + compatible = "renesas,r8a7796" ++ - R-Car D3 (R8A77995) ++ compatible = "renesas,r8a77995" + + + Boards: +@@ -53,6 +55,8 @@ Boards: + compatible = "renesas,blanche", "renesas,r8a7792" + - BOCK-W + compatible = "renesas,bockw", "renesas,r8a7778" ++ - Draak (RTP0RC77995SEB0010S) ++ compatible = "renesas,draak", "renesas,r8a77995" + - Genmai (RTK772100BC00000BR) + compatible = "renesas,genmai", "renesas,r7s72100" + - GR-Peach (X28A-M01-E/F) +@@ -64,6 +68,10 @@ Boards: + compatible = "renesas,h3ulcb", "renesas,r8a7795"; + - Henninger + compatible = "renesas,henninger", "renesas,r8a7791" ++ - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D) ++ compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745" ++ - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM) ++ compatible = "iwave,g22m", "renesas,r8a7745" + - iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven) + compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743" + - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) +diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +index 207682647d33..b455c5aa9139 100644 +--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt ++++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +@@ -16,18 +16,25 @@ Required Properties: + mapped region. + + - #clock-cells: should be 1. ++- #reset-cells: should be 1. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be + used in device tree sources. + ++Similarly a preprocessor macro for each reset line is defined in ++dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the ++device tree sources). ++ ++ + Example: Clock controller node: + + clkc: clock-controller@c1104000 { +- #clock-cells = <1>; + compatible = "amlogic,meson8b-clkc"; + reg = <0xc1108000 0x4>, <0xc1104000 0x460>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; + }; + + +diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt +index cb7ffc58c564..b1a8929c2536 100644 +--- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt ++++ b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt +@@ -13,6 +13,7 @@ Required properties: + + - compatible : Shall contain one or more of + - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX ++ - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX + - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX + + When compatible with generic versions, nodes must list the SoC-specific +diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt +index c6cb96a4fa93..4bbd1e9bf3be 100644 +--- a/Documentation/devicetree/bindings/display/renesas,du.txt ++++ b/Documentation/devicetree/bindings/display/renesas,du.txt +@@ -36,8 +36,10 @@ Required Properties: + When supplied they must be named "dclkin.x" with "x" being the input + clock numerical index. + +- - vsps: A list of phandles to the VSP nodes that handle the memory +- interfaces for the DU channels. ++ - vsps: A list of phandle and channel index tuples to the VSPs that handle ++ the memory interfaces for the DU channels. The phandle identifies the VSP ++ instance that serves the DU channel, and the channel index identifies the ++ LIF instance in that VSP. + + Required nodes: + +@@ -59,24 +61,24 @@ corresponding to each DU output. + R8A7796 (M3-W) DPAD HDMI LVDS - + + +-Example: R8A7790 (R-Car H2) DU ++Example: R8A7795 (R-Car H3) ES2.0 DU + +- du: du@feb00000 { +- compatible = "renesas,du-r8a7790"; +- reg = <0 0xfeb00000 0 0x70000>, +- <0 0xfeb90000 0 0x1c>, +- <0 0xfeb94000 0 0x1c>; +- reg-names = "du", "lvds.0", "lvds.1"; +- interrupt-parent = <&gic>; +- interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, +- <0 268 IRQ_TYPE_LEVEL_HIGH>, +- <0 269 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&mstp7_clks R8A7790_CLK_DU0>, +- <&mstp7_clks R8A7790_CLK_DU1>, +- <&mstp7_clks R8A7790_CLK_DU2>, +- <&mstp7_clks R8A7790_CLK_LVDS0>, +- <&mstp7_clks R8A7790_CLK_LVDS1>; +- clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1"; ++ du: display@feb00000 { ++ compatible = "renesas,du-r8a7795"; ++ reg = <0 0xfeb00000 0 0x80000>, ++ <0 0xfeb90000 0 0x14>; ++ reg-names = "du", "lvds.0"; ++ interrupts = , ++ , ++ , ++ ; ++ clocks = <&cpg CPG_MOD 724>, ++ <&cpg CPG_MOD 723>, ++ <&cpg CPG_MOD 722>, ++ <&cpg CPG_MOD 721>, ++ <&cpg CPG_MOD 727>; ++ clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0"; ++ vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; + + ports { + #address-cells = <1>; +@@ -89,12 +91,19 @@ Example: R8A7790 (R-Car H2) DU + }; + port@1 { + reg = <1>; +- du_out_lvds0: endpoint { ++ du_out_hdmi0: endpoint { ++ remote-endpoint = <&dw_hdmi0_in>; + }; + }; + port@2 { + reg = <2>; +- du_out_lvds1: endpoint { ++ du_out_hdmi1: endpoint { ++ remote-endpoint = <&dw_hdmi1_in>; ++ }; ++ }; ++ port@3 { ++ reg = <3>; ++ du_out_lvds0: endpoint { + }; + }; + }; +diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt +index 33d9e386dc45..41f0c1a07c56 100644 +--- a/Documentation/devicetree/bindings/dma/ti-edma.txt ++++ b/Documentation/devicetree/bindings/dma/ti-edma.txt +@@ -9,7 +9,12 @@ execute the actual DMA tansfer. + eDMA3 Channel Controller + + Required properties: +-- compatible: "ti,edma3-tpcc" for the channel controller(s) ++-------------------- ++- compatible: Should be: ++ - "ti,edma3-tpcc" for the channel controller(s) on OMAP, ++ AM33xx and AM43xx SoCs. ++ - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the ++ channel controller(s) on 66AK2G. + - #dma-cells: Should be set to <2>. The first number is the DMA request + number and the second is the TC the channel is serviced on. + - reg: Memory map of eDMA CC +@@ -19,8 +24,19 @@ Required properties: + - ti,tptcs: List of TPTCs associated with the eDMA in the following form: + <&tptc_phandle TC_priority_number>. The highest priority is 0. + ++SoC-specific Required properties: ++-------------------------------- ++The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only: ++- ti,hwmods: Name of the hwmods associated to the eDMA CC. ++ ++The following are mandatory properties for 66AK2G SoCs only: ++- power-domains:Should contain a phandle to a PM domain provider node ++ and an args specifier containing the device id ++ value. This property is as per the binding, ++ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt ++ + Optional properties: +-- ti,hwmods: Name of the hwmods associated to the eDMA CC ++------------------- + - ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow + these channels will be SW triggered channels. See example. + - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by +@@ -31,17 +47,34 @@ Optional properties: + eDMA3 Transfer Controller + + Required properties: +-- compatible: "ti,edma3-tptc" for the transfer controller(s) ++-------------------- ++- compatible: Should be: ++ - "ti,edma3-tptc" for the transfer controller(s) on OMAP, ++ AM33xx and AM43xx SoCs. ++ - "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the ++ transfer controller(s) on 66AK2G. + - reg: Memory map of eDMA TC + - interrupts: Interrupt number for TCerrint. + ++SoC-specific Required properties: ++-------------------------------- ++The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only: ++- ti,hwmods: Name of the hwmods associated to the eDMA TC. ++ ++The following are mandatory properties for 66AK2G SoCs only: ++- power-domains:Should contain a phandle to a PM domain provider node ++ and an args specifier containing the device id ++ value. This property is as per the binding, ++ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt ++ + Optional properties: +-- ti,hwmods: Name of the hwmods associated to the given eDMA TC ++------------------- + - interrupt-names: "edma3_tcerrint" + + ------------------------------------------------------------------------------ +-Example: ++Examples: + ++1. + edma: edma@49000000 { + compatible = "ti,edma3-tpcc"; + ti,hwmods = "tpcc"; +@@ -108,6 +141,58 @@ mcasp0: mcasp@48038000 { + dma-names = "tx", "rx"; + }; + ++2. ++edma1: edma@02728000 { ++ compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; ++ reg = <0x02728000 0x8000>; ++ reg-names = "edma3_cc"; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "edma3_ccint", "emda3_mperr", ++ "edma3_ccerrint"; ++ dma-requests = <64>; ++ #dma-cells = <2>; ++ ++ ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>; ++ ++ /* ++ * memcpy is disabled, can be enabled with: ++ * ti,edma-memcpy-channels = <12 13 14 15>; ++ * for example. ++ */ ++ ++ power-domains = <&k2g_pds 0x4f>; ++}; ++ ++edma1_tptc0: tptc@027b0000 { ++ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; ++ reg = <0x027b0000 0x400>; ++ power-domains = <&k2g_pds 0x4f>; ++}; ++ ++edma1_tptc1: tptc@027b8000 { ++ compatible = "ti, k2g-edma3-tptc", "ti,edma3-tptc"; ++ reg = <0x027b8000 0x400>; ++ power-domains = <&k2g_pds 0x4f>; ++}; ++ ++mmc0: mmc@23000000 { ++ compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc"; ++ reg = <0x23000000 0x400>; ++ interrupts = ; ++ dmas = <&edma1 24 0>, <&edma1 25 0>; ++ dma-names = "tx", "rx"; ++ bus-width = <4>; ++ ti,needs-special-reset; ++ no-1-8-v; ++ max-frequency = <96000000>; ++ power-domains = <&k2g_pds 0xb>; ++ clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>; ++ clock-names = "fck", "mmchsdb_fck"; ++ status = "disabled"; ++}; ++ + ------------------------------------------------------------------------------ + DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc + binding. +diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +index 5aa5926029ee..039219df05c5 100644 +--- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt ++++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +@@ -17,6 +17,7 @@ Required properties: + * which must be preceded by one of the following vendor specifics: + + "amlogic,meson-gxm-mali" + + "rockchip,rk3288-mali" ++ + "rockchip,rk3399-mali" + + - reg : Physical base address of the device and length of the register area. + +diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +index 11cc87aeb276..07bf0b9a5139 100644 +--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt ++++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +@@ -17,6 +17,7 @@ Required properties: + "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582 + "mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580 + "mediatek,mt6577-sysirq": for MT6577 ++ "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712 + "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701 + - interrupt-controller : Identifies the node as an interrupt controller + - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. +diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +index 0e026c151c1c..3a4ac401e6f9 100644 +--- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt ++++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +@@ -1,33 +1,55 @@ +-* TI Highspeed MMC host controller for OMAP ++* TI Highspeed MMC host controller for OMAP and 66AK2G family. + +-The Highspeed MMC Host Controller on TI OMAP family ++The Highspeed MMC Host Controller on TI OMAP and 66AK2G family + provides an interface for MMC, SD, and SDIO types of memory cards. + + This file documents differences between the core properties described + by mmc.txt and the properties used by the omap_hsmmc driver. + + Required properties: ++-------------------- + - compatible: + Should be "ti,omap2-hsmmc", for OMAP2 controllers + Should be "ti,omap3-hsmmc", for OMAP3 controllers + Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0 + Should be "ti,omap4-hsmmc", for OMAP4 controllers + Should be "ti,am33xx-hsmmc", for AM335x controllers +-- ti,hwmods: Must be "mmc", n is controller instance starting 1 ++ Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers. ++ ++SoC specific required properties: ++--------------------------------- ++The following are mandatory properties for OMAPs, AM33xx and AM43xx SoCs only: ++- ti,hwmods: Must be "mmc", n is controller instance starting 1. ++ ++The following are mandatory properties for 66AK2G SoCs only: ++- power-domains:Should contain a phandle to a PM domain provider node ++ and an args specifier containing the MMC device id ++ value. This property is as per the binding, ++ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt ++- clocks: Must contain an entry for each entry in clock-names. Should ++ be defined as per the he appropriate clock bindings consumer ++ usage in Documentation/devicetree/bindings/clock/ti,sci-clk.txt ++- clock-names: Shall be "fck" for the functional clock, ++ and "mmchsdb_fck" for the debounce clock. ++ + + Optional properties: +-ti,dual-volt: boolean, supports dual voltage cards +--supply: phandle to the regulator device tree node +-"supply-name" examples are "vmmc", "vmmc_aux"(deprecated)/"vqmmc" etc +-ti,non-removable: non-removable slot (like eMMC) +-ti,needs-special-reset: Requires a special softreset sequence +-ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed +-dmas: List of DMA specifiers with the controller specific format +-as described in the generic DMA client binding. A tx and rx +-specifier is required. +-dma-names: List of DMA request names. These strings correspond +-1:1 with the DMA specifiers listed in dmas. The string naming is +-to be "rx" and "tx" for RX and TX DMA requests, respectively. ++-------------------- ++- ti,dual-volt: boolean, supports dual voltage cards ++- -supply: phandle to the regulator device tree node ++ "supply-name" examples are "vmmc", ++ "vmmc_aux"(deprecated)/"vqmmc" etc ++- ti,non-removable: non-removable slot (like eMMC) ++- ti,needs-special-reset: Requires a special softreset sequence ++- ti,needs-special-hs-handling: HSMMC IP needs special setting ++ for handling High Speed ++- dmas: List of DMA specifiers with the controller specific ++ format as described in the generic DMA client ++ binding. A tx and rx specifier is required. ++- dma-names: List of DMA request names. These strings correspond ++ 1:1 with the DMA specifiers listed in dmas. ++ The string naming is to be "rx" and "tx" for ++ RX and TX DMA requests, respectively. + + Examples: + +diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt +index 5a1d8b0c39e9..2d504256b0d8 100644 +--- a/Documentation/devicetree/bindings/net/can/c_can.txt ++++ b/Documentation/devicetree/bindings/net/can/c_can.txt +@@ -11,9 +11,20 @@ Required properties: + - interrupts : property with a value describing the interrupt + number + +-Optional properties: ++The following are mandatory properties for DRA7x, AM33xx and AM43xx SoCs only: + - ti,hwmods : Must be "d_can" or "c_can", n being the + instance number ++ ++The following are mandatory properties for Keystone 2 66AK2G SoCs only: ++- power-domains : Should contain a phandle to a PM domain provider node ++ and an args specifier containing the DCAN device id ++ value. This property is as per the binding, ++ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt ++- clocks : CAN functional clock phandle. This property is as per the ++ binding, ++ Documentation/devicetree/bindings/clock/ti,sci-clk.txt ++ ++Optional properties: + - syscon-raminit : Handle to system control region that contains the + RAMINIT register, register offset to the RAMINIT + register and the CAN instance number (0 offset). +diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt +index 1d1168b805cc..214eaa9a6683 100644 +--- a/Documentation/devicetree/bindings/net/mediatek-net.txt ++++ b/Documentation/devicetree/bindings/net/mediatek-net.txt +@@ -20,8 +20,10 @@ Required properties: + "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC + - power-domains: phandle to the power domain that the ethernet is part of +-- resets: Should contain a phandle to the ethsys reset signal +-- reset-names: Should contain the reset signal name "eth" ++- resets: Should contain phandles to the ethsys reset signals ++- reset-names: Should contain the names of reset signal listed in the resets ++ property ++ These are "fe", "gmac" and "ppe" + - mediatek,ethsys: phandle to the syscon node that handles the port setup + - mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup + which is required for those SoCs equipped with SGMII such as MT7622 SoC. +diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt +index 127ae1f53e5a..6173af6885f8 100644 +--- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt ++++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt +@@ -276,7 +276,7 @@ pcie-controller { + clocks = <&gateclk 26>; + }; + +- pcie@10,0 { ++ pcie@a,0 { + device_type = "pci"; + assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; + reg = <0x5000 0 0 0 0>; +diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt +index 84404c9edff7..af21502e939c 100644 +--- a/Documentation/devicetree/bindings/power/renesas,apmu.txt ++++ b/Documentation/devicetree/bindings/power/renesas,apmu.txt +@@ -1,12 +1,13 @@ + DT bindings for the Renesas Advanced Power Management Unit + +-Renesas R-Car line of SoCs utilize one or more APMU hardware units ++Renesas R-Car and RZ/G1 SoCs utilize one or more APMU hardware units + for CPU core power domain control including SMP boot and CPU Hotplug. + + Required properties: + + - compatible: Should be "renesas,-apmu", "renesas,apmu" as fallback. + Examples with soctypes are: ++ - "renesas,r8a7743-apmu" (RZ/G1M) + - "renesas,r8a7790-apmu" (R-Car H2) + - "renesas,r8a7791-apmu" (R-Car M2-W) + - "renesas,r8a7792-apmu" (R-Car V2H) +diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt +index b6cf384597e1..f73abff3de43 100644 +--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt ++++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt +@@ -3,6 +3,7 @@ + Required properties: + - compatible should contain: + * "mediatek,mt2701-uart" for MT2701 compatible UARTS ++ * "mediatek,mt2712-uart" for MT2712 compatible UARTS + * "mediatek,mt6580-uart" for MT6580 compatible UARTS + * "mediatek,mt6582-uart" for MT6582 compatible UARTS + * "mediatek,mt6589-uart" for MT6589 compatible UARTS +diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt +index cc9f05d3cbc1..7dc5ce858a0e 100644 +--- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt ++++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt +@@ -21,6 +21,7 @@ Required Properties: + - "rockchip,rk3328-grf", "syscon": for rk3328 + - "rockchip,rk3368-grf", "syscon": for rk3368 + - "rockchip,rk3399-grf", "syscon": for rk3399 ++ - "rockchip,rv1108-grf", "syscon": for rv1108 + - compatible: PMUGRF should be one of the following: + - "rockchip,rk3368-pmugrf", "syscon": for rk3368 + - "rockchip,rk3399-pmugrf", "syscon": for rk3399 +@@ -28,6 +29,8 @@ Required Properties: + - "rockchip,rk3288-sgrf", "syscon": for rk3288 + - compatible: USB2PHYGRF should be one of the followings + - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328 ++- compatible: USBGRF should be one of the following ++ - "rockchip,rv1108-usbgrf", "syscon": for rv1108 + - reg: physical base address of the controller and length of memory mapped + region. + +diff --git a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt +index c705db07d820..66e6265fb0aa 100644 +--- a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt ++++ b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt +@@ -46,12 +46,13 @@ Required Properties: + - power-domains: phandle pointing to the corresponding PM domain node + and an ID representing the device. + +-See dt-bindings/genpd/k2g.h for the list of valid identifiers for k2g. ++See http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data for the list ++of valid identifiers for k2g. + + Example (K2G): + -------------------- + uart0: serial@02530c00 { + compatible = "ns16550a"; + ... +- power-domains = <&k2g_pds K2G_DEV_UART0>; ++ power-domains = <&k2g_pds 0x002c>; + }; +diff --git a/Documentation/devicetree/bindings/sram/renesas,smp-sram.txt b/Documentation/devicetree/bindings/sram/renesas,smp-sram.txt +new file mode 100644 +index 000000000000..712d05e3e15e +--- /dev/null ++++ b/Documentation/devicetree/bindings/sram/renesas,smp-sram.txt +@@ -0,0 +1,27 @@ ++* Renesas SMP SRAM ++ ++Renesas R-Car Gen2 and RZ/G1 SoCs need a small piece of SRAM for the jump stub ++for secondary CPU bringup and CPU hotplug. ++This memory is reserved by adding a child node to a "mmio-sram" node, cfr. ++Documentation/devicetree/bindings/sram/sram.txt. ++ ++Required child node properties: ++ - compatible: Must be "renesas,smp-sram", ++ - reg: Address and length of the reserved SRAM. ++ The full physical (bus) address must be aligned to a 256 KiB boundary. ++ ++ ++Example: ++ ++ icram1: sram@e63c0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63c0000 0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0xe63c0000 0x1000>; ++ ++ smp-sram@0 { ++ compatible = "renesas,smp-sram"; ++ reg = <0 0x10>; ++ }; ++ }; +diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt +index 5a79aeb620b3..69183f0fbc78 100644 +--- a/Documentation/devicetree/bindings/vendor-prefixes.txt ++++ b/Documentation/devicetree/bindings/vendor-prefixes.txt +@@ -48,6 +48,7 @@ avic Shanghai AVIC Optoelectronics Co., Ltd. + axentia Axentia Technologies AB + axis Axis Communications AB + bananapi BIPAI KEJI LIMITED ++bhf Beckhoff Automation GmbH & Co. KG + boe BOE Technology Group Co., Ltd. + bosch Bosch Sensortec GmbH + boundary Boundary Devices Inc. +diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +index 6a00939a059a..20ada673ab0c 100644 +--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt ++++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +@@ -3,9 +3,9 @@ Mediatek SoCs Watchdog timer + Required properties: + + - compatible should contain: +- * "mediatek,mt2701-wdt" for MT2701 compatible watchdog timers +- * "mediatek,mt6589-wdt" for all compatible watchdog timers (MT2701, +- MT6589) ++ "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 ++ "mediatek,mt6589-wdt": for MT6589 ++ "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 + + - reg : Specifies base physical address and size of the registers. + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 4b17f35dc9a7..faf46abaa4a2 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -46,6 +46,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ + at91sam9x35ek.dtb + dtb-$(CONFIG_SOC_SAM_V7) += \ + at91-kizbox2.dtb \ ++ at91-sama5d27_som1_ek.dtb \ + at91-sama5d2_xplained.dtb \ + at91-sama5d3_xplained.dtb \ + at91-tse850-3.dtb \ +@@ -73,7 +74,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ + bcm2835-rpi-a-plus.dtb \ + bcm2836-rpi-2-b.dtb \ + bcm2837-rpi-3-b.dtb \ +- bcm2835-rpi-zero.dtb ++ bcm2835-rpi-zero.dtb \ ++ bcm2835-rpi-zero-w.dtb + dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm4708-asus-rt-ac56u.dtb \ + bcm4708-asus-rt-ac68u.dtb \ +@@ -106,7 +108,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm953012hr.dtb \ + bcm953012k.dtb + dtb-$(CONFIG_ARCH_BCM_53573) += \ +- bcm47189-tenda-ac9.dtb ++ bcm47189-tenda-ac9.dtb \ ++ bcm947189acdbmr.dtb + dtb-$(CONFIG_ARCH_BCM_63XX) += \ + bcm963138dvt.dtb + dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ +@@ -180,6 +183,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ + exynos5440-ssdk5440.dtb \ + exynos5800-peach-pi.dtb + dtb-$(CONFIG_ARCH_GEMINI) += \ ++ gemini-dlink-dir-685.dtb \ + gemini-nas4220b.dtb \ + gemini-rut1xx.dtb \ + gemini-sq201.dtb \ +@@ -340,6 +344,7 @@ dtb-$(CONFIG_SOC_IMX51) += \ + imx51-ts4800.dtb + dtb-$(CONFIG_SOC_IMX53) += \ + imx53-ard.dtb \ ++ imx53-cx9020.dtb \ + imx53-m53evk.dtb \ + imx53-mba53.dtb \ + imx53-qsb.dtb \ +@@ -391,7 +396,9 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6dl-udoo.dtb \ + imx6dl-wandboard.dtb \ + imx6dl-wandboard-revb1.dtb \ ++ imx6q-apalis-eval.dtb \ + imx6q-apalis-ixora.dtb \ ++ imx6q-apalis-ixora-v1.1.dtb \ + imx6q-apf6dev.dtb \ + imx6q-arm2.dtb \ + imx6q-b450v3.dtb \ +@@ -466,7 +473,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ + imx6sx-udoo-neo-full.dtb + dtb-$(CONFIG_SOC_IMX6UL) += \ + imx6ul-14x14-evk.dtb \ +- imx6ul-geam-kit.dtb \ ++ imx6ul-geam.dtb \ + imx6ul-isiot-emmc.dtb \ + imx6ul-isiot-nand.dtb \ + imx6ul-liteboard.dtb \ +@@ -617,6 +624,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ + am335x-evmsk.dtb \ + am335x-icev2.dtb \ + am335x-lxm.dtb \ ++ am335x-moxa-uc-8100-me-t.dtb \ + am335x-nano.dtb \ + am335x-pepper.dtb \ + am335x-phycore-rdk.dtb \ +@@ -650,6 +658,7 @@ dtb-$(CONFIG_SOC_OMAP5) += \ + dtb-$(CONFIG_SOC_DRA7XX) += \ + am57xx-beagle-x15.dtb \ + am57xx-beagle-x15-revb1.dtb \ ++ am57xx-beagle-x15-revc.dtb \ + am57xx-cl-som-am57x.dtb \ + am57xx-sbc-am57x.dtb \ + am572x-idk.dtb \ +@@ -657,7 +666,8 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ + dra7-evm.dtb \ + dra72-evm.dtb \ + dra72-evm-revc.dtb \ +- dra71-evm.dtb ++ dra71-evm.dtb \ ++ dra76-evm.dtb + dtb-$(CONFIG_ARCH_ORION5X) += \ + orion5x-kuroboxpro.dtb \ + orion5x-lacie-d2-network.dtb \ +@@ -903,6 +913,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-a33-q8-tablet.dtb \ + sun8i-a33-sinlinx-sina33.dtb \ + sun8i-a83t-allwinner-h8homlet-v2.dtb \ ++ sun8i-a83t-bananapi-m3.dtb \ + sun8i-a83t-cubietruck-plus.dtb \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ +@@ -918,6 +929,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-h3-orangepi-pc-plus.dtb \ + sun8i-h3-orangepi-plus.dtb \ + sun8i-h3-orangepi-plus2e.dtb \ ++ sun8i-r16-bananapi-m2m.dtb \ + sun8i-r16-parrot.dtb \ + sun8i-v3s-licheepi-zero.dtb \ + sun8i-v3s-licheepi-zero-dock.dtb +@@ -970,7 +982,6 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \ + uniphier-pro4-sanji.dtb \ + uniphier-pxs2-gentil.dtb \ + uniphier-pxs2-vodka.dtb \ +- uniphier-sld3-ref.dtb \ + uniphier-sld8-ref.dtb + dtb-$(CONFIG_ARCH_VERSATILE) += \ + versatile-ab.dtb \ +@@ -1049,7 +1060,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt6580-evbp1.dtb \ + mt6589-aquaris5.dtb \ + mt6592-evb.dtb \ +- mt7623-evb.dtb \ ++ mt7623n-rfb-nand.dtb \ ++ mt7623n-bananapi-bpi-r2.dtb \ + mt8127-moose.dtb \ + mt8135-evbp1.dtb + dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb +diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi +index 1d154444dfef..48a15fc641f2 100644 +--- a/arch/arm/boot/dts/am335x-bone-common.dtsi ++++ b/arch/arm/boot/dts/am335x-bone-common.dtsi +@@ -319,13 +319,10 @@ &tps { + ti,pmic-shutdown-controller; + + charger { +- interrupts = <0>, <1>; +- interrupt-names = "USB", "AC"; + status = "okay"; + }; + + pwrbutton { +- interrupts = <2>; + status = "okay"; + }; + +diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts +index d8769799772e..59431b235944 100644 +--- a/arch/arm/boot/dts/am335x-chiliboard.dts ++++ b/arch/arm/boot/dts/am335x-chiliboard.dts +@@ -191,13 +191,10 @@ &tps { + interrupts = <7>; /* NNMI */ + + charger { +- interrupts = <0>, <1>; +- interrupt-names = "USB", "AC"; + status = "okay"; + }; + + pwrbutton { +- interrupts = <2>; + status = "okay"; + }; + }; +diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts +index 1c37a7c1ea17..ddd897556e03 100644 +--- a/arch/arm/boot/dts/am335x-evm.dts ++++ b/arch/arm/boot/dts/am335x-evm.dts +@@ -531,6 +531,7 @@ nand@0,0 { + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ++ ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; +diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts +new file mode 100644 +index 000000000000..f82233cd18e0 +--- /dev/null ++++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts +@@ -0,0 +1,525 @@ ++/* ++ * Copyright (C) 2017 MOXA Inc. - https://www.moxa.com/ ++ * ++ * Author: SZ Lin (林上智) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++/dts-v1/; ++ ++#include "am33xx.dtsi" ++ ++/ { ++ model = "Moxa UC-8100-ME-T"; ++ compatible = "moxa,uc-8100-me-t", "ti,am33xx"; ++ ++ cpus { ++ cpu@0 { ++ cpu0-supply = <&vdd1_reg>; ++ }; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x80000000 0x20000000>; /* 512 MB */ ++ }; ++ ++ vbat: vbat-regulator { ++ compatible = "regulator-fixed"; ++ }; ++ ++ /* Power supply provides a fixed 3.3V @3A */ ++ vmmcsd_fixed: vmmcsd-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vmmcsd_fixed"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ led1 { ++ label = "uc8100me:CEL1"; ++ gpios = <&gpio_xten 8 0>; ++ default-state = "off"; ++ }; ++ ++ led2 { ++ label = "uc8100me:CEL2"; ++ gpios = <&gpio_xten 9 0>; ++ default-state = "off"; ++ }; ++ ++ led3 { ++ label = "uc8100me:CEL3"; ++ gpios = <&gpio_xten 10 0>; ++ default-state = "off"; ++ }; ++ ++ led4 { ++ label = "uc8100me:DIA1"; ++ gpios = <&gpio_xten 11 0>; ++ default-state = "off"; ++ }; ++ led5 { ++ label = "uc8100me:DIA2"; ++ gpios = <&gpio_xten 12 0>; ++ default-state = "off"; ++ }; ++ led6 { ++ label = "uc8100me:DIA3"; ++ gpios = <&gpio_xten 13 0>; ++ default-state = "off"; ++ }; ++ led7 { ++ label = "uc8100me:SD"; ++ gpios = <&gpio_xten 14 0>; ++ default-state = "off"; ++ }; ++ led8 { ++ label = "uc8100me:USB"; ++ gpios = <&gpio_xten 15 0>; ++ default-state = "off"; ++ }; ++ led9 { ++ label = "uc8100me:USER"; ++ gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ }; ++ ++ buttons: push_button { ++ compatible = "gpio-keys"; ++ }; ++ ++}; ++ ++&am33xx_pinmux { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&minipcie_pins>; ++ ++ minipcie_pins: pinmux_minipcie { ++ pinctrl-single,pins = < ++ AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2_24 */ ++ AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ ++ AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/ ++ >; ++ }; ++ ++ push_button_pins: pinmux_push_button { ++ pinctrl-single,pins = < ++ AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ ++ >; ++ }; ++ ++ i2c0_pins: pinmux_i2c0_pins { ++ pinctrl-single,pins = < ++ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ ++ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ ++ >; ++ }; ++ ++ ++ i2c1_pins: pinmux_i2c1_pins { ++ pinctrl-single,pins = < ++ AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_ctsn.i2c1_sda */ ++ AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_rtsn.i2c1_scl */ ++ >; ++ }; ++ ++ uart0_pins: pinmux_uart0_pins { ++ pinctrl-single,pins = < ++ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ ++ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ ++ >; ++ }; ++ ++ uart1_pins: pinmux_uart1_pins { ++ pinctrl-single,pins = < ++ AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ ++ AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ ++ AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ ++ AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */ ++ >; ++ }; ++ ++ uart2_pins: pinmux_uart2_pins { ++ pinctrl-single,pins = < ++ AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE6) /* lcd_data14.uart5_ctsn */ ++ AM33XX_IOPAD(0x8dc, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* lcd_data15.uart5_rtsn */ ++ AM33XX_IOPAD(0x8c4, PIN_INPUT_PULLUP | MUX_MODE4) /* lcd_data9.uart5_rxd */ ++ AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE4) /* lcd_data8.uart5_txd */ ++ >; ++ }; ++ ++ cpsw_default: cpsw_default { ++ pinctrl-single,pins = < ++ /* Slave 1 */ ++ AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ ++ AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ ++ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ ++ AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ ++ AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ ++ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ ++ AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ ++ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_refclk.rmii1_refclk */ ++ ++ /* Slave 2 */ ++ AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */ ++ AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */ ++ AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */ ++ AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */ ++ AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */ ++ AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */ ++ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */ ++ AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */ ++ ++ >; ++ }; ++ ++ davinci_mdio_default: davinci_mdio_default { ++ pinctrl-single,pins = < ++ /* MDIO */ ++ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ ++ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ ++ >; ++ }; ++ ++ mmc0_pins_default: pinmux_mmc0_pins { ++ pinctrl-single,pins = < ++ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ ++ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ ++ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ ++ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ ++ AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ ++ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ ++ AM33XX_IOPAD(0x990, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */ ++ AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */ ++ >; ++ }; ++ ++ mmc2_pins_default: pinmux_mmc2_pins { ++ pinctrl-single,pins = < ++ /* eMMC */ ++ AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ ++ AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ ++ AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ ++ AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ ++ AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ ++ AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ ++ AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ ++ AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ ++ AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ ++ AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ ++ >; ++ }; ++ ++ spi0_pins: pinmux_spi0 { ++ pinctrl-single,pins = < ++ AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */ ++ AM33XX_IOPAD(0x95C, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ ++ AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ ++ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ ++ >; ++ }; ++ ++}; ++ ++&uart0 { ++ /* Console */ ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ /* UART 1 setting */ ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart5 { ++ /* UART 2 setting */ ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ tpm: tpm@20 { ++ compatible = "infineon,slb9645tt"; ++ reg = <0x20>; ++ }; ++ ++ tps: tps@2d { ++ compatible = "ti,tps65910"; ++ reg = <0x2d>; ++ }; ++ ++ eeprom: eeprom@50 { ++ compatible = "atmel,24c16"; ++ pagesize = <16>; ++ reg = <0x50>; ++ }; ++ ++ rtc_wdt: rtc_wdt@68 { ++ compatible = "dallas,ds1374"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ ++ status = "okay"; ++ clock-frequency = <400000>; ++ gpio_xten: gpio_xten@27 { ++ compatible = "nxp,pca9535"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ reg = <0x27>; ++ }; ++}; ++ ++&usb { ++ status = "okay"; ++}; ++ ++&usb_ctrl_mod { ++ status = "okay"; ++}; ++ ++&usb0_phy { ++ status = "okay"; ++}; ++ ++&usb1_phy { ++ status = "okay"; ++}; ++ ++&usb0 { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&usb1 { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&cppi41dma { ++ status = "okay"; ++}; ++ ++#include "tps65910.dtsi" ++ ++&tps { ++ vcc1-supply = <&vbat>; ++ vcc2-supply = <&vbat>; ++ vcc3-supply = <&vbat>; ++ vcc4-supply = <&vbat>; ++ vcc5-supply = <&vbat>; ++ vcc6-supply = <&vbat>; ++ vcc7-supply = <&vbat>; ++ vccio-supply = <&vbat>; ++ ++ regulators { ++ vrtc_reg: regulator@0 { ++ regulator-always-on; ++ }; ++ ++ vio_reg: regulator@1 { ++ regulator-always-on; ++ }; ++ ++ vdd1_reg: regulator@2 { ++ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ ++ regulator-name = "vdd_mpu"; ++ regulator-min-microvolt = <912500>; ++ regulator-max-microvolt = <1378000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ vdd2_reg: regulator@3 { ++ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ ++ regulator-name = "vdd_core"; ++ regulator-min-microvolt = <912500>; ++ regulator-max-microvolt = <1150000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ vdd3_reg: regulator@4 { ++ regulator-always-on; ++ }; ++ ++ vdig1_reg: regulator@5 { ++ regulator-always-on; ++ }; ++ ++ vdig2_reg: regulator@6 { ++ regulator-always-on; ++ }; ++ ++ vpll_reg: regulator@7 { ++ regulator-always-on; ++ }; ++ ++ vdac_reg: regulator@8 { ++ regulator-always-on; ++ }; ++ ++ vaux1_reg: regulator@9 { ++ regulator-always-on; ++ }; ++ ++ vaux2_reg: regulator@10 { ++ regulator-always-on; ++ }; ++ ++ vaux33_reg: regulator@11 { ++ regulator-always-on; ++ }; ++ ++ vmmc_reg: regulator@12 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vmmc_reg"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ }; ++}; ++ ++/* Power */ ++&vbat { ++ regulator-name = "vbat"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++}; ++ ++&mac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cpsw_default>; ++ dual_emac = <1>; ++ status = "okay"; ++}; ++ ++&davinci_mdio { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&davinci_mdio_default>; ++ status = "okay"; ++}; ++ ++&cpsw_emac0 { ++ status = "okay"; ++ phy_id = <&davinci_mdio>, <4>; ++ phy-mode = "rmii"; ++ dual_emac_res_vlan = <1>; ++}; ++ ++&cpsw_emac1 { ++ status = "okay"; ++ phy_id = <&davinci_mdio>, <5>; ++ phy-mode = "rmii"; ++ dual_emac_res_vlan = <2>; ++}; ++ ++&phy_sel { ++ reg= <0x44e10650 0xf5>; ++ rmii-clock-ext; ++}; ++ ++&sham { ++ status = "okay"; ++}; ++ ++&aes { ++ status = "okay"; ++}; ++ ++&gpio0 { ++ ti,no-reset-on-init; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ vmmc-supply = <&vmmcsd_fixed>; ++ bus-width = <4>; ++ pinctrl-0 = <&mmc0_pins_default>; ++ cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; ++ wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&mmc3 { ++ dmas = <&edma_xbar 12 0 1 ++ &edma_xbar 13 0 2>; ++ dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ vmmc-supply = <&vmmcsd_fixed>; ++ bus-width = <8>; ++ pinctrl-0 = <&mmc2_pins_default>; ++ ti,non-removable; ++ status = "okay"; ++}; ++ ++&buttons { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&push_button_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ button@0 { ++ label = "push_button"; ++ linux,code = <0x100>; ++ gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++/* SPI Busses */ ++&spi0 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ ++ m25p80@0 { ++ compatible = "mx25l6405d"; ++ spi-max-frequency = <40000000>; ++ ++ reg = <0>; ++ spi-cpol; ++ spi-cpha; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ /* reg : The partition's offset and size within the mtd bank. */ ++ partitions@0 { ++ label = "MLO"; ++ reg = <0x0 0x80000>; ++ }; ++ ++ partitions@1 { ++ label = "U-Boot"; ++ reg = <0x80000 0x100000>; ++ }; ++ ++ partitions@2 { ++ label = "U-Boot Env"; ++ reg = <0x180000 0x20000>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts +index 29a538ecd405..afb8eb0a0a16 100644 +--- a/arch/arm/boot/dts/am437x-gp-evm.dts ++++ b/arch/arm/boot/dts/am437x-gp-evm.dts +@@ -149,6 +149,13 @@ sound0_master: simple-audio-card,codec { + system-clock-frequency = <12000000>; + }; + }; ++ ++ beeper: beeper { ++ compatible = "gpio-beeper"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&beeper_pins>; ++ gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; ++ }; + }; + + &am43xx_pinmux { +@@ -510,6 +517,13 @@ AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM4372_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; ++ ++ beeper_pins: beeper_pins { ++ pinctrl-single,pins = < ++ AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */ ++ >; ++ }; ++ + }; + + &uart0 { +@@ -842,6 +856,7 @@ nand@0,0 { + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ++ ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; +diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts +index 54f40f370011..9d276af7c539 100644 +--- a/arch/arm/boot/dts/am43x-epos-evm.dts ++++ b/arch/arm/boot/dts/am43x-epos-evm.dts +@@ -564,6 +564,7 @@ nand@0,0 { + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ++ ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; +diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts +index 7b207835b2d1..debf9464403e 100644 +--- a/arch/arm/boot/dts/am571x-idk.dts ++++ b/arch/arm/boot/dts/am571x-idk.dts +@@ -11,6 +11,7 @@ + #include + #include + #include "am57xx-idk-common.dtsi" ++#include "dra72x-mmc-iodelay.dtsi" + + / { + model = "TI AM5718 IDK"; +@@ -64,13 +65,6 @@ mmc0-led { + }; + }; + +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&ldo1_reg>; +- bus-width = <4>; +- cd-gpios = <&gpio6 27 0>; /* gpio 219 */ +-}; +- + &omap_dwc3_2 { + extcon = <&extcon_usb2>; + }; +@@ -96,3 +90,30 @@ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; + }; ++ ++&pcie1_rc { ++ status = "okay"; ++ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; ++}; ++ ++&pcie1_ep { ++ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; ++ pinctrl-0 = <&mmc1_pins_default>; ++ pinctrl-1 = <&mmc1_pins_hs>; ++ pinctrl-2 = <&mmc1_pins_sdr12>; ++ pinctrl-3 = <&mmc1_pins_sdr25>; ++ pinctrl-4 = <&mmc1_pins_sdr50>; ++ pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; ++ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default", "hs", "ddr_1_8v"; ++ pinctrl-0 = <&mmc2_pins_default>; ++ pinctrl-1 = <&mmc2_pins_hs>; ++ pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; ++}; +diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts +index 9da6d83ca185..a578fe97ba3b 100644 +--- a/arch/arm/boot/dts/am572x-idk.dts ++++ b/arch/arm/boot/dts/am572x-idk.dts +@@ -12,6 +12,7 @@ + #include + #include + #include "am57xx-idk-common.dtsi" ++#include "dra74x-mmc-iodelay.dtsi" + + / { + model = "TI AM5728 IDK"; +@@ -67,6 +68,24 @@ mmc0-led { + }; + }; + ++&mmc1 { ++ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; ++ pinctrl-0 = <&mmc1_pins_default>; ++ pinctrl-1 = <&mmc1_pins_hs>; ++ pinctrl-2 = <&mmc1_pins_sdr12>; ++ pinctrl-3 = <&mmc1_pins_sdr25>; ++ pinctrl-4 = <&mmc1_pins_sdr50>; ++ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; ++ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default", "hs", "ddr_1_8v"; ++ pinctrl-0 = <&mmc2_pins_default>; ++ pinctrl-1 = <&mmc2_pins_hs>; ++ pinctrl-2 = <&mmc2_pins_ddr_rev20>; ++}; ++ + &omap_dwc3_2 { + extcon = <&extcon_usb2>; + }; +@@ -76,19 +95,16 @@ &extcon_usb2 { + vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; + }; + +-&mmc1 { +- status = "okay"; +- vmmc-supply = <&v3_3d>; +- vmmc_aux-supply = <&ldo1_reg>; +- bus-width = <4>; +- cd-gpios = <&gpio6 27 0>; /* gpio 219 */ +-}; +- + &sn65hvs882 { + load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + }; + +-&pcie1 { ++&pcie1_rc { ++ status = "okay"; ++ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; ++}; ++ ++&pcie1_ep { + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + }; + +diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +index fdfe5b16b806..49aeecd312b4 100644 +--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi ++++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +@@ -9,6 +9,7 @@ + + #include "dra74x.dtsi" + #include "am57xx-commercial-grade.dtsi" ++#include "dra74x-mmc-iodelay.dtsi" + #include + #include + +@@ -166,34 +167,6 @@ sound0_master: simple-audio-card,codec { + }; + }; + +-&dra7_pmx_core { +- mmc1_pins_default: mmc1_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ +- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ +- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ +- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ +- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ +- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ +- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ +- >; +- }; +- +- mmc2_pins_default: mmc2_pins_default { +- pinctrl-single,pins = < +- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ +- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ +- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ +- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ +- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ +- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ +- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ +- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ +- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ +- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ +- >; +- }; +-}; + &i2c1 { + status = "okay"; + clock-frequency = <400000>; +@@ -570,7 +543,12 @@ hdmi_out: endpoint { + }; + }; + +-&pcie1 { ++&pcie1_rc { ++ status = "ok"; ++ gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; ++}; ++ ++&pcie1_ep { + gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + }; + +diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts +index 39a92aff0a0d..5a77b334923d 100644 +--- a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts ++++ b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts +@@ -19,8 +19,23 @@ &tpd12s015 { + }; + + &mmc1 { ++ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; ++ pinctrl-0 = <&mmc1_pins_default>; ++ pinctrl-1 = <&mmc1_pins_hs>; ++ pinctrl-2 = <&mmc1_pins_sdr12>; ++ pinctrl-3 = <&mmc1_pins_sdr25>; ++ pinctrl-4 = <&mmc1_pins_sdr50>; ++ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>; ++ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; + vmmc-supply = <&vdd_3v3>; +- vmmc-aux-supply = <&ldo1_reg>; ++ vqmmc-supply = <&ldo1_reg>; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default", "hs", "ddr_1_8v"; ++ pinctrl-0 = <&mmc2_pins_default>; ++ pinctrl-1 = <&mmc2_pins_hs>; ++ pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; + }; + + /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */ +diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts b/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts +new file mode 100644 +index 000000000000..17c41da3b55f +--- /dev/null ++++ b/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts +@@ -0,0 +1,39 @@ ++/* ++ * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "am57xx-beagle-x15-common.dtsi" ++ ++/ { ++ model = "TI AM5728 BeagleBoard-X15 rev C"; ++}; ++ ++&tpd12s015 { ++ gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ ++ <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ ++ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ ++}; ++ ++&mmc1 { ++ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; ++ pinctrl-0 = <&mmc1_pins_default>; ++ pinctrl-1 = <&mmc1_pins_hs>; ++ pinctrl-2 = <&mmc1_pins_sdr12>; ++ pinctrl-3 = <&mmc1_pins_sdr25>; ++ pinctrl-4 = <&mmc1_pins_sdr50>; ++ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; ++ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; ++ vmmc-supply = <&vdd_3v3>; ++ vqmmc-supply = <&ldo1_reg>; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default", "hs", "ddr_1_8v"; ++ pinctrl-0 = <&mmc2_pins_default>; ++ pinctrl-1 = <&mmc2_pins_hs>; ++ pinctrl-2 = <&mmc2_pins_ddr_rev20>; ++}; +diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts +index 19a60a11c198..d6689106d2a8 100644 +--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts ++++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts +@@ -20,9 +20,20 @@ &tpd12s015 { + }; + + &mmc1 { ++ pinctrl-names = "default", "hs"; ++ pinctrl-0 = <&mmc1_pins_default>; ++ pinctrl-1 = <&mmc1_pins_hs>; ++ + vmmc-supply = <&ldo1_reg>; + }; + ++&mmc2 { ++ pinctrl-names = "default", "hs", "ddr_1_8v"; ++ pinctrl-0 = <&mmc2_pins_default>; ++ pinctrl-1 = <&mmc2_pins_hs>; ++ pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; ++}; ++ + /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */ + &phy1 { + max-speed = <100>; +diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi +index c536b2f5389f..97aa8e6a56da 100644 +--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi ++++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi +@@ -399,6 +399,14 @@ &usb2 { + dr_mode = "peripheral"; + }; + ++&mmc1 { ++ status = "okay"; ++ vmmc-supply = <&v3_3d>; ++ vqmmc-supply = <&ldo1_reg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ ++}; ++ + &mmc2 { + status = "okay"; + vmmc-supply = <&v3_3d>; +diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi +index f9cf1273f35e..b1cf5a26f3c2 100644 +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -72,7 +72,7 @@ bootrom { + reg = ; + }; + +- pciec: pcie-controller@82000000 { ++ pciec: pcie@82000000 { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; +@@ -100,6 +100,7 @@ pcie0: pcie@1,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; +@@ -117,6 +118,7 @@ pcie2: pcie@2,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; +diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi +index 50c5e8417802..7225c7ce9a8d 100644 +--- a/arch/arm/boot/dts/armada-375.dtsi ++++ b/arch/arm/boot/dts/armada-375.dtsi +@@ -582,7 +582,7 @@ coredivclk: corediv-clock@e8250 { + }; + }; + +- pciec: pcie-controller@82000000 { ++ pciec: pcie@82000000 { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; +@@ -610,6 +610,7 @@ pcie0: pcie@1,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <0>; +@@ -627,6 +628,7 @@ pcie1: pcie@2,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <0>; +diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi +index e392f6036f39..132596fd0860 100644 +--- a/arch/arm/boot/dts/armada-380.dtsi ++++ b/arch/arm/boot/dts/armada-380.dtsi +@@ -71,7 +71,7 @@ pinctrl@18000 { + }; + }; + +- pcie-controller { ++ pcie { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; +@@ -104,6 +104,7 @@ pcie@1,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <0>; +@@ -122,6 +123,7 @@ pcie@2,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <1>; +@@ -140,6 +142,7 @@ pcie@3,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <2>; +diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts +index db5b9f6b615d..25d2d720dc0e 100644 +--- a/arch/arm/boot/dts/armada-385-db-ap.dts ++++ b/arch/arm/boot/dts/armada-385-db-ap.dts +@@ -209,7 +209,7 @@ bm-bppi { + status = "okay"; + }; + +- pcie-controller { ++ pcie { + status = "okay"; + + /* +diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts +index be16ce39fb3d..06831e1e3f80 100644 +--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts ++++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts +@@ -96,7 +96,7 @@ usb3@f8000 { + }; + }; + +- pcie-controller { ++ pcie { + status = "okay"; + + pcie@1,0 { +diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi +index 7fcc4c4885cf..74863aff01c6 100644 +--- a/arch/arm/boot/dts/armada-385.dtsi ++++ b/arch/arm/boot/dts/armada-385.dtsi +@@ -70,7 +70,7 @@ cpu@1 { + }; + + soc { +- pciec: pcie-controller { ++ pciec: pcie { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; +@@ -109,6 +109,7 @@ pcie1: pcie@1,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <0>; +@@ -127,6 +128,7 @@ pcie2: pcie@2,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <1>; +@@ -145,6 +147,7 @@ pcie3: pcie@3,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <2>; +@@ -166,6 +169,7 @@ pcie4: pcie@4,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <3>; +diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts +index 0d5f1f062275..ee7b0089eff0 100644 +--- a/arch/arm/boot/dts/armada-388-clearfog.dts ++++ b/arch/arm/boot/dts/armada-388-clearfog.dts +@@ -62,7 +62,7 @@ usb3@f0000 { + }; + }; + +- pcie-controller { ++ pcie { + pcie@3,0 { + /* Port 2, Lane 0. CON2, nearest CPU. */ + reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; +diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi +index 0f5938bede53..68acfc968706 100644 +--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi ++++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi +@@ -104,7 +104,7 @@ usb3@f8000 { + }; + }; + +- pcie-controller { ++ pcie { + status = "okay"; + /* + * The two PCIe units are accessible through +diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts +index 1ac923826445..a4ec1fa37529 100644 +--- a/arch/arm/boot/dts/armada-388-db.dts ++++ b/arch/arm/boot/dts/armada-388-db.dts +@@ -172,7 +172,7 @@ bm-bppi { + status = "okay"; + }; + +- pcie-controller { ++ pcie { + status = "okay"; + /* + * The two PCIe units are accessible through +diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts +index 563901e0ec07..f503955dbd3b 100644 +--- a/arch/arm/boot/dts/armada-388-gp.dts ++++ b/arch/arm/boot/dts/armada-388-gp.dts +@@ -240,7 +240,7 @@ bm-bppi { + status = "okay"; + }; + +- pcie-controller { ++ pcie { + status = "okay"; + /* + * One PCIe units is accessible through +diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts +index af82f275eac2..9cc3ca0376b9 100644 +--- a/arch/arm/boot/dts/armada-388-rd.dts ++++ b/arch/arm/boot/dts/armada-388-rd.dts +@@ -117,7 +117,7 @@ usb3@f0000 { + }; + }; + +- pcie-controller { ++ pcie { + status = "okay"; + /* + * One PCIe units is accessible through +diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi +index af31f5d6c0e5..7ff0811e61db 100644 +--- a/arch/arm/boot/dts/armada-38x.dtsi ++++ b/arch/arm/boot/dts/armada-38x.dtsi +@@ -154,6 +154,13 @@ scu@c000 { + reg = <0xc000 0x58>; + }; + ++ timer@c200 { ++ compatible = "arm,cortex-a9-global-timer"; ++ reg = <0xc200 0x20>; ++ interrupts = ; ++ clocks = <&coreclk 2>; ++ }; ++ + timer@c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xc600 0x20>; +diff --git a/arch/arm/boot/dts/armada-390-db.dts b/arch/arm/boot/dts/armada-390-db.dts +index 2afed2ce4741..c718a5242595 100644 +--- a/arch/arm/boot/dts/armada-390-db.dts ++++ b/arch/arm/boot/dts/armada-390-db.dts +@@ -123,7 +123,7 @@ usb3@f8000 { + }; + }; + +- pcie-controller { ++ pcie { + status = "okay"; + + /* CON30 */ +diff --git a/arch/arm/boot/dts/armada-395-gp.dts b/arch/arm/boot/dts/armada-395-gp.dts +index 2cdbba804c1e..ef491b524fd6 100644 +--- a/arch/arm/boot/dts/armada-395-gp.dts ++++ b/arch/arm/boot/dts/armada-395-gp.dts +@@ -139,7 +139,7 @@ usb3@f0000 { + }; + }; + +- pcie-controller { ++ pcie { + status = "okay"; + + /* +diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts +index e8604281c3c9..f0e0379f7619 100644 +--- a/arch/arm/boot/dts/armada-398-db.dts ++++ b/arch/arm/boot/dts/armada-398-db.dts +@@ -118,7 +118,7 @@ usb3@f8000 { + }; + }; + +- pcie-controller { ++ pcie { + status = "okay"; + + pcie@1,0 { +diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi +index 60fbfd5907c7..ea657071e278 100644 +--- a/arch/arm/boot/dts/armada-39x.dtsi ++++ b/arch/arm/boot/dts/armada-39x.dtsi +@@ -442,7 +442,7 @@ thermal@e8078 { + }; + }; + +- pcie-controller { ++ pcie { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; +@@ -481,6 +481,7 @@ pcie@1,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <0>; +@@ -499,6 +500,7 @@ pcie@2,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <1>; +@@ -517,6 +519,7 @@ pcie@3,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <2>; +@@ -538,6 +541,7 @@ pcie@4,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <3>; +diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +index be22ec5236ac..bdd4c7a45fbf 100644 +--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi ++++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +@@ -91,7 +91,7 @@ bootrom { + /* + * 98DX3236 has 1 x1 PCIe unit Gen2.0 + */ +- pciec: pcie-controller@82000000 { ++ pciec: pcie@82000000 { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; +@@ -116,6 +116,7 @@ pcie1: pcie@1,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; +diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts +index a33974254d8c..065282c21789 100644 +--- a/arch/arm/boot/dts/armada-xp-db.dts ++++ b/arch/arm/boot/dts/armada-xp-db.dts +@@ -242,7 +242,7 @@ pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; +- pcie@10,0 { ++ pcie@a,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts +index d62bf7bea1df..ac9eab8ac186 100644 +--- a/arch/arm/boot/dts/armada-xp-gp.dts ++++ b/arch/arm/boot/dts/armada-xp-gp.dts +@@ -227,7 +227,7 @@ pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; +- pcie@10,0 { ++ pcie@a,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +index 9f25814077f2..129738f7973d 100644 +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -86,7 +86,7 @@ soc { + * configured as x4 or quad x1 lanes. One unit is + * x1 only. + */ +- pciec: pcie-controller@82000000 { ++ pciec: pcie@82000000 { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; +@@ -123,6 +123,7 @@ pcie1: pcie@1,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; +@@ -140,6 +141,7 @@ pcie2: pcie@2,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; +@@ -157,6 +159,7 @@ pcie3: pcie@3,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; +@@ -174,6 +177,7 @@ pcie4: pcie@4,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; +@@ -191,6 +195,7 @@ pcie5: pcie@5,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; +diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +index 2bfe07aebf1a..e58d597e37b9 100644 +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -87,7 +87,7 @@ soc { + * configured as x4 or quad x1 lanes. One unit is + * x4 only. + */ +- pciec: pcie-controller@82000000 { ++ pciec: pcie@82000000 { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; +@@ -138,6 +138,7 @@ pcie1: pcie@1,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; +@@ -155,6 +156,7 @@ pcie2: pcie@2,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; +@@ -172,6 +174,7 @@ pcie3: pcie@3,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; +@@ -189,6 +192,7 @@ pcie4: pcie@4,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; +@@ -206,6 +210,7 @@ pcie5: pcie@5,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; +@@ -223,6 +228,7 @@ pcie6: pcie@6,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 + 0x81000000 0 0 0x81000000 0x6 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 63>; + marvell,pcie-port = <1>; +@@ -240,6 +246,7 @@ pcie7: pcie@7,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 + 0x81000000 0 0 0x81000000 0x7 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 64>; + marvell,pcie-port = <1>; +@@ -257,6 +264,7 @@ pcie8: pcie@8,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 + 0x81000000 0 0 0x81000000 0x8 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 65>; + marvell,pcie-port = <1>; +@@ -274,6 +282,7 @@ pcie9: pcie@9,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; +diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +index 6c33935f7074..a5c961cee7de 100644 +--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +@@ -104,7 +104,7 @@ soc { + * configured as x4 or quad x1 lanes. Two units are + * x4/x1. + */ +- pciec: pcie-controller@82000000 { ++ pciec: pcie@82000000 { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; +@@ -159,6 +159,7 @@ pcie1: pcie@1,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; +@@ -176,6 +177,7 @@ pcie2: pcie@2,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; +@@ -193,6 +195,7 @@ pcie3: pcie@3,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; +@@ -210,6 +213,7 @@ pcie4: pcie@4,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; +@@ -227,6 +231,7 @@ pcie5: pcie@5,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; +@@ -244,6 +249,7 @@ pcie6: pcie@6,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 + 0x81000000 0 0 0x81000000 0x6 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 63>; + marvell,pcie-port = <1>; +@@ -261,6 +267,7 @@ pcie7: pcie@7,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 + 0x81000000 0 0 0x81000000 0x7 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 64>; + marvell,pcie-port = <1>; +@@ -278,6 +285,7 @@ pcie8: pcie@8,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 + 0x81000000 0 0 0x81000000 0x8 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 65>; + marvell,pcie-port = <1>; +@@ -295,6 +303,7 @@ pcie9: pcie@9,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; +@@ -303,7 +312,7 @@ pcie9: pcie@9,0 { + status = "disabled"; + }; + +- pcie10: pcie@10,0 { ++ pcie10: pcie@a,0 { + device_type = "pci"; + assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; + reg = <0x5000 0 0 0 0>; +@@ -312,6 +321,7 @@ pcie10: pcie@10,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 + 0x81000000 0 0 0x81000000 0xa 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 103>; + marvell,pcie-port = <3>; +diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi +index 8a04c7e2d818..22b958537d31 100644 +--- a/arch/arm/boot/dts/aspeed-g4.dtsi ++++ b/arch/arm/boot/dts/aspeed-g4.dtsi +@@ -26,7 +26,7 @@ ahb { + + fmc: flash-controller@1e620000 { + reg = < 0x1e620000 0x94 +- 0x20000000 0x02000000 >; ++ 0x20000000 0x10000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-fmc"; +@@ -41,7 +41,7 @@ flash@0 { + + spi: flash-controller@1e630000 { + reg = < 0x1e630000 0x18 +- 0x30000000 0x02000000 >; ++ 0x30000000 0x10000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-spi"; +diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +new file mode 100644 +index 000000000000..63a5af898165 +--- /dev/null ++++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +@@ -0,0 +1,102 @@ ++/* ++ * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board ++ * ++ * Copyright (c) 2017, Microchip Technology Inc. ++ * 2017 Cristian Birsan ++ * 2017 Claudiu Beznea ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include "sama5d2.dtsi" ++#include "sama5d2-pinfunc.h" ++ ++/ { ++ model = "Atmel SAMA5D27 SoM1"; ++ compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; ++ ++ clocks { ++ slow_xtal { ++ clock-frequency = <32768>; ++ }; ++ ++ main_xtal { ++ clock-frequency = <24000000>; ++ }; ++ }; ++ ++ ahb { ++ apb { ++ macb0: ethernet@f8008000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_macb0_default>; ++ phy-mode = "rmii"; ++ ++ ethernet-phy@1 { ++ reg = <0x1>; ++ interrupt-parent = <&pioA>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_macb0_phy_irq>; ++ }; ++ }; ++ ++ pinctrl@fc038000 { ++ ++ pinctrl_macb0_default: macb0_default { ++ pinmux = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_macb0_phy_irq: macb0_phy_irq { ++ pinmux = ; ++ bias-disable; ++ }; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +new file mode 100644 +index 000000000000..9c9088c99cc4 +--- /dev/null ++++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +@@ -0,0 +1,537 @@ ++/* ++ * at91-sama5d27_som1_ek.dts - Device Tree file for SAMA5D27-SOM1-EK board ++ * ++ * Copyright (c) 2017, Microchip Technology Inc. ++ * 2016 Nicolas Ferre ++ * 2017 Cristian Birsan ++ * 2017 Claudiu Beznea ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++/dts-v1/; ++#include "at91-sama5d27_som1.dtsi" ++#include ++#include ++ ++/ { ++ model = "Atmel SAMA5D27 SOM1 EK"; ++ compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ ahb { ++ usb0: gadget@00300000 { ++ atmel,vbus-gpio = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usba_vbus>; ++ status = "okay"; ++ }; ++ ++ usb1: ohci@00400000 { ++ num-ports = <3>; ++ atmel,vbus-gpio = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usb_default>; ++ status = "okay"; ++ }; ++ ++ usb2: ehci@00500000 { ++ status = "okay"; ++ }; ++ ++ sdmmc0: sdio-host@a0000000 { ++ bus-width = <8>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_sdmmc0_default>; ++ status = "okay"; ++ }; ++ ++ sdmmc1: sdio-host@b0000000 { ++ bus-width = <4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_sdmmc1_default>; ++ status = "okay"; ++ }; ++ ++ apb { ++ isc: isc@f0008000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_isc_base &pinctrl_isc_data_8bit &pinctrl_isc_data_9_10 &pinctrl_isc_data_11_12>; ++ status = "okay"; ++ }; ++ ++ spi0: spi@f8000000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_spi0_default>; ++ status = "okay"; ++ }; ++ ++ macb0: ethernet@f8008000 { ++ status = "okay"; ++ }; ++ ++ uart1: serial@f8020000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1_default>; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "okay"; ++ }; ++ ++ uart2: serial@f8024000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_mikrobus2_uart>; ++ atmel,use-dma-rx; ++ atmel-use-dma-tx; ++ status = "okay"; ++ }; ++ ++ pwm0: pwm@f802c000 { ++ status = "okay"; ++ }; ++ ++ flx1: flexcom@f8038000 { ++ atmel,flexcom-mode = ; ++ status = "disabled"; ++ ++ i2c2: i2c@600 { ++ compatible = "atmel,sama5d2-i2c"; ++ reg = <0x600 0x200>; ++ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; ++ dmas = <0>, <0>; ++ dma-names = "tx", "rx"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&flx1_clk>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_mikrobus_i2c>; ++ atmel,fifo-size = <16>; ++ status = "disabled"; ++ }; ++ }; ++ ++ shdwc@f8048010 { ++ atmel,shdwc-debouncer = <976>; ++ atmel,wakeup-rtc-timer; ++ ++ input@0 { ++ reg = <0>; ++ atmel,wakeup-type = "low"; ++ }; ++ }; ++ ++ watchdog@f8048040 { ++ status = "okay"; ++ }; ++ ++ can0: can@f8054000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_can0_default>; ++ }; ++ ++ uart3: serial@fc008000 { ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart3_default>; ++ status = "disabled"; ++ }; ++ ++ uart4: serial@fc00c000 { ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ pinctrl-name = "default"; ++ pinctrl-0 = <&pinctrl_mikrobus1_uart>; ++ status = "okay"; ++ }; ++ ++ flx3: flexcom@fc014000 { ++ atmel,flexcom-mode = ; ++ status = "disabled"; ++ ++ uart7: serial@200 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0x200 0x200>; ++ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; ++ clocks = <&flx3_clk>; ++ clock-names = "usart"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flx3_default>; ++ atmel,fifo-size = <32>; ++ status = "disabled"; ++ }; ++ ++ spi2: spi@400 { ++ compatible = "atmel,at91rm9200-spi"; ++ reg = <0x400 0x200>; ++ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; ++ clocks = <&flx3_clk>; ++ clock-names = "spi_clk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flx3_default>; ++ atmel,fifo-size = <16>; ++ status = "disabled"; ++ }; ++ }; ++ ++ flx4: flexcom@fc018000 { ++ atmel,flexcom-mode = ; ++ status = "okay"; ++ ++ uart6: serial@200 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0x200 0x200>; ++ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; ++ clocks = <&flx4_clk>; ++ clock-names = "usart"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flx4_default>; ++ atmel,fifo-size = <32>; ++ status = "disabled"; ++ }; ++ ++ spi3: spi@400 { ++ compatible = "atmel,at91rm9200-spi"; ++ reg = <0x400 0x200>; ++ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; ++ clocks = <&flx4_clk>; ++ clock-names = "spi_clk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; ++ atmel,fifo-size = <16>; ++ status = "okay"; ++ }; ++ ++ i2c3: i2c@600 { ++ compatible = "atmel,sama5d2-i2c"; ++ reg = <0x600 0x200>; ++ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; ++ dmas = <0>, <0>; ++ dma-names = "tx", "rx"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&flx4_clk>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flx4_default>; ++ atmel,fifo-size = <16>; ++ status = "disabled"; ++ }; ++ }; ++ ++ i2c1: i2c@fc028000 { ++ dmas = <0>, <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1_default>; ++ status = "okay"; ++ }; ++ ++ pinctrl@fc038000 { ++ ++ pinctrl_can0_default: can0_default { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_can1_default: can1_default { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_flx3_default: flx3_default { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_i2c1_default: i2c1_default { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_isc_base: isc_base { ++ pinmux = , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_isc_data_8bit: isc_data_8bit { ++ pinmux = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_isc_data_9_10: isc_data_9_10 { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_isc_data_11_12: isc_data_11_12 { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_key_gpio_default: key_gpio_default { ++ pinmux = ; ++ bias-pull-up; ++ }; ++ ++ pinctrl_led_gpio_default: led_gpio_default { ++ pinmux = , ++ , ++ ; ++ bias-pull-up; ++ }; ++ ++ pinctrl_sdmmc0_default: sdmmc0_default { ++ cmd_data { ++ pinmux = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ bias-pull-up; ++ }; ++ ++ ck_cd_vddsel { ++ pinmux = , ++ , ++ ; ++ bias-disable; ++ }; ++ }; ++ ++ pinctrl_sdmmc1_default: sdmmc1_default { ++ cmd_data { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ bias-pull-up; ++ }; ++ ++ conf-ck_cd { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ }; ++ ++ pinctrl_spi0_default: spi0_default { ++ pinmux = , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_uart1_default: uart1_default { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_uart3_default: uart3_default { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_usb_default: usb_default { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_usba_vbus: usba_vbus { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus1_an: mikrobus1_an { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus2_an: mikrobus2_an { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus1_rst: mikrobus1_rst { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus2_rst: mikrobus2_rst { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus2_spi_cs: mikrobus2_spi_cs { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus_spi: mikrobus_spi { ++ pinmux = , ++ , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus1_pwm: mikrobus1_pwm { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus2_pwm: mikrobus2_pwm { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus1_int: mikrobus1_int { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus2_int: mikrobus2_int { ++ pinmux = ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus1_uart: mikrobus1_uart { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus2_uart: mikrobus2_uart { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_mikrobus_i2c: mikrobus1_i2c { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_flx4_default: flx4_uart_default { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ }; ++ ++ can1: can@fc050000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_can1_default>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_key_gpio_default>; ++ ++ pb4 { ++ label = "USER"; ++ gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; ++ linux,code = <0x104>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_led_gpio_default>; ++ status = "okay"; ++ ++ red { ++ label = "red"; ++ gpios = <&pioA PIN_PA27 GPIO_ACTIVE_LOW>; ++ }; ++ ++ green { ++ label = "green"; ++ gpios = <&pioA PIN_PB1 GPIO_ACTIVE_LOW>; ++ }; ++ ++ blue { ++ label = "blue"; ++ gpios = <&pioA PIN_PA31 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts +index 2e2c3d1a1fa2..c7e9ccf2bc87 100644 +--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts ++++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts +@@ -68,7 +68,7 @@ main_xtal { + + ahb { + usb0: gadget@00300000 { +- atmel,vbus-gpio = <&pioA 31 GPIO_ACTIVE_HIGH>; ++ atmel,vbus-gpio = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +@@ -76,8 +76,8 @@ usb0: gadget@00300000 { + + usb1: ohci@00400000 { + num-ports = <3>; +- atmel,vbus-gpio = <0 /* &pioA 41 GPIO_ACTIVE_HIGH */ +- &pioA 42 GPIO_ACTIVE_HIGH ++ atmel,vbus-gpio = <0 /* &pioA PIN_PB9 GPIO_ACTIVE_HIGH */ ++ &pioA PIN_PB10 GPIO_ACTIVE_HIGH + 0 + >; + pinctrl-names = "default"; +@@ -127,7 +127,7 @@ macb0: ethernet@f8008000 { + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioA>; +- interrupts = <73 IRQ_TYPE_LEVEL_LOW>; ++ interrupts = ; + }; + }; + +@@ -160,9 +160,9 @@ pmic@5b { + compatible = "active-semi,act8945a"; + reg = <0x5b>; + active-semi,vsel-high; +- active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>; +- active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>; +- active-semi,irq_gpios = <&pioA 45 GPIO_ACTIVE_LOW>; ++ active-semi,chglev-gpios = <&pioA PIN_PA12 GPIO_ACTIVE_HIGH>; ++ active-semi,lbo-gpios = <&pioA PIN_PC8 GPIO_ACTIVE_LOW>; ++ active-semi,irq_gpios = <&pioA PIN_PB13 GPIO_ACTIVE_LOW>; + active-semi,input-voltage-threshold-microvolt = <6600>; + active-semi,precondition-timeout = <40>; + active-semi,total-timeout = <3>; +@@ -355,6 +355,14 @@ pinctrl_charger_lbo: charger_lbo { + bias-pull-up; + }; + ++ pinctrl_classd_default: classd_default { ++ pinmux = , ++ , ++ , ++ ; ++ bias-pull-up; ++ }; ++ + pinctrl_flx0_default: flx0_default { + pinmux = , + ; +@@ -488,6 +496,14 @@ pinctrl_usba_vbus: usba_vbus { + + }; + ++ classd: classd@fc048000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_classd_default>; ++ atmel,pwm-type = "diff"; ++ atmel,non-overlap-time = <10>; ++ status = "okay"; ++ }; ++ + can1: can@fc050000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; +@@ -504,7 +520,7 @@ gpio_keys { + + bp1 { + label = "PB_USER"; +- gpios = <&pioA 41 GPIO_ACTIVE_LOW>; ++ gpios = <&pioA PIN_PB9 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + }; + }; +@@ -517,17 +533,18 @@ leds { + + red { + label = "red"; +- gpios = <&pioA 38 GPIO_ACTIVE_LOW>; ++ gpios = <&pioA PIN_PB6 GPIO_ACTIVE_LOW>; + }; + ++ + green { + label = "green"; +- gpios = <&pioA 37 GPIO_ACTIVE_LOW>; ++ gpios = <&pioA PIN_PB5 GPIO_ACTIVE_LOW>; + }; + + blue { + label = "blue"; +- gpios = <&pioA 32 GPIO_ACTIVE_LOW>; ++ gpios = <&pioA PIN_PB0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi +index a4808c4fbc05..64fa3f9a39d3 100644 +--- a/arch/arm/boot/dts/at91sam9g45.dtsi ++++ b/arch/arm/boot/dts/at91sam9g45.dtsi +@@ -455,6 +455,16 @@ pinctrl@fffff200 { + >; + + /* shared pinctrl settings */ ++ ac97 { ++ pinctrl_ac97: ac97-0 { ++ atmel,pins = ++ ; /* AC97CK */ ++ }; ++ }; ++ + adc0 { + pinctrl_adc0_adtrg: adc0_adtrg { + atmel,pins = ; +@@ -1043,6 +1053,17 @@ ssc1: ssc@fffa0000 { + status = "disabled"; + }; + ++ ac97: sound@fffac000 { ++ compatible = "atmel,at91sam9263-ac97c"; ++ reg = <0xfffac000 0x4000>; ++ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ac97>; ++ clocks = <&ac97_clk>; ++ clock-names = "ac97_clk"; ++ status = "disabled"; ++ }; ++ + adc0: adc@fffb0000 { + #address-cells = <1>; + #size-cells = <0>; +diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts +index 2522c3308305..94c52c555f83 100644 +--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts ++++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts +@@ -166,6 +166,10 @@ usb2: gadget@fff78000 { + status = "okay"; + }; + ++ ac97: sound@fffac000 { ++ status = "okay"; ++ }; ++ + adc0: adc@fffb0000 { + pinctrl-names = "default"; + pinctrl-0 = < +diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi +index bf8c83815753..7c957ea06c66 100644 +--- a/arch/arm/boot/dts/bcm-cygnus.dtsi ++++ b/arch/arm/boot/dts/bcm-cygnus.dtsi +@@ -55,6 +55,11 @@ cpu@0 { + + /include/ "bcm-cygnus-clock.dtsi" + ++ pmu { ++ compatible = "arm,cortex-a9-pmu"; ++ interrupts = ; ++ }; ++ + core { + compatible = "simple-bus"; + ranges = <0x00000000 0x19000000 0x1000000>; +@@ -119,6 +124,21 @@ pinctrl: pinctrl@0301d0c8 { + compatible = "brcm,cygnus-pinmux"; + reg = <0x0301d0c8 0x30>, + <0x0301d24c 0x2c>; ++ ++ spi_0: spi_0 { ++ function = "spi0"; ++ groups = "spi0_grp"; ++ }; ++ ++ spi_1: spi_1 { ++ function = "spi1"; ++ groups = "spi1_grp"; ++ }; ++ ++ spi_2: spi_2 { ++ function = "spi2"; ++ groups = "spi2_grp"; ++ }; + }; + + mailbox: mailbox@03024024 { +@@ -300,6 +320,23 @@ msi1: msi-controller { + }; + }; + ++ dma0: dma@18018000 { ++ compatible = "arm,pl330", "arm,primecell"; ++ reg = <0x18018000 0x1000>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ clocks = <&apb_clk>; ++ clock-names = "apb_pclk"; ++ #dma-cells = <1>; ++ }; ++ + uart0: serial@18020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x18020000 0x100>; +@@ -324,7 +361,7 @@ uart1: serial@18021000 { + + uart2: serial@18022000 { + compatible = "snps,dw-apb-uart"; +- reg = <0x18020000 0x100>; ++ reg = <0x18022000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; +@@ -344,6 +381,52 @@ uart3: serial@18023000 { + status = "disabled"; + }; + ++ spi0: spi@18028000 { ++ compatible = "arm,pl022", "arm,primecell"; ++ reg = <0x18028000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ pinctrl-0 = <&spi_0>; ++ clocks = <&axi81_clk>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ spi1: spi@18029000 { ++ compatible = "arm,pl022", "arm,primecell"; ++ reg = <0x18029000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ pinctrl-0 = <&spi_1>; ++ clocks = <&axi81_clk>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ spi2: spi@1802a000 { ++ compatible = "arm,pl022", "arm,primecell"; ++ reg = <0x1802a000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ pinctrl-0 = <&spi_2>; ++ clocks = <&axi81_clk>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ sdhci0: sdhci@18041000 { ++ compatible = "brcm,sdhci-iproc-cygnus"; ++ reg = <0x18041000 0x100>; ++ interrupts = ; ++ clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>; ++ bus-width = <4>; ++ sdhci,auto-cmd12; ++ status = "disabled"; ++ }; ++ + eth0: ethernet@18042000 { + compatible = "brcm,amac"; + reg = <0x18042000 0x1000>, +@@ -353,6 +436,16 @@ eth0: ethernet@18042000 { + status = "disabled"; + }; + ++ sdhci1: sdhci@18043000 { ++ compatible = "brcm,sdhci-iproc-cygnus"; ++ reg = <0x18043000 0x100>; ++ interrupts = ; ++ clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>; ++ bus-width = <4>; ++ sdhci,auto-cmd12; ++ status = "disabled"; ++ }; ++ + nand: nand@18046000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x18046000 0x600>, <0xf8105408 0x600>, +@@ -366,6 +459,33 @@ nand: nand@18046000 { + brcm,nand-has-wp; + }; + ++ ehci0: usb@18048000 { ++ compatible = "generic-ehci"; ++ reg = <0x18048000 0x100>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ ohci0: usb@18048800 { ++ compatible = "generic-ohci"; ++ reg = <0x18048800 0x100>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ v3d: v3d@180a2000 { ++ compatible = "brcm,cygnus-v3d"; ++ reg = <0x180a2000 0x1000>; ++ clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>; ++ clock-names = "v3d_clk"; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ vc4: gpu { ++ compatible = "brcm,cygnus-vc4"; ++ }; ++ + gpio_asiu: gpio@180a5000 { + compatible = "brcm,cygnus-asiu-gpio"; + reg = <0x180a5000 0x668>; +@@ -444,19 +564,6 @@ touchscreen: touchscreen@180a6000 { + status = "disabled"; + }; + +- v3d: v3d@180a2000 { +- compatible = "brcm,cygnus-v3d"; +- reg = <0x180a2000 0x1000>; +- clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>; +- clock-names = "v3d_clk"; +- interrupts = ; +- status = "disabled"; +- }; +- +- vc4: gpu { +- compatible = "brcm,cygnus-vc4"; +- }; +- + adc: adc@180a6000 { + compatible = "brcm,iproc-static-adc"; + #io-channel-cells = <1>; +@@ -467,5 +574,19 @@ adc: adc@180a6000 { + interrupts = ; + status = "disabled"; + }; ++ ++ keypad: keypad@180ac000 { ++ compatible = "brcm,bcm-keypad"; ++ reg = <0x180ac000 0x14c>; ++ interrupts = ; ++ clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>; ++ clock-names = "peri_clk"; ++ clock-frequency = <31250>; ++ pull-up-enabled; ++ col-debounce-filter-period = <0>; ++ status-debounce-filter-period = <0>; ++ row-output-enabled; ++ status = "disabled"; ++ }; + }; + }; +diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi +index 7204d1def23d..dff66974feed 100644 +--- a/arch/arm/boot/dts/bcm-nsp.dtsi ++++ b/arch/arm/boot/dts/bcm-nsp.dtsi +@@ -215,6 +215,7 @@ sdio: sdhci@21000 { + interrupts = ; + sdhci,auto-cmd12; + clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>; ++ dma-coherent; + status = "disabled"; + }; + +@@ -224,6 +225,7 @@ amac0: ethernet@22000 { + <0x110000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; ++ dma-coherent; + status = "disabled"; + }; + +@@ -233,6 +235,7 @@ amac1: ethernet@23000 { + <0x111000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; ++ dma-coherent; + status = "disabled"; + }; + +@@ -242,6 +245,7 @@ amac2: ethernet@24000 { + <0x112000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; ++ dma-coherent; + status = "disabled"; + }; + +@@ -252,6 +256,7 @@ mailbox: mailbox@25000 { + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; ++ dma-coherent; + }; + + nand: nand@26000 { +@@ -297,6 +302,32 @@ qspi: qspi@27200 { + #size-cells = <0>; + }; + ++ xhci: usb@29000 { ++ compatible = "generic-xhci"; ++ reg = <0x29000 0x1000>; ++ interrupts = ; ++ phys = <&usb3_phy>; ++ phy-names = "usb3-phy"; ++ dma-coherent; ++ status = "disabled"; ++ }; ++ ++ ehci0: usb@2a000 { ++ compatible = "generic-ehci"; ++ reg = <0x2a000 0x100>; ++ interrupts = ; ++ dma-coherent; ++ status = "disabled"; ++ }; ++ ++ ohci0: usb@2b000 { ++ compatible = "generic-ohci"; ++ reg = <0x2b000 0x100>; ++ interrupts = ; ++ dma-coherent; ++ status = "disabled"; ++ }; ++ + crypto@2f000 { + compatible = "brcm,spum-nsp-crypto"; + reg = <0x2f000 0x900>; +@@ -321,20 +352,6 @@ pwm: pwm@31000 { + status = "disabled"; + }; + +- ehci0: usb@2a000 { +- compatible = "generic-ehci"; +- reg = <0x2a000 0x100>; +- interrupts = ; +- status = "disabled"; +- }; +- +- ohci0: usb@2b000 { +- compatible = "generic-ohci"; +- reg = <0x2b000 0x100>; +- interrupts = ; +- status = "disabled"; +- }; +- + rng: rng@33000 { + compatible = "brcm,bcm-nsp-rng"; + reg = <0x33000 0x14>; +@@ -376,6 +393,7 @@ i2c0: i2c@38000 { + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; ++ dma-coherent; + status = "disabled"; + }; + +@@ -446,6 +464,7 @@ sata: ahci@41000 { + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; ++ dma-coherent; + status = "disabled"; + + sata0: sata-port@0 { +@@ -460,6 +479,15 @@ sata1: sata-port@1 { + phy-names = "sata-phy"; + }; + }; ++ ++ usb3_phy: usb3-phy@104000 { ++ compatible = "brcm,ns-bx-usb3-phy"; ++ reg = <0x104000 0x1000>, ++ <0x032000 0x1000>; ++ reg-names = "dmp", "ccb-mii"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; + }; + + pcie0: pcie@18012000 { +@@ -483,6 +511,7 @@ pcie0: pcie@18012000 { + */ + ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; + ++ dma-coherent; + status = "disabled"; + + msi-parent = <&msi0>; +@@ -519,6 +548,7 @@ pcie1: pcie@18013000 { + */ + ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; + ++ dma-coherent; + status = "disabled"; + + msi-parent = <&msi1>; +@@ -555,6 +585,7 @@ pcie2: pcie@18014000 { + */ + ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; + ++ dma-coherent; + status = "disabled"; + + msi-parent = <&msi2>; +diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +index d0704540db6b..9f866491efdf 100644 +--- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts ++++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +@@ -99,3 +99,9 @@ i2s_alt0: i2s_alt0 { + &hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + }; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_gpio14>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts +index 46d078e29017..4b1af06c8dc0 100644 +--- a/arch/arm/boot/dts/bcm2835-rpi-a.dts ++++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts +@@ -94,3 +94,9 @@ i2s_alt2: i2s_alt2 { + &hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; + }; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_gpio14>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +index 432088ebb0a1..a846f1e781d8 100644 +--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts ++++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +@@ -101,3 +101,9 @@ i2s_alt0: i2s_alt0 { + &hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + }; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_gpio14>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +index 4133bc2cd9be..e860964e39fa 100644 +--- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts ++++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +@@ -94,3 +94,9 @@ i2s_alt2: i2s_alt2 { + &hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + }; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_gpio14>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts +index 4d56fe3006b0..5d77f3f8c4c5 100644 +--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts ++++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts +@@ -89,3 +89,9 @@ &gpio { + &hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; + }; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_gpio14>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +new file mode 100644 +index 000000000000..82651c3eb682 +--- /dev/null ++++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +@@ -0,0 +1,139 @@ ++/* ++ * Copyright (C) 2017 Stefan Wahren ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/dts-v1/; ++#include "bcm2835.dtsi" ++#include "bcm2835-rpi.dtsi" ++#include "bcm283x-rpi-usb-host.dtsi" ++ ++/ { ++ compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; ++ model = "Raspberry Pi Zero W"; ++ ++ /* Needed by firmware to properly init UARTs */ ++ aliases { ++ uart0 = "/soc/serial@7e201000"; ++ uart1 = "/soc/serial@7e215040"; ++ serial0 = "/soc/serial@7e201000"; ++ serial1 = "/soc/serial@7e215040"; ++ }; ++ ++ leds { ++ act { ++ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wl_on>; ++ reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&gpio { ++ /* ++ * This is based on the official GPU firmware DT blob. ++ * ++ * Legend: ++ * "NC" = not connected (no rail from the SoC) ++ * "FOO" = GPIO line named "FOO" on the schematic ++ * "FOO_N" = GPIO line named "FOO" on schematic, active low ++ */ ++ gpio-line-names = "GPIO0", ++ "GPIO1", ++ "SDA1", ++ "SCL1", ++ "GPIO_GCLK", ++ "GPIO5", ++ "GPIO6", ++ "SPI_CE1_N", ++ "SPI_CE0_N", ++ "SPI_MISO", ++ "SPI_MOSI", ++ "SPI_SCLK", ++ "GPIO12", ++ "GPIO13", ++ /* Serial port */ ++ "TXD0", ++ "RXD0", ++ "GPIO16", ++ "GPIO17", ++ "GPIO18", ++ "GPIO19", ++ "GPIO20", ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "GPIO26", ++ "GPIO27", ++ "SDA0", ++ "SCL0", ++ "NC", /* GPIO30 */ ++ "NC", /* GPIO31 */ ++ "NC", /* GPIO32 */ ++ "NC", /* GPIO33 */ ++ "NC", /* GPIO34 */ ++ "NC", /* GPIO35 */ ++ "NC", /* GPIO36 */ ++ "NC", /* GPIO37 */ ++ "NC", /* GPIO38 */ ++ "NC", /* GPIO39 */ ++ "CAM_GPIO1", /* GPIO40 */ ++ "WL_ON", /* GPIO41 */ ++ "NC", /* GPIO42 */ ++ "WIFI_CLK", /* GPIO43 */ ++ "CAM_GPIO0", /* GPIO44 */ ++ "BT_ON", /* GPIO45 */ ++ "HDMI_HPD_N", ++ "STATUS_LED_N", ++ /* Used by SD Card */ ++ "SD_CLK_R", ++ "SD_CMD_R", ++ "SD_DATA0_R", ++ "SD_DATA1_R", ++ "SD_DATA2_R", ++ "SD_DATA3_R"; ++ ++ pinctrl-0 = <&gpioout &alt0>; ++ ++ wl_on: wl-on { ++ brcm,pins = <41>; ++ brcm,function = ; ++ }; ++}; ++ ++&hdmi { ++ hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; ++}; ++ ++&sdhci { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ non-removable; ++ status = "okay"; ++ ++ brcmf: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_gpio14>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts +index 79a20d520931..70362405c595 100644 +--- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts ++++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts +@@ -103,3 +103,9 @@ i2s_alt0: i2s_alt0 { + &hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + }; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_gpio14>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi +index e55b362b9d6e..e36c392a2b8f 100644 +--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi ++++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi +@@ -39,7 +39,7 @@ gpioout: gpioout { + }; + + alt0: alt0 { +- brcm,pins = <4 5 7 8 9 10 11 14 15>; ++ brcm,pins = <4 5 7 8 9 10 11>; + brcm,function = ; + }; + }; +diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +index bf19e8cfb9e6..e8de41444b68 100644 +--- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts ++++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +@@ -39,3 +39,9 @@ i2s_alt0: i2s_alt0 { + &hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + }; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_gpio14>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi +index da3deeb42592..2c26d0be8b03 100644 +--- a/arch/arm/boot/dts/bcm2836.dtsi ++++ b/arch/arm/boot/dts/bcm2836.dtsi +@@ -36,6 +36,7 @@ timer { + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; ++ enable-method = "brcm,bcm2836-smp"; + + v7_cpu0: cpu@0 { + device_type = "cpu"; +diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +index c72a27d908b6..20725ca487f3 100644 +--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts ++++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +@@ -1 +1,51 @@ +-#include "arm64/broadcom/bcm2837-rpi-3-b.dts" ++/dts-v1/; ++#include "bcm2837.dtsi" ++#include "bcm2835-rpi.dtsi" ++#include "bcm283x-rpi-smsc9514.dtsi" ++#include "bcm283x-rpi-usb-host.dtsi" ++ ++/ { ++ compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; ++ model = "Raspberry Pi 3 Model B"; ++ ++ memory { ++ reg = <0 0x40000000>; ++ }; ++ ++ leds { ++ act { ++ gpios = <&gpio 47 0>; ++ }; ++ }; ++}; ++ ++/* uart0 communicates with the BT module */ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>; ++ status = "okay"; ++}; ++ ++/* uart1 is mapped to the pin header */ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_gpio14>; ++ status = "okay"; ++}; ++ ++/* SDHCI is used to control the SDIO for wireless */ ++&sdhci { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_gpio34>; ++ status = "okay"; ++ bus-width = <4>; ++ non-removable; ++}; ++ ++/* SDHOST is used to drive the SD card */ ++&sdhost { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdhost_gpio48>; ++ status = "okay"; ++ bus-width = <4>; ++}; +diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi +new file mode 100644 +index 000000000000..bc1cca5cf43c +--- /dev/null ++++ b/arch/arm/boot/dts/bcm2837.dtsi +@@ -0,0 +1,87 @@ ++#include "bcm283x.dtsi" ++ ++/ { ++ compatible = "brcm,bcm2837"; ++ ++ soc { ++ ranges = <0x7e000000 0x3f000000 0x1000000>, ++ <0x40000000 0x40000000 0x00001000>; ++ dma-ranges = <0xc0000000 0x00000000 0x3f000000>; ++ ++ local_intc: local_intc { ++ compatible = "brcm,bcm2836-l1-intc"; ++ reg = <0x40000000 0x100>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&local_intc>; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv7-timer"; ++ interrupt-parent = <&local_intc>; ++ interrupts = <0>, // PHYS_SECURE_PPI ++ <1>, // PHYS_NONSECURE_PPI ++ <3>, // VIRT_PPI ++ <2>; // HYP_PPI ++ always-on; ++ }; ++ ++ cpus: cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0>; ++ enable-method = "spin-table"; ++ cpu-release-addr = <0x0 0x000000d8>; ++ }; ++ ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <1>; ++ enable-method = "spin-table"; ++ cpu-release-addr = <0x0 0x000000e0>; ++ }; ++ ++ cpu2: cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <2>; ++ enable-method = "spin-table"; ++ cpu-release-addr = <0x0 0x000000e8>; ++ }; ++ ++ cpu3: cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <3>; ++ enable-method = "spin-table"; ++ cpu-release-addr = <0x0 0x000000f0>; ++ }; ++ }; ++}; ++ ++/* Make the BCM2835-style global interrupt controller be a child of the ++ * CPU-local interrupt controller. ++ */ ++&intc { ++ compatible = "brcm,bcm2836-armctrl-ic"; ++ reg = <0x7e00b200 0x200>; ++ interrupt-parent = <&local_intc>; ++ interrupts = <8>; ++}; ++ ++&cpu_thermal { ++ coefficients = <(-538) 412000>; ++}; ++ ++/* enable thermal sensor with the correct compatible property set */ ++&thermal { ++ compatible = "brcm,bcm2837-thermal"; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +index 62e1427b3f10..8b64caabaad8 100644 +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -52,6 +52,10 @@ leds { + usb { + label = "bcm53xx:blue:usb"; + gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; ++ trigger-sources = <&ohci_port1>, <&ehci_port1>, ++ <&xhci_port1>, <&ohci_port2>, ++ <&ehci_port2>; ++ linux,default-trigger = "usbport"; + }; + + power0 { +diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +index a5647efe4118..d7c34fa72b4b 100644 +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -48,6 +48,9 @@ power1 { + usb { + label = "bcm53xx:blue:usb"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; ++ trigger-sources = <&ohci_port1>, <&ehci_port1>, ++ <&xhci_port1>; ++ linux,default-trigger = "usbport"; + }; + + wireless { +diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +index 19ee924d7d53..83a4c60bb431 100644 +--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts ++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +@@ -42,16 +42,22 @@ power-amber { + usb2 { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>; ++ trigger-sources = <&ohci_port2>, <&ehci_port2>; ++ linux,default-trigger = "usbport"; + }; + + usb3-white { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; ++ trigger-sources = <&xhci_port1>; ++ linux,default-trigger = "usbport"; + }; + + usb3-green { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; ++ trigger-sources = <&ohci_port1>, <&ehci_port1>; ++ linux,default-trigger = "usbport"; + }; + + wps { +diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts +index a854a5174b7f..3ed8de42cb48 100644 +--- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts ++++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts +@@ -36,6 +36,8 @@ lan { + usb2-port1 { + label = "bcm53xx:green:usb2-port1"; + gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; ++ trigger-sources = <&ohci_port1>, <&ehci_port1>; ++ linux,default-trigger = "usbport"; + }; + + power { +@@ -67,6 +69,8 @@ wan-amber { + usb2-port2 { + label = "bcm53xx:green:usb2-port2"; + gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; ++ trigger-sources = <&ohci_port2>, <&ehci_port2>; ++ linux,default-trigger = "usbport"; + }; + }; + +diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts +index 97aa5d59a1d8..ec4a50e440f6 100644 +--- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts ++++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts +@@ -46,11 +46,16 @@ wps { + usb3 { + label = "bcm53xx:blue:usb3"; + gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; ++ trigger-sources = <&ohci_port1>, <&ehci_port1>, ++ <&xhci_port1>; ++ linux,default-trigger = "usbport"; + }; + + usb2 { + label = "bcm53xx:blue:usb2"; + gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; ++ trigger-sources = <&ohci_port2>, <&ehci_port2>; ++ linux,default-trigger = "usbport"; + }; + + wan-blue { +diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +index 51b0641b5f79..7cc7d344fe5b 100644 +--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts ++++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +@@ -71,6 +71,9 @@ wan-amber { + usb3-white { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; ++ trigger-sources = <&ohci_port1>, <&ehci_port1>, ++ <&xhci_port1>; ++ linux,default-trigger = "usbport"; + }; + + 2ghz { +diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +index 5f8621d00c50..bc1d1e10d4ac 100644 +--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts ++++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +@@ -59,6 +59,9 @@ lan2 { + usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; ++ trigger-sources = <&ohci_port1>, <&ehci_port1>, ++ <&xhci_port1>; ++ linux,default-trigger = "usbport"; + }; + + status { +diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +index 34417dac1cd0..19e61b5b066c 100644 +--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts ++++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +@@ -26,6 +26,8 @@ leds { + usb { + label = "bcm53xx:blue:usb"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; ++ trigger-sources = <&ohci_port1>, <&ehci_port1>; ++ linux,default-trigger = "usbport"; + }; + + wps { +diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi +index 98647d22b291..045b9bb857f9 100644 +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -272,6 +272,19 @@ ehci: ehci@21000 { + reg = <0x00021000 0x1000>; + interrupts = ; + phys = <&usb2_phy>; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ehci_port1: port@1 { ++ reg = <1>; ++ #trigger-source-cells = <0>; ++ }; ++ ++ ehci_port2: port@2 { ++ reg = <2>; ++ #trigger-source-cells = <0>; ++ }; + }; + + ohci: ohci@22000 { +@@ -280,6 +293,19 @@ ohci: ohci@22000 { + compatible = "generic-ohci"; + reg = <0x00022000 0x1000>; + interrupts = ; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ohci_port1: port@1 { ++ reg = <1>; ++ #trigger-source-cells = <0>; ++ }; ++ ++ ohci_port2: port@2 { ++ reg = <2>; ++ #trigger-source-cells = <0>; ++ }; + }; + }; + +@@ -300,6 +326,14 @@ xhci: xhci@23000 { + interrupts = ; + phys = <&usb3_phy>; + phy-names = "usb"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ xhci_port1: port@1 { ++ reg = <1>; ++ #trigger-source-cells = <0>; ++ }; + }; + }; + +diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi +index eae623f76401..c698a565b8ae 100644 +--- a/arch/arm/boot/dts/bcm53573.dtsi ++++ b/arch/arm/boot/dts/bcm53573.dtsi +@@ -138,10 +138,12 @@ ehci: ehci@4000 { + + ehci_port1: port@1 { + reg = <1>; ++ #trigger-source-cells = <0>; + }; + + ehci_port2: port@2 { + reg = <2>; ++ #trigger-source-cells = <0>; + }; + }; + +@@ -158,10 +160,12 @@ ohci: ohci@d000 { + + ohci_port1: port@1 { + reg = <1>; ++ #trigger-source-cells = <0>; + }; + + ohci_port2: port@2 { + reg = <2>; ++ #trigger-source-cells = <0>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts +index 000f5f19215e..53f990defd6a 100644 +--- a/arch/arm/boot/dts/bcm911360_entphn.dts ++++ b/arch/arm/boot/dts/bcm911360_entphn.dts +@@ -39,9 +39,12 @@ / { + model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)"; + compatible = "brcm,bcm11360", "brcm,cygnus"; + ++ aliases { ++ serial0 = &uart3; ++ }; ++ + chosen { +- stdout-path = &uart3; +- bootargs = "console=ttyS0,115200"; ++ stdout-path = "serial0:115200n8"; + }; + + gpio_keys { +diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/bcm947189acdbmr.dts +new file mode 100644 +index 000000000000..ef263412fea5 +--- /dev/null ++++ b/arch/arm/boot/dts/bcm947189acdbmr.dts +@@ -0,0 +1,97 @@ ++/* ++ * Copyright (C) 2017 Broadcom ++ * Author: Florian Fainelli ++ * ++ * Licensed under the ISC license. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm53573.dtsi" ++ ++/ { ++ compatible = "brcm,bcm947189acdbmr", "brcm,bcm47189", "brcm,bcm53573"; ++ model = "Broadcom BCM947189ACDBMR"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200 earlycon"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ wps { ++ label = "bcm53xx:blue:wps"; ++ gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ 5ghz { ++ label = "bcm53xx:blue:5ghz"; ++ gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ 2ghz { ++ label = "bcm53xx:blue:2ghz"; ++ gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ restart { ++ label = "Reset"; ++ linux,code = ; ++ gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ wps { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ spi { ++ compatible = "spi-gpio"; ++ num-chipselects = <1>; ++ gpio-sck = <&chipcommon 21 0>; ++ gpio-miso = <&chipcommon 22 0>; ++ gpio-mosi = <&chipcommon 23 0>; ++ cs-gpios = <&chipcommon 24 0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* External BCM6802 MoCA chip is connected */ ++ }; ++}; ++ ++&pcie0 { ++ ranges = <0x00000000 0 0 0 0 0x00100000>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ bridge@0,0,0 { ++ reg = <0x0000 0 0 0 0>; ++ ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ wifi@0,1,0 { ++ reg = <0x0000 0 0 0 0>; ++ ranges = <0x00000000 0 0 0 0x00100000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++ }; ++}; ++ ++&usb2 { ++ vcc-gpio = <&chipcommon 8 GPIO_ACTIVE_HIGH>; ++}; +diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts +index f5c42962c201..f9dd342cc2ae 100644 +--- a/arch/arm/boot/dts/bcm958522er.dts ++++ b/arch/arm/boot/dts/bcm958522er.dts +@@ -170,3 +170,11 @@ partition@700000 { + &uart0 { + status = "okay"; + }; ++ ++&usb3_phy { ++ status = "okay"; ++}; ++ ++&xhci { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts +index efcb1f67bdad..374508a9cfbf 100644 +--- a/arch/arm/boot/dts/bcm958525er.dts ++++ b/arch/arm/boot/dts/bcm958525er.dts +@@ -182,3 +182,11 @@ &sata { + &uart0 { + status = "okay"; + }; ++ ++&usb3_phy { ++ status = "okay"; ++}; ++ ++&xhci { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts +index b335ce02e32f..403250c5ad8e 100644 +--- a/arch/arm/boot/dts/bcm958525xmc.dts ++++ b/arch/arm/boot/dts/bcm958525xmc.dts +@@ -202,3 +202,11 @@ &sdio { + &uart0 { + status = "okay"; + }; ++ ++&usb3_phy { ++ status = "okay"; ++}; ++ ++&xhci { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts +index 16ab2d82a14b..fd8b8c689ffe 100644 +--- a/arch/arm/boot/dts/bcm958622hr.dts ++++ b/arch/arm/boot/dts/bcm958622hr.dts +@@ -219,3 +219,11 @@ fixed-link { + &uart0 { + status = "okay"; + }; ++ ++&usb3_phy { ++ status = "okay"; ++}; ++ ++&xhci { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts +index 9b921c6aa8f8..3bc50849d013 100644 +--- a/arch/arm/boot/dts/bcm958623hr.dts ++++ b/arch/arm/boot/dts/bcm958623hr.dts +@@ -227,3 +227,11 @@ fixed-link { + &uart0 { + status = "okay"; + }; ++ ++&usb3_phy { ++ status = "okay"; ++}; ++ ++&xhci { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts +index 006b08e41a3b..d94d14b3c745 100644 +--- a/arch/arm/boot/dts/bcm958625hr.dts ++++ b/arch/arm/boot/dts/bcm958625hr.dts +@@ -229,3 +229,11 @@ fixed-link { + &uart0 { + status = "okay"; + }; ++ ++&usb3_phy { ++ status = "okay"; ++}; ++ ++&xhci { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts +index 64740f85cf4c..2cf2392483b2 100644 +--- a/arch/arm/boot/dts/bcm958625k.dts ++++ b/arch/arm/boot/dts/bcm958625k.dts +@@ -264,3 +264,11 @@ &uart0 { + &uart1 { + status = "okay"; + }; ++ ++&usb3_phy { ++ status = "okay"; ++}; ++ ++&xhci { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts +index 45983c04a8a7..413dbd5d9f64 100644 +--- a/arch/arm/boot/dts/da850-lego-ev3.dts ++++ b/arch/arm/boot/dts/da850-lego-ev3.dts +@@ -249,6 +249,15 @@ battery_pins: pinmux_battery_pins { + 0x4c 0x00000080 0x000000f0 + >; + }; ++ ++ ev3_lcd_pins: pinmux_lcd { ++ pinctrl-single,bits = < ++ /* SIMO, GP2[11], GP2[12], CLK */ ++ 0x14 0x00188100 0x00ffff00 ++ /* GP5[0] */ ++ 0x30 0x80000000 0xf0000000 ++ >; ++ }; + }; + + &pinconf { +@@ -357,6 +366,21 @@ adc: adc@3 { + }; + }; + ++&spi1 { ++ status = "okay"; ++ pinctrl-0 = <&ev3_lcd_pins>; ++ pinctrl-names = "default"; ++ cs-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; ++ ++ display@0{ ++ compatible = "lego,ev3-lcd"; ++ reg = <0>; ++ spi-max-frequency = <10000000>; ++ a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ + &ehrpwm0 { + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/dove-d3plug.dts b/arch/arm/boot/dts/dove-d3plug.dts +index f5f59bb5a534..e88ff83f1dec 100644 +--- a/arch/arm/boot/dts/dove-d3plug.dts ++++ b/arch/arm/boot/dts/dove-d3plug.dts +@@ -88,7 +88,7 @@ spi-flash@0 { + &pcie { + status = "okay"; + /* Fresco Logic USB3.0 xHCI controller */ +- pcie-port@0 { ++ pcie@1 { + status = "okay"; + reset-gpios = <&gpio0 26 1>; + reset-delay-us = <20000>; +@@ -96,7 +96,7 @@ pcie-port@0 { + pinctrl-names = "default"; + }; + /* Mini-PCIe slot */ +- pcie-port@1 { ++ pcie@2 { + status = "okay"; + reset-gpios = <&gpio0 25 1>; + }; +diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi +index 698d58cea20d..1475d3672e56 100644 +--- a/arch/arm/boot/dts/dove.dtsi ++++ b/arch/arm/boot/dts/dove.dtsi +@@ -89,7 +89,7 @@ MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */ + MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ + MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ + +- pcie: pcie-controller { ++ pcie: pcie { + compatible = "marvell,dove-pcie"; + status = "disabled"; + device_type = "pci"; +@@ -106,7 +106,7 @@ pcie: pcie-controller { + 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ + 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ + +- pcie0: pcie-port@0 { ++ pcie0: pcie@1 { + device_type = "pci"; + status = "disabled"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +@@ -118,13 +118,14 @@ pcie0: pcie-port@0 { + #size-cells = <2>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ bus-range = <0x00 0xff>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 16>; + }; + +- pcie1: pcie-port@1 { ++ pcie1: pcie@2 { + device_type = "pci"; + status = "disabled"; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; +@@ -136,6 +137,7 @@ pcie1: pcie-port@1 { + #size-cells = <2>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; ++ bus-range = <0x00 0xff>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; +diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi +new file mode 100644 +index 000000000000..343e95f9a001 +--- /dev/null ++++ b/arch/arm/boot/dts/dra7-evm-common.dtsi +@@ -0,0 +1,258 @@ ++/* ++ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++/ { ++ chosen { ++ stdout-path = &uart1; ++ }; ++ ++ extcon_usb1: extcon_usb1 { ++ compatible = "linux,extcon-usb-gpio"; ++ id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ sound0: sound0 { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "DRA7xx-EVM"; ++ simple-audio-card,widgets = ++ "Headphone", "Headphone Jack", ++ "Line", "Line Out", ++ "Microphone", "Mic Jack", ++ "Line", "Line In"; ++ simple-audio-card,routing = ++ "Headphone Jack", "HPLOUT", ++ "Headphone Jack", "HPROUT", ++ "Line Out", "LLOUT", ++ "Line Out", "RLOUT", ++ "MIC3L", "Mic Jack", ++ "MIC3R", "Mic Jack", ++ "Mic Jack", "Mic Bias", ++ "LINE1L", "Line In", ++ "LINE1R", "Line In"; ++ simple-audio-card,format = "dsp_b"; ++ simple-audio-card,bitclock-master = <&sound0_master>; ++ simple-audio-card,frame-master = <&sound0_master>; ++ simple-audio-card,bitclock-inversion; ++ ++ sound0_master: simple-audio-card,cpu { ++ sound-dai = <&mcasp3>; ++ system-clock-frequency = <5644800>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&tlv320aic3106>; ++ clocks = <&atl_clkin2_ck>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ led0 { ++ label = "dra7:usr1"; ++ gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ ++ led1 { ++ label = "dra7:usr2"; ++ gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ ++ led2 { ++ label = "dra7:usr3"; ++ gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ ++ led3 { ++ label = "dra7:usr4"; ++ gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ autorepeat; ++ ++ USER1 { ++ label = "btnUser1"; ++ linux,code = ; ++ gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>; ++ }; ++ ++ USER2 { ++ label = "btnUser2"; ++ linux,code = ; ++ gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&i2c3 { ++ status = "okay"; ++ clock-frequency = <400000>; ++}; ++ ++&mcspi1 { ++ status = "okay"; ++}; ++ ++&mcspi2 { ++ status = "okay"; ++}; ++ ++&uart1 { ++ status = "okay"; ++ interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, ++ <&dra7_pmx_core 0x3e0>; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&uart3 { ++ status = "okay"; ++}; ++ ++&qspi { ++ status = "okay"; ++ ++ spi-max-frequency = <76800000>; ++ m25p80@0 { ++ compatible = "s25fl256s1"; ++ spi-max-frequency = <76800000>; ++ reg = <0>; ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <4>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ /* MTD partition table. ++ * The ROM checks the first four physical blocks ++ * for a valid file to boot and the flash here is ++ * 64KiB block size. ++ */ ++ partition@0 { ++ label = "QSPI.SPL"; ++ reg = <0x00000000 0x000010000>; ++ }; ++ partition@1 { ++ label = "QSPI.SPL.backup1"; ++ reg = <0x00010000 0x00010000>; ++ }; ++ partition@2 { ++ label = "QSPI.SPL.backup2"; ++ reg = <0x00020000 0x00010000>; ++ }; ++ partition@3 { ++ label = "QSPI.SPL.backup3"; ++ reg = <0x00030000 0x00010000>; ++ }; ++ partition@4 { ++ label = "QSPI.u-boot"; ++ reg = <0x00040000 0x00100000>; ++ }; ++ partition@5 { ++ label = "QSPI.u-boot-spl-os"; ++ reg = <0x00140000 0x00080000>; ++ }; ++ partition@6 { ++ label = "QSPI.u-boot-env"; ++ reg = <0x001c0000 0x00010000>; ++ }; ++ partition@7 { ++ label = "QSPI.u-boot-env.backup1"; ++ reg = <0x001d0000 0x0010000>; ++ }; ++ partition@8 { ++ label = "QSPI.kernel"; ++ reg = <0x001e0000 0x0800000>; ++ }; ++ partition@9 { ++ label = "QSPI.file-system"; ++ reg = <0x009e0000 0x01620000>; ++ }; ++ }; ++}; ++ ++&omap_dwc3_1 { ++ extcon = <&extcon_usb1>; ++}; ++ ++&usb1 { ++ dr_mode = "otg"; ++ extcon = <&extcon_usb1>; ++}; ++ ++&usb2 { ++ dr_mode = "host"; ++}; ++ ++&atl { ++ assigned-clocks = <&abe_dpll_sys_clk_mux>, ++ <&atl_gfclk_mux>, ++ <&dpll_abe_ck>, ++ <&dpll_abe_m2x2_ck>, ++ <&atl_clkin2_ck>; ++ assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; ++ assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; ++ ++ status = "okay"; ++ ++ atl2 { ++ bws = ; ++ aws = ; ++ }; ++}; ++ ++&mcasp3 { ++ #sound-dai-cells = <0>; ++ ++ assigned-clocks = <&mcasp3_ahclkx_mux>; ++ assigned-clock-parents = <&atl_clkin2_ck>; ++ ++ status = "okay"; ++ ++ op-mode = <0>; /* MCASP_IIS_MODE */ ++ tdm-slots = <2>; ++ /* 4 serializer */ ++ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ ++ 1 2 0 0 ++ >; ++ tx-num-evt = <32>; ++ rx-num-evt = <32>; ++}; ++ ++&mailbox5 { ++ status = "okay"; ++ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { ++ status = "okay"; ++ }; ++ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { ++ status = "okay"; ++ }; ++}; ++ ++&mailbox6 { ++ status = "okay"; ++ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { ++ status = "okay"; ++ }; ++ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { ++ status = "okay"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts +index f47fc4daf062..aa426dabb6c3 100644 +--- a/arch/arm/boot/dts/dra7-evm.dts ++++ b/arch/arm/boot/dts/dra7-evm.dts +@@ -8,9 +8,8 @@ + /dts-v1/; + + #include "dra74x.dtsi" +-#include +-#include +-#include ++#include "dra7-evm-common.dtsi" ++#include "dra74x-mmc-iodelay.dtsi" + + / { + model = "TI DRA742"; +@@ -21,8 +20,12 @@ memory@0 { + reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ + }; + +- chosen { +- stdout-path = &uart1; ++ evm_1v8_sw: fixedregulator-evm_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "evm_1v8"; ++ vin-supply = <&smps9_reg>; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; + }; + + evm_3v3_sd: fixedregulator-sd { +@@ -51,11 +54,6 @@ aic_dvdd: fixedregulator-aic_dvdd { + regulator-max-microvolt = <1800000>; + }; + +- extcon_usb1: extcon_usb1 { +- compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; +- }; +- + extcon_usb2: extcon_usb2 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; +@@ -73,85 +71,6 @@ vtt_fixed: fixedregulator-vtt { + gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; + }; + +- sound0: sound0 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "DRA7xx-EVM"; +- simple-audio-card,widgets = +- "Headphone", "Headphone Jack", +- "Line", "Line Out", +- "Microphone", "Mic Jack", +- "Line", "Line In"; +- simple-audio-card,routing = +- "Headphone Jack", "HPLOUT", +- "Headphone Jack", "HPROUT", +- "Line Out", "LLOUT", +- "Line Out", "RLOUT", +- "MIC3L", "Mic Jack", +- "MIC3R", "Mic Jack", +- "Mic Jack", "Mic Bias", +- "LINE1L", "Line In", +- "LINE1R", "Line In"; +- simple-audio-card,format = "dsp_b"; +- simple-audio-card,bitclock-master = <&sound0_master>; +- simple-audio-card,frame-master = <&sound0_master>; +- simple-audio-card,bitclock-inversion; +- +- sound0_master: simple-audio-card,cpu { +- sound-dai = <&mcasp3>; +- system-clock-frequency = <5644800>; +- }; +- +- simple-audio-card,codec { +- sound-dai = <&tlv320aic3106>; +- clocks = <&atl_clkin2_ck>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- led0 { +- label = "dra7:usr1"; +- gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led1 { +- label = "dra7:usr2"; +- gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led2 { +- label = "dra7:usr3"; +- gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- +- led3 { +- label = "dra7:usr4"; +- gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- autorepeat; +- +- USER1 { +- label = "btnUser1"; +- linux,code = ; +- gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>; +- }; +- +- USER2 { +- label = "btnUser2"; +- linux,code = ; +- gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>; +- }; +- }; + }; + + &dra7_pmx_core { +@@ -406,137 +325,49 @@ p1 { + }; + }; + +-&i2c3 { +- status = "okay"; +- clock-frequency = <400000>; +-}; +- +-&mcspi1 { +- status = "okay"; +-}; +- +-&mcspi2 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +- interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, +- <&dra7_pmx_core 0x3e0>; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- + &mmc1 { + status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins_default>; + vmmc-supply = <&evm_3v3_sd>; +- vmmc_aux-supply = <&ldo1_reg>; ++ vqmmc-supply = <&ldo1_reg>; + bus-width = <4>; + /* + * SDCD signal is not being used here - using the fact that GPIO mode + * is always hardwired. + */ + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104"; ++ pinctrl-0 = <&mmc1_pins_default>; ++ pinctrl-1 = <&mmc1_pins_hs>; ++ pinctrl-2 = <&mmc1_pins_sdr12>; ++ pinctrl-3 = <&mmc1_pins_sdr25>; ++ pinctrl-4 = <&mmc1_pins_sdr50>; ++ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>; ++ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; ++ pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; ++ pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; + }; + + &mmc2 { + status = "okay"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc2_pins_default>; +- vmmc-supply = <&evm_3v3_sw>; ++ vmmc-supply = <&evm_1v8_sw>; + bus-width = <8>; ++ pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; ++ pinctrl-0 = <&mmc2_pins_default>; ++ pinctrl-1 = <&mmc2_pins_hs>; ++ pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>; ++ pinctrl-3 = <&mmc2_pins_ddr_rev20>; ++ pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>; ++ pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; + }; + + &cpu0 { + cpu0-supply = <&smps123_reg>; + }; + +-&qspi { +- status = "okay"; +- +- spi-max-frequency = <76800000>; +- m25p80@0 { +- compatible = "s25fl256s1"; +- spi-max-frequency = <76800000>; +- reg = <0>; +- spi-tx-bus-width = <1>; +- spi-rx-bus-width = <4>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- /* MTD partition table. +- * The ROM checks the first four physical blocks +- * for a valid file to boot and the flash here is +- * 64KiB block size. +- */ +- partition@0 { +- label = "QSPI.SPL"; +- reg = <0x00000000 0x000010000>; +- }; +- partition@1 { +- label = "QSPI.SPL.backup1"; +- reg = <0x00010000 0x00010000>; +- }; +- partition@2 { +- label = "QSPI.SPL.backup2"; +- reg = <0x00020000 0x00010000>; +- }; +- partition@3 { +- label = "QSPI.SPL.backup3"; +- reg = <0x00030000 0x00010000>; +- }; +- partition@4 { +- label = "QSPI.u-boot"; +- reg = <0x00040000 0x00100000>; +- }; +- partition@5 { +- label = "QSPI.u-boot-spl-os"; +- reg = <0x00140000 0x00080000>; +- }; +- partition@6 { +- label = "QSPI.u-boot-env"; +- reg = <0x001c0000 0x00010000>; +- }; +- partition@7 { +- label = "QSPI.u-boot-env.backup1"; +- reg = <0x001d0000 0x0010000>; +- }; +- partition@8 { +- label = "QSPI.kernel"; +- reg = <0x001e0000 0x0800000>; +- }; +- partition@9 { +- label = "QSPI.file-system"; +- reg = <0x009e0000 0x01620000>; +- }; +- }; +-}; +- +-&omap_dwc3_1 { +- extcon = <&extcon_usb1>; +-}; +- + &omap_dwc3_2 { + extcon = <&extcon_usb2>; + }; + +-&usb1 { +- dr_mode = "otg"; +- extcon = <&extcon_usb1>; +-}; +- +-&usb2 { +- dr_mode = "host"; +-}; +- + &elm { + status = "okay"; + }; +@@ -556,6 +387,7 @@ nand@0,0 { + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ++ ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; +@@ -666,57 +498,6 @@ &dcan1 { + pinctrl-2 = <&dcan1_pins_default>; + }; + +-&atl { +- assigned-clocks = <&abe_dpll_sys_clk_mux>, +- <&atl_gfclk_mux>, +- <&dpll_abe_ck>, +- <&dpll_abe_m2x2_ck>, +- <&atl_clkin2_ck>; +- assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; +- assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; +- +- status = "okay"; +- +- atl2 { +- bws = ; +- aws = ; +- }; +-}; +- +-&mcasp3 { +- #sound-dai-cells = <0>; +- +- assigned-clocks = <&mcasp3_ahclkx_mux>; +- assigned-clock-parents = <&atl_clkin2_ck>; +- +- status = "okay"; +- +- op-mode = <0>; /* MCASP_IIS_MODE */ +- tdm-slots = <2>; +- /* 4 serializer */ +- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ +- 1 2 0 0 +- >; +- tx-num-evt = <32>; +- rx-num-evt = <32>; +-}; +- +-&mailbox5 { ++&pcie1_rc { + status = "okay"; +- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { +- status = "okay"; +- }; +- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { +- status = "okay"; +- }; +-}; +- +-&mailbox6 { +- status = "okay"; +- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { +- status = "okay"; +- }; +- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { +- status = "okay"; +- }; + }; +diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi +index 0f0f6f58bd18..02a136a4661a 100644 +--- a/arch/arm/boot/dts/dra7.dtsi ++++ b/arch/arm/boot/dts/dra7.dtsi +@@ -196,6 +196,7 @@ dra7_pmx_core: pinmux@1400 { + scm_conf1: scm_conf@1c04 { + compatible = "syscon"; + reg = <0x1c04 0x0020>; ++ #syscon-cells = <2>; + }; + + scm_conf_pcie: scm_conf@1c24 { +@@ -287,7 +288,11 @@ axi@0 { + #address-cells = <1>; + ranges = <0x51000000 0x51000000 0x3000 + 0x0 0x20000000 0x10000000>; +- pcie1: pcie@51000000 { ++ /** ++ * To enable PCI endpoint mode, disable the pcie1_rc ++ * node and enable pcie1_ep mode. ++ */ ++ pcie1_rc: pcie@51000000 { + compatible = "ti,dra7-pcie"; + reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; + reg-names = "rc_dbics", "ti_conf", "config"; +@@ -309,12 +314,28 @@ pcie1: pcie@51000000 { + <0 0 0 2 &pcie1_intc 2>, + <0 0 0 3 &pcie1_intc 3>, + <0 0 0 4 &pcie1_intc 4>; ++ status = "disabled"; + pcie1_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; ++ ++ pcie1_ep: pcie_ep@51000000 { ++ compatible = "ti,dra7-pcie-ep"; ++ reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; ++ reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; ++ interrupts = <0 232 0x4>; ++ num-lanes = <1>; ++ num-ib-windows = <4>; ++ num-ob-windows = <16>; ++ ti,hwmods = "pcie1"; ++ phys = <&pcie1_phy>; ++ phy-names = "pcie-phy0"; ++ ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; ++ status = "disabled"; ++ }; + }; + + axi@1 { +@@ -418,6 +439,14 @@ dsp1_system: dsp_system@40d00000 { + reg = <0x40d00000 0x100>; + }; + ++ dra7_iodelay_core: padconf@4844a000 { ++ compatible = "ti,dra7-iodelay"; ++ reg = <0x4844a000 0x0d1c>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #pinctrl-cells = <2>; ++ }; ++ + sdma: dma-controller@4a056000 { + compatible = "ti,omap4430-sdma"; + reg = <0x4a056000 0x1000>; +@@ -1037,6 +1066,7 @@ mmc1: mmc@4809c000 { + dma-names = "tx", "rx"; + status = "disabled"; + pbias-supply = <&pbias_mmc_reg>; ++ max-frequency = <192000000>; + }; + + mmc2: mmc@480b4000 { +@@ -1048,6 +1078,7 @@ mmc2: mmc@480b4000 { + dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; + dma-names = "tx", "rx"; + status = "disabled"; ++ max-frequency = <192000000>; + }; + + mmc3: mmc@480ad000 { +@@ -1059,6 +1090,8 @@ mmc3: mmc@480ad000 { + dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; + dma-names = "tx", "rx"; + status = "disabled"; ++ /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ ++ max-frequency = <64000000>; + }; + + mmc4: mmc@480d1000 { +@@ -1070,6 +1103,7 @@ mmc4: mmc@480d1000 { + dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; + dma-names = "tx", "rx"; + status = "disabled"; ++ max-frequency = <192000000>; + }; + + mmu0_dsp1: mmu@40d01000 { +diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts +index 9897e8fa6845..41c9132eb550 100644 +--- a/arch/arm/boot/dts/dra71-evm.dts ++++ b/arch/arm/boot/dts/dra71-evm.dts +@@ -7,6 +7,7 @@ + */ + + #include "dra72-evm-common.dtsi" ++#include "dra72x-mmc-iodelay.dtsi" + #include + + / { +@@ -32,6 +33,16 @@ vpo_sd_1v8_3v3: gpio-regulator-TPS74801 { + 3000000 0x1>; + }; + ++ evm_1v8_sw: fixedregulator-evm_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "evm_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&lp8732_buck0_reg>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ + poweroff: gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>; +@@ -162,7 +173,24 @@ p0 { + }; + + &mmc1 { +- vmmc_aux-supply = <&vpo_sd_1v8_3v3>; ++ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; ++ pinctrl-0 = <&mmc1_pins_default>; ++ pinctrl-1 = <&mmc1_pins_hs>; ++ pinctrl-2 = <&mmc1_pins_sdr12>; ++ pinctrl-3 = <&mmc1_pins_sdr25>; ++ pinctrl-4 = <&mmc1_pins_sdr50>; ++ pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; ++ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; ++ vqmmc-supply = <&vpo_sd_1v8_3v3>; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; ++ pinctrl-0 = <&mmc2_pins_default>; ++ pinctrl-1 = <&mmc2_pins_hs>; ++ pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; ++ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; ++ vmmc-supply = <&evm_1v8_sw>; + }; + + &mac { +diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi +index 85780549bc26..2e485a13dfd7 100644 +--- a/arch/arm/boot/dts/dra72-evm-common.dtsi ++++ b/arch/arm/boot/dts/dra72-evm-common.dtsi +@@ -311,6 +311,7 @@ nand@0,0 { + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ++ ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; +@@ -419,8 +420,6 @@ &mmc2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; +- +- vmmc-supply = <&evm_3v3_sw>; + bus-width = <8>; + ti,non-removable; + max-frequency = <192000000>; +@@ -564,3 +563,7 @@ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; + }; ++ ++&pcie1_rc { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts +index 6f9b6f31437e..bf588d00728d 100644 +--- a/arch/arm/boot/dts/dra72-evm-revc.dts ++++ b/arch/arm/boot/dts/dra72-evm-revc.dts +@@ -6,6 +6,7 @@ + * published by the Free Software Foundation. + */ + #include "dra72-evm-common.dtsi" ++#include "dra72x-mmc-iodelay.dtsi" + #include + + / { +@@ -15,6 +16,16 @@ memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ + }; ++ ++ evm_1v8_sw: fixedregulator-evm_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "evm_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&smps4_reg>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; + }; + + &i2c1 { +@@ -84,3 +95,24 @@ dp83867_1: ethernet-phy@3 { + ti,dp83867-rxctrl-strap-quirk; + }; + }; ++ ++&mmc1 { ++ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; ++ pinctrl-0 = <&mmc1_pins_default>; ++ pinctrl-1 = <&mmc1_pins_hs>; ++ pinctrl-2 = <&mmc1_pins_sdr12>; ++ pinctrl-3 = <&mmc1_pins_sdr25>; ++ pinctrl-4 = <&mmc1_pins_sdr50>; ++ pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; ++ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; ++ vqmmc-supply = <&ldo1_reg>; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; ++ pinctrl-0 = <&mmc2_pins_default>; ++ pinctrl-1 = <&mmc2_pins_hs>; ++ pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; ++ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; ++ vmmc-supply = <&evm_1v8_sw>; ++}; +diff --git a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi +index e6df676886c0..57bfe5caf5e4 100644 +--- a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi ++++ b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi +@@ -146,5 +146,5 @@ &dss { + }; + + &mmc1 { +- vmmc_aux-supply = <&ldo1_reg>; ++ vqmmc-supply = <&ldo1_reg>; + }; +diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts +index cd9c4ff12654..c572693b1665 100644 +--- a/arch/arm/boot/dts/dra72-evm.dts ++++ b/arch/arm/boot/dts/dra72-evm.dts +@@ -6,6 +6,7 @@ + * published by the Free Software Foundation. + */ + #include "dra72-evm-common.dtsi" ++#include "dra72x-mmc-iodelay.dtsi" + / { + model = "TI DRA722"; + +@@ -13,6 +14,16 @@ memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ + }; ++ ++ evm_1v8_sw: fixedregulator-evm_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "evm_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&smps4_reg>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; + }; + + &i2c1 { +@@ -43,3 +54,24 @@ &cpsw_emac0 { + phy_id = <&davinci_mdio>, <3>; + phy-mode = "rgmii"; + }; ++ ++&mmc1 { ++ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; ++ pinctrl-0 = <&mmc1_pins_default>; ++ pinctrl-1 = <&mmc1_pins_hs>; ++ pinctrl-2 = <&mmc1_pins_sdr12>; ++ pinctrl-3 = <&mmc1_pins_sdr25>; ++ pinctrl-4 = <&mmc1_pins_sdr50>; ++ pinctrl-5 = <&mmc1_pins_ddr50_rev10>; ++ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>; ++ vqmmc-supply = <&ldo1_reg>; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; ++ pinctrl-0 = <&mmc2_pins_default>; ++ pinctrl-1 = <&mmc2_pins_hs>; ++ pinctrl-2 = <&mmc2_pins_ddr_rev10>; ++ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>; ++ vmmc-supply = <&evm_1v8_sw>; ++}; +diff --git a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi +new file mode 100644 +index 000000000000..088013c6dc6e +--- /dev/null ++++ b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi +@@ -0,0 +1,350 @@ ++/* ++ * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs. ++ * ++ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/* ++ * Rules for modifying this file: ++ * a) Update of this file should typically correspond to a datamanual revision. ++ * Datamanual revision that was used should be updated in comment below. ++ * If there is no update to datamanual, do not update the values. If you ++ * need to use values different from that recommended by the datamanual ++ * for your design, then you should consider adding values to the device- ++ * -tree file for your board directly. ++ * b) We keep the mode names as close to the datamanual as possible. So ++ * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, ++ * we follow that in code too. ++ * c) If the values change between multiple revisions of silicon, we add ++ * a revision tag to both the new and old entry. Use 'rev10' for PG 1.0, ++ * 'rev20' for PG 2.0 and so on. ++ * d) The node name and node label should be the exact same string. This is ++ * to curb naming creativity and achieve consistency. ++ * e) If in future, DRA71x and DRA72x values differ, then add 'dra71_' and ++ * 'dra72_' tag to entries. Both the new and old entries should gain a tag. ++ * ++ * Datamanual Revisions: ++ * ++ * AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017 ++ * AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017 ++ * DRA71x : SPRS960B, Revised February 2017 ++ */ ++ ++&dra7_pmx_core { ++ mmc1_pins_default: mmc1_pins_default { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc1_pins_sdr12: mmc1_pins_sdr12 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc1_pins_hs: mmc1_pins_hs { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc1_pins_sdr25: mmc1_pins_sdr25 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc1_pins_sdr50: mmc1_pins_sdr50 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_clk.mmc1_clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ ++ DRA7XX_CORE_IOPAD(0x375C, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ ++ >; ++ }; ++ ++ mmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc1_pins_sdr104: mmc1_pins_sdr104 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc2_pins_default: mmc2_pins_default { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ ++ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ ++ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ ++ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ ++ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ ++ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ ++ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ ++ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ ++ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ ++ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ ++ >; ++ }; ++ ++ mmc2_pins_hs: mmc2_pins_hs { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ ++ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ ++ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ ++ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ ++ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ ++ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ ++ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ ++ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ ++ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ ++ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ ++ >; ++ }; ++ ++ mmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ ++ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ ++ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ ++ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ ++ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ ++ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ ++ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ ++ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ ++ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ ++ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ ++ >; ++ }; ++ ++ mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ ++ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ ++ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ ++ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ ++ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ ++ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ ++ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ ++ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ ++ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ ++ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ ++ >; ++ }; ++ ++ mmc2_pins_hs200: mmc2_pins_hs200 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ ++ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ ++ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ ++ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ ++ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ ++ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ ++ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ ++ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ ++ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ ++ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ ++ >; ++ }; ++}; ++ ++&dra7_iodelay_core { ++ ++ /* Corresponds to MMC1_MANUAL1 in datamanual */ ++ mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf { ++ pinctrl-pin-array = < ++ 0x618 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ ++ 0x624 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ ++ 0x630 A_DELAY_PS(1375) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ ++ 0x63C A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ ++ 0x648 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ ++ 0x654 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ ++ 0x620 A_DELAY_PS(1230) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ ++ 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ ++ 0x638 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ ++ 0x644 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ ++ 0x650 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ ++ 0x65C A_DELAY_PS(99) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ ++ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ ++ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ ++ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ ++ 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ ++ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ ++ >; ++ }; ++ ++ /* Corresponds to MMC1_MANUAL2 in datamanual */ ++ mmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf { ++ pinctrl-pin-array = < ++ 0x620 A_DELAY_PS(560) G_DELAY_PS(365) /* CFG_MMC1_CLK_OUT */ ++ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ ++ 0x638 A_DELAY_PS(29) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ ++ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ ++ 0x650 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ ++ 0x65c A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ ++ 0x628 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ ++ 0x634 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ ++ 0x640 A_DELAY_PS(433) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ ++ 0x64c A_DELAY_PS(287) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ ++ 0x658 A_DELAY_PS(351) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ ++ >; ++ }; ++ ++ /* Corresponds to MMC1_MANUAL2 in datamanual */ ++ mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { ++ pinctrl-pin-array = < ++ 0x620 A_DELAY_PS(520) G_DELAY_PS(320) /* CFG_MMC1_CLK_OUT */ ++ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ ++ 0x638 A_DELAY_PS(40) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ ++ 0x644 A_DELAY_PS(83) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ ++ 0x650 A_DELAY_PS(98) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ ++ 0x65c A_DELAY_PS(106) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ ++ 0x628 A_DELAY_PS(51) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ ++ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ ++ 0x640 A_DELAY_PS(363) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ ++ 0x64c A_DELAY_PS(199) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ ++ 0x658 A_DELAY_PS(273) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ ++ >; ++ }; ++ ++ /* Corresponds to MMC2_MANUAL1 in datamanual */ ++ mmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf { ++ pinctrl-pin-array = < ++ 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */ ++ 0x1a4 A_DELAY_PS(119) G_DELAY_PS(0) /* CFG_GPMC_A20_IN */ ++ 0x1b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_IN */ ++ 0x1bc A_DELAY_PS(18) G_DELAY_PS(0) /* CFG_GPMC_A22_IN */ ++ 0x1c8 A_DELAY_PS(894) G_DELAY_PS(0) /* CFG_GPMC_A23_IN */ ++ 0x1d4 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_IN */ ++ 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ ++ 0x1ec A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ ++ 0x1f8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_IN */ ++ 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ ++ 0x194 A_DELAY_PS(152) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ ++ 0x1ac A_DELAY_PS(206) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ ++ 0x1b8 A_DELAY_PS(78) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ ++ 0x1c4 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ ++ 0x1d0 A_DELAY_PS(266) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ ++ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ ++ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ ++ 0x1f4 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ ++ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ ++ 0x368 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ ++ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ ++ 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ ++ 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ ++ 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ ++ 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ ++ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ ++ 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ ++ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ ++ 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ ++ >; ++ }; ++ ++ /* Corresponds to MMC2_MANUAL3 in datamanual */ ++ mmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf { ++ pinctrl-pin-array = < ++ 0x194 A_DELAY_PS(150) G_DELAY_PS(95) /* CFG_GPMC_A19_OUT */ ++ 0x1ac A_DELAY_PS(250) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ ++ 0x1b8 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ ++ 0x1c4 A_DELAY_PS(100) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ ++ 0x1d0 A_DELAY_PS(870) G_DELAY_PS(415) /* CFG_GPMC_A23_OUT */ ++ 0x1dc A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ ++ 0x1e8 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ ++ 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ ++ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ ++ 0x368 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ ++ 0x190 A_DELAY_PS(695) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ ++ 0x1a8 A_DELAY_PS(924) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ ++ 0x1b4 A_DELAY_PS(719) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ ++ 0x1c0 A_DELAY_PS(824) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ ++ 0x1d8 A_DELAY_PS(877) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ ++ 0x1e4 A_DELAY_PS(446) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ ++ 0x1f0 A_DELAY_PS(847) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ ++ 0x1fc A_DELAY_PS(586) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ ++ 0x364 A_DELAY_PS(1039) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ ++ >; ++ }; ++ ++ /* Corresponds to MMC2_MANUAL3 in datamanual */ ++ mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf { ++ pinctrl-pin-array = < ++ 0x194 A_DELAY_PS(285) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ ++ 0x1ac A_DELAY_PS(189) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ ++ 0x1b8 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_OUT */ ++ 0x1c4 A_DELAY_PS(0) G_DELAY_PS(70) /* CFG_GPMC_A22_OUT */ ++ 0x1d0 A_DELAY_PS(730) G_DELAY_PS(360) /* CFG_GPMC_A23_OUT */ ++ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ ++ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ ++ 0x1f4 A_DELAY_PS(70) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ ++ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ ++ 0x368 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_CS1_OUT */ ++ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ ++ 0x1a8 A_DELAY_PS(231) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ ++ 0x1b4 A_DELAY_PS(39) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ ++ 0x1c0 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ ++ 0x1d8 A_DELAY_PS(176) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ ++ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ ++ 0x1f0 A_DELAY_PS(101) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ ++ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ ++ 0x364 A_DELAY_PS(360) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ ++ >; ++ }; ++}; +diff --git a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi +new file mode 100644 +index 000000000000..28ebb4eb884a +--- /dev/null ++++ b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi +@@ -0,0 +1,647 @@ ++/* ++ * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs. ++ * ++ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/* ++ * Rules for modifying this file: ++ * a) Update of this file should typically correspond to a datamanual revision. ++ * Datamanual revision that was used should be updated in comment below. ++ * If there is no update to datamanual, do not update the values. If you ++ * need to use values different from that recommended by the datamanual ++ * for your design, then you should consider adding values to the device- ++ * -tree file for your board directly. ++ * b) We keep the mode names as close to the datamanual as possible. So ++ * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, ++ * we follow that in code too. ++ * c) If the values change between multiple revisions of silicon, we add ++ * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, ++ * 'rev20' for PG 2.0 and so on. ++ * d) The node name and node label should be the exact same string. This is ++ * to curb naming creativity and achieve consistency. ++ * ++ * Datamanual Revisions: ++ * ++ * AM572x Silicon Revision 2.0: SPRS953B, Revised November 2016 ++ * AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016 ++ * ++ */ ++ ++&dra7_pmx_core { ++ mmc1_pins_default: mmc1_pins_default { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc1_pins_sdr12: mmc1_pins_sdr12 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc1_pins_hs: mmc1_pins_hs { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc1_pins_sdr25: mmc1_pins_sdr25 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc1_pins_sdr50: mmc1_pins_sdr50 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc1_pins_ddr50: mmc1_pins_ddr50 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc1_pins_sdr104: mmc1_pins_sdr104 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc2_pins_default: mmc2_pins_default { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ ++ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ ++ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ ++ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ ++ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ ++ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ ++ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ ++ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ ++ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ ++ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ ++ >; ++ }; ++ ++ mmc2_pins_hs: mmc2_pins_hs { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ ++ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ ++ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ ++ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ ++ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ ++ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ ++ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ ++ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ ++ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ ++ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ ++ >; ++ }; ++ ++ mmc2_pins_ddr_3_3v_rev11: mmc2_pins_ddr_3_3v_rev11 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ ++ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ ++ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ ++ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ ++ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ ++ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ ++ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ ++ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ ++ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ ++ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ ++ >; ++ }; ++ ++ mmc2_pins_ddr_1_8v_rev11: mmc2_pins_ddr_1_8v_rev11 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ ++ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ ++ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ ++ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ ++ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ ++ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ ++ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ ++ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ ++ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ ++ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ ++ >; ++ }; ++ ++ mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ ++ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ ++ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ ++ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ ++ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ ++ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ ++ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ ++ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ ++ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ ++ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ ++ >; ++ }; ++ ++ mmc2_pins_hs200: mmc2_pins_hs200 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ ++ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ ++ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ ++ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ ++ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ ++ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ ++ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ ++ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ ++ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ ++ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ ++ >; ++ }; ++ ++ mmc4_pins_default: mmc4_pins_default { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ ++ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ ++ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ ++ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ ++ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ ++ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ ++ >; ++ }; ++ ++ mmc4_pins_hs: mmc4_pins_hs { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ ++ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ ++ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ ++ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ ++ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ ++ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ ++ >; ++ }; ++ ++ mmc3_pins_default: mmc3_pins_default { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ ++ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ ++ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ ++ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ ++ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ ++ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ ++ >; ++ }; ++ ++ mmc3_pins_hs: mmc3_pins_hs { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ ++ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ ++ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ ++ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ ++ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ ++ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ ++ >; ++ }; ++ ++ mmc3_pins_sdr12: mmc3_pins_sdr12 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ ++ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ ++ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ ++ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ ++ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ ++ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ ++ >; ++ }; ++ ++ mmc3_pins_sdr25: mmc3_pins_sdr25 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ ++ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ ++ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ ++ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ ++ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ ++ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ ++ >; ++ }; ++ ++ mmc3_pins_sdr50: mmc3_pins_sdr50 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ ++ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ ++ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ ++ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ ++ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ ++ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ ++ >; ++ }; ++ ++ mmc4_pins_sdr12: mmc4_pins_sdr12 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ ++ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ ++ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ ++ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ ++ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ ++ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ ++ >; ++ }; ++ ++ mmc4_pins_sdr25: mmc4_pins_sdr25 { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ ++ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ ++ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ ++ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ ++ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ ++ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ ++ >; ++ }; ++}; ++ ++&dra7_iodelay_core { ++ ++ /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ ++ mmc1_iodelay_ddr_rev11_conf: mmc1_iodelay_ddr_rev11_conf { ++ pinctrl-pin-array = < ++ 0x618 A_DELAY_PS(572) G_DELAY_PS(540) /* CFG_MMC1_CLK_IN */ ++ 0x620 A_DELAY_PS(1525) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ ++ 0x624 A_DELAY_PS(0) G_DELAY_PS(600) /* CFG_MMC1_CMD_IN */ ++ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ ++ 0x62c A_DELAY_PS(55) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ ++ 0x630 A_DELAY_PS(403) G_DELAY_PS(120) /* CFG_MMC1_DAT0_IN */ ++ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ ++ 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ ++ 0x63c A_DELAY_PS(23) G_DELAY_PS(60) /* CFG_MMC1_DAT1_IN */ ++ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ ++ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ ++ 0x648 A_DELAY_PS(25) G_DELAY_PS(60) /* CFG_MMC1_DAT2_IN */ ++ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ ++ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ ++ 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ ++ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ ++ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ ++ >; ++ }; ++ ++ /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ ++ mmc1_iodelay_ddr_rev20_conf: mmc1_iodelay_ddr50_rev20_conf { ++ pinctrl-pin-array = < ++ 0x618 A_DELAY_PS(1076) G_DELAY_PS(330) /* CFG_MMC1_CLK_IN */ ++ 0x620 A_DELAY_PS(1271) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ ++ 0x624 A_DELAY_PS(722) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ ++ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ ++ 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ ++ 0x630 A_DELAY_PS(751) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ ++ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ ++ 0x638 A_DELAY_PS(20) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ ++ 0x63C A_DELAY_PS(256) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ ++ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ ++ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ ++ 0x648 A_DELAY_PS(263) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ ++ 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ ++ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ ++ 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ ++ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ ++ 0x65C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ ++ >; ++ }; ++ ++ /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ ++ mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf { ++ pinctrl-pin-array = < ++ 0x620 A_DELAY_PS(1063) G_DELAY_PS(17) /* CFG_MMC1_CLK_OUT */ ++ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ ++ 0x62c A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ ++ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ ++ 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ ++ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ ++ 0x644 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ ++ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ ++ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ ++ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ ++ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ ++ >; ++ }; ++ ++ /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ ++ mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { ++ pinctrl-pin-array = < ++ 0x620 A_DELAY_PS(600) G_DELAY_PS(400) /* CFG_MMC1_CLK_OUT */ ++ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ ++ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ ++ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ ++ 0x638 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ ++ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ ++ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ ++ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ ++ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ ++ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ ++ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ ++ >; ++ }; ++ ++ /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ ++ mmc2_iodelay_hs200_rev11_conf: mmc2_iodelay_hs200_rev11_conf { ++ pinctrl-pin-array = < ++ 0x190 A_DELAY_PS(621) G_DELAY_PS(600) /* CFG_GPMC_A19_OEN */ ++ 0x194 A_DELAY_PS(300) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ ++ 0x1a8 A_DELAY_PS(739) G_DELAY_PS(600) /* CFG_GPMC_A20_OEN */ ++ 0x1ac A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ ++ 0x1b4 A_DELAY_PS(812) G_DELAY_PS(600) /* CFG_GPMC_A21_OEN */ ++ 0x1b8 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ ++ 0x1c0 A_DELAY_PS(954) G_DELAY_PS(600) /* CFG_GPMC_A22_OEN */ ++ 0x1c4 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ ++ 0x1d0 A_DELAY_PS(1340) G_DELAY_PS(420) /* CFG_GPMC_A23_OUT */ ++ 0x1d8 A_DELAY_PS(935) G_DELAY_PS(600) /* CFG_GPMC_A24_OEN */ ++ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ ++ 0x1e4 A_DELAY_PS(525) G_DELAY_PS(600) /* CFG_GPMC_A25_OEN */ ++ 0x1e8 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ ++ 0x1f0 A_DELAY_PS(767) G_DELAY_PS(600) /* CFG_GPMC_A26_OEN */ ++ 0x1f4 A_DELAY_PS(225) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ ++ 0x1fc A_DELAY_PS(565) G_DELAY_PS(600) /* CFG_GPMC_A27_OEN */ ++ 0x200 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ ++ 0x364 A_DELAY_PS(969) G_DELAY_PS(600) /* CFG_GPMC_CS1_OEN */ ++ 0x368 A_DELAY_PS(180) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ ++ >; ++ }; ++ ++ /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ ++ mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf { ++ pinctrl-pin-array = < ++ 0x190 A_DELAY_PS(274) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ ++ 0x194 A_DELAY_PS(162) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ ++ 0x1a8 A_DELAY_PS(401) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ ++ 0x1ac A_DELAY_PS(73) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ ++ 0x1b4 A_DELAY_PS(465) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ ++ 0x1b8 A_DELAY_PS(115) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ ++ 0x1c0 A_DELAY_PS(633) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ ++ 0x1c4 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ ++ 0x1d0 A_DELAY_PS(935) G_DELAY_PS(280) /* CFG_GPMC_A23_OUT */ ++ 0x1d8 A_DELAY_PS(621) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ ++ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ ++ 0x1e4 A_DELAY_PS(183) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ ++ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ ++ 0x1f0 A_DELAY_PS(467) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ ++ 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ ++ 0x1fc A_DELAY_PS(262) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ ++ 0x200 A_DELAY_PS(46) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ ++ 0x364 A_DELAY_PS(684) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ ++ 0x368 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ ++ >; ++ }; ++ ++ /* Correspnds to MMC2_DDR_3V3_MANUAL1 in datamanual */ ++ mmc2_iodelay_ddr_3_3v_rev11_conf: mmc2_iodelay_ddr_3_3v_rev11_conf { ++ pinctrl-pin-array = < ++ 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ ++ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ ++ 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ ++ 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ ++ 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ ++ 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ ++ 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ ++ 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ ++ 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ ++ 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ ++ 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ ++ 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ ++ 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ ++ 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ ++ 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ ++ 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ ++ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ ++ 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ ++ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ ++ 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ ++ 0x1ec A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A26_IN */ ++ 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ ++ 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ ++ 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ ++ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ ++ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ ++ 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ ++ 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ ++ 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ ++ >; ++ }; ++ ++ /* Corresponds to MMC2_DDR_1V8_MANUAL1 in datamanual */ ++ mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf { ++ pinctrl-pin-array = < ++ 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */ ++ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ ++ 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ ++ 0x1a4 A_DELAY_PS(274) G_DELAY_PS(240) /* CFG_GPMC_A20_IN */ ++ 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ ++ 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ ++ 0x1b0 A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A21_IN */ ++ 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ ++ 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ ++ 0x1bc A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A22_IN */ ++ 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ ++ 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ ++ 0x1c8 A_DELAY_PS(514) G_DELAY_PS(360) /* CFG_GPMC_A23_IN */ ++ 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ ++ 0x1d4 A_DELAY_PS(187) G_DELAY_PS(120) /* CFG_GPMC_A24_IN */ ++ 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ ++ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ ++ 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ ++ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ ++ 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ ++ 0x1ec A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A26_IN */ ++ 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ ++ 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ ++ 0x1f8 A_DELAY_PS(121) G_DELAY_PS(60) /* CFG_GPMC_A27_IN */ ++ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ ++ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ ++ 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ ++ 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ ++ 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ ++ >; ++ }; ++ ++ /* Corresponds to MMC3_MANUAL1 in datamanual */ ++ mmc3_iodelay_manual1_rev20_conf: mmc3_iodelay_manual1_conf { ++ pinctrl-pin-array = < ++ 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ ++ 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ ++ 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ ++ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ ++ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ ++ 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ ++ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ ++ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ ++ 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ ++ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ ++ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ ++ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ ++ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ ++ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ ++ 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ ++ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ ++ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ ++ >; ++ }; ++ ++ /* Corresponds to MMC3_MANUAL1 in datamanual */ ++ mmc3_iodelay_manual1_rev11_conf: mmc3_iodelay_manual1_conf { ++ pinctrl-pin-array = < ++ 0x678 A_DELAY_PS(406) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ ++ 0x680 A_DELAY_PS(659) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ ++ 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ ++ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ ++ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ ++ 0x690 A_DELAY_PS(130) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ ++ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ ++ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ ++ 0x69c A_DELAY_PS(169) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ ++ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ ++ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ ++ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ ++ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ ++ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ ++ 0x6b4 A_DELAY_PS(457) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ ++ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ ++ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ ++ >; ++ }; ++ ++ /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ ++ mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf { ++ pinctrl-pin-array = < ++ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ ++ 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ ++ 0x84c A_DELAY_PS(96) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ ++ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ ++ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ ++ 0x870 A_DELAY_PS(582) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ ++ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ ++ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ ++ 0x87c A_DELAY_PS(391) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ ++ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ ++ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ ++ 0x888 A_DELAY_PS(561) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ ++ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ ++ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ ++ 0x894 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ ++ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ ++ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ ++ >; ++ }; ++ ++ /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ ++ mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf { ++ pinctrl-pin-array = < ++ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ ++ 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ ++ 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ ++ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ ++ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ ++ 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ ++ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ ++ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ ++ 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ ++ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ ++ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ ++ 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ ++ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ ++ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ ++ 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ ++ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ ++ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ ++ >; ++ }; ++ ++ /* Corresponds to MMC4_MANUAL1 in datamanual */ ++ mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf { ++ pinctrl-pin-array = < ++ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ ++ 0x848 A_DELAY_PS(2651) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ ++ 0x84c A_DELAY_PS(1572) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ ++ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ ++ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ ++ 0x870 A_DELAY_PS(1913) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ ++ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ ++ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ ++ 0x87c A_DELAY_PS(1721) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ ++ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ ++ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ ++ 0x888 A_DELAY_PS(1891) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ ++ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ ++ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ ++ 0x894 A_DELAY_PS(1919) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ ++ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ ++ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ ++ >; ++ }; ++ ++ /* Corresponds to MMC4_MANUAL1 in datamanual */ ++ mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf { ++ pinctrl-pin-array = < ++ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ ++ 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ ++ 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ ++ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ ++ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ ++ 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ ++ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ ++ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ ++ 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ ++ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ ++ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ ++ 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ ++ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ ++ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ ++ 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ ++ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ ++ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ ++ >; ++ }; ++}; +diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts +new file mode 100644 +index 000000000000..b024a65c6e27 +--- /dev/null ++++ b/arch/arm/boot/dts/dra76-evm.dts +@@ -0,0 +1,423 @@ ++/* ++ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++/dts-v1/; ++ ++#include "dra76x.dtsi" ++#include "dra7-evm-common.dtsi" ++#include ++ ++/ { ++ model = "TI DRA762 EVM"; ++ compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x80000000 0x0 0x80000000>; ++ }; ++ ++ vsys_12v0: fixedregulator-vsys12v0 { ++ /* main supply */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vsys_12v0"; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vsys_5v0: fixedregulator-vsys5v0 { ++ /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vsys_5v0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vsys_12v0>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vsys_3v3: fixedregulator-vsys3v3 { ++ /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vsys_3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vsys_12v0>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vio_3v3: fixedregulator-vio_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vio_3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vsys_3v3>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vio_3v3_sd: fixedregulator-sd { ++ compatible = "regulator-fixed"; ++ regulator-name = "vio_3v3_sd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vio_3v3>; ++ enable-active-high; ++ gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ vio_1v8: fixedregulator-vio_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vio_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&smps5_reg>; ++ }; ++ ++ vtt_fixed: fixedregulator-vtt { ++ compatible = "regulator-fixed"; ++ regulator-name = "vtt_fixed"; ++ regulator-min-microvolt = <1350000>; ++ regulator-max-microvolt = <1350000>; ++ vin-supply = <&vsys_3v3>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ aic_dvdd: fixedregulator-aic_dvdd { ++ /* TPS77018DBVT */ ++ compatible = "regulator-fixed"; ++ regulator-name = "aic_dvdd"; ++ vin-supply = <&vio_3v3>; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++}; ++ ++&dra7_pmx_core { ++ mmc1_pins_default: mmc1_pins_default { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ ++ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ ++ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ ++ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ ++ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ ++ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ ++ >; ++ }; ++ ++ mmc2_pins_default: mmc2_pins_default { ++ pinctrl-single,pins = < ++ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ ++ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ ++ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ ++ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ ++ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ ++ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ ++ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ ++ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ ++ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ ++ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ ++ >; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ tps65917: tps65917@58 { ++ compatible = "ti,tps65917"; ++ reg = <0x58>; ++ ti,system-power-controller; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ++ tps65917_pmic { ++ compatible = "ti,tps65917-pmic"; ++ ++ smps12-in-supply = <&vsys_3v3>; ++ smps3-in-supply = <&vsys_3v3>; ++ smps4-in-supply = <&vsys_3v3>; ++ smps5-in-supply = <&vsys_3v3>; ++ ldo1-in-supply = <&vsys_3v3>; ++ ldo2-in-supply = <&vsys_3v3>; ++ ldo3-in-supply = <&vsys_5v0>; ++ ldo4-in-supply = <&vsys_5v0>; ++ ldo5-in-supply = <&vsys_3v3>; ++ ++ tps65917_regulators: regulators { ++ smps12_reg: smps12 { ++ /* VDD_DSPEVE */ ++ regulator-name = "smps12"; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <1250000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ smps3_reg: smps3 { ++ /* VDD_CORE */ ++ regulator-name = "smps3"; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <1250000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ smps4_reg: smps4 { ++ /* VDD_IVA */ ++ regulator-name = "smps4"; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <1250000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ smps5_reg: smps5 { ++ /* VDDS1V8 */ ++ regulator-name = "smps5"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo1_reg: ldo1 { ++ /* LDO1_OUT --> VDA_PHY1_1V8 */ ++ regulator-name = "ldo1"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-allow-bypass; ++ }; ++ ++ ldo2_reg: ldo2 { ++ /* LDO2_OUT --> VDA_PHY2_1V8 */ ++ regulator-name = "ldo2"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-allow-bypass; ++ regulator-always-on; ++ }; ++ ++ ldo3_reg: ldo3 { ++ /* VDA_USB_3V3 */ ++ regulator-name = "ldo3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo5_reg: ldo5 { ++ /* VDDA_1V8_PLL */ ++ regulator-name = "ldo5"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ ldo4_reg: ldo4 { ++ /* VDD_SDIO_DV */ ++ regulator-name = "ldo4"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ }; ++ }; ++ ++ tps65917_power_button { ++ compatible = "ti,palmas-pwrbutton"; ++ interrupt-parent = <&tps65917>; ++ interrupts = <1 IRQ_TYPE_NONE>; ++ wakeup-source; ++ ti,palmas-long-press-seconds = <6>; ++ }; ++ }; ++ ++ lp87565: lp87565@60 { ++ compatible = "ti,lp87565-q1"; ++ reg = <0x60>; ++ ++ buck10-in-supply =<&vsys_3v3>; ++ buck23-in-supply =<&vsys_3v3>; ++ ++ regulators: regulators { ++ buck10_reg: buck10 { ++ /*VDD_MPU*/ ++ regulator-name = "buck10"; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <1250000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ buck23_reg: buck23 { ++ /* VDD_GPU*/ ++ regulator-name = "buck23"; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <1250000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ }; ++ }; ++ ++ pcf_lcd: pcf8757@20 { ++ compatible = "ti,pcf8575", "nxp,pcf8575"; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <3 IRQ_TYPE_EDGE_FALLING>; ++ }; ++ ++ pcf_gpio_21: pcf8757@21 { ++ compatible = "ti,pcf8575", "nxp,pcf8575"; ++ reg = <0x21>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <3 IRQ_TYPE_EDGE_FALLING>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ pcf_hdmi: pcf8575@26 { ++ compatible = "ti,pcf8575", "nxp,pcf8575"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ p1 { ++ /* vin6_sel_s0: high: VIN6, low: audio */ ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "vin6_sel_s0"; ++ }; ++ }; ++ ++ tlv320aic3106: tlv320aic3106@19 { ++ #sound-dai-cells = <0>; ++ compatible = "ti,tlv320aic3106"; ++ reg = <0x19>; ++ adc-settle-ms = <40>; ++ ai3x-micbias-vg = <1>; /* 2.0V */ ++ status = "okay"; ++ ++ /* Regulators */ ++ AVDD-supply = <&vio_3v3>; ++ IOVDD-supply = <&vio_3v3>; ++ DRVDD-supply = <&vio_3v3>; ++ DVDD-supply = <&aic_dvdd>; ++ }; ++}; ++ ++&cpu0 { ++ vdd-supply = <&buck10_reg>; ++}; ++ ++&mmc1 { ++ status = "okay"; ++ vmmc-supply = <&vio_3v3_sd>; ++ vmmc_aux-supply = <&ldo4_reg>; ++ bus-width = <4>; ++ /* ++ * SDCD signal is not being used here - using the fact that GPIO mode ++ * is always hardwired. ++ */ ++ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins_default>; ++}; ++ ++&mmc2 { ++ status = "okay"; ++ vmmc-supply = <&vio_1v8>; ++ bus-width = <8>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins_default>; ++}; ++ ++/* No RTC on this device */ ++&rtc { ++ status = "disabled"; ++}; ++ ++&mac { ++ status = "okay"; ++ ++ dual_emac; ++}; ++ ++&cpsw_emac0 { ++ phy_id = <&davinci_mdio>, <2>; ++ phy-mode = "rgmii-id"; ++ dual_emac_res_vlan = <1>; ++}; ++ ++&cpsw_emac1 { ++ phy_id = <&davinci_mdio>, <3>; ++ phy-mode = "rgmii-id"; ++ dual_emac_res_vlan = <2>; ++}; ++ ++&davinci_mdio { ++ dp83867_0: ethernet-phy@2 { ++ reg = <2>; ++ ti,rx-internal-delay = ; ++ ti,tx-internal-delay = ; ++ ti,fifo-depth = ; ++ ti,min-output-impedance; ++ ti,dp83867-rxctrl-strap-quirk; ++ }; ++ ++ dp83867_1: ethernet-phy@3 { ++ reg = <3>; ++ ti,rx-internal-delay = ; ++ ti,tx-internal-delay = ; ++ ti,fifo-depth = ; ++ ti,min-output-impedance; ++ ti,dp83867-rxctrl-strap-quirk; ++ }; ++}; ++ ++&usb2_phy1 { ++ phy-supply = <&ldo3_reg>; ++}; ++ ++&usb2_phy2 { ++ phy-supply = <&ldo3_reg>; ++}; ++ ++&qspi { ++ spi-max-frequency = <96000000>; ++ m25p80@0 { ++ spi-max-frequency = <96000000>; ++ }; ++}; +diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi +new file mode 100644 +index 000000000000..1c88c581ff18 +--- /dev/null ++++ b/arch/arm/boot/dts/dra76x.dtsi +@@ -0,0 +1,19 @@ ++/* ++ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "dra74x.dtsi" ++ ++/ { ++ compatible = "ti,dra762", "ti,dra7"; ++ ++}; ++ ++/* MCAN interrupts are hard-wired to irqs 67, 68 */ ++&crossbar_mpu { ++ ti,irqs-skip = <10 67 68 133 139 140>; ++}; +diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts +index 4bd2ee87124e..4cbfa09c6c4e 100644 +--- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts ++++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts +@@ -22,7 +22,6 @@ / { + }; + + &mshc_2 { +- num-slots = <1>; + cap-sd-highspeed; + disable-wp; + vqmmc-supply = <&ldo3_reg>; +diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi +index 59c89d7662a8..639c2e605f3c 100644 +--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi ++++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi +@@ -304,7 +304,6 @@ buck5_reg: BUCK5 { + }; + + &mshc_0 { +- num-slots = <1>; + non-removable; + cap-mmc-highspeed; + card-detect-delay = <200>; +diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts +index accee81da266..bbdfcbc6e7d2 100644 +--- a/arch/arm/boot/dts/exynos3250-monk.dts ++++ b/arch/arm/boot/dts/exynos3250-monk.dts +@@ -426,7 +426,6 @@ &i2s2 { + &mshc_0 { + #address-cells = <1>; + #size-cells = <0>; +- num-slots = <1>; + broken-cd; + non-removable; + cap-mmc-highspeed; +diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts +index 443e0c98dc73..0b45467d77a8 100644 +--- a/arch/arm/boot/dts/exynos3250-rinato.dts ++++ b/arch/arm/boot/dts/exynos3250-rinato.dts +@@ -220,21 +220,6 @@ &dsi_0 { + samsung,pll-clock-frequency = <24000000>; + status = "okay"; + +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- +- dsi_out: endpoint { +- remote-endpoint = <&dsi_in>; +- samsung,burst-clock-frequency = <250000000>; +- samsung,esc-clock-frequency = <20000000>; +- }; +- }; +- }; +- + panel@0 { + compatible = "samsung,s6e63j0x03"; + reg = <0>; +@@ -264,12 +249,6 @@ timing-0 { + vsync-len = <2>; + }; + }; +- +- port { +- dsi_in: endpoint { +- remote-endpoint = <&dsi_out>; +- }; +- }; + }; + }; + +@@ -642,7 +621,6 @@ &jpeg { + &mshc_0 { + #address-cells = <1>; + #size-cells = <0>; +- num-slots = <1>; + broken-cd; + non-removable; + cap-mmc-highspeed; +diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts +index 645feffb9239..7b6ab7265110 100644 +--- a/arch/arm/boot/dts/exynos4210-trats.dts ++++ b/arch/arm/boot/dts/exynos4210-trats.dts +@@ -202,21 +202,6 @@ &dsi_0 { + samsung,pll-clock-frequency = <24000000>; + status = "okay"; + +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- +- dsi_out: endpoint { +- remote-endpoint = <&dsi_in>; +- samsung,burst-clock-frequency = <500000000>; +- samsung,esc-clock-frequency = <20000000>; +- }; +- }; +- }; +- + panel@0 { + reg = <0>; + compatible = "samsung,s6e8aa0"; +@@ -244,12 +229,6 @@ timing-0 { + vsync-len = <2>; + }; + }; +- +- port { +- dsi_in: endpoint { +- remote-endpoint = <&dsi_out>; +- }; +- }; + }; + }; + +diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +index 4cd62487bb16..14ce2c69bc0b 100644 +--- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi ++++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +@@ -466,7 +466,6 @@ &mshc_0 { + pinctrl-names = "default"; + status = "okay"; + vmmc-supply = <&buck9_reg>; +- num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; +diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +index 219d587c5a85..102acd78be15 100644 +--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi ++++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +@@ -516,7 +516,6 @@ &mshc_0 { + mmc-pwrseq = <&emmc_pwrseq>; + status = "okay"; + +- num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; +diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts +index 7a83e2df18a6..8a89eb893d64 100644 +--- a/arch/arm/boot/dts/exynos4412-origen.dts ++++ b/arch/arm/boot/dts/exynos4412-origen.dts +@@ -488,7 +488,6 @@ &mshc_0 { + pinctrl-names = "default"; + status = "okay"; + +- num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; +diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts +index 35e9b94b86b8..bceb919ac637 100644 +--- a/arch/arm/boot/dts/exynos4412-trats2.dts ++++ b/arch/arm/boot/dts/exynos4412-trats2.dts +@@ -390,21 +390,6 @@ &dsi_0 { + samsung,pll-clock-frequency = <24000000>; + status = "okay"; + +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- +- dsi_out: endpoint { +- remote-endpoint = <&dsi_in>; +- samsung,burst-clock-frequency = <500000000>; +- samsung,esc-clock-frequency = <20000000>; +- }; +- }; +- }; +- + panel@0 { + compatible = "samsung,s6e8aa0"; + reg = <0>; +@@ -432,12 +417,6 @@ timing-0 { + vsync-len = <2>; + }; + }; +- +- port { +- dsi_in: endpoint { +- remote-endpoint = <&dsi_out>; +- }; +- }; + }; + }; + +@@ -901,7 +880,6 @@ &i2s0 { + }; + + &mshc_0 { +- num-slots = <1>; + broken-cd; + non-removable; + card-detect-delay = <200>; +diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts +index 6a432460eb77..18a7f396ac5f 100644 +--- a/arch/arm/boot/dts/exynos5250-arndale.dts ++++ b/arch/arm/boot/dts/exynos5250-arndale.dts +@@ -518,7 +518,6 @@ &i2s0 { + + &mmc_0 { + status = "okay"; +- num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; +@@ -533,7 +532,6 @@ &mmc_0 { + + &mmc_2 { + status = "okay"; +- num-slots = <1>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; +diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts +index 6632f657394e..062cba4c2c31 100644 +--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts ++++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts +@@ -346,7 +346,6 @@ &i2s0 { + + &mmc_0 { + status = "okay"; +- num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; +@@ -360,7 +359,6 @@ &mmc_0 { + + &mmc_2 { + status = "okay"; +- num-slots = <1>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; +diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi +index e1d293dbbe5d..8788880e459d 100644 +--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi ++++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi +@@ -530,7 +530,6 @@ &i2s0 { + /* eMMC flash */ + &mmc_0 { + status = "okay"; +- num-slots = <1>; + non-removable; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; +@@ -544,7 +543,6 @@ &mmc_0 { + /* uSD card */ + &mmc_2 { + status = "okay"; +- num-slots = <1>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; +@@ -564,7 +562,6 @@ &mmc_2 { + */ + &mmc_3 { + status = "okay"; +- num-slots = <1>; + non-removable; + cap-sdio-irq; + keep-power-in-suspend; +diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts +index 95c3bcace9dc..d53bfcbeb39c 100644 +--- a/arch/arm/boot/dts/exynos5250-spring.dts ++++ b/arch/arm/boot/dts/exynos5250-spring.dts +@@ -427,7 +427,6 @@ &i2s0 { + + &mmc_0 { + status = "okay"; +- num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; +@@ -445,7 +444,6 @@ &mmc_0 { + */ + &mmc_1 { + status = "okay"; +- num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; +diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts +index d0cc300cfb4b..73b7cdd5f522 100644 +--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts ++++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts +@@ -67,7 +67,6 @@ &uart3 { + + &mmc_0 { + status = "okay"; +- num-slots = <1>; + broken-cd; + bypass-smu; + cap-mmc-highspeed; +@@ -83,7 +82,6 @@ &mmc_0 { + + &mmc_2 { + status = "okay"; +- num-slots = <1>; + cap-sd-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; +diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts +index 6cc74d97daae..9cb7726ef8d0 100644 +--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts ++++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts +@@ -41,7 +41,6 @@ firmware@02037000 { + + &mmc_0 { + status = "okay"; +- num-slots = <1>; + cap-mmc-highspeed; + broken-cd; + card-detect-delay = <200>; +@@ -53,7 +52,6 @@ &mmc_0 { + + &mmc_2 { + status = "okay"; +- num-slots = <1>; + cap-sd-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; +diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts +index f9a75bfd3f2b..683a4cfb4a23 100644 +--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts ++++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts +@@ -699,7 +699,6 @@ &i2s0 { + /* eMMC flash */ + &mmc_0 { + status = "okay"; +- num-slots = <1>; + mmc-hs200-1_8v; + cap-mmc-highspeed; + non-removable; +@@ -717,7 +716,6 @@ &mmc_0 { + /* WiFi SDIO module */ + &mmc_1 { + status = "okay"; +- num-slots = <1>; + non-removable; + cap-sdio-irq; + keep-power-in-suspend; +@@ -737,7 +735,6 @@ &mmc_1 { + /* uSD card */ + &mmc_2 { + status = "okay"; +- num-slots = <1>; + cap-sd-highspeed; + card-detect-delay = <200>; + clock-frequency = <400000000>; +diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi +index bc4954e69f7b..7a00be7ea6d7 100644 +--- a/arch/arm/boot/dts/exynos5440.dtsi ++++ b/arch/arm/boot/dts/exynos5440.dtsi +@@ -317,6 +317,7 @@ pcie_0: pcie@290000 { + phys = <&pcie_phy0>; + ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ ++ bus-range = <0x00 0xff>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 53>; +@@ -339,6 +340,7 @@ pcie_1: pcie@2a0000 { + phys = <&pcie_phy1>; + ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ ++ bus-range = <0x00 0xff>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 56>; +diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts +index 953dc8677dc8..b2b95ff205e8 100644 +--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts ++++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts +@@ -667,7 +667,6 @@ &i2s0 { + /* eMMC flash */ + &mmc_0 { + status = "okay"; +- num-slots = <1>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; +@@ -686,7 +685,6 @@ &mmc_0 { + /* WiFi SDIO module */ + &mmc_1 { + status = "okay"; +- num-slots = <1>; + non-removable; + cap-sdio-irq; + keep-power-in-suspend; +@@ -706,7 +704,6 @@ &mmc_1 { + /* uSD card */ + &mmc_2 { + status = "okay"; +- num-slots = <1>; + cap-sd-highspeed; + card-detect-delay = <200>; + clock-frequency = <400000000>; +diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts +new file mode 100644 +index 000000000000..e75e2d44371c +--- /dev/null ++++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts +@@ -0,0 +1,246 @@ ++/* ++ * Device Tree file for D-Link DIR-685 Xtreme N Storage Router ++ */ ++ ++/dts-v1/; ++ ++#include "gemini.dtsi" ++#include ++ ++/ { ++ model = "D-Link DIR-685 Xtreme N Storage Router"; ++ compatible = "dlink,dir-685", "cortina,gemini"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ memory { ++ /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */ ++ device_type = "memory"; ++ reg = <0x00000000 0x8000000>; ++ }; ++ ++ chosen { ++ stdout-path = "uart0:115200n8"; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ button-esc { ++ debounce_interval = <50>; ++ wakeup-source; ++ linux,code = ; ++ label = "reset"; ++ /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */ ++ gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; ++ }; ++ button-eject { ++ debounce_interval = <50>; ++ wakeup-source; ++ linux,code = ; ++ label = "unmount"; ++ /* Collides with LPC LFRAME, UART RTS, SSP TXD */ ++ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ led-wps { ++ label = "dir685:blue:WPS"; ++ /* Collides with ICE */ ++ gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; ++ default-state = "on"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ /* ++ * These two LEDs are on the side of the device. ++ * For electrical reasons, both LEDs cannot be active ++ * at the same time so only blue or orange can on at ++ * one time. Enabling both makes the LED go dark. ++ * The LEDs both sit inside the unmount button and the ++ * label on the case says "unmount". ++ */ ++ led-blue-hd { ++ label = "dir685:blue:HD"; ++ /* Collides with LPC_SERIRQ, UART DTR, SSP FSC pins */ ++ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ led-orange-hd { ++ label = "dir685:orange:HD"; ++ /* Collides with LPC_LAD[2], UART DSR, SSP ECLK pins */ ++ gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ }; ++ ++ /* ++ * This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM. ++ * Since the platform has no temperature sensor, this is controlled ++ * from userspace by using the hard disks S.M.A.R.T. temperature ++ * sensor. It is turned on when the temperature exceeds 46 degrees ++ * and turned off when the temperatures goes below 41 degrees ++ * (celsius). ++ */ ++ gpio-fan { ++ compatible = "gpio-fan"; ++ /* Collides with IDE */ ++ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; ++ gpio-fan,speed-map = <0 0>, <10000 1>; ++ #cooling-cells = <2>; ++ }; ++ ++ /* ++ * The touchpad input is connected to a GPIO bit-banged ++ * I2C bus. ++ */ ++ gpio-i2c { ++ compatible = "i2c-gpio"; ++ /* Collides with ICE */ ++ gpios = <&gpio0 5 0>, /* SDA */ ++ <&gpio0 6 0>; /* SCL */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ touchkeys@26 { ++ compatible = "dlink,dir685-touchkeys"; ++ reg = <0x26>; ++ interrupt-parent = <&gpio0>; ++ /* Collides with NAND flash */ ++ interrupts = <17 IRQ_TYPE_EDGE_FALLING>; ++ }; ++ }; ++ ++ soc { ++ flash@30000000 { ++ status = "okay"; ++ /* 32MB of flash */ ++ reg = <0x30000000 0x02000000>; ++ ++ /* ++ * This "RedBoot" is the Storlink derivative. ++ */ ++ partition@0 { ++ label = "RedBoot"; ++ reg = <0x00000000 0x00040000>; ++ read-only; ++ }; ++ /* ++ * Between the boot loader and the rootfs is the kernel ++ * in a custom Storlink format flashed from the boot ++ * menu. The rootfs is in squashfs format. ++ */ ++ partition@1800c0 { ++ label = "rootfs"; ++ reg = <0x001800c0 0x01dbff40>; ++ read-only; ++ }; ++ partition@1f40000 { ++ label = "upgrade"; ++ reg = <0x01f40000 0x00040000>; ++ read-only; ++ }; ++ partition@1f80000 { ++ label = "rgdb"; ++ reg = <0x01f80000 0x00040000>; ++ read-only; ++ }; ++ /* ++ * This partition contains MAC addresses for WAN, ++ * WLAN and LAN, and the country code (for wireless ++ * I guess). ++ */ ++ partition@1fc0000 { ++ label = "nvram"; ++ reg = <0x01fc0000 0x00020000>; ++ read-only; ++ }; ++ partition@1fe0000 { ++ label = "LangPack"; ++ reg = <0x01fe0000 0x00020000>; ++ read-only; ++ }; ++ }; ++ ++ syscon: syscon@40000000 { ++ pinctrl { ++ /* ++ * gpio0bgrp cover line 5, 6 used by TK I2C ++ * gpio0bgrp cover line 7 used by WPS LED ++ * gpio0cgrp cover line 8, 13 used by keys ++ * and 11, 12 used by the HD LEDs ++ * gpio0egrp cover line 16 used by VDISP ++ * gpio0fgrp cover line 17 used by TK IRQ ++ * gpio0ggrp cover line 20 used by panel CS ++ * gpio0hgrp cover line 21,22 used by RTL8366RB ++ */ ++ gpio0_default_pins: pinctrl-gpio0 { ++ mux { ++ function = "gpio0"; ++ groups = "gpio0bgrp", ++ "gpio0cgrp", ++ "gpio0egrp", ++ "gpio0fgrp", ++ "gpio0ggrp", ++ "gpio0hgrp"; ++ }; ++ }; ++ /* ++ * gpio1bgrp cover line 5,8,7 used by panel SPI ++ * also line 6 used by the fan ++ * ++ */ ++ gpio1_default_pins: pinctrl-gpio1 { ++ mux { ++ function = "gpio1"; ++ groups = "gpio1bgrp"; ++ }; ++ }; ++ }; ++ }; ++ ++ sata: sata@46000000 { ++ cortina,gemini-ata-muxmode = <0>; ++ cortina,gemini-enable-sata-bridge; ++ status = "okay"; ++ }; ++ ++ gpio0: gpio@4d000000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio0_default_pins>; ++ }; ++ ++ gpio1: gpio@4e000000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio1_default_pins>; ++ }; ++ ++ pci@50000000 { ++ status = "okay"; ++ interrupt-map-mask = <0xf800 0 0 7>; ++ interrupt-map = ++ <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ ++ <0x4800 0 0 2 &pci_intc 1>, ++ <0x4800 0 0 3 &pci_intc 2>, ++ <0x4800 0 0 4 &pci_intc 3>, ++ <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ ++ <0x5000 0 0 2 &pci_intc 2>, ++ <0x5000 0 0 3 &pci_intc 3>, ++ <0x5000 0 0 4 &pci_intc 0>, ++ <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ ++ <0x5800 0 0 2 &pci_intc 3>, ++ <0x5800 0 0 3 &pci_intc 0>, ++ <0x5800 0 0 4 &pci_intc 1>, ++ <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ ++ <0x6000 0 0 2 &pci_intc 0>, ++ <0x6000 0 0 3 &pci_intc 1>, ++ <0x6000 0 0 4 &pci_intc 2>; ++ }; ++ ++ ata@63000000 { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts +index 55f6a4f1f801..b4fc58c8cf8d 100644 +--- a/arch/arm/boot/dts/gemini-nas4220b.dts ++++ b/arch/arm/boot/dts/gemini-nas4220b.dts +@@ -33,6 +33,7 @@ button@29 { + wakeup-source; + linux,code = ; + label = "Backup button"; ++ /* Conflict with TVC */ + gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + }; + button@31 { +@@ -40,6 +41,7 @@ button@31 { + wakeup-source; + linux,code = ; + label = "Softreset button"; ++ /* Conflict with TVC */ + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + }; + }; +@@ -48,11 +50,13 @@ leds { + compatible = "gpio-leds"; + led@28 { + label = "nas4220b:orange:hdd"; ++ /* Conflict with TVC */ + gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + led@30 { + label = "nas4220b:green:os"; ++ /* Conflict with TVC */ + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; +@@ -99,12 +103,32 @@ partition@fe0000 { + }; + }; + ++ syscon: syscon@40000000 { ++ pinctrl { ++ /* ++ * gpio1dgrp cover line 28-31 otherwise used ++ * by TVC. ++ */ ++ gpio1_default_pins: pinctrl-gpio1 { ++ mux { ++ function = "gpio1"; ++ groups = "gpio1dgrp"; ++ }; ++ }; ++ }; ++ }; ++ + sata: sata@46000000 { + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; + }; + ++ gpio1: gpio@4e000000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio1_default_pins>; ++ }; ++ + ata@63000000 { + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini-rut1xx.dts +index 7b920bfbda32..3613b264f45f 100644 +--- a/arch/arm/boot/dts/gemini-rut1xx.dts ++++ b/arch/arm/boot/dts/gemini-rut1xx.dts +@@ -33,6 +33,7 @@ button@28 { + wakeup-source; + linux,code = ; + label = "Reset to defaults"; ++ /* Conflict with TVC */ + gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + }; + }; +@@ -42,12 +43,14 @@ leds { + led@7 { + /* FIXME: add the LED color */ + label = "rut1xx::gsm"; ++ /* Conflict with ICE */ + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + led@31 { + /* FIXME: add the LED color */ + label = "rut1xx::power"; ++ /* Conflict with NAND CE0 */ + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; +@@ -61,5 +64,41 @@ flash@30000000 { + reg = <0x30000000 0x00800000>; + /* TODO: add flash partitions here */ + }; ++ ++ syscon: syscon@40000000 { ++ pinctrl { ++ /* ++ * gpio0bgrp cover line 7 used by GSM LED ++ * gpio0fgrp cover line 17 used by power LED ++ */ ++ gpio0_default_pins: pinctrl-gpio0 { ++ mux { ++ function = "gpio0"; ++ groups = "gpio0bgrp", ++ "gpio0fgrp"; ++ }; ++ }; ++ /* ++ * gpio1dgrp cover line 28-31 otherwise used ++ * by TVC. ++ */ ++ gpio1_default_pins: pinctrl-gpio1 { ++ mux { ++ function = "gpio1"; ++ groups = "gpio1dgrp"; ++ }; ++ }; ++ }; ++ }; ++ ++ gpio0: gpio@4d000000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio0_default_pins>; ++ }; ++ ++ gpio1: gpio@4e000000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio1_default_pins>; ++ }; + }; + }; +diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts +index 4d200f0bcd45..7cfa9caf47d4 100644 +--- a/arch/arm/boot/dts/gemini-sq201.dts ++++ b/arch/arm/boot/dts/gemini-sq201.dts +@@ -33,6 +33,7 @@ button@18 { + wakeup-source; + linux,code = ; + label = "factory reset"; ++ /* Conflict with NAND flash */ + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + }; +@@ -41,12 +42,14 @@ leds { + compatible = "gpio-leds"; + led@20 { + label = "sq201:green:info"; ++ /* Conflict with parallel flash */ + gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + led@31 { + label = "sq201:green:usb"; ++ /* Conflict with parallel and NAND flash */ + gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "usb-host"; +@@ -55,7 +58,15 @@ led@31 { + + soc { + flash@30000000 { +- status = "okay"; ++ /* ++ * Flash access can be enabled, with the side effect ++ * of disabling access to GPIO LED on GPIO0[20] which ++ * reuse one of the parallel flash chip select lines. ++ * Also the default firmware on the machine has the ++ * problem that since it uses the flash, the two LEDS ++ * on the right become numb. ++ */ ++ /* status = "okay"; */ + /* 16MB of flash */ + reg = <0x30000000 0x01000000>; + +@@ -93,12 +104,35 @@ partition@fe0000 { + }; + }; + ++ syscon: syscon@40000000 { ++ pinctrl { ++ /* ++ * gpio0fgrp cover line 18 used by reset button ++ * gpio0ggrp cover line 20 used by info LED ++ * gpio0kgrp cover line 31 used by USB LED ++ */ ++ gpio0_default_pins: pinctrl-gpio0 { ++ mux { ++ function = "gpio0"; ++ groups = "gpio0fgrp", ++ "gpio0ggrp", ++ "gpio0kgrp"; ++ }; ++ }; ++ }; ++ }; ++ + sata: sata@46000000 { + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; + }; + ++ gpio0: gpio@4d000000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio0_default_pins>; ++ }; ++ + pci@50000000 { + status = "okay"; + interrupt-map-mask = <0xf800 0 0 7>; +diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts +index 63b756e3bf5a..38a49e750478 100644 +--- a/arch/arm/boot/dts/gemini-wbd111.dts ++++ b/arch/arm/boot/dts/gemini-wbd111.dts +@@ -33,6 +33,7 @@ button@5 { + wakeup-source; + linux,code = ; + label = "reset"; ++ /* Conflict with ICE */ + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + }; + }; +@@ -42,21 +43,25 @@ leds { + + led@1 { + label = "wbd111:red:L3"; ++ /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@2 { + label = "wbd111:green:L4"; ++ /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@3 { + label = "wbd111:red:L4"; ++ /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@5 { + label = "wbd111:green:L3"; ++ /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; +@@ -98,5 +103,26 @@ partition@7e0000 { + read-only; + }; + }; ++ ++ syscon: syscon@40000000 { ++ pinctrl { ++ /* ++ * gpio0agrp cover line 0-4 ++ * gpio0bgrp cover line 5 ++ */ ++ gpio0_default_pins: pinctrl-gpio0 { ++ mux { ++ function = "gpio0"; ++ groups = "gpio0agrp", ++ "gpio0bgrp"; ++ }; ++ }; ++ }; ++ }; ++ ++ gpio0: gpio@4d000000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio0_default_pins>; ++ }; + }; + }; +diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts +index 9747f5a47807..f77e34e0df0b 100644 +--- a/arch/arm/boot/dts/gemini-wbd222.dts ++++ b/arch/arm/boot/dts/gemini-wbd222.dts +@@ -33,6 +33,7 @@ button@5 { + wakeup-source; + linux,code = ; + label = "reset"; ++ /* Conflict with ICE */ + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + }; + }; +@@ -42,21 +43,25 @@ leds { + + led@1 { + label = "wbd111:red:L3"; ++ /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@2 { + label = "wbd111:green:L4"; ++ /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@3 { + label = "wbd111:red:L4"; ++ /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@5 { + label = "wbd111:green:L3"; ++ /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; +@@ -98,5 +103,26 @@ partition@7e0000 { + read-only; + }; + }; ++ ++ syscon: syscon@40000000 { ++ pinctrl { ++ /* ++ * gpio0agrp cover line 0-4 ++ * gpio0bgrp cover line 5 ++ */ ++ gpio0_default_pins: pinctrl-gpio0 { ++ mux { ++ function = "gpio0"; ++ groups = "gpio0agrp", ++ "gpio0bgrp"; ++ }; ++ }; ++ }; ++ }; ++ ++ gpio0: gpio@4d000000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio0_default_pins>; ++ }; + }; + }; +diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi +index 141d8d3a1d07..c68e8d430234 100644 +--- a/arch/arm/boot/dts/gemini.dtsi ++++ b/arch/arm/boot/dts/gemini.dtsi +@@ -5,6 +5,8 @@ + /include/ "skeleton.dtsi" + + #include ++#include ++#include + #include + + / { +@@ -18,6 +20,8 @@ soc { + flash@30000000 { + compatible = "cortina,gemini-flash", "cfi-flash"; + syscon = <&syscon>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pflash_default_pins>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; +@@ -39,22 +43,123 @@ syscon-reboot { + /* RESET_GLOBAL | RESET_CPU1 */ + mask = <0xC0000000>; + }; ++ ++ pinctrl { ++ compatible = "cortina,gemini-pinctrl"; ++ regmap = <&syscon>; ++ /* Hog the DRAM pins */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&dram_default_pins>, <&system_default_pins>, ++ <&vcontrol_default_pins>; ++ ++ dram_default_pins: pinctrl-dram { ++ mux { ++ function = "dram"; ++ groups = "dramgrp"; ++ }; ++ }; ++ rtc_default_pins: pinctrl-rtc { ++ mux { ++ function = "rtc"; ++ groups = "rtcgrp"; ++ }; ++ }; ++ power_default_pins: pinctrl-power { ++ mux { ++ function = "power"; ++ groups = "powergrp"; ++ }; ++ }; ++ cir_default_pins: pinctrl-cir { ++ mux { ++ function = "cir"; ++ groups = "cirgrp"; ++ }; ++ }; ++ system_default_pins: pinctrl-system { ++ mux { ++ function = "system"; ++ groups = "systemgrp"; ++ }; ++ }; ++ vcontrol_default_pins: pinctrl-vcontrol { ++ mux { ++ function = "vcontrol"; ++ groups = "vcontrolgrp"; ++ }; ++ }; ++ ice_default_pins: pinctrl-ice { ++ mux { ++ function = "ice"; ++ groups = "icegrp"; ++ }; ++ }; ++ uart_default_pins: pinctrl-uart { ++ mux { ++ function = "uart"; ++ groups = "uartrxtxgrp"; ++ }; ++ }; ++ pflash_default_pins: pinctrl-pflash { ++ mux { ++ function = "pflash"; ++ groups = "pflashgrp"; ++ }; ++ }; ++ usb_default_pins: pinctrl-usb { ++ mux { ++ function = "usb"; ++ groups = "usbgrp"; ++ }; ++ }; ++ gmii_default_pins: pinctrl-gmii { ++ mux { ++ function = "gmii"; ++ groups = "gmiigrp"; ++ }; ++ }; ++ pci_default_pins: pinctrl-pci { ++ mux { ++ function = "pci"; ++ groups = "pcigrp"; ++ }; ++ }; ++ sata_default_pins: pinctrl-sata { ++ mux { ++ function = "sata"; ++ groups = "satagrp"; ++ }; ++ }; ++ /* Activate both groups of pins for this state */ ++ sata_and_ide_pins: pinctrl-sata-ide { ++ mux0 { ++ function = "sata"; ++ groups = "satagrp"; ++ }; ++ mux1 { ++ function = "ide"; ++ groups = "idegrp"; ++ }; ++ }; ++ }; + }; + + watchdog@41000000 { + compatible = "cortina,gemini-watchdog"; + reg = <0x41000000 0x1000>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +- resets = <&syscon 23>; +- clocks = <&syscon 2>; ++ resets = <&syscon GEMINI_RESET_WDOG>; ++ clocks = <&syscon GEMINI_CLK_APB>; + }; + + uart0: serial@42000000 { + compatible = "ns16550a"; + reg = <0x42000000 0x100>; +- resets = <&syscon 18>; +- clocks = <&syscon 6>; ++ resets = <&syscon GEMINI_RESET_UART>; ++ clocks = <&syscon GEMINI_CLK_UART>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart_default_pins>; + reg-shift = <2>; + }; + +@@ -65,9 +170,9 @@ timer@43000000 { + interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ + <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ + <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ +- resets = <&syscon 17>; ++ resets = <&syscon GEMINI_RESET_TIMER>; + /* APB clock or RTC clock */ +- clocks = <&syscon 2>, <&syscon 0>; ++ clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; + clock-names = "PCLK", "EXTCLK"; + syscon = <&syscon>; + }; +@@ -76,20 +181,30 @@ rtc@45000000 { + compatible = "cortina,gemini-rtc"; + reg = <0x45000000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; +- resets = <&syscon 16>; +- clocks = <&syscon 2>, <&syscon 0>; ++ resets = <&syscon GEMINI_RESET_RTC>; ++ clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; + clock-names = "PCLK", "EXTCLK"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtc_default_pins>; + }; + + sata: sata@46000000 { + compatible = "cortina,gemini-sata-bridge"; + reg = <0x46000000 0x100>; +- resets = <&syscon 26>, +- <&syscon 27>; ++ resets = <&syscon GEMINI_RESET_SATA0>, ++ <&syscon GEMINI_RESET_SATA1>; + reset-names = "sata0", "sata1"; +- clocks = <&syscon 10>, +- <&syscon 11>; ++ clocks = <&syscon GEMINI_CLK_GATE_SATA0>, ++ <&syscon GEMINI_CLK_GATE_SATA1>; + clock-names = "SATA0_PCLK", "SATA1_PCLK"; ++ /* ++ * This defines the special "ide" state that needs ++ * to be explicitly enabled to enable the IDE pins, ++ * as these pins are normally used for other things. ++ */ ++ pinctrl-names = "default", "ide"; ++ pinctrl-0 = <&sata_default_pins>; ++ pinctrl-1 = <&sata_and_ide_pins>; + syscon = <&syscon>; + status = "disabled"; + }; +@@ -97,7 +212,7 @@ sata: sata@46000000 { + intcon: interrupt-controller@48000000 { + compatible = "faraday,ftintc010"; + reg = <0x48000000 0x1000>; +- resets = <&syscon 14>; ++ resets = <&syscon GEMINI_RESET_INTCON0>; + interrupt-controller; + #interrupt-cells = <2>; + }; +@@ -106,14 +221,16 @@ power-controller@4b000000 { + compatible = "cortina,gemini-power-controller"; + reg = <0x4b000000 0x100>; + interrupts = <26 IRQ_TYPE_EDGE_RISING>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&power_default_pins>; + }; + + gpio0: gpio@4d000000 { + compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; + reg = <0x4d000000 0x100>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; +- resets = <&syscon 20>; +- clocks = <&syscon 2>; ++ resets = <&syscon GEMINI_RESET_GPIO0>; ++ clocks = <&syscon GEMINI_CLK_APB>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +@@ -124,8 +241,8 @@ gpio1: gpio@4e000000 { + compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; + reg = <0x4e000000 0x100>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; +- resets = <&syscon 21>; +- clocks = <&syscon 2>; ++ resets = <&syscon GEMINI_RESET_GPIO1>; ++ clocks = <&syscon GEMINI_CLK_APB>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +@@ -136,8 +253,8 @@ gpio2: gpio@4f000000 { + compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; + reg = <0x4f000000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; +- resets = <&syscon 22>; +- clocks = <&syscon 2>; ++ resets = <&syscon GEMINI_RESET_GPIO2>; ++ clocks = <&syscon GEMINI_CLK_APB>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +@@ -151,9 +268,11 @@ pci@50000000 { + * to configure the host bridge. + */ + reg = <0x50000000 0x100>; +- resets = <&syscon 7>; +- clocks = <&syscon 15>, <&syscon 4>; ++ resets = <&syscon GEMINI_RESET_PCI>; ++ clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>; + clock-names = "PCLK", "PCICLK"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pci_default_pins>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; +@@ -193,8 +312,8 @@ ata@63000000 { + compatible = "cortina,gemini-pata", "faraday,ftide010"; + reg = <0x63000000 0x1000>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; +- resets = <&syscon 2>; +- clocks = <&syscon 14>; ++ resets = <&syscon GEMINI_RESET_IDE>; ++ clocks = <&syscon GEMINI_CLK_GATE_IDE>; + clock-names = "PCLK"; + sata = <&sata>; + status = "disabled"; +@@ -204,8 +323,8 @@ ata@63400000 { + compatible = "cortina,gemini-pata", "faraday,ftide010"; + reg = <0x63400000 0x1000>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; +- resets = <&syscon 2>; +- clocks = <&syscon 14>; ++ resets = <&syscon GEMINI_RESET_IDE>; ++ clocks = <&syscon GEMINI_CLK_GATE_IDE>; + clock-names = "PCLK"; + sata = <&sata>; + status = "disabled"; +@@ -217,8 +336,8 @@ dma-controller@67000000 { + arm,primecell-periphid = <0x0003b080>; + reg = <0x67000000 0x1000>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; +- resets = <&syscon 10>; +- clocks = <&syscon 1>; ++ resets = <&syscon GEMINI_RESET_DMAC>; ++ clocks = <&syscon GEMINI_CLK_AHB>; + clock-names = "apb_pclk"; + /* Bus interface AHB1 (AHB0) is totally tilted */ + lli-bus-interface-ahb2; +diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi +index 0ade3619f3c3..09ce8b81fafa 100644 +--- a/arch/arm/boot/dts/imx25.dtsi ++++ b/arch/arm/boot/dts/imx25.dtsi +@@ -452,6 +452,13 @@ scc: crypto@53fac000 { + interrupt-names = "scm", "smn"; + }; + ++ rngb: rngb@53fb0000 { ++ compatible = "fsl,imx25-rngb"; ++ reg = <0x53fb0000 0x4000>; ++ clocks = <&clks 109>; ++ interrupts = <22>; ++ }; ++ + esdhc1: esdhc@53fb4000 { + compatible = "fsl,imx25-esdhc"; + reg = <0x53fb4000 0x4000>; +diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/imx53-cx9020.dts +new file mode 100644 +index 000000000000..4f54fd4418a3 +--- /dev/null ++++ b/arch/arm/boot/dts/imx53-cx9020.dts +@@ -0,0 +1,297 @@ ++/* ++ * Copyright 2017 Beckhoff Automation GmbH & Co. KG ++ * based on imx53-qsb.dts ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/dts-v1/; ++#include "imx53.dtsi" ++ ++/ { ++ model = "Beckhoff CX9020 Embedded PC"; ++ compatible = "bhf,cx9020", "fsl,imx53"; ++ ++ chosen { ++ stdout-path = &uart2; ++ }; ++ ++ memory { ++ reg = <0x70000000 0x20000000>, ++ <0xb0000000 0x20000000>; ++ }; ++ ++ display-0 { ++ #address-cells =<1>; ++ #size-cells = <0>; ++ compatible = "fsl,imx-parallel-display"; ++ interface-pix-fmt = "rgb24"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ipu_disp0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ display0_in: endpoint { ++ remote-endpoint = <&ipu_di0_disp0>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ display0_out: endpoint { ++ remote-endpoint = <&tfp410_in>; ++ }; ++ }; ++ }; ++ ++ dvi-connector { ++ compatible = "dvi-connector"; ++ ddc-i2c-bus = <&i2c2>; ++ digital; ++ ++ port { ++ dvi_connector_in: endpoint { ++ remote-endpoint = <&tfp410_out>; ++ }; ++ }; ++ }; ++ ++ dvi-converter { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "ti,tfp410"; ++ ++ port@0 { ++ reg = <0>; ++ ++ tfp410_in: endpoint { ++ remote-endpoint = <&display0_out>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ tfp410_out: endpoint { ++ remote-endpoint = <&dvi_connector_in>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pwr-r { ++ gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ ++ pwr-g { ++ gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ pwr-b { ++ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ ++ sd1-b { ++ linux,default-trigger = "mmc0"; ++ gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ sd2-b { ++ linux,default-trigger = "mmc1"; ++ gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ regulator-3p2v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P2V"; ++ regulator-min-microvolt = <3200000>; ++ regulator-max-microvolt = <3200000>; ++ regulator-always-on; ++ }; ++ ++ reg_usb_vbus: regulator-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++}; ++ ++&esdhc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_esdhc1>; ++ cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&esdhc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_esdhc2>; ++ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&fec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_fec>; ++ phy-mode = "rmii"; ++ phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ status = "okay"; ++}; ++ ++&ipu_di0_disp0 { ++ remote-endpoint = <&display0_in>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2>; ++ fsl,dte-mode; ++ status = "okay"; ++}; ++ ++&usbh1 { ++ vbus-supply = <®_usb_vbus>; ++ phy_type = "utmi"; ++ status = "okay"; ++}; ++ ++&usbotg { ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&vpu { ++ status = "okay"; ++}; ++ ++&iomuxc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hog>; ++ ++ pinctrl_hog: hoggrp { ++ fsl,pins = < ++ MX53_PAD_GPIO_0__CCM_CLKO 0x1c4 ++ MX53_PAD_GPIO_16__I2C3_SDA 0x1c4 ++ MX53_PAD_EIM_D22__GPIO3_22 0x1c4 ++ MX53_PAD_EIM_D23__GPIO3_23 0x1e4 ++ MX53_PAD_EIM_D24__GPIO3_24 0x1e4 ++ >; ++ }; ++ ++ pinctrl_esdhc1: esdhc1grp { ++ fsl,pins = < ++ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 ++ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 ++ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 ++ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 ++ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 ++ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 ++ MX53_PAD_GPIO_1__ESDHC1_CD 0x1c4 ++ MX53_PAD_EIM_D17__GPIO3_17 0x1e4 ++ MX53_PAD_GPIO_3__GPIO1_3 0x1c4 ++ >; ++ }; ++ ++ pinctrl_esdhc2: esdhc2grp { ++ fsl,pins = < ++ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 ++ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 ++ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 ++ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 ++ MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 ++ MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 ++ MX53_PAD_GPIO_4__ESDHC2_CD 0x1e4 ++ MX53_PAD_EIM_D20__GPIO3_20 0x1e4 ++ MX53_PAD_GPIO_8__GPIO1_8 0x1c4 ++ >; ++ }; ++ ++ pinctrl_fec: fecgrp { ++ fsl,pins = < ++ MX53_PAD_FEC_MDC__FEC_MDC 0x4 ++ MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc ++ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 ++ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 ++ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 ++ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 ++ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 ++ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 ++ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 ++ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 ++ >; ++ }; ++ ++ pinctrl_i2c2: i2c2grp { ++ fsl,pins = < ++ MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 ++ MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 ++ >; ++ }; ++ ++ pinctrl_ipu_disp0: ipudisp0grp { ++ fsl,pins = < ++ MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 ++ MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 ++ MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 ++ MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 ++ MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5 ++ MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 ++ MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 ++ MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 ++ MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 ++ MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 ++ MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 ++ MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 ++ MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 ++ MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 ++ MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 ++ MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 ++ MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 ++ MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 ++ MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 ++ MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 ++ MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 ++ MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 ++ MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 ++ MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 ++ MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 ++ MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 ++ MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 ++ MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 ++ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 ++ >; ++ }; ++ ++ pinctrl_uart2: uart2grp { ++ fsl,pins = < ++ MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4 ++ MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4 ++ MX53_PAD_EIM_D28__UART2_RTS 0x1e4 ++ MX53_PAD_EIM_D29__UART2_CTS 0x1e4 ++ >; ++ }; ++}; +diff --git a/arch/arm/boot/dts/imx53-pinfunc.h b/arch/arm/boot/dts/imx53-pinfunc.h +index aec406bc65eb..59f9c29e3fe2 100644 +--- a/arch/arm/boot/dts/imx53-pinfunc.h ++++ b/arch/arm/boot/dts/imx53-pinfunc.h +@@ -524,6 +524,7 @@ + #define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0 + #define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0 + #define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0 ++#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0 + #define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0 + #define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0 + #define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0 +@@ -533,6 +534,7 @@ + #define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0 + #define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0 + #define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1 ++#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0 + #define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0 + #define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0 + #define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0 +@@ -541,6 +543,7 @@ + #define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0 + #define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0 + #define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0 ++#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0 + #define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1 + #define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1 + #define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1 +@@ -548,6 +551,7 @@ + #define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0 + #define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0 + #define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0 ++#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0 + #define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1 + #define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0 + #define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2 +diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi +index 2e516f4985e4..8bf0d89cdd35 100644 +--- a/arch/arm/boot/dts/imx53.dtsi ++++ b/arch/arm/boot/dts/imx53.dtsi +@@ -433,6 +433,15 @@ gpt: timer@53fa0000 { + clock-names = "ipg", "per"; + }; + ++ srtc: srtc@53fa4000 { ++ compatible = "fsl,imx53-rtc", "fsl,imx25-rtc"; ++ reg = <0x53fa4000 0x4000>; ++ interrupts = <24>; ++ interrupt-parent = <&tzic>; ++ clocks = <&clks IMX5_CLK_SRTC_GATE>; ++ clock-names = "ipg"; ++ }; ++ + iomuxc: iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc"; + reg = <0x53fa8000 0x4000>; +diff --git a/arch/arm/boot/dts/imx6dl-gw52xx.dts b/arch/arm/boot/dts/imx6dl-gw52xx.dts +index a2e0b73fdd4a..5f9f8948100d 100644 +--- a/arch/arm/boot/dts/imx6dl-gw52xx.dts ++++ b/arch/arm/boot/dts/imx6dl-gw52xx.dts +@@ -17,3 +17,61 @@ / { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX"; + compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl"; + }; ++ ++&i2c3 { ++ adv7180: camera@20 { ++ compatible = "adi,adv7180"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_adv7180>; ++ reg = <0x20>; ++ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; ++ interrupt-parent = <&gpio3>; ++ interrupts = <30 IRQ_TYPE_LEVEL_LOW>; ++ ++ port { ++ adv7180_to_ipu1_csi1_mux: endpoint { ++ remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; ++ bus-width = <8>; ++ }; ++ }; ++ }; ++}; ++ ++&ipu1_csi1_from_ipu1_csi1_mux { ++ bus-width = <8>; ++}; ++ ++&ipu1_csi1_mux_from_parallel_sensor { ++ remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; ++ bus-width = <8>; ++}; ++ ++&ipu1_csi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ipu1_csi1>; ++}; ++ ++&iomuxc { ++ pinctrl_adv7180: adv7180grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 ++ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 ++ >; ++ }; ++ ++ pinctrl_ipu1_csi1: ipu1_csi1grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 ++ MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 ++ MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 ++ MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 ++ MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 ++ MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 ++ MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 ++ MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 ++ MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 ++ MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 ++ MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 ++ >; ++ }; ++}; +diff --git a/arch/arm/boot/dts/imx6dl-gw53xx.dts b/arch/arm/boot/dts/imx6dl-gw53xx.dts +index 6844b708d2f8..9bfc620d37bd 100644 +--- a/arch/arm/boot/dts/imx6dl-gw53xx.dts ++++ b/arch/arm/boot/dts/imx6dl-gw53xx.dts +@@ -17,3 +17,61 @@ / { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX"; + compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl"; + }; ++ ++&i2c3 { ++ adv7180: camera@20 { ++ compatible = "adi,adv7180"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_adv7180>; ++ reg = <0x20>; ++ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; ++ interrupt-parent = <&gpio3>; ++ interrupts = <30 IRQ_TYPE_LEVEL_LOW>; ++ ++ port { ++ adv7180_to_ipu1_csi1_mux: endpoint { ++ remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; ++ bus-width = <8>; ++ }; ++ }; ++ }; ++}; ++ ++&ipu1_csi1_from_ipu1_csi1_mux { ++ bus-width = <8>; ++}; ++ ++&ipu1_csi1_mux_from_parallel_sensor { ++ remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; ++ bus-width = <8>; ++}; ++ ++&ipu1_csi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ipu1_csi1>; ++}; ++ ++&iomuxc { ++ pinctrl_adv7180: adv7180grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 ++ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 ++ >; ++ }; ++ ++ pinctrl_ipu1_csi1: ipu1_csi1grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 ++ MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 ++ MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 ++ MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 ++ MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 ++ MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 ++ MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 ++ MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 ++ MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 ++ MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 ++ MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 ++ >; ++ }; ++}; +diff --git a/arch/arm/boot/dts/imx6dl-gw54xx.dts b/arch/arm/boot/dts/imx6dl-gw54xx.dts +index be915412f852..b909bdf9a2ef 100644 +--- a/arch/arm/boot/dts/imx6dl-gw54xx.dts ++++ b/arch/arm/boot/dts/imx6dl-gw54xx.dts +@@ -17,3 +17,61 @@ / { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX"; + compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl"; + }; ++ ++&i2c3 { ++ adv7180: camera@20 { ++ compatible = "adi,adv7180"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_adv7180>; ++ reg = <0x20>; ++ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; ++ interrupt-parent = <&gpio3>; ++ interrupts = <30 IRQ_TYPE_LEVEL_LOW>; ++ ++ port { ++ adv7180_to_ipu1_csi1_mux: endpoint { ++ remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; ++ bus-width = <8>; ++ }; ++ }; ++ }; ++}; ++ ++&ipu1_csi1_from_ipu1_csi1_mux { ++ bus-width = <8>; ++}; ++ ++&ipu1_csi1_mux_from_parallel_sensor { ++ remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; ++ bus-width = <8>; ++}; ++ ++&ipu1_csi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ipu1_csi1>; ++}; ++ ++&iomuxc { ++ pinctrl_adv7180: adv7180grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 ++ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 ++ >; ++ }; ++ ++ pinctrl_ipu1_csi1: ipu1_csi1grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 ++ MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 ++ MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 ++ MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 ++ MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 ++ MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 ++ MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 ++ MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 ++ MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 ++ MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 ++ MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 ++ >; ++ }; ++}; +diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts +index 29b45f2e64e0..275c6c05219d 100644 +--- a/arch/arm/boot/dts/imx6dl-riotboard.dts ++++ b/arch/arm/boot/dts/imx6dl-riotboard.dts +@@ -101,6 +101,51 @@ &fec { + status = "okay"; + }; + ++&gpio1 { ++ gpio-line-names = ++ "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL", ++ "I2C3_SDA", "I2C4_SCL", ++ "I2C4_SDA", "", "", "", "", "", "", "", ++ "", "PWM3", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&gpio3 { ++ gpio-line-names = ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "USB_OTG_VBUS", "", ++ "UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", ""; ++}; ++ ++&gpio4 { ++ gpio-line-names = ++ "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", ++ "UART5_TXD", "UART5_RXD", "", "", "", "", "", "", ++ "GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "", ++ "CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO", ++ "CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27", ++ "CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31"; ++}; ++ ++&gpio5 { ++ gpio-line-names = ++ "", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06", ++ "GPIO5_07", ++ "GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO", ++ "CSPI2_CS0", "CSPI2_CLK", "", "", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&gpio7 { ++ gpio-line-names = ++ "SD3_CD", "SD3_WP", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", ""; ++}; ++ + &hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts +new file mode 100644 +index 000000000000..4bbfe3d61027 +--- /dev/null ++++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts +@@ -0,0 +1,278 @@ ++/* ++ * Copyright 2014-2017 Toradex AG ++ * Copyright 2012 Freescale Semiconductor, Inc. ++ * Copyright 2011 Linaro Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include "imx6q.dtsi" ++#include "imx6qdl-apalis.dtsi" ++ ++/ { ++ model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board"; ++ compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q", ++ "fsl,imx6q"; ++ ++ aliases { ++ i2c0 = &i2c1; ++ i2c1 = &i2c3; ++ i2c2 = &i2c2; ++ rtc0 = &rtc_i2c; ++ rtc1 = &snvs_rtc; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpio_keys>; ++ ++ wakeup { ++ label = "Wake-Up"; ++ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <10>; ++ wakeup-source; ++ }; ++ }; ++ ++ lcd_display: display@di0 { ++ compatible = "fsl,imx-parallel-display"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interface-pix-fmt = "rgb24"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ipu1_lcdif>; ++ status = "okay"; ++ ++ port@0 { ++ reg = <0>; ++ ++ lcd_display_in: endpoint { ++ remote-endpoint = <&ipu1_di1_disp1>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ lcd_display_out: endpoint { ++ remote-endpoint = <&lcd_panel_in>; ++ }; ++ }; ++ }; ++ ++ panel: panel { ++ /* ++ * edt,et057090dhu: EDT 5.7" LCD TFT ++ * edt,et070080dh6: EDT 7.0" LCD TFT ++ */ ++ compatible = "edt,et057090dhu"; ++ backlight = <&backlight>; ++ ++ port { ++ lcd_panel_in: endpoint { ++ remote-endpoint = <&lcd_display_out>; ++ }; ++ }; ++ }; ++ ++ reg_pcie_switch: regulator-pcie-switch { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie_switch"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ status = "okay"; ++ }; ++}; ++ ++&backlight { ++ brightness-levels = <0 127 191 223 239 247 251 255>; ++ default-brightness-level = <1>; ++ status = "okay"; ++}; ++ ++&can1 { ++ status = "okay"; ++}; ++ ++&can2 { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ ++&i2c1 { ++ status = "okay"; ++ ++ pcie-switch@58 { ++ compatible = "plx,pex8605"; ++ reg = <0x58>; ++ }; ++ ++ /* M41T0M6 real time clock on carrier board */ ++ rtc_i2c: rtc@68 { ++ compatible = "st,m41t00"; ++ reg = <0x68>; ++ }; ++}; ++ ++/* ++ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier ++ * board) ++ */ ++&i2c3 { ++ status = "okay"; ++}; ++ ++&ipu1_di1_disp1 { ++ remote-endpoint = <&lcd_display_in>; ++}; ++ ++&ldb { ++ status = "okay"; ++}; ++ ++&pcie { ++ /* active-high meaning opposite of regular PERST# active-low polarity */ ++ reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; ++ reset-gpio-active-high; ++ vpcie-supply = <®_pcie_switch>; ++ status = "okay"; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&pwm3 { ++ status = "okay"; ++}; ++ ++&pwm4 { ++ status = "okay"; ++}; ++ ++®_usb_otg_vbus { ++ status = "okay"; ++}; ++ ++®_usb_host_vbus { ++ status = "okay"; ++}; ++ ++&sata { ++ status = "okay"; ++}; ++ ++&sound_spdif { ++ status = "okay"; ++}; ++ ++&spdif { ++ status = "okay"; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&uart4 { ++ status = "okay"; ++}; ++ ++&uart5 { ++ status = "okay"; ++}; ++ ++&usbh1 { ++ vbus-supply = <®_usb_host_vbus>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ vbus-supply = <®_usb_otg_vbus>; ++ status = "okay"; ++}; ++ ++/* MMC1 */ ++&usdhc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; ++ cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++/* SD1 */ ++&usdhc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; ++ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&iomuxc { ++ /* ++ * Mux the Apalis GPIOs ++ */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 ++ &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 ++ &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 ++ &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 ++ >; ++}; +diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +new file mode 100644 +index 000000000000..a35c7a54ad3b +--- /dev/null ++++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +@@ -0,0 +1,291 @@ ++/* ++ * Copyright 2014-2017 Toradex AG ++ * Copyright 2012 Freescale Semiconductor, Inc. ++ * Copyright 2011 Linaro Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include "imx6q.dtsi" ++#include "imx6qdl-apalis.dtsi" ++ ++/ { ++ model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1"; ++ compatible = "toradex,apalis_imx6q-ixora-v1.1", ++ "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q", ++ "fsl,imx6q"; ++ ++ aliases { ++ i2c0 = &i2c1; ++ i2c1 = &i2c3; ++ i2c2 = &i2c2; ++ rtc0 = &rtc_i2c; ++ rtc1 = &snvs_rtc; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpio_keys>; ++ ++ wakeup { ++ label = "Wake-Up"; ++ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <10>; ++ wakeup-source; ++ }; ++ }; ++ ++ lcd_display: display@di0 { ++ compatible = "fsl,imx-parallel-display"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interface-pix-fmt = "rgb24"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ipu1_lcdif>; ++ status = "okay"; ++ ++ port@0 { ++ reg = <0>; ++ ++ lcd_display_in: endpoint { ++ remote-endpoint = <&ipu1_di1_disp1>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ lcd_display_out: endpoint { ++ remote-endpoint = <&lcd_panel_in>; ++ }; ++ }; ++ }; ++ ++ panel: panel { ++ /* ++ * edt,et057090dhu: EDT 5.7" LCD TFT ++ * edt,et070080dh6: EDT 7.0" LCD TFT ++ */ ++ compatible = "edt,et057090dhu"; ++ backlight = <&backlight>; ++ ++ port { ++ lcd_panel_in: endpoint { ++ remote-endpoint = <&lcd_display_out>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_leds_ixora>; ++ ++ led4-green { ++ label = "LED_4_GREEN"; ++ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led4-red { ++ label = "LED_4_RED"; ++ gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led5-green { ++ label = "LED_5_GREEN"; ++ gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led5-red { ++ label = "LED_5_RED"; ++ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&backlight { ++ brightness-levels = <0 127 191 223 239 247 251 255>; ++ default-brightness-level = <1>; ++ status = "okay"; ++}; ++ ++&can1 { ++ status = "okay"; ++}; ++ ++&can2 { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ ++&i2c1 { ++ status = "okay"; ++ ++ /* M41T0M6 real time clock on carrier board */ ++ rtc_i2c: rtc@68 { ++ compatible = "st,m41t00"; ++ reg = <0x68>; ++ }; ++}; ++ ++/* ++ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier ++ * board) ++ */ ++&i2c3 { ++ status = "okay"; ++}; ++ ++&ipu1_di1_disp1 { ++ remote-endpoint = <&lcd_display_in>; ++}; ++ ++&ldb { ++ status = "okay"; ++}; ++ ++&pcie { ++ /* active-high meaning opposite of regular PERST# active-low polarity */ ++ reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; ++ reset-gpio-active-high; ++ status = "okay"; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&pwm3 { ++ status = "okay"; ++}; ++ ++&pwm4 { ++ status = "okay"; ++}; ++ ++®_usb_otg_vbus { ++ status = "okay"; ++}; ++ ++®_usb_host_vbus { ++ status = "okay"; ++}; ++ ++&sata { ++ status = "okay"; ++}; ++ ++&sound_spdif { ++ status = "okay"; ++}; ++ ++&spdif { ++ status = "okay"; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&uart4 { ++ status = "okay"; ++}; ++ ++&uart5 { ++ status = "okay"; ++}; ++ ++&usbh1 { ++ vbus-supply = <®_usb_host_vbus>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ vbus-supply = <®_usb_otg_vbus>; ++ status = "okay"; ++}; ++ ++/* MMC1 */ ++&usdhc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>; ++ cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&iomuxc { ++ /* ++ * Mux the Apalis GPIOs ++ */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 ++ &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 ++ &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 ++ &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 ++ >; ++ ++ pinctrl_leds_ixora: ledsixoragrp { ++ fsl,pins = < ++ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 ++ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 ++ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 ++ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 ++ >; ++ }; ++}; +diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts +index 88cc7f51a4e9..60d33e99de76 100644 +--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts ++++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts +@@ -1,5 +1,5 @@ + /* +- * Copyright 2014-2016 Toradex AG ++ * Copyright 2014-2017 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * +@@ -55,13 +55,9 @@ / { + "fsl,imx6q"; + + aliases { +- i2c0 = &i2cddc; +- i2c1 = &i2c1; ++ i2c0 = &i2c1; ++ i2c1 = &i2c3; + i2c2 = &i2c2; +- i2c3 = &i2c3; +- }; +- +- aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; +@@ -164,15 +160,10 @@ &can2 { + }; + + &hdmi { +- ddc-i2c-bus = <&i2cddc>; +- status = "okay"; +-}; +- +-&i2cddc { + status = "okay"; + }; + +-/* GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ ++/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ + &i2c1 { + status = "okay"; + +@@ -188,6 +179,14 @@ rtc_i2c: rtc@68 { + }; + }; + ++/* ++ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier ++ * board) ++ */ ++&i2c3 { ++ status = "okay"; ++}; ++ + &ipu1_di1_disp1 { + remote-endpoint = <&lcd_display_in>; + }; +@@ -268,16 +267,13 @@ &usbotg { + /* SD1 */ + &usdhc2 { + pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sd_cd>; ++ pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + &iomuxc { +- /* +- * Mux the Apalis GPIOs +- * GPIO5, 6 used by optional fusion_F0710A kernel module +- */ ++ /* Mux the Apalis GPIOs */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 + &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 +diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts +index 2c1e98e0cf7b..46bdc6722715 100644 +--- a/arch/arm/boot/dts/imx6q-b850v3.dts ++++ b/arch/arm/boot/dts/imx6q-b850v3.dts +@@ -57,7 +57,7 @@ &clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, +- <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>; ++ <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, +diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi +index c90b26f00e24..1015e55ca8f7 100644 +--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi ++++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi +@@ -111,6 +111,11 @@ m25_eeprom: m25p80@0 { + }; + + &i2c1 { ++ pinctrl-names = "default", "gpio"; ++ pinctrl-1 = <&pinctrl_i2c1_gpio>; ++ sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; ++ scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; ++ + pca9547: mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; +@@ -261,6 +266,43 @@ mux1_i2c8: i2c@7 { + }; + }; + ++&i2c2 { ++ pinctrl-names = "default", "gpio"; ++ pinctrl-1 = <&pinctrl_i2c2_gpio>; ++ sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; ++ scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default", "gpio"; ++ pinctrl-1 = <&pinctrl_i2c3_gpio>; ++ sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; ++ scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; ++}; ++ ++&iomuxc { ++ pinctrl_i2c1_gpio: i2c1gpiogrp { ++ fsl,pins = < ++ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_i2c2_gpio: i2c2gpiogrp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 ++ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_i2c3_gpio: i2c3gpiogrp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 ++ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 ++ >; ++ }; ++}; ++ + &usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; +diff --git a/arch/arm/boot/dts/imx6q-gw52xx.dts b/arch/arm/boot/dts/imx6q-gw52xx.dts +index a12c47e5ee05..0b8ae007ad73 100644 +--- a/arch/arm/boot/dts/imx6q-gw52xx.dts ++++ b/arch/arm/boot/dts/imx6q-gw52xx.dts +@@ -18,6 +18,64 @@ / { + compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q"; + }; + ++&i2c3 { ++ adv7180: camera@20 { ++ compatible = "adi,adv7180"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_adv7180>; ++ reg = <0x20>; ++ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; ++ interrupt-parent = <&gpio3>; ++ interrupts = <30 IRQ_TYPE_LEVEL_LOW>; ++ ++ port { ++ adv7180_to_ipu2_csi1_mux: endpoint { ++ remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; ++ bus-width = <8>; ++ }; ++ }; ++ }; ++}; ++ ++&ipu2_csi1_from_ipu2_csi1_mux { ++ bus-width = <8>; ++}; ++ ++&ipu2_csi1_mux_from_parallel_sensor { ++ remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; ++ bus-width = <8>; ++}; ++ ++&ipu2_csi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ipu2_csi1>; ++}; ++ ++&iomuxc { ++ pinctrl_adv7180: adv7180grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 ++ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 ++ >; ++ }; ++ ++ pinctrl_ipu2_csi1: ipu2_csi1grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 ++ MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 ++ MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 ++ MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 ++ MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 ++ MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 ++ MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 ++ MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 ++ MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 ++ MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 ++ MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 ++ >; ++ }; ++}; ++ + &sata { + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/imx6q-gw53xx.dts b/arch/arm/boot/dts/imx6q-gw53xx.dts +index d76aaa83dad0..a56ef77eff3f 100644 +--- a/arch/arm/boot/dts/imx6q-gw53xx.dts ++++ b/arch/arm/boot/dts/imx6q-gw53xx.dts +@@ -18,6 +18,64 @@ / { + compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q"; + }; + ++&i2c3 { ++ adv7180: camera@20 { ++ compatible = "adi,adv7180"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_adv7180>; ++ reg = <0x20>; ++ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; ++ interrupt-parent = <&gpio3>; ++ interrupts = <30 IRQ_TYPE_LEVEL_LOW>; ++ ++ port { ++ adv7180_to_ipu2_csi1_mux: endpoint { ++ remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; ++ bus-width = <8>; ++ }; ++ }; ++ }; ++}; ++ ++&ipu2_csi1_from_ipu2_csi1_mux { ++ bus-width = <8>; ++}; ++ ++&ipu2_csi1_mux_from_parallel_sensor { ++ remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; ++ bus-width = <8>; ++}; ++ ++&ipu2_csi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ipu2_csi1>; ++}; ++ + &sata { + status = "okay"; + }; ++ ++&iomuxc { ++ pinctrl_adv7180: adv7180grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 ++ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 ++ >; ++ }; ++ ++ pinctrl_ipu2_csi1: ipu2_csi1grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 ++ MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 ++ MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 ++ MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 ++ MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 ++ MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 ++ MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 ++ MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 ++ MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 ++ MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 ++ MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 ++ >; ++ }; ++}; +diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/imx6q-gw54xx.dts +index 6e8f53e92a2d..56e5b5050fcf 100644 +--- a/arch/arm/boot/dts/imx6q-gw54xx.dts ++++ b/arch/arm/boot/dts/imx6q-gw54xx.dts +@@ -18,6 +18,64 @@ / { + compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; + }; + ++&i2c3 { ++ adv7180: camera@20 { ++ compatible = "adi,adv7180"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_adv7180>; ++ reg = <0x20>; ++ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; ++ interrupt-parent = <&gpio3>; ++ interrupts = <30 IRQ_TYPE_LEVEL_LOW>; ++ ++ port { ++ adv7180_to_ipu2_csi1_mux: endpoint { ++ remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; ++ bus-width = <8>; ++ }; ++ }; ++ }; ++}; ++ ++&ipu2_csi1_from_ipu2_csi1_mux { ++ bus-width = <8>; ++}; ++ ++&ipu2_csi1_mux_from_parallel_sensor { ++ remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; ++ bus-width = <8>; ++}; ++ ++&ipu2_csi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ipu2_csi1>; ++}; ++ + &sata { + status = "okay"; + }; ++ ++&iomuxc { ++ pinctrl_adv7180: adv7180grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 ++ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 ++ >; ++ }; ++ ++ pinctrl_ipu2_csi1: ipu2_csi1grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 ++ MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 ++ MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 ++ MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 ++ MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 ++ MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 ++ MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 ++ MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 ++ MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 ++ MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 ++ MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 ++ >; ++ }; ++}; +diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi +index ba01dd76d887..ea339fa58f4a 100644 +--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi +@@ -1,5 +1,5 @@ + /* +- * Copyright 2014-2016 Toradex AG ++ * Copyright 2014-2017 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * +@@ -56,18 +56,6 @@ backlight: backlight { + status = "disabled"; + }; + +- /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */ +- i2cddc: i2c@0 { +- compatible = "i2c-gpio"; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c_ddc>; +- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */ +- &gpio2 30 GPIO_ACTIVE_HIGH /* scl */ +- >; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- status = "disabled"; +- }; +- + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; +@@ -210,10 +198,13 @@ ethphy: ethernet-phy@7 { + }; + }; + +-/* +- * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier +- * board) +- */ ++&hdmi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hdmi_ddc>; ++ status = "disabled"; ++}; ++ ++/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ + &i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; +@@ -374,7 +365,8 @@ stmpe_touchscreen { + }; + + /* +- * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused) ++ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier ++ * board) + */ + &i2c3 { + clock-frequency = <100000>; +@@ -460,7 +452,7 @@ &usbotg { + /* MMC1 */ + &usdhc1 { + pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; ++ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; + vqmmc-supply = <®_3p3v>; + bus-width = <8>; + voltage-ranges = <3300 3300>; +@@ -640,11 +632,10 @@ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + +- pinctrl_i2c_ddc: gpioi2cddcgrp { ++ pinctrl_hdmi_ddc: hdmiddcgrp { + fsl,pins = < +- /* DDC bitbang */ +- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 +- MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 ++ MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 ++ MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + +@@ -912,7 +903,7 @@ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + +- pinctrl_usdhc1: usdhc1grp { ++ pinctrl_usdhc1_4bit: usdhc1grp_4bit { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 +@@ -920,6 +911,11 @@ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 ++ >; ++ }; ++ ++ pinctrl_usdhc1_8bit: usdhc1grp_8bit { ++ fsl,pins = < + MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 + MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 + MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 +diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +index e8c1edc82e6e..885556260bd0 100644 +--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +@@ -231,6 +231,37 @@ &i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; ++ ++ adv7180: camera@20 { ++ compatible = "adi,adv7180"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_adv7180>; ++ reg = <0x20>; ++ powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; ++ interrupt-parent = <&gpio5>; ++ interrupts = <23 IRQ_TYPE_LEVEL_LOW>; ++ ++ port { ++ adv7180_to_ipu1_csi0_mux: endpoint { ++ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; ++ bus-width = <8>; ++ }; ++ }; ++ }; ++}; ++ ++&ipu1_csi0_from_ipu1_csi0_mux { ++ bus-width = <8>; ++}; ++ ++&ipu1_csi0_mux_from_parallel_sensor { ++ remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; ++ bus-width = <8>; ++}; ++ ++&ipu1_csi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ipu1_csi0>; + }; + + &pcie { +@@ -302,6 +333,13 @@ &wdog1 { + + &iomuxc { + imx6qdl-gw51xx { ++ pinctrl_adv7180: adv7180grp { ++ fsl,pins = < ++ MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 ++ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 ++ >; ++ }; ++ + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 +@@ -372,6 +410,22 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + ++ pinctrl_ipu1_csi0: ipu1csi0grp { ++ fsl,pins = < ++ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 ++ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 ++ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 ++ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 ++ >; ++ }; ++ + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 +diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +index 91991d63a69c..115d706228ef 100644 +--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +@@ -377,7 +377,6 @@ &ssi1 { + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +index 5bc6ed1a5b35..24be7965056c 100644 +--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +@@ -368,7 +368,6 @@ &ssi1 { + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +index 66fcf838e964..4594b2279169 100644 +--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +@@ -416,7 +416,6 @@ &ssi2 { + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +- uart-has-rtscts; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi +index 57374dddf98d..1a0faa1a14c8 100644 +--- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi +@@ -261,6 +261,37 @@ &i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; ++ ++ adv7180: camera@20 { ++ compatible = "adi,adv7180"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_adv7180>; ++ reg = <0x20>; ++ powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; ++ interrupt-parent = <&gpio5>; ++ interrupts = <23 IRQ_TYPE_LEVEL_LOW>; ++ ++ port { ++ adv7180_to_ipu1_csi0_mux: endpoint { ++ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; ++ bus-width = <8>; ++ }; ++ }; ++ }; ++}; ++ ++&ipu1_csi0_from_ipu1_csi0_mux { ++ bus-width = <8>; ++}; ++ ++&ipu1_csi0_mux_from_parallel_sensor { ++ remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; ++ bus-width = <8>; ++}; ++ ++&ipu1_csi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ipu1_csi0>; + }; + + &pcie { +@@ -340,6 +371,13 @@ &wdog1 { + }; + + &iomuxc { ++ pinctrl_adv7180: adv7180grp { ++ fsl,pins = < ++ MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 ++ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 ++ >; ++ }; ++ + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 +@@ -387,6 +425,22 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + ++ pinctrl_ipu1_csi0: ipu1csi0grp { ++ fsl,pins = < ++ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 ++ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 ++ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 ++ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 ++ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 ++ >; ++ }; ++ + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 +diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi +index 5fab5be414fe..7ca291e9dbdb 100644 +--- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi +@@ -184,7 +184,6 @@ &pcie { + }; + + &ssi1 { +- fsl,mode = "i2s-slave"; + status = "okay"; + }; + +diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +index f22e5879340b..d309a4d0eb08 100644 +--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +@@ -108,6 +108,18 @@ reg_wlan_vmmc: regulator@4 { + startup-delay-us = <70000>; + enable-active-high; + }; ++ ++ reg_usb_h1_vbus: regulator@5 { ++ compatible = "regulator-fixed"; ++ reg = <5>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usbh1>; ++ regulator-name = "usb_h1_vbus"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; + }; + + gpio-keys { +@@ -515,6 +527,12 @@ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + ++ pinctrl_usbh1: usbh1grp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 ++ >; ++ }; ++ + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +@@ -629,6 +647,7 @@ &uart2 { + }; + + &usbh1 { ++ vbus-supply = <®_usb_h1_vbus>; + status = "okay"; + }; + +diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +index afe7449c47da..756c5054f047 100644 +--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +@@ -123,6 +123,18 @@ reg_2p8v: regulator@6 { + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; ++ ++ reg_usb_h1_vbus: regulator@7 { ++ compatible = "regulator-fixed"; ++ reg = <7>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usbh1>; ++ regulator-name = "usb_h1_vbus"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; + }; + + mipi_xclk: mipi_xclk { +@@ -610,6 +622,12 @@ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + ++ pinctrl_usbh1: usbh1grp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 ++ >; ++ }; ++ + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 +@@ -705,6 +723,7 @@ &uart2 { + }; + + &usbh1 { ++ vbus-supply = <®_usb_h1_vbus>; + status = "okay"; + }; + +diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +index 5d94b5ee6aa0..eeb7679fd348 100644 +--- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +@@ -59,6 +59,14 @@ mdio1: mdio { + pinctrl-0 = <&pinctrl_mdio1>; + gpios = <&gpio6 5 GPIO_ACTIVE_HIGH + &gpio6 4 GPIO_ACTIVE_HIGH>; ++ ++ phy: ethernet-phy@0 { ++ pinctrl-0 = <&pinctrl_rmii_phy_irq>; ++ pinctrl-names = "default"; ++ reg = <0>; ++ interrupt-parent = <&gpio3>; ++ interrupts = <30 IRQ_TYPE_LEVEL_LOW>; ++ }; + }; + + reg_28p0v: regulator-28p0v { +@@ -615,14 +623,106 @@ &fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; ++ phy-handle = <&phy>; + phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + phy-reset-duration = <100>; + phy-supply = <®_3p3v>; + status = "okay"; + +- fixed-link { +- speed = <100>; +- full-duplex; ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ switch: switch@0 { ++ compatible = "marvell,mv88e6085"; ++ pinctrl-0 = <&pinctrl_switch_irq>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ dsa,member = <0 0>; ++ eeprom-length = <512>; ++ interrupt-parent = <&gpio6>; ++ interrupts = <3 IRQ_TYPE_EDGE_FALLING>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ label = "gigabit_proc"; ++ phy-handle = <&switchphy0>; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ label = "netaux"; ++ phy-handle = <&switchphy1>; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ label = "cpu"; ++ ethernet = <&fec>; ++ ++ fixed-link { ++ speed = <100>; ++ full-duplex; ++ }; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ label = "netright"; ++ phy-handle = <&switchphy3>; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ label = "netleft"; ++ phy-handle = <&switchphy4>; ++ }; ++ }; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ switchphy0: switchphy@0 { ++ reg = <0>; ++ interrupt-parent = <&switch>; ++ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ switchphy1: switchphy@1 { ++ reg = <1>; ++ interrupt-parent = <&switch>; ++ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ switchphy2: switchphy@2 { ++ reg = <2>; ++ interrupt-parent = <&switch>; ++ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ switchphy3: switchphy@3 { ++ reg = <3>; ++ interrupt-parent = <&switch>; ++ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ switchphy4: switchphy@4 { ++ reg = <4>; ++ interrupt-parent = <&switch>; ++ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ }; ++ }; + }; + }; + +@@ -840,6 +940,12 @@ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x40010000 + >; + }; + ++ pinctrl_switch_irq: switchgrp { ++ fsl,pins = < ++ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x4001b000 ++ >; ++ }; ++ + pinctrl_tc358767: tc358767grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x10 +diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi +index a9723b94bafa..8884b4a3cafb 100644 +--- a/arch/arm/boot/dts/imx6qdl.dtsi ++++ b/arch/arm/boot/dts/imx6qdl.dtsi +@@ -769,6 +769,7 @@ snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; ++ value = <0x60>; + mask = <0x60>; + status = "disabled"; + }; +diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi +index 3243af4a9984..3f76f980947e 100644 +--- a/arch/arm/boot/dts/imx6sl.dtsi ++++ b/arch/arm/boot/dts/imx6sl.dtsi +@@ -655,6 +655,7 @@ snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; ++ value = <0x60>; + mask = <0x60>; + status = "disabled"; + }; +diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi +index f16b9df9d0c6..6c7eb54be9e2 100644 +--- a/arch/arm/boot/dts/imx6sx.dtsi ++++ b/arch/arm/boot/dts/imx6sx.dtsi +@@ -710,6 +710,7 @@ snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; ++ value = <0x60>; + mask = <0x60>; + status = "disabled"; + }; +diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts +index d2be8aa3370b..9c23e017d86a 100644 +--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts ++++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts +@@ -22,7 +22,7 @@ memory { + reg = <0x80000000 0x20000000>; + }; + +- backlight { ++ backlight_display: backlight-display { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; +@@ -78,6 +78,17 @@ dailink_master: simple-audio-card,codec { + clocks = <&clks IMX6UL_CLK_SAI2>; + }; + }; ++ ++ panel { ++ compatible = "innolux,at043tn24"; ++ backlight = <&backlight_display>; ++ ++ port { ++ panel_in: endpoint { ++ remote-endpoint = <&display_out>; ++ }; ++ }; ++ }; + }; + + &clks { +@@ -139,31 +150,11 @@ &lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; +- display = <&display0>; + status = "okay"; + +- display0: display { +- bits-per-pixel = <16>; +- bus-width = <24>; +- +- display-timings { +- native-mode = <&timing0>; +- +- timing0: timing0 { +- clock-frequency = <9200000>; +- hactive = <480>; +- vactive = <272>; +- hfront-porch = <8>; +- hback-porch = <4>; +- hsync-len = <41>; +- vback-porch = <2>; +- vfront-porch = <4>; +- vsync-len = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; ++ port { ++ display_out: endpoint { ++ remote-endpoint = <&panel_in>; + }; + }; + }; +@@ -316,7 +307,6 @@ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 +- MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + +diff --git a/arch/arm/boot/dts/imx6ul-geam-kit.dts b/arch/arm/boot/dts/imx6ul-geam-kit.dts +deleted file mode 100644 +index 142e60cab65f..000000000000 +--- a/arch/arm/boot/dts/imx6ul-geam-kit.dts ++++ /dev/null +@@ -1,101 +0,0 @@ +-/* +- * Copyright (C) 2016 Amarula Solutions B.V. +- * Copyright (C) 2016 Engicam S.r.l. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-#include +-#include "imx6ul-geam.dtsi" +- +-/ { +- model = "Engicam GEAM6UL"; +- compatible = "engicam,imx6ul-geam", "fsl,imx6ul"; +-}; +- +-&can1 { +- status = "okay"; +-}; +- +-&can2 { +- status = "okay"; +-}; +- +-&lcdif { +- display = <&display0>; +- status = "okay"; +- +- display0: display { +- bits-per-pixel = <16>; +- bus-width = <18>; +- status = "okay"; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <28000000>; +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <30>; +- hback-porch = <30>; +- hsync-len = <64>; +- vback-porch = <5>; +- vfront-porch = <5>; +- vsync-len = <20>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- }; +- }; +-}; +- +-&usdhc1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- status = "okay"; +-}; +- +-&tsc { +- measure-delay-time = <0x1ffff>; +- pre-charge-time = <0x1fff>; +- status = "okay"; +-}; +diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/imx6ul-geam.dts +new file mode 100644 +index 000000000000..571eea7f1c6b +--- /dev/null ++++ b/arch/arm/boot/dts/imx6ul-geam.dts +@@ -0,0 +1,480 @@ ++/* ++ * Copyright (C) 2016 Amarula Solutions B.V. ++ * Copyright (C) 2016 Engicam S.r.l. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include "imx6ul.dtsi" ++ ++/ { ++ model = "Engicam GEAM6UL Starter Kit"; ++ compatible = "engicam,imx6ul-geam", "fsl,imx6ul"; ++ ++ memory { ++ reg = <0x80000000 0x08000000>; ++ }; ++ ++ backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm8 0 100000>; ++ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 ++ 10 11 12 13 14 15 16 17 18 19 ++ 20 21 22 23 24 25 26 27 28 29 ++ 30 31 32 33 34 35 36 37 38 39 ++ 40 41 42 43 44 45 46 47 48 49 ++ 50 51 52 53 54 55 56 57 58 59 ++ 60 61 62 63 64 65 66 67 68 69 ++ 70 71 72 73 74 75 76 77 78 79 ++ 80 81 82 83 84 85 86 87 88 89 ++ 90 91 92 93 94 95 96 97 98 99 ++ 100>; ++ default-brightness-level = <100>; ++ }; ++ ++ chosen { ++ stdout-path = &uart1; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "1P8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "imx6ul-geam-sgtl5000"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,bitclock-master = <&dailink_master>; ++ simple-audio-card,frame-master = <&dailink_master>; ++ simple-audio-card,widgets = ++ "Microphone", "Mic Jack", ++ "Line", "Line In", ++ "Line", "Line Out", ++ "Headphone", "Headphone Jack"; ++ simple-audio-card,routing = ++ "MIC_IN", "Mic Jack", ++ "Mic Jack", "Mic Bias", ++ "Headphone Jack", "HP_OUT"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&sai2>; ++ }; ++ ++ dailink_master: simple-audio-card,codec { ++ sound-dai = <&sgtl5000>; ++ clocks = <&clks IMX6UL_CLK_SAI2>; ++ }; ++ }; ++}; ++ ++&can1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexcan1>; ++ xceiver-supply = <®_3p3v>; ++ status = "okay"; ++}; ++ ++&can2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexcan2>; ++ xceiver-supply = <®_3p3v>; ++ status = "okay"; ++}; ++ ++&fec1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_enet1>; ++ phy-mode = "rmii"; ++ phy-handle = <ðphy0>; ++ status = "okay"; ++}; ++ ++&fec2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_enet2>; ++ phy-mode = "rmii"; ++ phy-handle = <ðphy1>; ++ status = "okay"; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ethphy0: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ }; ++ ++ ethphy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++ }; ++}; ++ ++&gpmi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpmi_nand>; ++ nand-on-flash-bbt; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1>; ++ status = "okay"; ++ ++ sgtl5000: codec@a { ++ compatible = "fsl,sgtl5000"; ++ reg = <0x0a>; ++ clocks = <&clks IMX6UL_CLK_OSC>; ++ clock-names = "mclk"; ++ VDDA-supply = <®_3p3v>; ++ VDDIO-supply = <®_3p3v>; ++ VDDD-supply = <®_1p8v>; ++ }; ++}; ++ ++&i2c2 { ++ clock_frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ status = "okay"; ++}; ++ ++&lcdif { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_lcdif_dat ++ &pinctrl_lcdif_ctrl>; ++ display = <&display0>; ++ status = "okay"; ++ ++ display0: display { ++ bits-per-pixel = <16>; ++ bus-width = <18>; ++ ++ display-timings { ++ native-mode = <&timing0>; ++ timing0: timing0 { ++ clock-frequency = <28000000>; ++ hactive = <800>; ++ vactive = <480>; ++ hfront-porch = <30>; ++ hback-porch = <30>; ++ hsync-len = <64>; ++ vback-porch = <5>; ++ vfront-porch = <5>; ++ vsync-len = <20>; ++ hsync-active = <0>; ++ vsync-active = <0>; ++ de-active = <1>; ++ pixelclk-active = <0>; ++ }; ++ }; ++ }; ++}; ++ ++&pwm8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm8>; ++ status = "okay"; ++}; ++ ++&tsc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_tsc>; ++ xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; ++}; ++ ++&sai2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_sai2>; ++ status = "okay"; ++}; ++ ++&tsc { ++ measure-delay-time = <0x1ffff>; ++ pre-charge-time = <0x1fff>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2>; ++ status = "okay"; ++}; ++ ++&usbotg1 { ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&usbotg2 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usdhc1 { ++ pinctrl-names = "default", "state_100mhz", "state_200mhz"; ++ pinctrl-0 = <&pinctrl_usdhc1>; ++ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; ++ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; ++ bus-width = <4>; ++ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; ++ no-1-8-v; ++ status = "okay"; ++}; ++ ++&iomuxc { ++ pinctrl_enet1: enet1grp { ++ fsl,pins = < ++ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 ++ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 ++ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 ++ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 ++ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 ++ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 ++ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 ++ >; ++ }; ++ ++ pinctrl_enet2: enet2grp { ++ fsl,pins = < ++ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 ++ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 ++ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 ++ MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */ ++ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 ++ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 ++ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 ++ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 ++ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 ++ MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031 ++ >; ++ }; ++ ++ pinctrl_flexcan1: flexcan1grp { ++ fsl,pins = < ++ MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 ++ MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 ++ >; ++ }; ++ ++ pinctrl_flexcan2: flexcan2grp { ++ fsl,pins = < ++ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 ++ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 ++ >; ++ }; ++ ++ pinctrl_gpmi_nand: gpmi-nand { ++ fsl,pins = < ++ MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 ++ MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 ++ MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 ++ MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 ++ MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 ++ MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 ++ MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 ++ MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 ++ MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 ++ MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 ++ MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 ++ MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 ++ MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 ++ MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 ++ MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 ++ >; ++ }; ++ ++ pinctrl_i2c1: i2c1grp { ++ fsl,pins = < ++ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 ++ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 ++ >; ++ }; ++ ++ pinctrl_i2c2: i2c2grp { ++ fsl,pins = < ++ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 ++ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 ++ >; ++ }; ++ ++ pinctrl_lcdif_ctrl: lcdifctrlgrp { ++ fsl,pins = < ++ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 ++ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 ++ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 ++ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 ++ >; ++ }; ++ ++ pinctrl_lcdif_dat: lcdifdatgrp { ++ fsl,pins = < ++ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 ++ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 ++ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 ++ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 ++ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 ++ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 ++ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 ++ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 ++ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 ++ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 ++ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 ++ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 ++ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 ++ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 ++ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 ++ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 ++ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 ++ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 ++ >; ++ }; ++ ++ pinctrl_pwm8: pwm8grp { ++ fsl,pins = < ++ MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 ++ >; ++ }; ++ ++ pinctrl_tsc: tscgrp { ++ fsl,pin = < ++ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 ++ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 ++ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 ++ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 ++ >; ++ }; ++ ++ pinctrl_sai2: sai2grp { ++ fsl,pins = < ++ MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 ++ MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031 ++ MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 ++ MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 ++ MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 ++ >; ++ }; ++ ++ pinctrl_uart1: uart1grp { ++ fsl,pins = < ++ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 ++ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_uart2: uart2grp { ++ fsl,pins = < ++ MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 ++ MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 ++ MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 ++ MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_usdhc1: usdhc1grp { ++ fsl,pins = < ++ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 ++ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 ++ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 ++ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 ++ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 ++ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 ++ >; ++ }; ++ ++ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { ++ fsl,pins = < ++ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 ++ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 ++ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 ++ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 ++ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 ++ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 ++ >; ++ }; ++ ++ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { ++ fsl,pins = < ++ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 ++ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 ++ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 ++ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 ++ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 ++ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 ++ >; ++ }; ++ ++ pinctrl_usdhc2: usdhc2grp { ++ fsl,pins = < ++ MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070 ++ MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070 ++ MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070 ++ MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070 ++ MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070 ++ MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070 ++ >; ++ }; ++}; +diff --git a/arch/arm/boot/dts/imx6ul-geam.dtsi b/arch/arm/boot/dts/imx6ul-geam.dtsi +deleted file mode 100644 +index eb94d956808b..000000000000 +--- a/arch/arm/boot/dts/imx6ul-geam.dtsi ++++ /dev/null +@@ -1,406 +0,0 @@ +-/* +- * Copyright (C) 2016 Amarula Solutions B.V. +- * Copyright (C) 2016 Engicam S.r.l. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include "imx6ul.dtsi" +- +-/ { +- memory { +- reg = <0x80000000 0x08000000>; +- }; +- +- backlight { +- compatible = "pwm-backlight"; +- pwms = <&pwm8 0 100000>; +- brightness-levels = < 0 1 2 3 4 5 6 7 8 9 +- 10 11 12 13 14 15 16 17 18 19 +- 20 21 22 23 24 25 26 27 28 29 +- 30 31 32 33 34 35 36 37 38 39 +- 40 41 42 43 44 45 46 47 48 49 +- 50 51 52 53 54 55 56 57 58 59 +- 60 61 62 63 64 65 66 67 68 69 +- 70 71 72 73 74 75 76 77 78 79 +- 80 81 82 83 84 85 86 87 88 89 +- 90 91 92 93 94 95 96 97 98 99 +- 100>; +- default-brightness-level = <100>; +- }; +- +- chosen { +- stdout-path = &uart1; +- }; +- +- reg_1p8v: regulator-1p8v { +- compatible = "regulator-fixed"; +- regulator-name = "1P8V"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- reg_3p3v: regulator-3p3v { +- compatible = "regulator-fixed"; +- regulator-name = "3P3V"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- }; +-}; +- +-&can1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan1>; +- xceiver-supply = <®_3p3v>; +-}; +- +-&can2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_flexcan2>; +- xceiver-supply = <®_3p3v>; +-}; +- +-&fec1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet1>; +- phy-mode = "rmii"; +- phy-handle = <ðphy0>; +- status = "okay"; +-}; +- +-&fec2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_enet2>; +- phy-mode = "rmii"; +- phy-handle = <ðphy1>; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ethphy0: ethernet-phy@0 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; +- }; +- +- ethphy1: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +- }; +-}; +- +-&gpmi { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpmi_nand>; +- nand-on-flash-bbt; +- status = "okay"; +-}; +- +-&i2c1 { +- clock-frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c1>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock_frequency = <100000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_i2c2>; +- status = "okay"; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif_dat +- &pinctrl_lcdif_ctrl>; +- display = <&display0>; +-}; +- +-&pwm8 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm8>; +- status = "okay"; +-}; +- +-&tsc { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_tsc>; +- xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; +-}; +- +-&sai2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_sai2>; +- status = "okay"; +-}; +- +-&uart1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart2>; +- status = "okay"; +-}; +- +-&usbotg1 { +- dr_mode = "peripheral"; +- status = "okay"; +-}; +- +-&usbotg2 { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usdhc1 { +- pinctrl-names = "default", "state_100mhz", "state_200mhz"; +- pinctrl-0 = <&pinctrl_usdhc1>; +- pinctrl-1 = <&pinctrl_usdhc1_100mhz>; +- pinctrl-2 = <&pinctrl_usdhc1_200mhz>; +- bus-width = <4>; +- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; +- no-1-8-v; +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_enet1: enet1grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 +- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 +- >; +- }; +- +- pinctrl_enet2: enet2grp { +- fsl,pins = < +- MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 +- MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 +- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 +- MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */ +- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 +- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 +- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 +- MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031 +- >; +- }; +- +- pinctrl_flexcan1: flexcan1grp { +- fsl,pins = < +- MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 +- MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 +- >; +- }; +- +- pinctrl_flexcan2: flexcan2grp { +- fsl,pins = < +- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 +- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 +- >; +- }; +- +- pinctrl_gpmi_nand: gpmi-nand { +- fsl,pins = < +- MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 +- MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 +- MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 +- MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 +- MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 +- MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 +- MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 +- MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 +- MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 +- MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 +- MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 +- MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 +- MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 +- MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 +- MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 +- >; +- }; +- +- pinctrl_i2c1: i2c1grp { +- fsl,pins = < +- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 +- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_i2c2: i2c2grp { +- fsl,pins = < +- MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 +- MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 +- >; +- }; +- +- pinctrl_lcdif_ctrl: lcdifctrlgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 +- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 +- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 +- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 +- >; +- }; +- +- pinctrl_lcdif_dat: lcdifdatgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 +- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 +- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 +- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 +- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 +- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 +- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 +- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 +- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 +- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 +- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 +- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 +- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 +- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 +- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 +- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 +- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 +- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 +- >; +- }; +- +- pinctrl_pwm8: pwm8grp { +- fsl,pins = < +- MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 +- >; +- }; +- +- pinctrl_tsc: tscgrp { +- fsl,pin = < +- MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 +- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 +- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 +- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 +- >; +- }; +- +- pinctrl_sai2: sai2grp { +- fsl,pins = < +- MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 +- MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031 +- MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 +- MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 +- MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 +- >; +- }; +- +- pinctrl_uart1: uart1grp { +- fsl,pins = < +- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 +- >; +- }; +- +- pinctrl_uart2: uart2grp { +- fsl,pins = < +- MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 +- MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 +- MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 +- MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 +- >; +- }; +- +- pinctrl_usdhc1: usdhc1grp { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 +- >; +- }; +- +- pinctrl_usdhc1_100mhz: usdhc1grp100mhz { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 +- >; +- }; +- +- pinctrl_usdhc1_200mhz: usdhc1grp200mhz { +- fsl,pins = < +- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 +- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 +- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 +- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 +- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 +- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 +- >; +- }; +- +- pinctrl_usdhc2: usdhc2grp { +- fsl,pins = < +- MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070 +- MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070 +- MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070 +- MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070 +- MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070 +- MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070 +- >; +- }; +-}; +diff --git a/arch/arm/boot/dts/imx6ul-isiot-common.dtsi b/arch/arm/boot/dts/imx6ul-isiot-common.dtsi +deleted file mode 100644 +index 2beaab6e272e..000000000000 +--- a/arch/arm/boot/dts/imx6ul-isiot-common.dtsi ++++ /dev/null +@@ -1,141 +0,0 @@ +-/* +- * Copyright (C) 2016 Amarula Solutions B.V. +- * Copyright (C) 2016 Engicam S.r.l. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 as published by the Free Software Foundation. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-&i2c1 { +- stmpe811: gpio-expander@44 { +- compatible = "st,stmpe811"; +- reg = <0x44>; +- #address-cells = <1>; +- #size-cells = <0>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_stmpe>; +- interrupt-parent = <&gpio1>; +- interrupts = <18 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- stmpe: touchscreen { +- compatible = "st,stmpe-ts"; +- st,sample-time = <4>; +- st,mod-12b = <1>; +- st,ref-sel = <0>; +- st,adc-freq = <1>; +- st,ave-ctrl = <1>; +- st,touch-det-delay = <2>; +- st,settling = <2>; +- st,fraction-z = <7>; +- st,i-drive = <1>; +- }; +- }; +-}; +- +-&lcdif { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_lcdif_dat +- &pinctrl_lcdif_ctrl>; +- display = <&display0>; +- status = "okay"; +- +- display0: display { +- bits-per-pixel = <16>; +- bus-width = <18>; +- +- display-timings { +- native-mode = <&timing0>; +- timing0: timing0 { +- clock-frequency = <28000000>; +- hactive = <800>; +- vactive = <480>; +- hfront-porch = <30>; +- hback-porch = <30>; +- hsync-len = <64>; +- vback-porch = <5>; +- vfront-porch = <5>; +- vsync-len = <20>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; +- }; +- }; +-}; +- +-&iomuxc { +- pinctrl_lcdif_ctrl: lcdifctrlgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 +- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 +- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 +- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 +- >; +- }; +- +- pinctrl_lcdif_dat: lcdifdatgrp { +- fsl,pins = < +- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 +- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 +- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 +- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 +- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 +- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 +- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 +- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 +- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 +- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 +- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 +- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 +- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 +- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 +- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 +- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 +- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 +- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 +- >; +- }; +- +- pinctrl_stmpe: stmpegrp { +- fsl,pins = < +- MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0 +- >; +- }; +-}; +diff --git a/arch/arm/boot/dts/imx6ul-isiot-emmc.dts b/arch/arm/boot/dts/imx6ul-isiot-emmc.dts +index 73a1d0f0b9d5..f5b422898e61 100644 +--- a/arch/arm/boot/dts/imx6ul-isiot-emmc.dts ++++ b/arch/arm/boot/dts/imx6ul-isiot-emmc.dts +@@ -43,7 +43,6 @@ + /dts-v1/; + + #include "imx6ul-isiot.dtsi" +-#include "imx6ul-isiot-common.dtsi" + + / { + model = "Engicam Is.IoT MX6UL eMMC Starter kit"; +diff --git a/arch/arm/boot/dts/imx6ul-isiot-nand.dts b/arch/arm/boot/dts/imx6ul-isiot-nand.dts +index da29a86eb6a8..de15e1c75dd1 100644 +--- a/arch/arm/boot/dts/imx6ul-isiot-nand.dts ++++ b/arch/arm/boot/dts/imx6ul-isiot-nand.dts +@@ -43,7 +43,6 @@ + /dts-v1/; + + #include "imx6ul-isiot.dtsi" +-#include "imx6ul-isiot-common.dtsi" + + / { + model = "Engicam Is.IoT MX6UL NAND Starter kit"; +diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi +index ea30380ad7a4..950fb28b630a 100644 +--- a/arch/arm/boot/dts/imx6ul-isiot.dtsi ++++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi +@@ -69,6 +69,68 @@ backlight { + 100>; + default-brightness-level = <100>; + }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "1P8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "imx6ul-isiot-sgtl5000"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,bitclock-master = <&dailink_master>; ++ simple-audio-card,frame-master = <&dailink_master>; ++ simple-audio-card,widgets = ++ "Microphone", "Mic Jack", ++ "Line", "Line In", ++ "Line", "Line Out", ++ "Headphone", "Headphone Jack"; ++ simple-audio-card,routing = ++ "MIC_IN", "Mic Jack", ++ "Mic Jack", "Mic Bias", ++ "Headphone Jack", "HP_OUT"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&sai2>; ++ }; ++ ++ dailink_master: simple-audio-card,codec { ++ sound-dai = <&sgtl5000>; ++ clocks = <&clks IMX6UL_CLK_SAI2>; ++ }; ++ }; ++}; ++ ++&fec1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_enet1>; ++ phy-mode = "rmii"; ++ phy-handle = <ðphy0>; ++ status = "okay"; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ethphy0: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ }; ++ }; + }; + + &i2c1 { +@@ -76,6 +138,42 @@ &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; ++ ++ sgtl5000: codec@a { ++ compatible = "fsl,sgtl5000"; ++ reg = <0x0a>; ++ clocks = <&clks IMX6UL_CLK_OSC>; ++ clock-names = "mclk"; ++ VDDA-supply = <®_3p3v>; ++ VDDIO-supply = <®_3p3v>; ++ VDDD-supply = <®_1p8v>; ++ }; ++ ++ stmpe811: gpio-expander@44 { ++ compatible = "st,stmpe811"; ++ reg = <0x44>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_stmpe>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <18 IRQ_TYPE_EDGE_FALLING>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ++ stmpe: touchscreen { ++ compatible = "st,stmpe-ts"; ++ st,sample-time = <4>; ++ st,mod-12b = <1>; ++ st,ref-sel = <0>; ++ st,adc-freq = <1>; ++ st,ave-ctrl = <1>; ++ st,touch-det-delay = <2>; ++ st,settling = <2>; ++ st,fraction-z = <7>; ++ st,i-drive = <1>; ++ }; ++ }; + }; + + &i2c2 { +@@ -85,6 +183,38 @@ &i2c2 { + status = "okay"; + }; + ++&lcdif { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_lcdif_dat ++ &pinctrl_lcdif_ctrl>; ++ display = <&display0>; ++ status = "okay"; ++ ++ display0: display { ++ bits-per-pixel = <16>; ++ bus-width = <18>; ++ ++ display-timings { ++ native-mode = <&timing0>; ++ timing0: timing0 { ++ clock-frequency = <28000000>; ++ hactive = <800>; ++ vactive = <480>; ++ hfront-porch = <30>; ++ hback-porch = <30>; ++ hsync-len = <64>; ++ vback-porch = <5>; ++ vfront-porch = <5>; ++ vsync-len = <20>; ++ hsync-active = <0>; ++ vsync-active = <0>; ++ de-active = <1>; ++ pixelclk-active = <0>; ++ }; ++ }; ++ }; ++}; ++ + &pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; +@@ -115,6 +245,21 @@ &usdhc1 { + }; + + &iomuxc { ++ pinctrl_enet1: enet1grp { ++ fsl,pins = < ++ MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0 ++ MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0 ++ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 ++ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 ++ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 ++ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 ++ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 ++ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 ++ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 ++ MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 ++ >; ++ }; ++ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 +@@ -129,6 +274,38 @@ MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 + >; + }; + ++ pinctrl_lcdif_ctrl: lcdifctrlgrp { ++ fsl,pins = < ++ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 ++ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 ++ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 ++ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 ++ >; ++ }; ++ ++ pinctrl_lcdif_dat: lcdifdatgrp { ++ fsl,pins = < ++ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 ++ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 ++ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 ++ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 ++ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 ++ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 ++ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 ++ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 ++ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 ++ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 ++ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 ++ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 ++ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 ++ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 ++ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 ++ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 ++ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 ++ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 ++ >; ++ }; ++ + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 +@@ -145,6 +322,12 @@ MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 + >; + }; + ++ pinctrl_stmpe: stmpegrp { ++ fsl,pins = < ++ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0 ++ >; ++ }; ++ + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 +diff --git a/arch/arm/boot/dts/imx6ul-liteboard.dts b/arch/arm/boot/dts/imx6ul-liteboard.dts +index ed1d891d6a89..1d863a16bcf0 100644 +--- a/arch/arm/boot/dts/imx6ul-liteboard.dts ++++ b/arch/arm/boot/dts/imx6ul-liteboard.dts +@@ -124,6 +124,10 @@ ethphy0: ethernet-phy@0 { + }; + }; + ++&snvs_poweroff { ++ status = "okay"; ++}; ++ + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi +index 6da2b77edd46..f11a241a340d 100644 +--- a/arch/arm/boot/dts/imx6ul.dtsi ++++ b/arch/arm/boot/dts/imx6ul.dtsi +@@ -614,6 +614,7 @@ snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; ++ value = <0x60>; + mask = <0x60>; + status = "disabled"; + }; +diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi +index d7753f79937a..0a3915868aa3 100644 +--- a/arch/arm/boot/dts/imx7-colibri.dtsi ++++ b/arch/arm/boot/dts/imx7-colibri.dtsi +@@ -106,6 +106,15 @@ &fec1 { + fsl,magic-packet; + }; + ++&gpmi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpmi_nand>; ++ fsl,use-minimum-ecc; ++ nand-on-flash-bbt; ++ nand-ecc-mode = "hw"; ++ status = "okay"; ++}; ++ + &i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; +diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts +index 0a24d1bf3c39..44637cabcc56 100644 +--- a/arch/arm/boot/dts/imx7d-sdb.dts ++++ b/arch/arm/boot/dts/imx7d-sdb.dts +@@ -117,6 +117,37 @@ reg_brcm: regulator-brcm { + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; ++ ++ reg_lcd_3v3: regulator-lcd-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "lcd-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ reg_can2_3v3: regulator-can2-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "can2-3v3"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexcan2_reg>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; ++ }; ++ ++ panel { ++ compatible = "innolux,at043tn24"; ++ pinctrl-0 = <&pinctrl_backlight>; ++ enable-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; ++ power-supply = <®_lcd_3v3>; ++ ++ port { ++ panel_in: endpoint { ++ remote-endpoint = <&display_out>; ++ }; ++ }; ++ }; + }; + + &adc1 { +@@ -168,6 +199,7 @@ &fec1 { + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; ++ phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { +@@ -197,6 +229,13 @@ &fec2 { + status = "okay"; + }; + ++&flexcan2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexcan2>; ++ xceiver-supply = <®_can2_3v3>; ++ status = "okay"; ++}; ++ + &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; +@@ -285,8 +324,8 @@ vgen5_reg: vldo3 { + }; + + vgen6_reg: vldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + }; +@@ -322,31 +361,11 @@ codec: wm8960@1a { + &lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; +- display = <&display0>; + status = "okay"; + +- display0: display { +- bits-per-pixel = <16>; +- bus-width = <24>; +- +- display-timings { +- native-mode = <&timing0>; +- +- timing0: timing0 { +- clock-frequency = <9200000>; +- hactive = <480>; +- vactive = <272>; +- hfront-porch = <8>; +- hback-porch = <4>; +- hsync-len = <41>; +- vback-porch = <2>; +- vfront-porch = <4>; +- vsync-len = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <0>; +- }; ++ port { ++ display_out: endpoint { ++ remote-endpoint = <&panel_in>; + }; + }; + }; +@@ -356,12 +375,6 @@ &pcie { + status = "okay"; + }; + +-&pwm1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_pwm1>; +- status = "okay"; +-}; +- + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +@@ -488,6 +501,20 @@ MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + >; + }; + ++ pinctrl_flexcan2: flexcan2grp { ++ fsl,pins = < ++ MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 ++ MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 ++ >; ++ }; ++ ++ pinctrl_flexcan2_reg: flexcan2reggrp { ++ fsl,pins = < ++ MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ ++ >; ++ }; ++ ++ + pinctrl_hog: hoggrp { + fsl,pins = < + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 +@@ -701,9 +728,9 @@ MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; + +- pinctrl_pwm1: pwm1grp { ++ pinctrl_backlight: backlightgrp { + fsl,pins = < +- MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0 ++ MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x110b0 + >; + }; + }; +diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi +index 4cf6c458b583..82ad26e766eb 100644 +--- a/arch/arm/boot/dts/imx7s.dtsi ++++ b/arch/arm/boot/dts/imx7s.dtsi +@@ -540,6 +540,7 @@ snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; ++ value = <0x60>; + mask = <0x60>; + }; + +@@ -1021,5 +1022,36 @@ fec1: ethernet@30be0000 { + status = "disabled"; + }; + }; ++ ++ dma_apbh: dma-apbh@33000000 { ++ compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; ++ reg = <0x33000000 0x2000>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; ++ #dma-cells = <1>; ++ dma-channels = <4>; ++ clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; ++ }; ++ ++ gpmi: gpmi-nand@33002000{ ++ compatible = "fsl,imx7d-gpmi-nand"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0x33002000 0x2000>, <0x33004000 0x4000>; ++ reg-names = "gpmi-nand", "bch"; ++ interrupts = ; ++ interrupt-names = "bch"; ++ clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, ++ <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; ++ clock-names = "gpmi_io", "gpmi_bch_apb"; ++ dmas = <&dma_apbh 0>; ++ dma-names = "rx-tx"; ++ status = "disabled"; ++ assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; ++ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; ++ }; + }; + }; +diff --git a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/keystone-k2e-evm.dts +index ae1ebe7ee021..f1f32c54e72f 100644 +--- a/arch/arm/boot/dts/keystone-k2e-evm.dts ++++ b/arch/arm/boot/dts/keystone-k2e-evm.dts +@@ -16,6 +16,19 @@ / { + compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"; + model = "Texas Instruments Keystone 2 Edison EVM"; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ dsp_common_memory: dsp-common-memory@81f800000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00000008 0x1f800000 0x00000000 0x800000>; ++ reusable; ++ status = "okay"; ++ }; ++ }; ++ + soc { + + clocks { +@@ -160,3 +173,8 @@ ethphy1: ethernet-phy@1 { + reg = <1>; + }; + }; ++ ++&dsp0 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi +index 0dd4cdd6d40c..819ab8345916 100644 +--- a/arch/arm/boot/dts/keystone-k2e.dtsi ++++ b/arch/arm/boot/dts/keystone-k2e.dtsi +@@ -45,6 +45,10 @@ cpu@3 { + }; + }; + ++ aliases { ++ rproc0 = &dsp0; ++ }; ++ + soc { + /include/ "keystone-k2e-clocks.dtsi" + +@@ -114,6 +118,22 @@ dspgpio0: keystone_dsp_gpio@02620240 { + gpio,syscon-dev = <&devctrl 0x240>; + }; + ++ dsp0: dsp@10800000 { ++ compatible = "ti,k2e-dsp"; ++ reg = <0x10800000 0x00080000>, ++ <0x10e00000 0x00008000>, ++ <0x10f00000 0x00008000>; ++ reg-names = "l2sram", "l1pram", "l1dram"; ++ clocks = <&clkgem0>; ++ ti,syscon-dev = <&devctrl 0x844>; ++ resets = <&pscrst 0>; ++ interrupt-parent = <&kirq0>; ++ interrupts = <0 8>; ++ interrupt-names = "vring", "exception"; ++ kick-gpios = <&dspgpio0 27 0>; ++ status = "disabled"; ++ }; ++ + pcie1: pcie@21020000 { + compatible = "ti,keystone-pcie","snps,dw-pcie"; + clocks = <&clkpcie1>; +diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts +index 61883cb969d2..f462f1043531 100644 +--- a/arch/arm/boot/dts/keystone-k2g-evm.dts ++++ b/arch/arm/boot/dts/keystone-k2g-evm.dts +@@ -25,6 +25,26 @@ memory@800000000 { + reg = <0x00000008 0x00000000 0x00000000 0x80000000>; + }; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ dsp_common_memory: dsp-common-memory@81f800000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00000008 0x1f800000 0x00000000 0x800000>; ++ reusable; ++ status = "okay"; ++ }; ++ }; ++ ++ vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin { ++ compatible = "regulator-fixed"; ++ regulator-name = "mmc0_fixed"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; + }; + + &k2g_pinctrl { +@@ -34,6 +54,33 @@ K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd. + K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; ++ ++ mmc0_pins: pinmux_mmc0_pins { ++ pinctrl-single,pins = < ++ K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */ ++ K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */ ++ K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */ ++ K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */ ++ K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */ ++ K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */ ++ K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc0_sdcd.gpio1_12 */ ++ >; ++ }; ++ ++ mmc1_pins: pinmux_mmc1_pins { ++ pinctrl-single,pins = < ++ K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */ ++ K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */ ++ K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat5.mmc1_dat5 */ ++ K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat4.mmc1_dat4 */ ++ K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ ++ K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ ++ K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ ++ K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ ++ K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ ++ K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ ++ >; ++ }; + }; + + &uart0 { +@@ -41,3 +88,27 @@ &uart0 { + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; ++ ++&gpio1 { ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <&vcc3v3_dcin_reg>; ++ cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */ ++ status = "okay"; ++}; ++ ++&dsp0 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts +index d820d37b5148..78692745e0af 100644 +--- a/arch/arm/boot/dts/keystone-k2g-ice.dts ++++ b/arch/arm/boot/dts/keystone-k2g-ice.dts +@@ -17,6 +17,19 @@ memory@800000000 { + device_type = "memory"; + reg = <0x00000008 0x00000000 0x00000000 0x20000000>; + }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ dsp_common_memory: dsp-common-memory@81f800000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00000008 0x1f800000 0x00000000 0x800000>; ++ reusable; ++ status = "okay"; ++ }; ++ }; + }; + + &k2g_pinctrl { +@@ -33,3 +46,8 @@ &uart0 { + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; ++ ++&dsp0 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi +index a789f75a1ed5..826b286665e6 100644 +--- a/arch/arm/boot/dts/keystone-k2g.dtsi ++++ b/arch/arm/boot/dts/keystone-k2g.dtsi +@@ -15,6 +15,7 @@ + + #include + #include ++#include + + / { + compatible = "ti,k2g","ti,keystone"; +@@ -27,6 +28,7 @@ / { + + aliases { + serial0 = &uart0; ++ rproc0 = &dsp0; + }; + + cpus { +@@ -113,6 +115,24 @@ uart0: serial@02530c00 { + status = "disabled"; + }; + ++ dcan0: can@0260B200 { ++ compatible = "ti,am4372-d_can", "ti,am3352-d_can"; ++ reg = <0x0260B200 0x200>; ++ interrupts = ; ++ status = "disabled"; ++ power-domains = <&k2g_pds 0x0008>; ++ clocks = <&k2g_clks 0x0008 1>; ++ }; ++ ++ dcan1: can@0260B400 { ++ compatible = "ti,am4372-d_can", "ti,am3352-d_can"; ++ reg = <0x0260B400 0x200>; ++ interrupts = ; ++ status = "disabled"; ++ power-domains = <&k2g_pds 0x0009>; ++ clocks = <&k2g_clks 0x0009 1>; ++ }; ++ + kirq0: keystone_irq@026202a0 { + compatible = "ti,keystone-irq"; + interrupts = ; +@@ -128,6 +148,22 @@ dspgpio0: keystone_dsp_gpio@02620240 { + gpio,syscon-dev = <&devctrl 0x240>; + }; + ++ dsp0: dsp@10800000 { ++ compatible = "ti,k2g-dsp"; ++ reg = <0x10800000 0x00100000>, ++ <0x10e00000 0x00008000>, ++ <0x10f00000 0x00008000>; ++ reg-names = "l2sram", "l1pram", "l1dram"; ++ power-domains = <&k2g_pds 0x0046>; ++ ti,syscon-dev = <&devctrl 0x844>; ++ resets = <&k2g_reset 0x0046 0x1>; ++ interrupt-parent = <&kirq0>; ++ interrupts = <0 8>; ++ interrupt-names = "vring", "exception"; ++ kick-gpios = <&dspgpio0 27 0>; ++ status = "disabled"; ++ }; ++ + msgmgr: msgmgr@02a00000 { + compatible = "ti,k2g-message-manager"; + #mbox-cells = <2>; +@@ -139,5 +175,173 @@ msgmgr: msgmgr@02a00000 { + interrupts = , + ; + }; ++ ++ pmmc: pmmc@02921c00 { ++ compatible = "ti,k2g-sci"; ++ /* ++ * In case of rare platforms that does not use k2g as ++ * system master, use /delete-property/ ++ */ ++ ti,system-reboot-controller; ++ mbox-names = "rx", "tx"; ++ mboxes= <&msgmgr 5 2>, ++ <&msgmgr 0 0>; ++ reg-names = "debug_messages"; ++ reg = <0x02921c00 0x400>; ++ ++ k2g_pds: power-controller { ++ compatible = "ti,sci-pm-domain"; ++ #power-domain-cells = <1>; ++ }; ++ ++ k2g_clks: clocks { ++ compatible = "ti,k2g-sci-clk"; ++ #clock-cells = <2>; ++ }; ++ ++ k2g_reset: reset-controller { ++ compatible = "ti,sci-reset"; ++ #reset-cells = <2>; ++ }; ++ }; ++ ++ gpio0: gpio@2603000 { ++ compatible = "ti,k2g-gpio", "ti,keystone-gpio"; ++ reg = <0x02603000 0x100>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ti,ngpio = <144>; ++ ti,davinci-gpio-unbanked = <0>; ++ clocks = <&k2g_clks 0x001b 0x0>; ++ clock-names = "gpio"; ++ }; ++ ++ gpio1: gpio@260a000 { ++ compatible = "ti,k2g-gpio", "ti,keystone-gpio"; ++ reg = <0x0260a000 0x100>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ti,ngpio = <68>; ++ ti,davinci-gpio-unbanked = <0>; ++ clocks = <&k2g_clks 0x001c 0x0>; ++ clock-names = "gpio"; ++ }; ++ ++ edma0: edma@02700000 { ++ compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; ++ reg = <0x02700000 0x8000>; ++ reg-names = "edma3_cc"; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "edma3_ccint", "emda3_mperr", ++ "edma3_ccerrint"; ++ dma-requests = <64>; ++ #dma-cells = <2>; ++ ++ ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; ++ ++ ti,edma-memcpy-channels = <32 33 34 35>; ++ ++ power-domains = <&k2g_pds 0x3f>; ++ }; ++ ++ edma0_tptc0: tptc@02760000 { ++ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; ++ reg = <0x02760000 0x400>; ++ power-domains = <&k2g_pds 0x3f>; ++ }; ++ ++ edma0_tptc1: tptc@02768000 { ++ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; ++ reg = <0x02768000 0x400>; ++ power-domains = <&k2g_pds 0x3f>; ++ }; ++ ++ edma1: edma@02728000 { ++ compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; ++ reg = <0x02728000 0x8000>; ++ reg-names = "edma3_cc"; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "edma3_ccint", "emda3_mperr", ++ "edma3_ccerrint"; ++ dma-requests = <64>; ++ #dma-cells = <2>; ++ ++ ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>; ++ ++ /* ++ * memcpy is disabled, can be enabled with: ++ * ti,edma-memcpy-channels = <12 13 14 15>; ++ * for example. ++ */ ++ ++ power-domains = <&k2g_pds 0x4f>; ++ }; ++ ++ edma1_tptc0: tptc@027b0000 { ++ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; ++ reg = <0x027b0000 0x400>; ++ power-domains = <&k2g_pds 0x4f>; ++ }; ++ ++ edma1_tptc1: tptc@027b8000 { ++ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; ++ reg = <0x027b8000 0x400>; ++ power-domains = <&k2g_pds 0x4f>; ++ }; ++ ++ mmc0: mmc@23000000 { ++ compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc"; ++ reg = <0x23000000 0x400>; ++ interrupts = ; ++ dmas = <&edma1 24 0>, <&edma1 25 0>; ++ dma-names = "tx", "rx"; ++ bus-width = <4>; ++ ti,needs-special-reset; ++ no-1-8-v; ++ max-frequency = <96000000>; ++ power-domains = <&k2g_pds 0xb>; ++ clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>; ++ clock-names = "fck", "mmchsdb_fck"; ++ status = "disabled"; ++ }; ++ ++ mmc1: mmc@23100000 { ++ compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc"; ++ reg = <0x23100000 0x400>; ++ interrupts = ; ++ dmas = <&edma1 26 0>, <&edma1 27 0>; ++ dma-names = "tx", "rx"; ++ bus-width = <8>; ++ ti,needs-special-reset; ++ ti,non-removable; ++ max-frequency = <96000000>; ++ power-domains = <&k2g_pds 0xc>; ++ clocks = <&k2g_clks 0xc 1>, <&k2g_clks 0xc 2>; ++ clock-names = "fck", "mmchsdb_fck"; ++ status = "disabled"; ++ }; + }; + }; +diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts +index 2156ff92d08f..6dd13b98aaba 100644 +--- a/arch/arm/boot/dts/keystone-k2hk-evm.dts ++++ b/arch/arm/boot/dts/keystone-k2hk-evm.dts +@@ -16,6 +16,19 @@ / { + compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"; + model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ dsp_common_memory: dsp-common-memory@81f800000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00000008 0x1f800000 0x00000000 0x800000>; ++ reusable; ++ status = "okay"; ++ }; ++ }; ++ + soc { + clocks { + refclksys: refclksys { +@@ -184,3 +197,43 @@ ethphy1: ethernet-phy@1 { + reg = <1>; + }; + }; ++ ++&dsp0 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; ++ ++&dsp1 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; ++ ++&dsp2 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; ++ ++&dsp3 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; ++ ++&dsp4 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; ++ ++&dsp5 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; ++ ++&dsp6 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; ++ ++&dsp7 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi +index 69d449430511..31dc00e4e5fd 100644 +--- a/arch/arm/boot/dts/keystone-k2hk.dtsi ++++ b/arch/arm/boot/dts/keystone-k2hk.dtsi +@@ -45,6 +45,17 @@ cpu@3 { + }; + }; + ++ aliases { ++ rproc0 = &dsp0; ++ rproc1 = &dsp1; ++ rproc2 = &dsp2; ++ rproc3 = &dsp3; ++ rproc4 = &dsp4; ++ rproc5 = &dsp5; ++ rproc6 = &dsp6; ++ rproc7 = &dsp7; ++ }; ++ + soc { + /include/ "keystone-k2hk-clocks.dtsi" + +@@ -134,6 +145,134 @@ dspgpio7: keystone_dsp_gpio@262025c { + gpio,syscon-dev = <&devctrl 0x25c>; + }; + ++ dsp0: dsp@10800000 { ++ compatible = "ti,k2hk-dsp"; ++ reg = <0x10800000 0x00100000>, ++ <0x10e00000 0x00008000>, ++ <0x10f00000 0x00008000>; ++ reg-names = "l2sram", "l1pram", "l1dram"; ++ clocks = <&clkgem0>; ++ ti,syscon-dev = <&devctrl 0x40>; ++ resets = <&pscrst 0>; ++ interrupt-parent = <&kirq0>; ++ interrupts = <0 8>; ++ interrupt-names = "vring", "exception"; ++ kick-gpios = <&dspgpio0 27 0>; ++ status = "disabled"; ++ }; ++ ++ dsp1: dsp@11800000 { ++ compatible = "ti,k2hk-dsp"; ++ reg = <0x11800000 0x00100000>, ++ <0x11e00000 0x00008000>, ++ <0x11f00000 0x00008000>; ++ reg-names = "l2sram", "l1pram", "l1dram"; ++ clocks = <&clkgem1>; ++ ti,syscon-dev = <&devctrl 0x44>; ++ resets = <&pscrst 1>; ++ interrupt-parent = <&kirq0>; ++ interrupts = <1 9>; ++ interrupt-names = "vring", "exception"; ++ kick-gpios = <&dspgpio1 27 0>; ++ status = "disabled"; ++ }; ++ ++ dsp2: dsp@12800000 { ++ compatible = "ti,k2hk-dsp"; ++ reg = <0x12800000 0x00100000>, ++ <0x12e00000 0x00008000>, ++ <0x12f00000 0x00008000>; ++ reg-names = "l2sram", "l1pram", "l1dram"; ++ clocks = <&clkgem2>; ++ ti,syscon-dev = <&devctrl 0x48>; ++ resets = <&pscrst 2>; ++ interrupt-parent = <&kirq0>; ++ interrupts = <2 10>; ++ interrupt-names = "vring", "exception"; ++ kick-gpios = <&dspgpio2 27 0>; ++ status = "disabled"; ++ }; ++ ++ dsp3: dsp@13800000 { ++ compatible = "ti,k2hk-dsp"; ++ reg = <0x13800000 0x00100000>, ++ <0x13e00000 0x00008000>, ++ <0x13f00000 0x00008000>; ++ reg-names = "l2sram", "l1pram", "l1dram"; ++ clocks = <&clkgem3>; ++ ti,syscon-dev = <&devctrl 0x4c>; ++ resets = <&pscrst 3>; ++ interrupt-parent = <&kirq0>; ++ interrupts = <3 11>; ++ interrupt-names = "vring", "exception"; ++ kick-gpios = <&dspgpio3 27 0>; ++ status = "disabled"; ++ }; ++ ++ dsp4: dsp@14800000 { ++ compatible = "ti,k2hk-dsp"; ++ reg = <0x14800000 0x00100000>, ++ <0x14e00000 0x00008000>, ++ <0x14f00000 0x00008000>; ++ reg-names = "l2sram", "l1pram", "l1dram"; ++ clocks = <&clkgem4>; ++ ti,syscon-dev = <&devctrl 0x50>; ++ resets = <&pscrst 4>; ++ interrupt-parent = <&kirq0>; ++ interrupts = <4 12>; ++ interrupt-names = "vring", "exception"; ++ kick-gpios = <&dspgpio4 27 0>; ++ status = "disabled"; ++ }; ++ ++ dsp5: dsp@15800000 { ++ compatible = "ti,k2hk-dsp"; ++ reg = <0x15800000 0x00100000>, ++ <0x15e00000 0x00008000>, ++ <0x15f00000 0x00008000>; ++ reg-names = "l2sram", "l1pram", "l1dram"; ++ clocks = <&clkgem5>; ++ ti,syscon-dev = <&devctrl 0x54>; ++ resets = <&pscrst 5>; ++ interrupt-parent = <&kirq0>; ++ interrupts = <5 13>; ++ interrupt-names = "vring", "exception"; ++ kick-gpios = <&dspgpio5 27 0>; ++ status = "disabled"; ++ }; ++ ++ dsp6: dsp@16800000 { ++ compatible = "ti,k2hk-dsp"; ++ reg = <0x16800000 0x00100000>, ++ <0x16e00000 0x00008000>, ++ <0x16f00000 0x00008000>; ++ reg-names = "l2sram", "l1pram", "l1dram"; ++ clocks = <&clkgem6>; ++ ti,syscon-dev = <&devctrl 0x58>; ++ resets = <&pscrst 6>; ++ interrupt-parent = <&kirq0>; ++ interrupts = <6 14>; ++ interrupt-names = "vring", "exception"; ++ kick-gpios = <&dspgpio6 27 0>; ++ status = "disabled"; ++ }; ++ ++ dsp7: dsp@17800000 { ++ compatible = "ti,k2hk-dsp"; ++ reg = <0x17800000 0x00100000>, ++ <0x17e00000 0x00008000>, ++ <0x17f00000 0x00008000>; ++ reg-names = "l2sram", "l1pram", "l1dram"; ++ clocks = <&clkgem7>; ++ ti,syscon-dev = <&devctrl 0x5c>; ++ resets = <&pscrst 7>; ++ interrupt-parent = <&kirq0>; ++ interrupts = <7 15>; ++ interrupt-names = "vring", "exception"; ++ kick-gpios = <&dspgpio7 27 0>; ++ status = "disabled"; ++ }; ++ + mdio: mdio@02090300 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; +diff --git a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/keystone-k2l-evm.dts +index 056b42f99d7a..528667618db4 100644 +--- a/arch/arm/boot/dts/keystone-k2l-evm.dts ++++ b/arch/arm/boot/dts/keystone-k2l-evm.dts +@@ -16,6 +16,19 @@ / { + compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone"; + model = "Texas Instruments Keystone 2 Lamarr EVM"; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ dsp_common_memory: dsp-common-memory@81f800000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00000008 0x1f800000 0x00000000 0x800000>; ++ reusable; ++ status = "okay"; ++ }; ++ }; ++ + soc { + clocks { + refclksys: refclksys { +@@ -133,3 +146,23 @@ ethphy1: ethernet-phy@1 { + reg = <1>; + }; + }; ++ ++&dsp0 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; ++ ++&dsp1 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; ++ ++&dsp2 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; ++ ++&dsp3 { ++ memory-region = <&dsp_common_memory>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi +index 148650406cf7..4431310bc922 100644 +--- a/arch/arm/boot/dts/keystone-k2l.dtsi ++++ b/arch/arm/boot/dts/keystone-k2l.dtsi +@@ -33,6 +33,13 @@ cpu@1 { + }; + }; + ++ aliases { ++ rproc0 = &dsp0; ++ rproc1 = &dsp1; ++ rproc2 = &dsp2; ++ rproc3 = &dsp3; ++ }; ++ + soc { + /include/ "keystone-k2l-clocks.dtsi" + +@@ -268,6 +275,70 @@ dspgpio3: keystone_dsp_gpio@262024c { + gpio,syscon-dev = <&devctrl 0x24c>; + }; + ++ dsp0: dsp@10800000 { ++ compatible = "ti,k2l-dsp"; ++ reg = <0x10800000 0x00100000>, ++ <0x10e00000 0x00008000>, ++ <0x10f00000 0x00008000>; ++ reg-names = "l2sram", "l1pram", "l1dram"; ++ clocks = <&clkgem0>; ++ ti,syscon-dev = <&devctrl 0x844>; ++ resets = <&pscrst 0>; ++ interrupt-parent = <&kirq0>; ++ interrupts = <0 8>; ++ interrupt-names = "vring", "exception"; ++ kick-gpios = <&dspgpio0 27 0>; ++ status = "disabled"; ++ }; ++ ++ dsp1: dsp@11800000 { ++ compatible = "ti,k2l-dsp"; ++ reg = <0x11800000 0x00100000>, ++ <0x11e00000 0x00008000>, ++ <0x11f00000 0x00008000>; ++ reg-names = "l2sram", "l1pram", "l1dram"; ++ clocks = <&clkgem1>; ++ ti,syscon-dev = <&devctrl 0x848>; ++ resets = <&pscrst 1>; ++ interrupt-parent = <&kirq0>; ++ interrupts = <1 9>; ++ interrupt-names = "vring", "exception"; ++ kick-gpios = <&dspgpio1 27 0>; ++ status = "disabled"; ++ }; ++ ++ dsp2: dsp@12800000 { ++ compatible = "ti,k2l-dsp"; ++ reg = <0x12800000 0x00100000>, ++ <0x12e00000 0x00008000>, ++ <0x12f00000 0x00008000>; ++ reg-names = "l2sram", "l1pram", "l1dram"; ++ clocks = <&clkgem2>; ++ ti,syscon-dev = <&devctrl 0x84c>; ++ resets = <&pscrst 2>; ++ interrupt-parent = <&kirq0>; ++ interrupts = <2 10>; ++ interrupt-names = "vring", "exception"; ++ kick-gpios = <&dspgpio2 27 0>; ++ status = "disabled"; ++ }; ++ ++ dsp3: dsp@13800000 { ++ compatible = "ti,k2l-dsp"; ++ reg = <0x13800000 0x00100000>, ++ <0x13e00000 0x00008000>, ++ <0x13f00000 0x00008000>; ++ reg-names = "l2sram", "l1pram", "l1dram"; ++ clocks = <&clkgem3>; ++ ti,syscon-dev = <&devctrl 0x850>; ++ resets = <&pscrst 3>; ++ interrupt-parent = <&kirq0>; ++ interrupts = <3 11>; ++ interrupt-names = "vring", "exception"; ++ kick-gpios = <&dspgpio3 27 0>; ++ status = "disabled"; ++ }; ++ + mdio: mdio@26200f00 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; +diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi +index d573e03f3134..f003f3f1bd65 100644 +--- a/arch/arm/boot/dts/kirkwood-6192.dtsi ++++ b/arch/arm/boot/dts/kirkwood-6192.dtsi +@@ -1,6 +1,6 @@ + / { + mbus@f1000000 { +- pciec: pcie-controller@82000000 { ++ pciec: pcie@82000000 { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; +@@ -24,6 +24,7 @@ pcie0: pcie@1,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; +diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi +index 748d0b62f233..47d4b3d3d9e9 100644 +--- a/arch/arm/boot/dts/kirkwood-6281.dtsi ++++ b/arch/arm/boot/dts/kirkwood-6281.dtsi +@@ -1,6 +1,6 @@ + / { + mbus@f1000000 { +- pciec: pcie-controller@82000000 { ++ pciec: pcie@82000000 { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; +@@ -24,6 +24,7 @@ pcie0: pcie@1,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; +diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi +index bb63d2d50fc5..a13dad0a7c08 100644 +--- a/arch/arm/boot/dts/kirkwood-6282.dtsi ++++ b/arch/arm/boot/dts/kirkwood-6282.dtsi +@@ -1,6 +1,6 @@ + / { + mbus@f1000000 { +- pciec: pcie-controller@82000000 { ++ pciec: pcie@82000000 { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; +@@ -28,6 +28,7 @@ pcie0: pcie@1,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; +@@ -45,6 +46,7 @@ pcie1: pcie@2,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 10>; + marvell,pcie-port = <1>; +diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +index 720c210d491d..90d4d71b6683 100644 +--- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi ++++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +@@ -1,6 +1,6 @@ + / { + mbus@f1000000 { +- pciec: pcie-controller@82000000 { ++ pciec: pcie@82000000 { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; +@@ -24,6 +24,7 @@ pcie0: pcie@1,0 { + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; +diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +index 43e9364083de..b4575bbaf085 100644 +--- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts ++++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +@@ -192,7 +192,7 @@ &mmc1 { + interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins &mmc1_cd>; +- cd-gpios = <&gpio4 31 IRQ_TYPE_LEVEL_LOW>; /* gpio127 */ ++ cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio127 */ + vmmc-supply = <&vmmc1>; + bus-width = <4>; + cap-power-off-card; +diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi +index 15204e44161d..cd6ad072e72c 100644 +--- a/arch/arm/boot/dts/meson.dtsi ++++ b/arch/arm/boot/dts/meson.dtsi +@@ -86,14 +86,14 @@ hwrng: rng@8100 { + }; + + uart_A: serial@84c0 { +- compatible = "amlogic,meson-uart"; ++ compatible = "amlogic,meson6-uart", "amlogic,meson-uart"; + reg = <0x84c0 0x18>; + interrupts = ; + status = "disabled"; + }; + + uart_B: serial@84dc { +- compatible = "amlogic,meson-uart"; ++ compatible = "amlogic,meson6-uart", "amlogic,meson-uart"; + reg = <0x84dc 0x18>; + interrupts = ; + status = "disabled"; +@@ -108,6 +108,20 @@ i2c_A: i2c@8500 { + status = "disabled"; + }; + ++ pwm_ab: pwm@8550 { ++ compatible = "amlogic,meson-pwm"; ++ reg = <0x8550 0x10>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm_cd: pwm@8650 { ++ compatible = "amlogic,meson-pwm"; ++ reg = <0x8650 0x10>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + saradc: adc@8680 { + compatible = "amlogic,meson-saradc"; + reg = <0x8680 0x34>; +@@ -117,7 +131,7 @@ saradc: adc@8680 { + }; + + uart_C: serial@8700 { +- compatible = "amlogic,meson-uart"; ++ compatible = "amlogic,meson6-uart", "amlogic,meson-uart"; + reg = <0x8700 0x18>; + interrupts = ; + status = "disabled"; +@@ -182,7 +196,7 @@ ir_receiver: ir-receiver@480 { + }; + + uart_AO: serial@4c0 { +- compatible = "amlogic,meson-uart"; ++ compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart"; + reg = <0x4c0 0x18>; + interrupts = ; + status = "disabled"; +@@ -230,5 +244,13 @@ ethmac: ethernet@c9410000 { + interrupt-names = "macirq"; + status = "disabled"; + }; ++ ++ ahb_sram: sram@d9000000 { ++ compatible = "mmio-sram"; ++ reg = <0xd9000000 0x20000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0xd9000000 0x20000>; ++ }; + }; + }; /* end of / */ +diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi +index 8557b6117a4b..ef281d290052 100644 +--- a/arch/arm/boot/dts/meson6.dtsi ++++ b/arch/arm/boot/dts/meson6.dtsi +@@ -70,9 +70,37 @@ cpu@201 { + }; + }; + ++ xtal: xtal-clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ clock-output-names = "xtal"; ++ #clock-cells = <0>; ++ }; ++ + clk81: clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; /* end of / */ ++ ++ ++&uart_AO { ++ clocks = <&xtal>, <&clk81>, <&clk81>; ++ clock-names = "xtal", "pclk", "baud"; ++}; ++ ++&uart_A { ++ clocks = <&xtal>, <&clk81>, <&clk81>; ++ clock-names = "xtal", "pclk", "baud"; ++}; ++ ++&uart_B { ++ clocks = <&xtal>, <&clk81>, <&clk81>; ++ clock-names = "xtal", "pclk", "baud"; ++}; ++ ++&uart_C { ++ clocks = <&xtal>, <&clk81>, <&clk81>; ++ clock-names = "xtal", "pclk", "baud"; ++}; +diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi +index cada35828931..b98d44fde6b6 100644 +--- a/arch/arm/boot/dts/meson8.dtsi ++++ b/arch/arm/boot/dts/meson8.dtsi +@@ -168,10 +168,18 @@ mux { + &cbus { + clkc: clock-controller@4000 { + #clock-cells = <1>; ++ #reset-cells = <1>; + compatible = "amlogic,meson8-clkc"; + reg = <0x8000 0x4>, <0x4000 0x460>; + }; + ++ pwm_ef: pwm@86c0 { ++ compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; ++ reg = <0x86c0 0x10>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + pinctrl_cbus: pinctrl@9880 { + compatible = "amlogic,meson8-cbus-pinctrl"; + reg = <0x9880 0x10>; +@@ -270,6 +278,14 @@ &L2 { + arm,filter-ranges = <0x100000 0xc0000000>; + }; + ++&pwm_ab { ++ compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; ++}; ++ ++&pwm_cd { ++ compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; ++}; ++ + &saradc { + compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; + clocks = <&clkc CLKID_XTAL>, +diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi +index 72e4f425f190..bc278da7df0d 100644 +--- a/arch/arm/boot/dts/meson8b.dtsi ++++ b/arch/arm/boot/dts/meson8b.dtsi +@@ -119,6 +119,7 @@ mux { + &cbus { + clkc: clock-controller@4000 { + #clock-cells = <1>; ++ #reset-cells = <1>; + compatible = "amlogic,meson8b-clkc"; + reg = <0x8000 0x4>, <0x4000 0x460>; + }; +@@ -129,20 +130,6 @@ reset: reset-controller@4404 { + #reset-cells = <1>; + }; + +- pwm_ab: pwm@8550 { +- compatible = "amlogic,meson8b-pwm"; +- reg = <0x8550 0x10>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- pwm_cd: pwm@8650 { +- compatible = "amlogic,meson8b-pwm"; +- reg = <0x8650 0x10>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- + pwm_ef: pwm@86c0 { + compatible = "amlogic,meson8b-pwm"; + reg = <0x86c0 0x10>; +@@ -150,12 +137,6 @@ pwm_ef: pwm@86c0 { + status = "disabled"; + }; + +- wdt: watchdog@9900 { +- compatible = "amlogic,meson8b-wdt"; +- reg = <0x9900 0x8>; +- interrupts = <0 0 1>; +- }; +- + pinctrl_cbus: pinctrl@9880 { + compatible = "amlogic,meson8b-cbus-pinctrl"; + reg = <0x9880 0x10>; +@@ -193,6 +174,14 @@ &L2 { + arm,filter-ranges = <0x100000 0xc0000000>; + }; + ++&pwm_ab { ++ compatible = "amlogic,meson8b-pwm"; ++}; ++ ++&pwm_cd { ++ compatible = "amlogic,meson8b-pwm"; ++}; ++ + &saradc { + compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; + clocks = <&clkc CLKID_XTAL>, +@@ -242,3 +231,7 @@ &usb1_phy { + clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; + }; ++ ++&wdt { ++ compatible = "amlogic,meson8b-wdt"; ++}; +diff --git a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi +index 1eb5da1dc8f0..4d61e5b1334a 100644 +--- a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi ++++ b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi +@@ -255,5 +255,6 @@ vaudio: VAUDIO { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-enable-ramp-delay = <1000>; ++ regulator-initial-mode = <0x00>; /* NORMAL */ + }; + }; +diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi +index f1efdc63656a..afe12e5b51f9 100644 +--- a/arch/arm/boot/dts/mt2701.dtsi ++++ b/arch/arm/boot/dts/mt2701.dtsi +@@ -13,6 +13,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -533,6 +534,7 @@ larb0: larb@14010000 { + compatible = "mediatek,mt2701-smi-larb"; + reg = <0 0x14010000 0 0x1000>; + mediatek,smi = <&smi_common>; ++ mediatek,larb-id = <0>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; +@@ -549,6 +551,7 @@ larb2: larb@15001000 { + compatible = "mediatek,mt2701-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; ++ mediatek,larb-id = <2>; + clocks = <&imgsys CLK_IMG_SMI_COMM>, + <&imgsys CLK_IMG_SMI_COMM>; + clock-names = "apb", "smi"; +@@ -579,6 +582,7 @@ larb1: larb@16010000 { + compatible = "mediatek,mt2701-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; ++ mediatek,larb-id = <1>; + clocks = <&vdecsys CLK_VDEC_CKGEN>, + <&vdecsys CLK_VDEC_LARB>; + clock-names = "apb", "smi"; +@@ -591,12 +595,114 @@ hifsys: syscon@1a000000 { + #clock-cells = <1>; + }; + ++ usb0: usb@1a1c0000 { ++ compatible = "mediatek,mt8173-xhci"; ++ reg = <0 0x1a1c0000 0 0x1000>, ++ <0 0x1a1c4700 0 0x0100>; ++ reg-names = "mac", "ippc"; ++ interrupts = ; ++ clocks = <&hifsys CLK_HIFSYS_USB0PHY>, ++ <&topckgen CLK_TOP_ETHIF_SEL>; ++ clock-names = "sys_ck", "ref_ck"; ++ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; ++ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; ++ status = "disabled"; ++ }; ++ ++ u3phy0: usb-phy@1a1c4000 { ++ compatible = "mediatek,mt2701-u3phy"; ++ reg = <0 0x1a1c4000 0 0x0700>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ u2port0: usb-phy@1a1c4800 { ++ reg = <0 0x1a1c4800 0 0x0100>; ++ clocks = <&topckgen CLK_TOP_USB_PHY48M>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ status = "okay"; ++ }; ++ ++ u3port0: usb-phy@1a1c4900 { ++ reg = <0 0x1a1c4900 0 0x0700>; ++ clocks = <&clk26m>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ status = "okay"; ++ }; ++ }; ++ ++ usb1: usb@1a240000 { ++ compatible = "mediatek,mt8173-xhci"; ++ reg = <0 0x1a240000 0 0x1000>, ++ <0 0x1a244700 0 0x0100>; ++ reg-names = "mac", "ippc"; ++ interrupts = ; ++ clocks = <&hifsys CLK_HIFSYS_USB1PHY>, ++ <&topckgen CLK_TOP_ETHIF_SEL>; ++ clock-names = "sys_ck", "ref_ck"; ++ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; ++ phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; ++ status = "disabled"; ++ }; ++ ++ u3phy1: usb-phy@1a244000 { ++ compatible = "mediatek,mt2701-u3phy"; ++ reg = <0 0x1a244000 0 0x0700>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ u2port1: usb-phy@1a244800 { ++ reg = <0 0x1a244800 0 0x0100>; ++ clocks = <&topckgen CLK_TOP_USB_PHY48M>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ status = "okay"; ++ }; ++ ++ u3port1: usb-phy@1a244900 { ++ reg = <0 0x1a244900 0 0x0700>; ++ clocks = <&clk26m>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ status = "okay"; ++ }; ++ }; ++ + ethsys: syscon@1b000000 { + compatible = "mediatek,mt2701-ethsys", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + ++ eth: ethernet@1b100000 { ++ compatible = "mediatek,mt2701-eth", "syscon"; ++ reg = <0 0x1b100000 0 0x20000>; ++ interrupts = , ++ , ++ ; ++ clocks = <&topckgen CLK_TOP_ETHIF_SEL>, ++ <ðsys CLK_ETHSYS_ESW>, ++ <ðsys CLK_ETHSYS_GP1>, ++ <ðsys CLK_ETHSYS_GP2>, ++ <&apmixedsys CLK_APMIXED_TRGPLL>; ++ clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; ++ resets = <ðsys MT2701_ETHSYS_FE_RST>, ++ <ðsys MT2701_ETHSYS_GMAC_RST>, ++ <ðsys MT2701_ETHSYS_PPE_RST>; ++ reset-names = "fe", "gmac", "ppe"; ++ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; ++ mediatek,ethsys = <ðsys>; ++ mediatek,pctl = <&syscfg_pctl_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + bdpsys: syscon@1c000000 { + compatible = "mediatek,mt2701-bdpsys", "syscon"; + reg = <0 0x1c000000 0 0x1000>; +diff --git a/arch/arm/boot/dts/mt6323.dtsi b/arch/arm/boot/dts/mt6323.dtsi +new file mode 100644 +index 000000000000..7c783d6c750e +--- /dev/null ++++ b/arch/arm/boot/dts/mt6323.dtsi +@@ -0,0 +1,241 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: John Crispin ++ * Sean Wang ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++&pwrap { ++ pmic: mt6323 { ++ compatible = "mediatek,mt6323"; ++ interrupt-parent = <&pio>; ++ interrupts = <150 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ++ mt6323regulator: mt6323regulator{ ++ compatible = "mediatek,mt6323-regulator"; ++ ++ mt6323_vproc_reg: buck_vproc{ ++ regulator-name = "vproc"; ++ regulator-min-microvolt = < 700000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <12500>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6323_vsys_reg: buck_vsys{ ++ regulator-name = "vsys"; ++ regulator-min-microvolt = <1400000>; ++ regulator-max-microvolt = <2987500>; ++ regulator-ramp-delay = <25000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6323_vpa_reg: buck_vpa{ ++ regulator-name = "vpa"; ++ regulator-min-microvolt = < 500000>; ++ regulator-max-microvolt = <3650000>; ++ }; ++ ++ mt6323_vtcxo_reg: ldo_vtcxo{ ++ regulator-name = "vtcxo"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-enable-ramp-delay = <90>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6323_vcn28_reg: ldo_vcn28{ ++ regulator-name = "vcn28"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-enable-ramp-delay = <185>; ++ }; ++ ++ mt6323_vcn33_bt_reg: ldo_vcn33_bt{ ++ regulator-name = "vcn33_bt"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3600000>; ++ regulator-enable-ramp-delay = <185>; ++ }; ++ ++ mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{ ++ regulator-name = "vcn33_wifi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3600000>; ++ regulator-enable-ramp-delay = <185>; ++ }; ++ ++ mt6323_va_reg: ldo_va{ ++ regulator-name = "va"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-enable-ramp-delay = <216>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6323_vcama_reg: ldo_vcama{ ++ regulator-name = "vcama"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-enable-ramp-delay = <216>; ++ }; ++ ++ mt6323_vio28_reg: ldo_vio28{ ++ regulator-name = "vio28"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-enable-ramp-delay = <216>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6323_vusb_reg: ldo_vusb{ ++ regulator-name = "vusb"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <216>; ++ regulator-boot-on; ++ }; ++ ++ mt6323_vmc_reg: ldo_vmc{ ++ regulator-name = "vmc"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <36>; ++ regulator-boot-on; ++ }; ++ ++ mt6323_vmch_reg: ldo_vmch{ ++ regulator-name = "vmch"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <36>; ++ regulator-boot-on; ++ }; ++ ++ mt6323_vemc3v3_reg: ldo_vemc3v3{ ++ regulator-name = "vemc3v3"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <36>; ++ regulator-boot-on; ++ }; ++ ++ mt6323_vgp1_reg: ldo_vgp1{ ++ regulator-name = "vgp1"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <216>; ++ }; ++ ++ mt6323_vgp2_reg: ldo_vgp2{ ++ regulator-name = "vgp2"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-enable-ramp-delay = <216>; ++ }; ++ ++ mt6323_vgp3_reg: ldo_vgp3{ ++ regulator-name = "vgp3"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-enable-ramp-delay = <216>; ++ }; ++ ++ mt6323_vcn18_reg: ldo_vcn18{ ++ regulator-name = "vcn18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-enable-ramp-delay = <216>; ++ }; ++ ++ mt6323_vsim1_reg: ldo_vsim1{ ++ regulator-name = "vsim1"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-enable-ramp-delay = <216>; ++ }; ++ ++ mt6323_vsim2_reg: ldo_vsim2{ ++ regulator-name = "vsim2"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-enable-ramp-delay = <216>; ++ }; ++ ++ mt6323_vrtc_reg: ldo_vrtc{ ++ regulator-name = "vrtc"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6323_vcamaf_reg: ldo_vcamaf{ ++ regulator-name = "vcamaf"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <216>; ++ }; ++ ++ mt6323_vibr_reg: ldo_vibr{ ++ regulator-name = "vibr"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <36>; ++ }; ++ ++ mt6323_vrf18_reg: ldo_vrf18{ ++ regulator-name = "vrf18"; ++ regulator-min-microvolt = <1825000>; ++ regulator-max-microvolt = <1825000>; ++ regulator-enable-ramp-delay = <187>; ++ }; ++ ++ mt6323_vm_reg: ldo_vm{ ++ regulator-name = "vm"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-enable-ramp-delay = <216>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6323_vio18_reg: ldo_vio18{ ++ regulator-name = "vio18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-enable-ramp-delay = <216>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6323_vcamd_reg: ldo_vcamd{ ++ regulator-name = "vcamd"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-enable-ramp-delay = <216>; ++ }; ++ ++ mt6323_vcamio_reg: ldo_vcamio{ ++ regulator-name = "vcamio"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-enable-ramp-delay = <216>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts +deleted file mode 100644 +index b60b41cad592..000000000000 +--- a/arch/arm/boot/dts/mt7623-evb.dts ++++ /dev/null +@@ -1,33 +0,0 @@ +-/* +- * Copyright (c) 2016 MediaTek Inc. +- * Author: John Crispin +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-/dts-v1/; +-#include "mt7623.dtsi" +- +-/ { +- model = "MediaTek MT7623 evaluation board"; +- compatible = "mediatek,mt7623-evb", "mediatek,mt7623"; +- +- chosen { +- stdout-path = &uart2; +- }; +- +- memory { +- reg = <0 0x80000000 0 0x40000000>; +- }; +-}; +- +-&uart2 { +- status = "okay"; +-}; +diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi +index d81158b2b02f..ec8a07415cb3 100644 +--- a/arch/arm/boot/dts/mt7623.dtsi ++++ b/arch/arm/boot/dts/mt7623.dtsi +@@ -21,36 +21,99 @@ + #include + #include + #include ++#include + #include "skeleton64.dtsi" + + / { + compatible = "mediatek,mt7623"; + interrupt-parent = <&sysirq>; + ++ cpu_opp_table: opp_table { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-98000000 { ++ opp-hz = /bits/ 64 <98000000>; ++ opp-microvolt = <1050000>; ++ }; ++ ++ opp-198000000 { ++ opp-hz = /bits/ 64 <198000000>; ++ opp-microvolt = <1050000>; ++ }; ++ ++ opp-398000000 { ++ opp-hz = /bits/ 64 <398000000>; ++ opp-microvolt = <1050000>; ++ }; ++ ++ opp-598000000 { ++ opp-hz = /bits/ 64 <598000000>; ++ opp-microvolt = <1050000>; ++ }; ++ ++ opp-747500000 { ++ opp-hz = /bits/ 64 <747500000>; ++ opp-microvolt = <1050000>; ++ }; ++ ++ opp-1040000000 { ++ opp-hz = /bits/ 64 <1040000000>; ++ opp-microvolt = <1150000>; ++ }; ++ ++ opp-1196000000 { ++ opp-hz = /bits/ 64 <1196000000>; ++ opp-microvolt = <1200000>; ++ }; ++ ++ opp-1300000000 { ++ opp-hz = /bits/ 64 <1300000000>; ++ opp-microvolt = <1300000>; ++ }; ++ }; ++ + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt6589-smp"; + +- cpu@0 { ++ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; ++ clocks = <&infracfg CLK_INFRA_CPUSEL>, ++ <&apmixedsys CLK_APMIXED_MAINPLL>; ++ clock-names = "cpu", "intermediate"; ++ operating-points-v2 = <&cpu_opp_table>; ++ #cooling-cells = <2>; ++ cooling-min-level = <0>; ++ cooling-max-level = <7>; ++ clock-frequency = <1300000000>; + }; +- cpu@1 { ++ ++ cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clock-frequency = <1300000000>; + }; +- cpu@2 { ++ ++ cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clock-frequency = <1300000000>; + }; +- cpu@3 { ++ ++ cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clock-frequency = <1300000000>; + }; + }; + +@@ -74,6 +137,58 @@ clk26m: oscillator@0 { + clock-output-names = "clk26m"; + }; + ++ thermal-zones { ++ cpu_thermal: cpu_thermal { ++ polling-delay-passive = <1000>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&thermal 0>; ++ ++ trips { ++ cpu_passive: cpu_passive { ++ temperature = <47000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_active: cpu_active { ++ temperature = <67000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_hot: cpu_hot { ++ temperature = <87000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ ++ cpu_crit { ++ temperature = <107000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_passive>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ ++ map1 { ++ trip = <&cpu_active>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ ++ map2 { ++ trip = <&cpu_hot>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ }; ++ + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; +@@ -172,7 +287,7 @@ pwrap: pwrap@1000d000 { + clock-names = "spi", "wrap"; + }; + +- cir: cir@0x10013000 { ++ cir: cir@10013000 { + compatible = "mediatek,mt7623-cir"; + reg = <0 0x10013000 0 0x1000>; + interrupts = ; +@@ -193,7 +308,7 @@ sysirq: interrupt-controller@10200100 { + efuse: efuse@10206000 { + compatible = "mediatek,mt7623-efuse", + "mediatek,mt8173-efuse"; +- reg = <0 0x10206000 0 0x1000>; ++ reg = <0 0x10206000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + thermal_calibration_data: calib@424 { +@@ -371,6 +486,31 @@ thermal: thermal@1100b000 { + nvmem-cell-names = "calibration-data"; + }; + ++ nandc: nfi@1100d000 { ++ compatible = "mediatek,mt7623-nfc", ++ "mediatek,mt2701-nfc"; ++ reg = <0 0x1100d000 0 0x1000>; ++ interrupts = ; ++ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; ++ clocks = <&pericfg CLK_PERI_NFI>, ++ <&pericfg CLK_PERI_NFI_PAD>; ++ clock-names = "nfi_clk", "pad_clk"; ++ status = "disabled"; ++ ecc-engine = <&bch>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ bch: ecc@1100e000 { ++ compatible = "mediatek,mt7623-ecc", ++ "mediatek,mt2701-ecc"; ++ reg = <0 0x1100e000 0 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_NFI_ECC>; ++ clock-names = "nfiecc_clk"; ++ status = "disabled"; ++ }; ++ + spi1: spi@11016000 { + compatible = "mediatek,mt7623-spi", + "mediatek,mt2701-spi"; +@@ -399,31 +539,6 @@ spi2: spi@11017000 { + status = "disabled"; + }; + +- nandc: nfi@1100d000 { +- compatible = "mediatek,mt7623-nfc", +- "mediatek,mt2701-nfc"; +- reg = <0 0x1100d000 0 0x1000>; +- interrupts = ; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; +- clocks = <&pericfg CLK_PERI_NFI>, +- <&pericfg CLK_PERI_NFI_PAD>; +- clock-names = "nfi_clk", "pad_clk"; +- status = "disabled"; +- ecc-engine = <&bch>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- bch: ecc@1100e000 { +- compatible = "mediatek,mt7623-ecc", +- "mediatek,mt2701-ecc"; +- reg = <0 0x1100e000 0 0x1000>; +- interrupts = ; +- clocks = <&pericfg CLK_PERI_NFI_ECC>; +- clock-names = "nfiecc_clk"; +- status = "disabled"; +- }; +- + afe: audio-controller@11220000 { + compatible = "mediatek,mt7623-audio", + "mediatek,mt2701-audio"; +@@ -538,13 +653,22 @@ mmc1: mmc@11240000 { + compatible = "mediatek,mt7623-mmc", + "mediatek,mt8135-mmc"; + reg = <0 0x11240000 0 0x1000>; +- interrupts = ; ++ interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_1>, + <&topckgen CLK_TOP_MSDC30_1_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + ++ hifsys: syscon@1a000000 { ++ compatible = "mediatek,mt7623-hifsys", ++ "mediatek,mt2701-hifsys", ++ "syscon"; ++ reg = <0 0x1a000000 0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ + usb1: usb@1a1c0000 { + compatible = "mediatek,mt7623-xhci", + "mediatek,mt8173-xhci"; +@@ -561,7 +685,8 @@ usb1: usb@1a1c0000 { + }; + + u3phy1: usb-phy@1a1c4000 { +- compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy"; ++ compatible = "mediatek,mt7623-u3phy", ++ "mediatek,mt2701-u3phy"; + reg = <0 0x1a1c4000 0 0x0700>; + clocks = <&clk26m>; + clock-names = "u3phya_ref"; +@@ -599,7 +724,8 @@ usb2: usb@1a240000 { + }; + + u3phy2: usb-phy@1a244000 { +- compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy"; ++ compatible = "mediatek,mt7623-u3phy", ++ "mediatek,mt2701-u3phy"; + reg = <0 0x1a244000 0 0x0700>; + clocks = <&clk26m>; + clock-names = "u3phya_ref"; +@@ -621,15 +747,6 @@ u3port1: usb-phy@1a244900 { + }; + }; + +- hifsys: syscon@1a000000 { +- compatible = "mediatek,mt7623-hifsys", +- "mediatek,mt2701-hifsys", +- "syscon"; +- reg = <0 0x1a000000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- + ethsys: syscon@1b000000 { + compatible = "mediatek,mt7623-ethsys", + "mediatek,mt2701-ethsys", +@@ -639,7 +756,9 @@ ethsys: syscon@1b000000 { + }; + + eth: ethernet@1b100000 { +- compatible = "mediatek,mt2701-eth", "syscon"; ++ compatible = "mediatek,mt7623-eth", ++ "mediatek,mt2701-eth", ++ "syscon"; + reg = <0 0x1b100000 0 0x20000>; + interrupts = , + , +@@ -650,6 +769,10 @@ eth: ethernet@1b100000 { + <ðsys CLK_ETHSYS_GP2>, + <&apmixedsys CLK_APMIXED_TRGPLL>; + clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; ++ resets = <ðsys MT2701_ETHSYS_FE_RST>, ++ <ðsys MT2701_ETHSYS_GMAC_RST>, ++ <ðsys MT2701_ETHSYS_PPE_RST>; ++ reset-names = "fe", "gmac", "ppe"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; + mediatek,ethsys = <ðsys>; + mediatek,pctl = <&syscfg_pctl_a>; +diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +new file mode 100644 +index 000000000000..688a86378cee +--- /dev/null ++++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +@@ -0,0 +1,487 @@ ++/* ++ * Copyright 2017 Sean Wang ++ * ++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ */ ++ ++/dts-v1/; ++#include ++#include "mt7623.dtsi" ++#include "mt6323.dtsi" ++ ++/ { ++ model = "Bananapi BPI-R2"; ++ compatible = "bananapi,bpi-r2", "mediatek,mt7623"; ++ ++ aliases { ++ serial2 = &uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:115200n8"; ++ }; ++ ++ cpus { ++ cpu@0 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ ++ cpu@1 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ ++ cpu@2 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ ++ cpu@3 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&key_pins_a>; ++ ++ factory { ++ label = "factory"; ++ linux,code = ; ++ gpios = <&pio 256 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wps { ++ label = "wps"; ++ linux,code = ; ++ gpios = <&pio 257 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_pins_a>; ++ ++ blue { ++ label = "bpi-r2:pio:blue"; ++ gpios = <&pio 241 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ ++ green { ++ label = "bpi-r2:pio:green"; ++ gpios = <&pio 240 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ ++ red { ++ label = "bpi-r2:pio:red"; ++ gpios = <&pio 239 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ }; ++ ++ memory@80000000 { ++ reg = <0 0x80000000 0 0x40000000>; ++ }; ++}; ++ ++&cir { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cir_pins_a>; ++ status = "okay"; ++}; ++ ++&crypto { ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ ++ gmac0: mac@0 { ++ compatible = "mediatek,eth-mac"; ++ reg = <0>; ++ phy-mode = "trgmii"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ pause; ++ }; ++ }; ++ ++ mdio: mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ switch@0 { ++ compatible = "mediatek,mt7530"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ pinctrl-names = "default"; ++ reset-gpios = <&pio 33 0>; ++ core-supply = <&mt6323_vpa_reg>; ++ io-supply = <&mt6323_vemc3v3_reg>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ port@0 { ++ reg = <0>; ++ label = "wan"; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ label = "lan0"; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ label = "lan1"; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ label = "lan2"; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ label = "lan3"; ++ }; ++ ++ port@6 { ++ reg = <6>; ++ label = "cpu"; ++ ethernet = <&gmac0>; ++ phy-mode = "trgmii"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins_a>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins_a>; ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ pinctrl-1 = <&mmc0_pins_uhs>; ++ status = "okay"; ++ bus-width = <8>; ++ max-frequency = <50000000>; ++ cap-mmc-highspeed; ++ vmmc-supply = <&mt6323_vemc3v3_reg>; ++ vqmmc-supply = <&mt6323_vio18_reg>; ++ non-removable; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc1_pins_default>; ++ pinctrl-1 = <&mmc1_pins_uhs>; ++ status = "okay"; ++ bus-width = <4>; ++ max-frequency = <50000000>; ++ cap-sd-highspeed; ++ cd-gpios = <&pio 261 0>; ++ vmmc-supply = <&mt6323_vmch_reg>; ++ vqmmc-supply = <&mt6323_vio18_reg>; ++}; ++ ++&pio { ++ cir_pins_a:cir@0 { ++ pins_cir { ++ pinmux = ; ++ bias-disable; ++ }; ++ }; ++ ++ i2c0_pins_a: i2c@0 { ++ pins_i2c0 { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ }; ++ ++ i2c1_pins_a: i2c@1 { ++ pin_i2c1 { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ }; ++ ++ i2s0_pins_a: i2s@0 { ++ pin_i2s0 { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ drive-strength = ; ++ bias-pull-down; ++ }; ++ }; ++ ++ i2s1_pins_a: i2s@1 { ++ pin_i2s1 { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ drive-strength = ; ++ bias-pull-down; ++ }; ++ }; ++ ++ key_pins_a: keys@0 { ++ pins_keys { ++ pinmux = , ++ ; ++ input-enable; ++ }; ++ }; ++ ++ led_pins_a: leds@0 { ++ pins_leds { ++ pinmux = , ++ , ++ ; ++ }; ++ }; ++ ++ mmc0_pins_default: mmc0default { ++ pins_cmd_dat { ++ pinmux = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ input-enable; ++ bias-pull-up; ++ }; ++ ++ pins_clk { ++ pinmux = ; ++ bias-pull-down; ++ }; ++ ++ pins_rst { ++ pinmux = ; ++ bias-pull-up; ++ }; ++ }; ++ ++ mmc0_pins_uhs: mmc0 { ++ pins_cmd_dat { ++ pinmux = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ input-enable; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ pins_clk { ++ pinmux = ; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ ++ pins_rst { ++ pinmux = ; ++ bias-pull-up; ++ }; ++ }; ++ ++ mmc1_pins_default: mmc1default { ++ pins_cmd_dat { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ input-enable; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ pins_clk { ++ pinmux = ; ++ bias-pull-down; ++ drive-strength = ; ++ }; ++ ++ pins_wp { ++ pinmux = ; ++ input-enable; ++ bias-pull-up; ++ }; ++ ++ pins_insert { ++ pinmux = ; ++ bias-pull-up; ++ }; ++ }; ++ ++ mmc1_pins_uhs: mmc1 { ++ pins_cmd_dat { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ input-enable; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ pins_clk { ++ pinmux = ; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ }; ++ ++ pwm_pins_a: pwm@0 { ++ pins_pwm { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ }; ++ }; ++ ++ spi0_pins_a: spi@0 { ++ pins_spi { ++ pinmux = , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ }; ++ ++ uart0_pins_a: uart@0 { ++ pins_dat { ++ pinmux = , ++ ; ++ }; ++ }; ++ ++ uart1_pins_a: uart@1 { ++ pins_dat { ++ pinmux = , ++ ; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins_a>; ++ status = "okay"; ++}; ++ ++&pwrap { ++ mt6323 { ++ mt6323led: led { ++ compatible = "mediatek,mt6323-led"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ led@0 { ++ reg = <0>; ++ label = "bpi-r2:isink:green"; ++ default-state = "off"; ++ }; ++ ++ led@1 { ++ reg = <1>; ++ label = "bpi-r2:isink:red"; ++ default-state = "off"; ++ }; ++ ++ led@2 { ++ reg = <2>; ++ label = "bpi-r2:isink:blue"; ++ default-state = "off"; ++ }; ++ }; ++ }; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins_a>; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "disabled"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins_a>; ++ status = "disabled"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb1 { ++ vusb33-supply = <&mt6323_vusb_reg>; ++ status = "okay"; ++}; ++ ++&usb2 { ++ vusb33-supply = <&mt6323_vusb_reg>; ++ status = "okay"; ++}; ++ ++&u3phy1 { ++ status = "okay"; ++}; ++ ++&u3phy2 { ++ status = "okay"; ++}; ++ +diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts b/arch/arm/boot/dts/mt7623n-rfb-nand.dts +new file mode 100644 +index 000000000000..17c578f0d261 +--- /dev/null ++++ b/arch/arm/boot/dts/mt7623n-rfb-nand.dts +@@ -0,0 +1,111 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: John Crispin ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "mt7623n-rfb.dtsi" ++ ++/ { ++ model = "MediaTek MT7623N NAND reference board"; ++ compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623"; ++}; ++ ++&bch { ++ status = "okay"; ++}; ++ ++&nandc { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&nand_pins_default>; ++ ++ nand@0 { ++ reg = <0>; ++ spare_per_sector = <64>; ++ nand-ecc-mode = "hw"; ++ nand-ecc-strength = <12>; ++ nand-ecc-step-size = <1024>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "preloader"; ++ reg = <0x0 0x40000>; ++ }; ++ ++ partition@40000 { ++ label = "uboot"; ++ reg = <0x40000 0x80000>; ++ }; ++ ++ partition@C0000 { ++ label = "uboot-env"; ++ reg = <0xC0000 0x40000>; ++ }; ++ ++ partition@140000 { ++ label = "bootimg"; ++ reg = <0x140000 0x2000000>; ++ }; ++ ++ partition@2140000 { ++ label = "recovery"; ++ reg = <0x2140000 0x2000000>; ++ }; ++ ++ partition@4140000 { ++ label = "rootfs"; ++ reg = <0x4140000 0x1000000>; ++ }; ++ ++ partition@5140000 { ++ label = "usrdata"; ++ reg = <0x5140000 0x1000000>; ++ }; ++ }; ++ }; ++}; ++ ++&pio { ++ nand_pins_default: nanddefault { ++ pins_ale { ++ pinmux = ; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ ++ pins_dat { ++ pinmux = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ input-enable; ++ drive-strength = ; ++ bias-pull-up; ++ }; ++ ++ pins_we { ++ pinmux = ; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/mt7623n-rfb.dtsi b/arch/arm/boot/dts/mt7623n-rfb.dtsi +new file mode 100644 +index 000000000000..256c5fd947bf +--- /dev/null ++++ b/arch/arm/boot/dts/mt7623n-rfb.dtsi +@@ -0,0 +1,92 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: John Crispin ++ * Sean Wang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "mt7623.dtsi" ++#include "mt6323.dtsi" ++ ++/ { ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:115200n8"; ++ }; ++ ++ cpus { ++ cpu0 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ ++ cpu1 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ ++ cpu2 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ ++ cpu3 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ }; ++ ++ memory@80000000 { ++ reg = <0 0x80000000 0 0x40000000>; ++ }; ++ ++ usb_p1_vbus: regulator@0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&pio 135 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++}; ++ ++&mmc0 { ++ vmmc-supply = <&mt6323_vemc3v3_reg>; ++ vqmmc-supply = <&mt6323_vio18_reg>; ++}; ++ ++&mmc1 { ++ vmmc-supply = <&mt6323_vmch_reg>; ++ vqmmc-supply = <&mt6323_vmc_reg>; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb1 { ++ vbus-supply = <&usb_p1_vbus>; ++ status = "okay"; ++}; ++ ++&u3phy1 { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts +index 673cee2234b2..683b96a8f73e 100644 +--- a/arch/arm/boot/dts/omap3-beagle-xm.dts ++++ b/arch/arm/boot/dts/omap3-beagle-xm.dts +@@ -299,7 +299,7 @@ &i2c3 { + + &mmc1 { + vmmc-supply = <&vmmc1>; +- vmmc_aux-supply = <&vsim>; ++ vqmmc-supply = <&vsim>; + bus-width = <8>; + }; + +diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts +index 4be85ce59dd1..4d2eaf843fa9 100644 +--- a/arch/arm/boot/dts/omap3-beagle.dts ++++ b/arch/arm/boot/dts/omap3-beagle.dts +@@ -283,7 +283,7 @@ &i2c3 { + + &mmc1 { + vmmc-supply = <&vmmc1>; +- vmmc_aux-supply = <&vsim>; ++ vqmmc-supply = <&vsim>; + bus-width = <8>; + }; + +diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts +index 53ae04f9104d..3d293b345e99 100644 +--- a/arch/arm/boot/dts/omap3-cm-t3517.dts ++++ b/arch/arm/boot/dts/omap3-cm-t3517.dts +@@ -129,7 +129,7 @@ &mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&wl12xx_vmmc2>; +- vmmc_aux-supply = <&wl12xx_vaux2>; ++ vqmmc-supply = <&wl12xx_vaux2>; + non-removable; + bus-width = <4>; + cap-power-off-card; +diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts +index 2294f5b0aa10..bdf4b7fdda39 100644 +--- a/arch/arm/boot/dts/omap3-cm-t3730.dts ++++ b/arch/arm/boot/dts/omap3-cm-t3730.dts +@@ -69,7 +69,7 @@ &mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&wl12xx_vmmc2>; +- vmmc_aux-supply = <&wl12xx_vaux2>; ++ vqmmc-supply = <&wl12xx_vaux2>; + non-removable; + bus-width = <4>; + cap-power-off-card; +diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi +index 82aa9c4a0f1c..0c0bb1b01b0b 100644 +--- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi ++++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi +@@ -149,7 +149,7 @@ &i2c3 { + + &mmc1 { + vmmc-supply = <&vmmc1>; +- vmmc_aux-supply = <&vsim>; ++ vqmmc-supply = <&vsim>; + bus-width = <8>; + }; + +diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi +index 2b1d6977a535..ff35803088e3 100644 +--- a/arch/arm/boot/dts/omap3-evm-common.dtsi ++++ b/arch/arm/boot/dts/omap3-evm-common.dtsi +@@ -115,7 +115,7 @@ tsc2046@0 { + &mmc1 { + interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; + vmmc-supply = <&vmmc1>; +- vmmc_aux-supply = <&vsim>; ++ vqmmc-supply = <&vsim>; + bus-width = <8>; + }; + +diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts +index 49f37084e435..26c20e1167b9 100644 +--- a/arch/arm/boot/dts/omap3-n900.dts ++++ b/arch/arm/boot/dts/omap3-n900.dts +@@ -144,6 +144,15 @@ battery: n900-battery { + io-channel-names = "temp", "bsi", "vbat"; + }; + ++ rear_camera: camera@0 { ++ compatible = "linux,camera"; ++ ++ module { ++ model = "TCM8341MD"; ++ sensor = <&cam1>; ++ }; ++ }; ++ + pwm9: dmtimer-pwm { + compatible = "ti,omap-dmtimer-pwm"; + #pwm-cells = <3>; +@@ -164,6 +173,31 @@ vctcxo: vctcxo { + }; + }; + ++&isp { ++ vdds_csib-supply = <&vaux2>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&camera_pins>; ++ ++ ports { ++ port@1 { ++ reg = <1>; ++ ++ csi_isp: endpoint { ++ remote-endpoint = <&csi_cam1>; ++ bus-type = <3>; /* CCP2 */ ++ clock-lanes = <1>; ++ data-lanes = <0>; ++ lane-polarity = <0 0>; ++ clock-inv = <0>; ++ /* Select strobe = <1> for back camera, <0> for front camera */ ++ strobe = <1>; ++ crc = <0>; ++ }; ++ }; ++ }; ++}; ++ + &omap3_pmx_core { + pinctrl-names = "default"; + +@@ -328,6 +362,22 @@ modem_pins: pinmux_modem { + OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */ + >; + }; ++ ++ camera_pins: pinmux_camera { ++ pinctrl-single,pins = < ++ OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */ ++ OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */ ++ OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */ ++ OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE7) /* cam_d4 */ ++ OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6 */ ++ OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7 */ ++ OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE0) /* cam_d8 */ ++ OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE0) /* cam_d9 */ ++ OMAP3_CORE1_IOPAD(0x212a, PIN_OUTPUT | MUX_MODE7) /* cam_d10 */ ++ OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE7) /* cam_xclkb */ ++ OMAP3_CORE1_IOPAD(0x2132, PIN_OUTPUT | MUX_MODE0) /* cam_strobe */ ++ >; ++ }; + }; + + &i2c1 { +@@ -726,6 +776,40 @@ lis302dl: lis3lv02d@1d { + st,max-limit-y = <32>; + st,max-limit-z = <32>; + }; ++ ++ cam1: camera@3e { ++ compatible = "toshiba,et8ek8"; ++ reg = <0x3e>; ++ ++ vana-supply = <&vaux4>; ++ ++ clocks = <&isp 0>; ++ clock-names = "extclk"; ++ clock-frequency = <9600000>; ++ ++ reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ ++ ++ port { ++ csi_cam1: endpoint { ++ bus-type = <3>; /* CCP2 */ ++ strobe = <1>; ++ clock-inv = <0>; ++ crc = <1>; ++ ++ remote-endpoint = <&csi_isp>; ++ }; ++ }; ++ }; ++ ++ /* D/A converter for auto-focus */ ++ ad5820: dac@0c { ++ compatible = "adi,ad5820"; ++ reg = <0x0c>; ++ ++ VANA-supply = <&vaux4>; ++ ++ #io-channel-cells = <0>; ++ }; + }; + + &mmc1 { +@@ -733,6 +817,9 @@ &mmc1 { + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + bus-width = <4>; ++ /* For debugging, it is often good idea to remove this GPIO. ++ It means you can remove back cover (to reboot by removing ++ battery) and still use the MMC card. */ + cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */ + }; + +@@ -741,7 +828,7 @@ &mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&vaux3>; +- vmmc_aux-supply = <&vsim>; ++ vqmmc-supply = <&vsim>; + bus-width = <8>; + non-removable; + no-sdio; +diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi +index cd220342a805..f25e158e7163 100644 +--- a/arch/arm/boot/dts/omap3-overo-base.dtsi ++++ b/arch/arm/boot/dts/omap3-overo-base.dtsi +@@ -181,7 +181,7 @@ &mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&w3cbw003c_npoweron>; +- vmmc_aux-supply = <&w3cbw003c_wifi_nreset>; ++ vqmmc-supply = <&w3cbw003c_wifi_nreset>; + bus-width = <4>; + cap-sdio-irq; + non-removable; +diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi +index 06ac0f80bcf0..9a601d15247b 100644 +--- a/arch/arm/boot/dts/omap3-tao3530.dtsi ++++ b/arch/arm/boot/dts/omap3-tao3530.dtsi +@@ -223,7 +223,7 @@ &mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; +- vmmc_aux-supply = <&vsim>; ++ vqmmc-supply = <&vsim>; + cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; + bus-width = <8>; + }; +diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts +index 45e2ce0803de..96d0301a336a 100644 +--- a/arch/arm/boot/dts/omap3-zoom3.dts ++++ b/arch/arm/boot/dts/omap3-zoom3.dts +@@ -174,7 +174,7 @@ &twl_gpio { + + &mmc1 { + vmmc-supply = <&vmmc1>; +- vmmc_aux-supply = <&vsim>; ++ vqmmc-supply = <&vsim>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi +index a3ff4933dbc1..bdaf30c8c405 100644 +--- a/arch/arm/boot/dts/omap3.dtsi ++++ b/arch/arm/boot/dts/omap3.dtsi +@@ -713,14 +713,12 @@ usbhshost: usbhshost@48064000 { + usbhsohci: ohci@48064400 { + compatible = "ti,ohci-omap3"; + reg = <0x48064400 0x400>; +- interrupt-parent = <&intc>; + interrupts = <76>; + }; + + usbhsehci: ehci@48064800 { + compatible = "ti,ehci-omap"; + reg = <0x48064800 0x400>; +- interrupt-parent = <&intc>; + interrupts = <77>; + }; + }; +@@ -831,7 +829,6 @@ ssi_port1: ssi-port@4805a000 { + reg-names = "tx", + "rx"; + +- interrupt-parent = <&intc>; + interrupts = <67>, + <68>; + }; +@@ -844,7 +841,6 @@ ssi_port2: ssi-port@4805b000 { + reg-names = "tx", + "rx"; + +- interrupt-parent = <&intc>; + interrupts = <69>, + <70>; + }; +diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts +index abd6921143be..908951eb5943 100644 +--- a/arch/arm/boot/dts/omap3430-sdp.dts ++++ b/arch/arm/boot/dts/omap3430-sdp.dts +@@ -33,7 +33,7 @@ twl: twl@48 { + + &mmc1 { + vmmc-supply = <&vmmc1>; +- vmmc_aux-supply = <&vsim>; ++ vqmmc-supply = <&vsim>; + /* + * S6-3 must be in ON position for 8 bit mode to function + * Else, use 4 bit mode +diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts +index 10ca1c174995..8b93d37310f2 100644 +--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts ++++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts +@@ -129,6 +129,34 @@ touchscreen_reset { + output-high; + line-name = "touchscreen-reset"; + }; ++ ++ pwm8: dmtimer-pwm-8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vibrator_direction_pin>; ++ ++ compatible = "ti,omap-dmtimer-pwm"; ++ #pwm-cells = <3>; ++ ti,timers = <&timer8>; ++ ti,clock-source = <0x01>; ++ }; ++ ++ pwm9: dmtimer-pwm-9 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vibrator_enable_pin>; ++ ++ compatible = "ti,omap-dmtimer-pwm"; ++ #pwm-cells = <3>; ++ ti,timers = <&timer9>; ++ ti,clock-source = <0x01>; ++ }; ++ ++ vibrator { ++ compatible = "pwm-vibrator"; ++ pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>; ++ pwm-names = "enable", "direction"; ++ direction-duty-cycle-ns = <10000000>; ++ }; ++ + }; + + &dsi1 { +@@ -373,7 +401,7 @@ OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) + /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */ + dss_hdmi_pins: pinmux_dss_hdmi_pins { + pinctrl-single,pins = < +- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) ++ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) + OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) + OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) + >; +@@ -488,6 +516,18 @@ usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins { + OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3) + >; + }; ++ ++ vibrator_direction_pin: pinmux_vibrator_direction_pin { ++ pinctrl-single,pins = < ++ OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */ ++ >; ++ }; ++ ++ vibrator_enable_pin: pinmux_vibrator_enable_pin { ++ pinctrl-single,pins = < ++ OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */ ++ >; ++ }; + }; + + &uart3 { +diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts +index 1b825128a7b9..a9a584b5b955 100644 +--- a/arch/arm/boot/dts/omap4-duovero-parlor.dts ++++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts +@@ -100,7 +100,7 @@ OMAP4_IOPAD(0x070, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enab + dss_hdmi_pins: pinmux_dss_hdmi_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) /* hdmi_hpd.gpio_63 */ +- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ ++ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ + OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ + >; +diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi +index edbc4090297d..2b48e51c372a 100644 +--- a/arch/arm/boot/dts/omap4-panda-common.dtsi ++++ b/arch/arm/boot/dts/omap4-panda-common.dtsi +@@ -267,7 +267,7 @@ OMAP4_IOPAD(0x184, PIN_OUTPUT | MUX_MODE3) /* gpio_0 */ + + dss_hdmi_pins: pinmux_dss_hdmi_pins { + pinctrl-single,pins = < +- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ ++ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ + >; +diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts +index b4d19a7ae393..3d3140fd9659 100644 +--- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts ++++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts +@@ -10,7 +10,7 @@ + /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */ + &dss_hdmi_pins { + pinctrl-single,pins = < +- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ ++ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ + >; +diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts +index d728ec963111..280d92d42bf1 100644 +--- a/arch/arm/boot/dts/omap4-sdp.dts ++++ b/arch/arm/boot/dts/omap4-sdp.dts +@@ -290,7 +290,7 @@ OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + + dss_hdmi_pins: pinmux_dss_hdmi_pins { + pinctrl-single,pins = < +- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ ++ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ + >; +diff --git a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi +index 74940b6d7719..676d8dd0624a 100644 +--- a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi ++++ b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi +@@ -122,7 +122,7 @@ OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ + + dss_hdmi_pins: pinmux_dss_hdmi_pins { + pinctrl-single,pins = < +- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ ++ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ + >; +diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi +index 4caadb253249..7824b2631cb6 100644 +--- a/arch/arm/boot/dts/omap5-board-common.dtsi ++++ b/arch/arm/boot/dts/omap5-board-common.dtsi +@@ -290,7 +290,7 @@ OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */ + + dss_hdmi_pins: pinmux_dss_hdmi_pins { + pinctrl-single,pins = < +- OMAP5_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ ++ OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ + OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ + >; +diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts +index 78397f66d0b2..552a5c4c5942 100644 +--- a/arch/arm/boot/dts/omap5-cm-t54.dts ++++ b/arch/arm/boot/dts/omap5-cm-t54.dts +@@ -266,7 +266,7 @@ OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */ + + dss_hdmi_pins: pinmux_dss_hdmi_pins { + pinctrl-single,pins = < +- OMAP5_IOPAD(0x013c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec */ ++ OMAP5_IOPAD(0x013c, PIN_INPUT | MUX_MODE0) /* hdmi_cec */ + OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */ + OMAP5_IOPAD(0x0142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda */ + >; +diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +index b9457dd21a69..e413b21ee331 100644 +--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +@@ -20,27 +20,12 @@ / { + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1"; + compatible = "qcom,ipq4019"; + +- clocks { +- xo: xo { +- compatible = "fixed-clock"; +- clock-frequency = <48000000>; +- #clock-cells = <0>; +- }; +- }; +- + soc { +- +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupts = <1 2 0xf08>, +- <1 3 0xf08>, +- <1 4 0xf08>, +- <1 1 0xf08>; +- clock-frequency = <48000000>; ++ rng@22000 { ++ status = "ok"; + }; + +- pinctrl@0x01000000 { ++ pinctrl@1000000 { + serial_pins: serial_pinmux { + mux { + pins = "gpio60", "gpio61"; +@@ -108,5 +93,13 @@ crypto@8e3a000 { + watchdog@b017000 { + status = "ok"; + }; ++ ++ wifi@a000000 { ++ status = "ok"; ++ }; ++ ++ wifi@a800000 { ++ status = "ok"; ++ }; + }; + }; +diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi +index 4b7d97275c62..10d112a4078e 100644 +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -96,6 +96,21 @@ sleep_clk: sleep_clk { + clock-frequency = <32768>; + #clock-cells = <0>; + }; ++ ++ xo: xo { ++ compatible = "fixed-clock"; ++ clock-frequency = <48000000>; ++ #clock-cells = <0>; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv7-timer"; ++ interrupts = <1 2 0xf08>, ++ <1 3 0xf08>, ++ <1 4 0xf08>, ++ <1 1 0xf08>; ++ clock-frequency = <48000000>; + }; + + soc { +@@ -119,7 +134,15 @@ gcc: clock-controller@1800000 { + reg = <0x1800000 0x60000>; + }; + +- tlmm: pinctrl@0x01000000 { ++ rng@22000 { ++ compatible = "qcom,prng"; ++ reg = <0x22000 0x140>; ++ clocks = <&gcc GCC_PRNG_AHB_CLK>; ++ clock-names = "core"; ++ status = "disabled"; ++ }; ++ ++ tlmm: pinctrl@1000000 { + compatible = "qcom,ipq4019-pinctrl"; + reg = <0x01000000 0x300000>; + gpio-controller; +@@ -269,5 +292,89 @@ restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>; + }; ++ ++ wifi0: wifi@a000000 { ++ compatible = "qcom,ipq4019-wifi"; ++ reg = <0xa000000 0x200000>; ++ resets = <&gcc WIFI0_CPU_INIT_RESET>, ++ <&gcc WIFI0_RADIO_SRIF_RESET>, ++ <&gcc WIFI0_RADIO_WARM_RESET>, ++ <&gcc WIFI0_RADIO_COLD_RESET>, ++ <&gcc WIFI0_CORE_WARM_RESET>, ++ <&gcc WIFI0_CORE_COLD_RESET>; ++ reset-names = "wifi_cpu_init", "wifi_radio_srif", ++ "wifi_radio_warm", "wifi_radio_cold", ++ "wifi_core_warm", "wifi_core_cold"; ++ clocks = <&gcc GCC_WCSS2G_CLK>, ++ <&gcc GCC_WCSS2G_REF_CLK>, ++ <&gcc GCC_WCSS2G_RTC_CLK>; ++ clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", ++ "wifi_wcss_rtc"; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", "msi1", "msi2", "msi3", ++ "msi4", "msi5", "msi6", "msi7", ++ "msi8", "msi9", "msi10", "msi11", ++ "msi12", "msi13", "msi14", "msi15", ++ "legacy"; ++ status = "disabled"; ++ }; ++ ++ wifi1: wifi@a800000 { ++ compatible = "qcom,ipq4019-wifi"; ++ reg = <0xa800000 0x200000>; ++ resets = <&gcc WIFI1_CPU_INIT_RESET>, ++ <&gcc WIFI1_RADIO_SRIF_RESET>, ++ <&gcc WIFI1_RADIO_WARM_RESET>, ++ <&gcc WIFI1_RADIO_COLD_RESET>, ++ <&gcc WIFI1_CORE_WARM_RESET>, ++ <&gcc WIFI1_CORE_COLD_RESET>; ++ reset-names = "wifi_cpu_init", "wifi_radio_srif", ++ "wifi_radio_warm", "wifi_radio_cold", ++ "wifi_core_warm", "wifi_core_cold"; ++ clocks = <&gcc GCC_WCSS5G_CLK>, ++ <&gcc GCC_WCSS5G_REF_CLK>, ++ <&gcc GCC_WCSS5G_RTC_CLK>; ++ clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", ++ "wifi_wcss_rtc"; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", "msi1", "msi2", "msi3", ++ "msi4", "msi5", "msi6", "msi7", ++ "msi8", "msi9", "msi10", "msi11", ++ "msi12", "msi13", "msi14", "msi15", ++ "legacy"; ++ status = "disabled"; ++ }; + }; + }; +diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi +index c5ee68a3f7f5..a39207625354 100644 +--- a/arch/arm/boot/dts/qcom-msm8974.dtsi ++++ b/arch/arm/boot/dts/qcom-msm8974.dtsi +@@ -779,7 +779,7 @@ tpiu_in: endpoint { + }; + + replicator@fc31c000 { +- compatible = "qcom,coresight-replicator1x", "arm,primecell"; ++ compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0xfc31c000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; +diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts +index 52a7b586bac7..cd4d5ff7749e 100644 +--- a/arch/arm/boot/dts/r7s72100-genmai.dts ++++ b/arch/arm/boot/dts/r7s72100-genmai.dts +@@ -11,6 +11,8 @@ + + /dts-v1/; + #include "r7s72100.dtsi" ++#include ++#include + + / { + model = "Genmai"; +@@ -34,6 +36,54 @@ lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; ++ ++ leds { ++ status = "okay"; ++ compatible = "gpio-leds"; ++ ++ led1 { ++ gpios = <&port4 10 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led2 { ++ gpios = <&port4 11 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&pinctrl { ++ ++ scif2_pins: serial2 { ++ /* P3_0 as TxD2; P3_2 as RxD2 */ ++ pinmux = , ; ++ }; ++ ++ i2c2_pins: i2c2 { ++ /* RIIC2: P1_4 as SCL, P1_5 as SDA */ ++ pinmux = , ; ++ }; ++ ++ ether_pins: ether { ++ /* Ethernet on Ports 1,2,3,5 */ ++ pinmux = ,/* P1_14 = ET_COL */ ++ , /* P5_9 = ET_MDC */ ++ , /* P3_3 = ET_MDIO */ ++ , /* P3_4 = ET_RXCLK */ ++ , /* P3_5 = ET_RXER */ ++ , /* P3_6 = ET_RXDV */ ++ , /* P2_0 = ET_TXCLK */ ++ , /* P2_1 = ET_TXER */ ++ , /* P2_2 = ET_TXEN */ ++ , /* P2_3 = ET_CRS */ ++ , /* P2_4 = ET_TXD0 */ ++ , /* P2_5 = ET_TXD1 */ ++ , /* P2_6 = ET_TXD2 */ ++ , /* P2_7 = ET_TXD3 */ ++ , /* P2_8 = ET_RXD0 */ ++ , /* P2_9 = ET_RXD1 */ ++ ,/* P2_10 = ET_RXD2 */ ++ ;/* P2_11 = ET_RXD3 */ ++ }; + }; + + &extal_clk { +@@ -52,12 +102,28 @@ &mtu2 { + status = "okay"; + }; + ++ðer { ++ pinctrl-names = "default"; ++ pinctrl-0 = <ðer_pins>; ++ ++ status = "okay"; ++ ++ renesas,no-ether-link; ++ phy-handle = <&phy0>; ++ phy0: ethernet-phy@0 { ++ reg = <0>; ++ }; ++}; ++ + &i2c2 { + status = "okay"; + clock-frequency = <400000>; + ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ + eeprom@50 { +- compatible = "renesas,24c128"; ++ compatible = "renesas,24c128", "atmel,24c128"; + reg = <0x50>; + pagesize = <64>; + }; +@@ -68,6 +134,9 @@ &rtc { + }; + + &scif2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&scif2_pins>; ++ + status = "okay"; + }; + +diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts +index 72df20a04320..5dcaaf131d27 100644 +--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts ++++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts +@@ -10,6 +10,8 @@ + + /dts-v1/; + #include "r7s72100.dtsi" ++#include ++#include + + / { + model = "RSKRZA1"; +@@ -33,6 +35,15 @@ lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; ++ ++ leds { ++ status = "okay"; ++ compatible = "gpio-leds"; ++ ++ led0 { ++ gpios = <&port7 1 GPIO_ACTIVE_LOW>; ++ }; ++ }; + }; + + &extal_clk { +@@ -47,11 +58,57 @@ &rtc_x1_clk { + clock-frequency = <32768>; + }; + ++&pinctrl { ++ ++ /* Serial Console */ ++ scif2_pins: serial2 { ++ pinmux = , /* TxD2 */ ++ ; /* RxD2 */ ++ }; ++ ++ /* Ethernet */ ++ ether_pins: ether { ++ /* Ethernet on Ports 1,2,3,5 */ ++ pinmux = , /* ET_COL */ ++ , /* ET_MDC */ ++ , /* ET_MDIO */ ++ , /* ET_RXCLK */ ++ , /* ET_RXER */ ++ , /* ET_RXDV */ ++ , /* ET_TXCLK */ ++ , /* ET_TXER */ ++ , /* ET_TXEN */ ++ , /* ET_CRS */ ++ , /* ET_TXD0 */ ++ , /* ET_TXD1 */ ++ , /* ET_TXD2 */ ++ , /* ET_TXD3 */ ++ , /* ET_RXD0 */ ++ , /* ET_RXD1 */ ++ , /* ET_RXD2 */ ++ ; /* ET_RXD3 */ ++ }; ++ ++ /* SDHI ch1 on CN1 */ ++ sdhi1_pins: sdhi1 { ++ pinmux = , /* SD_CD_1 */ ++ , /* SD_WP_1 */ ++ , /* SD_D1_1 */ ++ , /* SD_D0_1 */ ++ , /* SD_CLK_1 */ ++ , /* SD_CMD_1 */ ++ , /* SD_D3_1 */ ++ ; /* SD_D2_1 */ ++ }; ++}; ++ + &mtu2 { + status = "okay"; + }; + + ðer { ++ pinctrl-names = "default"; ++ pinctrl-0 = <ðer_pins>; + status = "okay"; + renesas,no-ether-link; + phy-handle = <&phy0>; +@@ -61,6 +118,8 @@ phy0: ethernet-phy@0 { + }; + + &sdhi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdhi1_pins>; + bus-width = <4>; + status = "okay"; + }; +@@ -78,5 +137,7 @@ &rtc { + }; + + &scif2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&scif2_pins>; + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi +index 5cf53e9943af..4ed12a4d9d51 100644 +--- a/arch/arm/boot/dts/r7s72100.dtsi ++++ b/arch/arm/boot/dts/r7s72100.dtsi +@@ -207,6 +207,84 @@ cpu@0 { + }; + }; + ++ pinctrl: pin-controller@fcfe3000 { ++ compatible = "renesas,r7s72100-ports"; ++ ++ reg = <0xfcfe3000 0x4230>; ++ ++ port0: gpio-0 { ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pinctrl 0 0 6>; ++ }; ++ ++ port1: gpio-1 { ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pinctrl 0 16 16>; ++ }; ++ ++ port2: gpio-2 { ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pinctrl 0 32 16>; ++ }; ++ ++ port3: gpio-3 { ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pinctrl 0 48 16>; ++ }; ++ ++ port4: gpio-4 { ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pinctrl 0 64 16>; ++ }; ++ ++ port5: gpio-5 { ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pinctrl 0 80 11>; ++ }; ++ ++ port6: gpio-6 { ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pinctrl 0 96 16>; ++ }; ++ ++ port7: gpio-7 { ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pinctrl 0 112 16>; ++ }; ++ ++ port8: gpio-8 { ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pinctrl 0 128 16>; ++ }; ++ ++ port9: gpio-9 { ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pinctrl 0 144 8>; ++ }; ++ ++ port10: gpio-10 { ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pinctrl 0 160 16>; ++ }; ++ ++ port11: gpio-11 { ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pinctrl 0 176 16>; ++ }; ++ }; ++ + scif0: serial@e8007000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8007000 64>; +diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +index 9b54783cc2a5..081af0192851 100644 +--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts ++++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +@@ -17,9 +17,40 @@ / { + + aliases { + serial0 = &scif0; ++ ethernet0 = &avb; ++ }; ++}; ++ ++&pfc { ++ scif0_pins: scif0 { ++ groups = "scif0_data_d"; ++ function = "scif0"; ++ }; ++ ++ avb_pins: avb { ++ groups = "avb_mdio", "avb_gmii"; ++ function = "avb"; + }; + }; + + &scif0 { ++ pinctrl-0 = <&scif0_pins>; ++ pinctrl-names = "default"; ++ + status = "okay"; + }; ++ ++&avb { ++ pinctrl-0 = <&avb_pins>; ++ pinctrl-names = "default"; ++ ++ phy-handle = <&phy3>; ++ phy-mode = "gmii"; ++ renesas,no-ether-link; ++ status = "okay"; ++ ++ phy3: ethernet-phy@3 { ++ reg = <3>; ++ micrel,led-mode = <1>; ++ }; ++}; +diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi +index 001ca9144f4b..ff7993818637 100644 +--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi ++++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi +@@ -22,8 +22,34 @@ memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x20000000>; + }; ++ ++ reg_3p3v: 3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; + }; + + &extal_clk { + clock-frequency = <20000000>; + }; ++ ++&pfc { ++ mmcif0_pins: mmc { ++ groups = "mmc_data8_b", "mmc_ctrl"; ++ function = "mmc"; ++ }; ++}; ++ ++&mmcif0 { ++ pinctrl-0 = <&mmcif0_pins>; ++ pinctrl-names = "default"; ++ ++ vmmc-supply = <®_3p3v>; ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts +index 3a22538208f2..3d918d106593 100644 +--- a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts ++++ b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts +@@ -1,7 +1,7 @@ + /* + * Device Tree Source for the SK-RZG1M board + * +- * Copyright (C) 2016 Cogent Embedded, Inc. ++ * Copyright (C) 2016-2017 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any +@@ -39,11 +39,34 @@ &extal_clk { + clock-frequency = <20000000>; + }; + ++&pfc { ++ scif0_pins: scif0 { ++ groups = "scif0_data_d"; ++ function = "scif0"; ++ }; ++ ++ ether_pins: ether { ++ groups = "eth_link", "eth_mdio", "eth_rmii"; ++ function = "eth"; ++ }; ++ ++ phy1_pins: phy1 { ++ groups = "intc_irq0"; ++ function = "intc"; ++ }; ++}; ++ + &scif0 { ++ pinctrl-0 = <&scif0_pins>; ++ pinctrl-names = "default"; ++ + status = "okay"; + }; + + ðer { ++ pinctrl-0 = <ðer_pins &phy1_pins>; ++ pinctrl-names = "default"; ++ + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; +diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi +index 0ddac81742e4..14222c72f0e0 100644 +--- a/arch/arm/boot/dts/r8a7743.dtsi ++++ b/arch/arm/boot/dts/r8a7743.dtsi +@@ -1,7 +1,7 @@ + /* + * Device Tree Source for the r8a7743 SoC + * +- * Copyright (C) 2016 Cogent Embedded Inc. ++ * Copyright (C) 2016-2017 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any +@@ -18,9 +18,19 @@ / { + #address-cells = <2>; + #size-cells = <2>; + ++ aliases { ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c2 = &i2c2; ++ i2c3 = &i2c3; ++ i2c4 = &i2c4; ++ i2c5 = &i2c5; ++ }; ++ + cpus { + #address-cells = <1>; + #size-cells = <0>; ++ enable-method = "renesas,apmu"; + + cpu0: cpu@0 { + device_type = "cpu"; +@@ -28,8 +38,26 @@ cpu0: cpu@0 { + reg = <0>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; ++ clock-latency = <300000>; /* 300 us */ + power-domains = <&sysc R8A7743_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; ++ ++ /* kHz - uV - OPPs unknown yet */ ++ operating-points = <1500000 1000000>, ++ <1312500 1000000>, ++ <1125000 1000000>, ++ < 937500 1000000>, ++ < 750000 1000000>, ++ < 375000 1000000>; ++ }; ++ ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a15"; ++ reg = <1>; ++ clock-frequency = <1500000000>; ++ power-domains = <&sysc R8A7743_PD_CA15_CPU1>; ++ next-level-cache = <&L2_CA15>; + }; + + L2_CA15: cache-controller-0 { +@@ -48,6 +76,12 @@ soc { + #size-cells = <2>; + ranges; + ++ apmu@e6152000 { ++ compatible = "renesas,r8a7743-apmu", "renesas,apmu"; ++ reg = <0 0xe6152000 0 0x188>; ++ cpus = <&cpu0 &cpu1>; ++ }; ++ + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; +@@ -65,6 +99,126 @@ gic: interrupt-controller@f1001000 { + resets = <&cpg 408>; + }; + ++ gpio0: gpio@e6050000 { ++ compatible = "renesas,gpio-r8a7743", ++ "renesas,gpio-rcar"; ++ reg = <0 0xe6050000 0 0x50>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 0 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ clocks = <&cpg CPG_MOD 912>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 912>; ++ }; ++ ++ gpio1: gpio@e6051000 { ++ compatible = "renesas,gpio-r8a7743", ++ "renesas,gpio-rcar"; ++ reg = <0 0xe6051000 0 0x50>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 32 26>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ clocks = <&cpg CPG_MOD 911>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 911>; ++ }; ++ ++ gpio2: gpio@e6052000 { ++ compatible = "renesas,gpio-r8a7743", ++ "renesas,gpio-rcar"; ++ reg = <0 0xe6052000 0 0x50>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 64 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ clocks = <&cpg CPG_MOD 910>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 910>; ++ }; ++ ++ gpio3: gpio@e6053000 { ++ compatible = "renesas,gpio-r8a7743", ++ "renesas,gpio-rcar"; ++ reg = <0 0xe6053000 0 0x50>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 96 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ clocks = <&cpg CPG_MOD 909>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 909>; ++ }; ++ ++ gpio4: gpio@e6054000 { ++ compatible = "renesas,gpio-r8a7743", ++ "renesas,gpio-rcar"; ++ reg = <0 0xe6054000 0 0x50>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 128 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ clocks = <&cpg CPG_MOD 908>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 908>; ++ }; ++ ++ gpio5: gpio@e6055000 { ++ compatible = "renesas,gpio-r8a7743", ++ "renesas,gpio-rcar"; ++ reg = <0 0xe6055000 0 0x50>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 160 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ clocks = <&cpg CPG_MOD 907>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 907>; ++ }; ++ ++ gpio6: gpio@e6055400 { ++ compatible = "renesas,gpio-r8a7743", ++ "renesas,gpio-rcar"; ++ reg = <0 0xe6055400 0 0x50>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 192 32>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ clocks = <&cpg CPG_MOD 905>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 905>; ++ }; ++ ++ gpio7: gpio@e6055800 { ++ compatible = "renesas,gpio-r8a7743", ++ "renesas,gpio-rcar"; ++ reg = <0 0xe6055800 0 0x50>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-ranges = <&pfc 0 224 26>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ clocks = <&cpg CPG_MOD 904>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 904>; ++ }; ++ + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7743", "renesas,irqc"; + #interrupt-cells = <2>; +@@ -123,6 +277,11 @@ sysc: system-controller@e6180000 { + #power-domain-cells = <1>; + }; + ++ pfc: pin-controller@e6060000 { ++ compatible = "renesas,pfc-r8a7743"; ++ reg = <0 0xe6060000 0 0x250>; ++ }; ++ + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; +@@ -189,6 +348,94 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + dma-channels = <15>; + }; + ++ /* The memory map in the User's Manual maps the cores to bus ++ * numbers ++ */ ++ i2c0: i2c@e6508000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,i2c-r8a7743", ++ "renesas,rcar-gen2-i2c"; ++ reg = <0 0xe6508000 0 0x40>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 931>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 931>; ++ i2c-scl-internal-delay-ns = <6>; ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@e6518000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,i2c-r8a7743", ++ "renesas,rcar-gen2-i2c"; ++ reg = <0 0xe6518000 0 0x40>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 930>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 930>; ++ i2c-scl-internal-delay-ns = <6>; ++ status = "disabled"; ++ }; ++ ++ i2c2: i2c@e6530000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,i2c-r8a7743", ++ "renesas,rcar-gen2-i2c"; ++ reg = <0 0xe6530000 0 0x40>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 929>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 929>; ++ i2c-scl-internal-delay-ns = <6>; ++ status = "disabled"; ++ }; ++ ++ i2c3: i2c@e6540000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,i2c-r8a7743", ++ "renesas,rcar-gen2-i2c"; ++ reg = <0 0xe6540000 0 0x40>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 928>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 928>; ++ i2c-scl-internal-delay-ns = <6>; ++ status = "disabled"; ++ }; ++ ++ i2c4: i2c@e6520000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,i2c-r8a7743", ++ "renesas,rcar-gen2-i2c"; ++ reg = <0 0xe6520000 0 0x40>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 927>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 927>; ++ i2c-scl-internal-delay-ns = <6>; ++ status = "disabled"; ++ }; ++ ++ i2c5: i2c@e6528000 { ++ /* doesn't need pinmux */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,i2c-r8a7743", ++ "renesas,rcar-gen2-i2c"; ++ reg = <0 0xe6528000 0 0x40>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 925>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 925>; ++ i2c-scl-internal-delay-ns = <110>; ++ status = "disabled"; ++ }; ++ + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; +@@ -468,6 +715,29 @@ hscif2: serial@e62d0000 { + status = "disabled"; + }; + ++ icram2: sram@e6300000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe6300000 0 0x40000>; ++ }; ++ ++ icram0: sram@e63a0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63a0000 0 0x12000>; ++ }; ++ ++ icram1: sram@e63c0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63c0000 0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0xe63c0000 0x1000>; ++ ++ smp-sram@0 { ++ compatible = "renesas,smp-sram"; ++ reg = <0 0x10>; ++ }; ++ }; ++ + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7743"; + reg = <0 0xee700000 0 0x400>; +@@ -480,6 +750,35 @@ ether: ethernet@ee700000 { + #size-cells = <0>; + status = "disabled"; + }; ++ ++ avb: ethernet@e6800000 { ++ compatible = "renesas,etheravb-r8a7743", ++ "renesas,etheravb-rcar-gen2"; ++ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 812>; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 812>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ mmcif0: mmc@ee200000 { ++ compatible = "renesas,mmcif-r8a7743", ++ "renesas,sh-mmcif"; ++ reg = <0 0xee200000 0 0x80>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 315>; ++ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, ++ <&dmac1 0xd1>, <&dmac1 0xd2>; ++ dma-names = "tx", "rx", "tx", "rx"; ++ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 315>; ++ reg-io-width = <4>; ++ max-frequency = <97500000>; ++ status = "disabled"; ++ }; + }; + + /* External root clock */ +diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts +index 97840b340197..b4d679b04ad6 100644 +--- a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts ++++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts +@@ -1,7 +1,7 @@ + /* + * Device Tree Source for the SK-RZG1E board + * +- * Copyright (C) 2016 Cogent Embedded, Inc. ++ * Copyright (C) 2016-2017 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any +@@ -34,11 +34,34 @@ &extal_clk { + clock-frequency = <20000000>; + }; + ++&pfc { ++ scif2_pins: scif2 { ++ groups = "scif2_data"; ++ function = "scif2"; ++ }; ++ ++ ether_pins: ether { ++ groups = "eth_link", "eth_mdio", "eth_rmii"; ++ function = "eth"; ++ }; ++ ++ phy1_pins: phy1 { ++ groups = "intc_irq8"; ++ function = "intc"; ++ }; ++}; ++ + &scif2 { ++ pinctrl-0 = <&scif2_pins>; ++ pinctrl-names = "default"; ++ + status = "okay"; + }; + + ðer { ++ pinctrl-0 = <ðer_pins &phy1_pins>; ++ pinctrl-names = "default"; ++ + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; +diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi +index 2feb0084bb3b..aff90dfb8b32 100644 +--- a/arch/arm/boot/dts/r8a7745.dtsi ++++ b/arch/arm/boot/dts/r8a7745.dtsi +@@ -1,7 +1,7 @@ + /* + * Device Tree Source for the r8a7745 SoC + * +- * Copyright (C) 2016 Cogent Embedded Inc. ++ * Copyright (C) 2016-2017 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any +@@ -123,6 +123,11 @@ sysc: system-controller@e6180000 { + #power-domain-cells = <1>; + }; + ++ pfc: pin-controller@e6060000 { ++ compatible = "renesas,pfc-r8a7745"; ++ reg = <0 0xe6060000 0 0x11c>; ++ }; ++ + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; +@@ -468,6 +473,29 @@ hscif2: serial@e62d0000 { + status = "disabled"; + }; + ++ icram2: sram@e6300000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe6300000 0 0x40000>; ++ }; ++ ++ icram0: sram@e63a0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63a0000 0 0x12000>; ++ }; ++ ++ icram1: sram@e63c0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63c0000 0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0xe63c0000 0x1000>; ++ ++ smp-sram@0 { ++ compatible = "renesas,smp-sram"; ++ reg = <0 0x10>; ++ }; ++ }; ++ + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7745"; + reg = <0 0xee700000 0 0x400>; +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index 2805a8608d4b..16358bf8d1db 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -830,6 +830,24 @@ hscif1: serial@e62c8000 { + status = "disabled"; + }; + ++ icram0: sram@e63a0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63a0000 0 0x12000>; ++ }; ++ ++ icram1: sram@e63c0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63c0000 0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0xe63c0000 0x1000>; ++ ++ smp-sram@0 { ++ compatible = "renesas,smp-sram"; ++ reg = <0 0x10>; ++ }; ++ }; ++ + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7790"; + reg = <0 0xee700000 0 0x400>; +@@ -855,7 +873,7 @@ avb: ethernet@e6800000 { + }; + + sata0: sata@ee300000 { +- compatible = "renesas,sata-r8a7790"; ++ compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata"; + reg = <0 0xee300000 0 0x2000>; + interrupts = ; + clocks = <&mstp8_clks R8A7790_CLK_SATA0>; +@@ -864,7 +882,7 @@ sata0: sata@ee300000 { + }; + + sata1: sata@ee500000 { +- compatible = "renesas,sata-r8a7790"; ++ compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata"; + reg = <0 0xee500000 0 0x2000>; + interrupts = ; + clocks = <&mstp8_clks R8A7790_CLK_SATA1>; +@@ -909,7 +927,7 @@ usb2: usb-channel@2 { + }; + + vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a7790"; ++ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7790_CLK_VIN0>; +@@ -918,7 +936,7 @@ vin0: video@e6ef0000 { + }; + + vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a7790"; ++ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7790_CLK_VIN1>; +@@ -927,7 +945,7 @@ vin1: video@e6ef1000 { + }; + + vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a7790"; ++ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7790_CLK_VIN2>; +@@ -936,7 +954,7 @@ vin2: video@e6ef2000 { + }; + + vin3: video@e6ef3000 { +- compatible = "renesas,vin-r8a7790"; ++ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7790_CLK_VIN3>; +diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts +index 001e6116c47c..0ce0b278e1cb 100644 +--- a/arch/arm/boot/dts/r8a7791-koelsch.dts ++++ b/arch/arm/boot/dts/r8a7791-koelsch.dts +@@ -642,11 +642,19 @@ adv7180: endpoint { + }; + }; + ++ cec_clock: cec-clock { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <12000000>; ++ }; ++ + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&cec_clock>; ++ clock-names = "cec"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; +@@ -702,7 +710,7 @@ adv7612_out: endpoint { + }; + + eeprom@50 { +- compatible = "renesas,24c02"; ++ compatible = "renesas,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi +index bd93f699ad84..f1d1a9772153 100644 +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -890,6 +890,24 @@ hscif2: serial@e62d0000 { + status = "disabled"; + }; + ++ icram0: sram@e63a0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63a0000 0 0x12000>; ++ }; ++ ++ icram1: sram@e63c0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63c0000 0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0xe63c0000 0x1000>; ++ ++ smp-sram@0 { ++ compatible = "renesas,smp-sram"; ++ reg = <0 0x10>; ++ }; ++ }; ++ + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7791"; + reg = <0 0xee700000 0 0x400>; +@@ -915,7 +933,7 @@ avb: ethernet@e6800000 { + }; + + sata0: sata@ee300000 { +- compatible = "renesas,sata-r8a7791"; ++ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; + reg = <0 0xee300000 0 0x2000>; + interrupts = ; + clocks = <&mstp8_clks R8A7791_CLK_SATA0>; +@@ -924,7 +942,7 @@ sata0: sata@ee300000 { + }; + + sata1: sata@ee500000 { +- compatible = "renesas,sata-r8a7791"; ++ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; + reg = <0 0xee500000 0 0x2000>; + interrupts = ; + clocks = <&mstp8_clks R8A7791_CLK_SATA1>; +@@ -969,7 +987,7 @@ usb2: usb-channel@2 { + }; + + vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a7791"; ++ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7791_CLK_VIN0>; +@@ -978,7 +996,7 @@ vin0: video@e6ef0000 { + }; + + vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a7791"; ++ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7791_CLK_VIN1>; +@@ -987,7 +1005,7 @@ vin1: video@e6ef1000 { + }; + + vin2: video@e6ef2000 { +- compatible = "renesas,vin-r8a7791"; ++ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7791_CLK_VIN2>; +diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi +index 0efecb232ee5..2623f39bed2b 100644 +--- a/arch/arm/boot/dts/r8a7792.dtsi ++++ b/arch/arm/boot/dts/r8a7792.dtsi +@@ -465,6 +465,24 @@ hscif1: serial@e62c8000 { + status = "disabled"; + }; + ++ icram0: sram@e63a0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63a0000 0 0x12000>; ++ }; ++ ++ icram1: sram@e63c0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63c0000 0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0xe63c0000 0x1000>; ++ ++ smp-sram@0 { ++ compatible = "renesas,smp-sram"; ++ reg = <0 0x10>; ++ }; ++ }; ++ + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7792"; + reg = <0 0xee100000 0 0x328>; +diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi +index 13b980f27bbc..497716b6fbe2 100644 +--- a/arch/arm/boot/dts/r8a7793.dtsi ++++ b/arch/arm/boot/dts/r8a7793.dtsi +@@ -848,6 +848,24 @@ hscif2: serial@e62d0000 { + status = "disabled"; + }; + ++ icram0: sram@e63a0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63a0000 0 0x12000>; ++ }; ++ ++ icram1: sram@e63c0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63c0000 0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0xe63c0000 0x1000>; ++ ++ smp-sram@0 { ++ compatible = "renesas,smp-sram"; ++ reg = <0 0x10>; ++ }; ++ }; ++ + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7793"; + reg = <0 0xee700000 0 0x400>; +diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi +index 7d9a81d970d8..26535414203a 100644 +--- a/arch/arm/boot/dts/r8a7794.dtsi ++++ b/arch/arm/boot/dts/r8a7794.dtsi +@@ -588,6 +588,24 @@ hscif2: serial@e62d0000 { + status = "disabled"; + }; + ++ icram0: sram@e63a0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63a0000 0 0x12000>; ++ }; ++ ++ icram1: sram@e63c0000 { ++ compatible = "mmio-sram"; ++ reg = <0 0xe63c0000 0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0xe63c0000 0x1000>; ++ ++ smp-sram@0 { ++ compatible = "renesas,smp-sram"; ++ reg = <0 0x10>; ++ }; ++ }; ++ + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7794"; + reg = <0 0xee700000 0 0x400>; +@@ -783,7 +801,7 @@ qspi: spi@e6b10000 { + }; + + vin0: video@e6ef0000 { +- compatible = "renesas,vin-r8a7794"; ++ compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7794_CLK_VIN0>; +@@ -792,7 +810,7 @@ vin0: video@e6ef0000 { + }; + + vin1: video@e6ef1000 { +- compatible = "renesas,vin-r8a7794"; ++ compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7794_CLK_VIN1>; +diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts +index 5726135b7f8a..fdb1570bc7d3 100644 +--- a/arch/arm/boot/dts/rk3036-kylin.dts ++++ b/arch/arm/boot/dts/rk3036-kylin.dts +@@ -357,7 +357,6 @@ &sdio { + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; + sd-uhs-sdr12; +@@ -372,7 +371,6 @@ &sdmmc { + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + }; +diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi +index ec91325d3b6e..4916c65e0ace 100644 +--- a/arch/arm/boot/dts/rk3036.dtsi ++++ b/arch/arm/boot/dts/rk3036.dtsi +@@ -287,7 +287,6 @@ emmc: dwmmc@1021c000 { + fifo-depth = <0x100>; + mmc-ddr-1_8v; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + resets = <&cru SRST_EMMC>; +@@ -599,7 +598,7 @@ sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>; + }; + +- sdmmc_cd: sdmcc-cd { ++ sdmmc_cd: sdmmc-cd { + rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>; + }; + +diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts +index e1f5198723b2..ef1eabf2512c 100644 +--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts ++++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts +@@ -190,7 +190,6 @@ vcc28_cif: regulator@12 { + #include "tps65910.dtsi" + + &mmc0 { /* sdmmc */ +- num-slots = <1>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; +@@ -202,7 +201,6 @@ &mmc0 { /* sdmmc */ + }; + + &mmc1 { /* wifi */ +- num-slots = <1>; + status = "okay"; + non-removable; + +diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts +index 7ca1cf5241e0..13e285c53def 100644 +--- a/arch/arm/boot/dts/rk3066a-mk808.dts ++++ b/arch/arm/boot/dts/rk3066a-mk808.dts +@@ -132,7 +132,6 @@ &mmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; +- num-slots = <1>; + vmmc-supply = <&vcc_sd>; + status = "okay"; + }; +@@ -141,7 +140,6 @@ &mmc1 { + bus-width = <4>; + disable-wp; + non-removable; +- num-slots = <1>; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_wifi>; +diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts +index 8907deaab18e..400cbf9609e3 100644 +--- a/arch/arm/boot/dts/rk3066a-rayeager.dts ++++ b/arch/arm/boot/dts/rk3066a-rayeager.dts +@@ -185,7 +185,6 @@ &emmc { + cap-mmc-highspeed; + disable-wp; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; + vmmc-supply = <&vcc_emmc>; +@@ -336,7 +335,6 @@ &i2c4 { + &mmc0 { + bus-width = <4>; + disable-wp; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + vmmc-supply = <&vcc_sd>; +@@ -349,7 +347,6 @@ &mmc1 { + bus-width = <4>; + disable-wp; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; + vmmc-supply = <&vccio_wl>; +diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts +index 5b2a0b6885cd..8ba9e06062f3 100644 +--- a/arch/arm/boot/dts/rk3188-px3-evb.dts ++++ b/arch/arm/boot/dts/rk3188-px3-evb.dts +@@ -89,7 +89,6 @@ &emmc { + cap-mmc-highspeed; + disable-wp; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; + status = "okay"; +@@ -256,7 +255,6 @@ gsl1680: touchscreen@40 { + }; + + &mmc0 { +- num-slots = <1>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; +diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts +index ca0a1c4bc15c..53d6fc2fdbce 100644 +--- a/arch/arm/boot/dts/rk3188-radxarock.dts ++++ b/arch/arm/boot/dts/rk3188-radxarock.dts +@@ -296,7 +296,6 @@ vcc28: REG12 { + }; + + &mmc0 { +- num-slots = <1>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; +diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts +index 1b55192b7d04..73e384585755 100644 +--- a/arch/arm/boot/dts/rk3229-evb.dts ++++ b/arch/arm/boot/dts/rk3229-evb.dts +@@ -40,7 +40,8 @@ + + /dts-v1/; + +-#include "rk322x.dtsi" ++#include ++#include "rk3229.dtsi" + + / { + model = "Rockchip RK3229 Evaluation board"; +@@ -51,6 +52,15 @@ memory@60000000 { + reg = <0x60000000 0x40000000>; + }; + ++ dc_12v: dc-12v-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "dc_12v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ + ext_gmac: ext_gmac { + compatible = "fixed-clock"; + clock-frequency = <125000000>; +@@ -67,6 +77,7 @@ vcc_host: vcc-host-regulator { + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; ++ vin-supply = <&vcc_sys>; + }; + + vcc_phy: vcc-phy-regulator { +@@ -77,9 +88,98 @@ vcc_phy: vcc-phy-regulator { + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; ++ vin-supply = <&vccio_1v8>; ++ }; ++ ++ vcc_sys: vcc-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&dc_12v>; ++ }; ++ ++ vccio_1v8: vccio-1v8-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vccio_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ vin-supply = <&vcc_sys>; ++ }; ++ ++ vccio_3v3: vccio-3v3-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vccio_3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <&vcc_sys>; ++ }; ++ ++ vdd_arm: vdd-arm-regulator { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm1 0 25000 1>; ++ pwm-supply = <&vcc_sys>; ++ regulator-name = "vdd_arm"; ++ regulator-min-microvolt = <950000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vdd_log: vdd-log-regulator { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm2 0 25000 1>; ++ pwm-supply = <&vcc_sys>; ++ regulator-name = "vdd_log"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ autorepeat; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwr_key>; ++ ++ power_key: power-key { ++ label = "GPIO Key Power"; ++ gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <100>; ++ wakeup-source; ++ }; + }; + }; + ++&cpu0 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&emmc { ++ cap-mmc-highspeed; ++ disable-wp; ++ non-removable; ++ status = "okay"; ++}; ++ + &gmac { + assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; +@@ -96,7 +196,21 @@ &gmac { + status = "okay"; + }; + ++&io_domains { ++ status = "okay"; ++ ++ vccio1-supply = <&vccio_3v3>; ++ vccio2-supply = <&vccio_1v8>; ++ vccio4-supply = <&vccio_3v3>; ++}; ++ + &pinctrl { ++ keys { ++ pwr_key: pwr-key { ++ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; +@@ -104,6 +218,19 @@ host_vbus_drv: host-vbus-drv { + }; + }; + ++&pwm1 { ++ status = "okay"; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ ++ status = "okay"; ++}; ++ + &uart2 { + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/rk3229.dtsi b/arch/arm/boot/dts/rk3229.dtsi +new file mode 100644 +index 000000000000..6fe6c15fc13a +--- /dev/null ++++ b/arch/arm/boot/dts/rk3229.dtsi +@@ -0,0 +1,89 @@ ++/* ++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include "rk322x.dtsi" ++ ++/ { ++ compatible = "rockchip,rk3229"; ++ ++ /delete-node/ opp-table0; ++ ++ cpu0_opp_table: opp_table0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <950000>; ++ clock-latency-ns = <40000>; ++ opp-suspend; ++ }; ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <975000>; ++ }; ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <1000000>; ++ }; ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <1175000>; ++ }; ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1275000>; ++ }; ++ opp-1296000000 { ++ opp-hz = /bits/ 64 <1296000000>; ++ opp-microvolt = <1325000>; ++ }; ++ opp-1392000000 { ++ opp-hz = /bits/ 64 <1392000000>; ++ opp-microvolt = <1375000>; ++ }; ++ opp-1464000000 { ++ opp-hz = /bits/ 64 <1464000000>; ++ opp-microvolt = <1400000>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi +index f3e4ffd9f818..06814421eed2 100644 +--- a/arch/arm/boot/dts/rk322x.dtsi ++++ b/arch/arm/boot/dts/rk322x.dtsi +@@ -55,6 +55,7 @@ aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; ++ spi0 = &spi0; + }; + + cpus { +@@ -70,6 +71,7 @@ cpu0: cpu@f00 { + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; ++ enable-method = "psci"; + }; + + cpu1: cpu@f01 { +@@ -78,6 +80,7 @@ cpu1: cpu@f01 { + reg = <0xf01>; + resets = <&cru SRST_CORE1>; + operating-points-v2 = <&cpu0_opp_table>; ++ enable-method = "psci"; + }; + + cpu2: cpu@f02 { +@@ -86,6 +89,7 @@ cpu2: cpu@f02 { + reg = <0xf02>; + resets = <&cru SRST_CORE2>; + operating-points-v2 = <&cpu0_opp_table>; ++ enable-method = "psci"; + }; + + cpu3: cpu@f03 { +@@ -94,6 +98,7 @@ cpu3: cpu@f03 { + reg = <0xf03>; + resets = <&cru SRST_CORE3>; + operating-points-v2 = <&cpu0_opp_table>; ++ enable-method = "psci"; + }; + }; + +@@ -151,6 +156,11 @@ arm-pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + ++ psci { ++ compatible = "arm,psci-1.0", "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; +@@ -196,6 +206,19 @@ i2s0: i2s0@100c0000 { + status = "disabled"; + }; + ++ spdif: spdif@100d0000 { ++ compatible = "rockchip,rk3228-spdif"; ++ reg = <0x100d0000 0x1000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; ++ clock-names = "mclk", "hclk"; ++ dmas = <&pdma 10>; ++ dma-names = "tx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdif_tx>; ++ status = "disabled"; ++ }; ++ + i2s2: i2s2@100e0000 { + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; + reg = <0x100e0000 0x4000>; +@@ -215,6 +238,11 @@ grf: syscon@11000000 { + #address-cells = <1>; + #size-cells = <1>; + ++ io_domains: io-domains { ++ compatible = "rockchip,rk3228-io-voltage-domain"; ++ status = "disabled"; ++ }; ++ + u2phy0: usb2-phy@760 { + compatible = "rockchip,rk3228-usb2phy"; + reg = <0x0760 0x0c>; +@@ -309,6 +337,23 @@ uart2: serial@11030000 { + status = "disabled"; + }; + ++ efuse: efuse@11040000 { ++ compatible = "rockchip,rk3228-efuse"; ++ reg = <0x11040000 0x20>; ++ clocks = <&cru PCLK_EFUSE_256>; ++ clock-names = "pclk_efuse"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ /* Data cells */ ++ efuse_id: id@7 { ++ reg = <0x7 0x10>; ++ }; ++ cpu_leakage: cpu_leakage@17 { ++ reg = <0x17 0x1>; ++ }; ++ }; ++ + i2c0: i2c@11050000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11050000 0x1000>; +@@ -361,6 +406,19 @@ i2c3: i2c@11080000 { + status = "disabled"; + }; + ++ spi0: spi@11090000 { ++ compatible = "rockchip,rk3228-spi"; ++ reg = <0x11090000 0x1000>; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; ++ clock-names = "spiclk", "apb_pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; ++ status = "disabled"; ++ }; ++ + wdt: watchdog@110a0000 { + compatible = "snps,dw-wdt"; + reg = <0x110a0000 0x100>; +@@ -500,8 +558,70 @@ tsadc: tsadc@11150000 { + status = "disabled"; + }; + ++ vpu_mmu: iommu@20020800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x20020800 0x100>; ++ interrupts = ; ++ interrupt-names = "vpu_mmu"; ++ iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ vdec_mmu: iommu@20030480 { ++ compatible = "rockchip,iommu"; ++ reg = <0x20030480 0x40>, <0x200304c0 0x40>; ++ interrupts = ; ++ interrupt-names = "vdec_mmu"; ++ iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ vop_mmu: iommu@20053f00 { ++ compatible = "rockchip,iommu"; ++ reg = <0x20053f00 0x100>; ++ interrupts = ; ++ interrupt-names = "vop_mmu"; ++ iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ iep_mmu: iommu@20070800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x20070800 0x100>; ++ interrupts = ; ++ interrupt-names = "iep_mmu"; ++ iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ sdmmc: dwmmc@30000000 { ++ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; ++ reg = <0x30000000 0x4000>; ++ interrupts = ; ++ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, ++ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; ++ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; ++ fifo-depth = <0x100>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; ++ status = "disabled"; ++ }; ++ ++ sdio: dwmmc@30010000 { ++ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; ++ reg = <0x30010000 0x4000>; ++ interrupts = ; ++ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, ++ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; ++ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; ++ fifo-depth = <0x100>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; ++ status = "disabled"; ++ }; ++ + emmc: dwmmc@30020000 { +- compatible = "rockchip,rk3288-dw-mshc"; ++ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x30020000 0x4000>; + interrupts = ; + clock-frequency = <37500000>; +@@ -511,7 +631,6 @@ emmc: dwmmc@30020000 { + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + bus-width = <8>; + default-sample-phase = <158>; +- num-slots = <1>; + fifo-depth = <0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +@@ -710,6 +829,40 @@ pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { + drive-strength = <12>; + }; + ++ sdmmc { ++ sdmmc_clk: sdmmc-clk { ++ rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; ++ }; ++ ++ sdmmc_cmd: sdmmc-cmd { ++ rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; ++ }; ++ ++ sdmmc_bus4: sdmmc-bus4 { ++ rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, ++ <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, ++ <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, ++ <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; ++ }; ++ }; ++ ++ sdio { ++ sdio_clk: sdio-clk { ++ rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; ++ }; ++ ++ sdio_cmd: sdio-cmd { ++ rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; ++ }; ++ ++ sdio_bus4: sdio-bus4 { ++ rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, ++ <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, ++ <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, ++ <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; ++ }; ++ }; ++ + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; +@@ -797,6 +950,42 @@ i2c3_xfer: i2c3-xfer { + }; + }; + ++ spi-0 { ++ spi0_clk: spi0-clk { ++ rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>; ++ }; ++ spi0_cs0: spi0-cs0 { ++ rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>; ++ }; ++ spi0_tx: spi0-tx { ++ rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; ++ }; ++ spi0_rx: spi0-rx { ++ rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; ++ }; ++ spi0_cs1: spi0-cs1 { ++ rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>; ++ }; ++ }; ++ ++ spi-1 { ++ spi1_clk: spi1-clk { ++ rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>; ++ }; ++ spi1_cs0: spi1-cs0 { ++ rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>; ++ }; ++ spi1_rx: spi1-rx { ++ rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>; ++ }; ++ spi1_tx: spi1-tx { ++ rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>; ++ }; ++ spi1_cs1: spi1-cs1 { ++ rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>; ++ }; ++ }; ++ + i2s1 { + i2s1_bus: i2s1-bus { + rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>, +@@ -835,6 +1024,12 @@ pwm3_pin: pwm3-pin { + }; + }; + ++ spdif { ++ spdif_tx: spdif-tx { ++ rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>; ++ }; ++ }; ++ + tsadc { + otp_gpio: otp-gpio { + rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>; +diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi +index 0dec94c3583b..39b61dce97ad 100644 +--- a/arch/arm/boot/dts/rk3288-evb.dtsi ++++ b/arch/arm/boot/dts/rk3288-evb.dtsi +@@ -45,7 +45,44 @@ + / { + memory@0 { + device_type = "memory"; +- reg = <0x0 0x80000000>; ++ reg = <0x0 0x0 0x0 0x80000000>; ++ }; ++ ++ adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 1>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1800000>; ++ ++ button-up { ++ label = "Volume Up"; ++ linux,code = ; ++ press-threshold-microvolt = <100000>; ++ }; ++ ++ button-down { ++ label = "Volume Down"; ++ linux,code = ; ++ press-threshold-microvolt = <300000>; ++ }; ++ ++ menu { ++ label = "Menu"; ++ linux,code = ; ++ press-threshold-microvolt = <640000>; ++ }; ++ ++ esc { ++ label = "Esc"; ++ linux,code = ; ++ press-threshold-microvolt = <1000000>; ++ }; ++ ++ home { ++ label = "Home"; ++ linux,code = ; ++ press-threshold-microvolt = <1300000>; ++ }; + }; + + backlight: backlight { +@@ -212,19 +249,22 @@ &emmc { + cap-mmc-highspeed; + disable-wp; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + status = "okay"; + }; + ++&saradc { ++ vref-supply = <&vcc_18>; ++ status = "okay"; ++}; ++ + &sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; /* wp not hooked up */ +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +@@ -248,6 +288,11 @@ &gmac { + status = "ok"; + }; + ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ + &hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts +index 61d1c1028317..41405974253a 100644 +--- a/arch/arm/boot/dts/rk3288-fennec.dts ++++ b/arch/arm/boot/dts/rk3288-fennec.dts +@@ -47,7 +47,7 @@ / { + compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; + + memory@0 { +- reg = <0x0 0x80000000>; ++ reg = <0x0 0x0 0x0 0x80000000>; + device_type = "memory"; + }; + +@@ -77,7 +77,6 @@ &emmc { + cap-mmc-highspeed; + disable-wp; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + status = "okay"; +@@ -99,6 +98,11 @@ &gmac { + status = "okay"; + }; + ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ + &hdmi { + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +index 813496618d08..5f05815f47e0 100644 +--- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi ++++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +@@ -47,7 +47,7 @@ + / { + memory@0 { + device_type = "memory"; +- reg = <0 0x80000000>; ++ reg = <0x0 0x0 0x0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { +@@ -78,7 +78,6 @@ &emmc { + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; +diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts +index b11a282c334c..7da0947ababb 100644 +--- a/arch/arm/boot/dts/rk3288-firefly-reload.dts ++++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts +@@ -269,7 +269,6 @@ &sdmmc { + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; +@@ -284,7 +283,6 @@ &sdio0 { + disable-wp; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; + sd-uhs-sdr12; +diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi +index 32dabae12e67..b9e6f3a97240 100644 +--- a/arch/arm/boot/dts/rk3288-firefly.dtsi ++++ b/arch/arm/boot/dts/rk3288-firefly.dtsi +@@ -46,7 +46,7 @@ + / { + memory@0 { + device_type = "memory"; +- reg = <0 0x80000000>; ++ reg = <0x0 0x0 0x0 0x80000000>; + }; + + adc-keys { +@@ -208,7 +208,6 @@ &emmc { + cap-mmc-highspeed; + disable-wp; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; +@@ -527,7 +526,6 @@ &sdio0 { + bus-width = <4>; + disable-wp; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>; + vmmc-supply = <&vbat_wl>; +@@ -541,7 +539,6 @@ &sdmmc { + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; +diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts +index 30e93f694ae8..4d923aa6ed11 100644 +--- a/arch/arm/boot/dts/rk3288-miqi.dts ++++ b/arch/arm/boot/dts/rk3288-miqi.dts +@@ -54,7 +54,7 @@ chosen { + + memory@0 { + device_type = "memory"; +- reg = <0 0x80000000>; ++ reg = <0x0 0x0 0x0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { +@@ -126,7 +126,6 @@ &emmc { + cap-mmc-highspeed; + disable-wp; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; +@@ -404,7 +403,6 @@ &sdmmc { + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; +diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts +index 3dda79579b51..1241cbcfc16f 100644 +--- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts ++++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts +@@ -263,7 +263,6 @@ &sdmmc { + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vdd_io_sd>; +diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi +index 26cd3ad45160..99cfae875e12 100644 +--- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi ++++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi +@@ -55,7 +55,7 @@ / { + */ + memory { + device_type = "memory"; +- reg = <0 0x8000000>; ++ reg = <0x0 0x0 0x0 0x8000000>; + }; + + aliases { +@@ -136,7 +136,6 @@ &emmc { + cap-mmc-highspeed; + disable-wp; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + vmmc-supply = <&vdd_3v3_io>; +diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts +index aa1f9ecff231..f084e0c8dcb3 100644 +--- a/arch/arm/boot/dts/rk3288-popmetal.dts ++++ b/arch/arm/boot/dts/rk3288-popmetal.dts +@@ -50,7 +50,7 @@ / { + + memory@0 { + device_type = "memory"; +- reg = <0 0x80000000>; ++ reg = <0x0 0x0 0x0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { +@@ -150,7 +150,6 @@ &emmc { + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + vmmc-supply = <&vcc_io>; +@@ -164,7 +163,6 @@ &sdmmc { + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; /* wp not hooked up */ +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + sd-uhs-sdr12; +diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts +index 1145b62edde7..e95215c9788b 100644 +--- a/arch/arm/boot/dts/rk3288-r89.dts ++++ b/arch/arm/boot/dts/rk3288-r89.dts +@@ -50,7 +50,7 @@ / { + + memory@0 { + device_type = "memory"; +- reg = <0x0 0x80000000>; ++ reg = <0x0 0x0 0x0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { +@@ -354,7 +354,6 @@ &sdmmc { + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc_sdmmc>; +diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi +index 749a9b86e6e2..b9c471fcbd42 100644 +--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi ++++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi +@@ -43,7 +43,7 @@ + + / { + memory@0 { +- reg = <0x0 0x80000000>; ++ reg = <0x0 0x0 0x0 0x80000000>; + device_type = "memory"; + }; + +@@ -89,7 +89,6 @@ &emmc { + cap-mmc-highspeed; + disable-wp; + non-removable; +- num-slots = <1>; + mmc-pwrseq = <&emmc_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts +index 8ed25e9f60bc..0e084b8a86ac 100644 +--- a/arch/arm/boot/dts/rk3288-rock2-square.dts ++++ b/arch/arm/boot/dts/rk3288-rock2-square.dts +@@ -147,7 +147,6 @@ &sdio0 { + disable-wp; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk &sdio0_int>; + vmmc-supply = <&vcc_io>; +@@ -161,7 +160,6 @@ &sdmmc { + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; /* wp not hooked up */ +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; +diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts +index f601c78386a9..346b0d8b474d 100644 +--- a/arch/arm/boot/dts/rk3288-tinker.dts ++++ b/arch/arm/boot/dts/rk3288-tinker.dts +@@ -50,7 +50,7 @@ / { + compatible = "asus,rk3288-tinker", "rockchip,rk3288"; + + memory { +- reg = <0x0 0x80000000>; ++ reg = <0x0 0x0 0x0 0x80000000>; + device_type = "memory"; + }; + +@@ -156,6 +156,11 @@ &gmac { + status = "ok"; + }; + ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ + &hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +@@ -465,7 +470,6 @@ &sdmmc { + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; /* wp not hooked up */ +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi +index aef07101e9ab..95e9bee8bca2 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi +@@ -117,7 +117,6 @@ &sdmmc { + card-detect-delay = <200>; + cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>; + rockchip,default-sample-phase = <90>; +- num-slots = <1>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index d709fa1847f9..6e5bd8974f22 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -49,7 +49,7 @@ + / { + memory@0 { + device_type = "memory"; +- reg = <0x0 0x80000000>; ++ reg = <0x0 0x0 0x0 0x80000000>; + }; + + gpio_keys: gpio-keys { +@@ -156,7 +156,6 @@ &emmc { + mmc-hs200-1_8v; + mmc-pwrseq = <&emmc_pwrseq>; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + }; +@@ -372,7 +371,6 @@ &sdio0 { + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; + sd-uhs-sdr12; +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 858e1fed762a..356ed1e62452 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -49,8 +49,8 @@ + #include + + / { +- #address-cells = <1>; +- #size-cells = <1>; ++ #address-cells = <2>; ++ #size-cells = <2>; + + compatible = "rockchip,rk3288"; + +@@ -139,13 +139,13 @@ cpu3: cpu@503 { + + amba { + compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; ++ #address-cells = <2>; ++ #size-cells = <2>; + ranges; + + dmac_peri: dma-controller@ff250000 { + compatible = "arm,pl330", "arm,primecell"; +- reg = <0xff250000 0x4000>; ++ reg = <0x0 0xff250000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; +@@ -156,7 +156,7 @@ dmac_peri: dma-controller@ff250000 { + + dmac_bus_ns: dma-controller@ff600000 { + compatible = "arm,pl330", "arm,primecell"; +- reg = <0xff600000 0x4000>; ++ reg = <0x0 0xff600000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; +@@ -168,7 +168,7 @@ dmac_bus_ns: dma-controller@ff600000 { + + dmac_bus_s: dma-controller@ffb20000 { + compatible = "arm,pl330", "arm,primecell"; +- reg = <0xffb20000 0x4000>; ++ reg = <0x0 0xffb20000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; +@@ -179,8 +179,8 @@ dmac_bus_s: dma-controller@ffb20000 { + }; + + reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; ++ #address-cells = <2>; ++ #size-cells = <2>; + ranges; + + /* +@@ -194,7 +194,7 @@ reserved-memory { + * is found. + */ + dma-unusable@fe000000 { +- reg = <0xfe000000 0x1000000>; ++ reg = <0x0 0xfe000000 0x0 0x1000000>; + }; + }; + +@@ -217,7 +217,7 @@ timer { + + timer: timer@ff810000 { + compatible = "rockchip,rk3288-timer"; +- reg = <0xff810000 0x20>; ++ reg = <0x0 0xff810000 0x0 0x20>; + interrupts = ; + clocks = <&xin24m>, <&cru PCLK_TIMER>; + clock-names = "timer", "pclk"; +@@ -236,7 +236,7 @@ sdmmc: dwmmc@ff0c0000 { + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; +- reg = <0xff0c0000 0x4000>; ++ reg = <0x0 0xff0c0000 0x0 0x4000>; + resets = <&cru SRST_MMC0>; + reset-names = "reset"; + status = "disabled"; +@@ -250,7 +250,7 @@ sdio0: dwmmc@ff0d0000 { + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; +- reg = <0xff0d0000 0x4000>; ++ reg = <0x0 0xff0d0000 0x0 0x4000>; + resets = <&cru SRST_SDIO0>; + reset-names = "reset"; + status = "disabled"; +@@ -264,7 +264,7 @@ sdio1: dwmmc@ff0e0000 { + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; +- reg = <0xff0e0000 0x4000>; ++ reg = <0x0 0xff0e0000 0x0 0x4000>; + resets = <&cru SRST_SDIO1>; + reset-names = "reset"; + status = "disabled"; +@@ -278,7 +278,7 @@ emmc: dwmmc@ff0f0000 { + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; +- reg = <0xff0f0000 0x4000>; ++ reg = <0x0 0xff0f0000 0x0 0x4000>; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; + status = "disabled"; +@@ -286,7 +286,7 @@ emmc: dwmmc@ff0f0000 { + + saradc: saradc@ff100000 { + compatible = "rockchip,saradc"; +- reg = <0xff100000 0x100>; ++ reg = <0x0 0xff100000 0x0 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; +@@ -305,7 +305,7 @@ spi0: spi@ff110000 { + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +- reg = <0xff110000 0x1000>; ++ reg = <0x0 0xff110000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -320,7 +320,7 @@ spi1: spi@ff120000 { + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +- reg = <0xff120000 0x1000>; ++ reg = <0x0 0xff120000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -335,7 +335,7 @@ spi2: spi@ff130000 { + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; +- reg = <0xff130000 0x1000>; ++ reg = <0x0 0xff130000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -343,7 +343,7 @@ spi2: spi@ff130000 { + + i2c1: i2c@ff140000 { + compatible = "rockchip,rk3288-i2c"; +- reg = <0xff140000 0x1000>; ++ reg = <0x0 0xff140000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; +@@ -356,7 +356,7 @@ i2c1: i2c@ff140000 { + + i2c3: i2c@ff150000 { + compatible = "rockchip,rk3288-i2c"; +- reg = <0xff150000 0x1000>; ++ reg = <0x0 0xff150000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; +@@ -369,7 +369,7 @@ i2c3: i2c@ff150000 { + + i2c4: i2c@ff160000 { + compatible = "rockchip,rk3288-i2c"; +- reg = <0xff160000 0x1000>; ++ reg = <0x0 0xff160000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; +@@ -382,7 +382,7 @@ i2c4: i2c@ff160000 { + + i2c5: i2c@ff170000 { + compatible = "rockchip,rk3288-i2c"; +- reg = <0xff170000 0x1000>; ++ reg = <0x0 0xff170000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; +@@ -395,7 +395,7 @@ i2c5: i2c@ff170000 { + + uart0: serial@ff180000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; +- reg = <0xff180000 0x100>; ++ reg = <0x0 0xff180000 0x0 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; +@@ -408,7 +408,7 @@ uart0: serial@ff180000 { + + uart1: serial@ff190000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; +- reg = <0xff190000 0x100>; ++ reg = <0x0 0xff190000 0x0 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; +@@ -421,7 +421,7 @@ uart1: serial@ff190000 { + + uart2: serial@ff690000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; +- reg = <0xff690000 0x100>; ++ reg = <0x0 0xff690000 0x0 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; +@@ -434,7 +434,7 @@ uart2: serial@ff690000 { + + uart3: serial@ff1b0000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; +- reg = <0xff1b0000 0x100>; ++ reg = <0x0 0xff1b0000 0x0 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; +@@ -447,7 +447,7 @@ uart3: serial@ff1b0000 { + + uart4: serial@ff1c0000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; +- reg = <0xff1c0000 0x100>; ++ reg = <0x0 0xff1c0000 0x0 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; +@@ -535,7 +535,7 @@ map0 { + + tsadc: tsadc@ff280000 { + compatible = "rockchip,rk3288-tsadc"; +- reg = <0xff280000 0x100>; ++ reg = <0x0 0xff280000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; +@@ -552,7 +552,7 @@ tsadc: tsadc@ff280000 { + + gmac: ethernet@ff290000 { + compatible = "rockchip,rk3288-gmac"; +- reg = <0xff290000 0x10000>; ++ reg = <0x0 0xff290000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; +@@ -572,7 +572,7 @@ gmac: ethernet@ff290000 { + + usb_host0_ehci: usb@ff500000 { + compatible = "generic-ehci"; +- reg = <0xff500000 0x100>; ++ reg = <0x0 0xff500000 0x0 0x100>; + interrupts = ; + clocks = <&cru HCLK_USBHOST0>; + clock-names = "usbhost"; +@@ -586,7 +586,7 @@ usb_host0_ehci: usb@ff500000 { + usb_host1: usb@ff540000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; +- reg = <0xff540000 0x40000>; ++ reg = <0x0 0xff540000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USBHOST1>; + clock-names = "otg"; +@@ -599,7 +599,7 @@ usb_host1: usb@ff540000 { + usb_otg: usb@ff580000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; +- reg = <0xff580000 0x40000>; ++ reg = <0x0 0xff580000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; +@@ -614,7 +614,7 @@ usb_otg: usb@ff580000 { + + usb_hsic: usb@ff5c0000 { + compatible = "generic-ehci"; +- reg = <0xff5c0000 0x100>; ++ reg = <0x0 0xff5c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru HCLK_HSIC>; + clock-names = "usbhost"; +@@ -623,7 +623,7 @@ usb_hsic: usb@ff5c0000 { + + i2c0: i2c@ff650000 { + compatible = "rockchip,rk3288-i2c"; +- reg = <0xff650000 0x1000>; ++ reg = <0x0 0xff650000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; +@@ -636,7 +636,7 @@ i2c0: i2c@ff650000 { + + i2c2: i2c@ff660000 { + compatible = "rockchip,rk3288-i2c"; +- reg = <0xff660000 0x1000>; ++ reg = <0x0 0xff660000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; +@@ -649,7 +649,7 @@ i2c2: i2c@ff660000 { + + pwm0: pwm@ff680000 { + compatible = "rockchip,rk3288-pwm"; +- reg = <0xff680000 0x10>; ++ reg = <0x0 0xff680000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; +@@ -660,7 +660,7 @@ pwm0: pwm@ff680000 { + + pwm1: pwm@ff680010 { + compatible = "rockchip,rk3288-pwm"; +- reg = <0xff680010 0x10>; ++ reg = <0x0 0xff680010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; +@@ -671,7 +671,7 @@ pwm1: pwm@ff680010 { + + pwm2: pwm@ff680020 { + compatible = "rockchip,rk3288-pwm"; +- reg = <0xff680020 0x10>; ++ reg = <0x0 0xff680020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; +@@ -682,7 +682,7 @@ pwm2: pwm@ff680020 { + + pwm3: pwm@ff680030 { + compatible = "rockchip,rk3288-pwm"; +- reg = <0xff680030 0x10>; ++ reg = <0x0 0xff680030 0x0 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; +@@ -693,10 +693,10 @@ pwm3: pwm@ff680030 { + + bus_intmem@ff700000 { + compatible = "mmio-sram"; +- reg = <0xff700000 0x18000>; ++ reg = <0x0 0xff700000 0x0 0x18000>; + #address-cells = <1>; + #size-cells = <1>; +- ranges = <0 0xff700000 0x18000>; ++ ranges = <0 0x0 0xff700000 0x18000>; + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x00 0x10>; +@@ -705,12 +705,12 @@ smp-sram@0 { + + sram@ff720000 { + compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; +- reg = <0xff720000 0x1000>; ++ reg = <0x0 0xff720000 0x0 0x1000>; + }; + + pmu: power-management@ff730000 { + compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; +- reg = <0xff730000 0x100>; ++ reg = <0x0 0xff730000 0x0 0x100>; + + power: power-controller { + compatible = "rockchip,rk3288-power-controller"; +@@ -831,12 +831,12 @@ reboot-mode { + + sgrf: syscon@ff740000 { + compatible = "rockchip,rk3288-sgrf", "syscon"; +- reg = <0xff740000 0x1000>; ++ reg = <0x0 0xff740000 0x0 0x1000>; + }; + + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3288-cru"; +- reg = <0xff760000 0x1000>; ++ reg = <0x0 0xff760000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; +@@ -854,7 +854,7 @@ cru: clock-controller@ff760000 { + + grf: syscon@ff770000 { + compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; +- reg = <0xff770000 0x1000>; ++ reg = <0x0 0xff770000 0x0 0x1000>; + + edp_phy: edp-phy { + compatible = "rockchip,rk3288-dp-phy"; +@@ -903,7 +903,7 @@ usbphy2: usb-phy@348 { + + wdt: watchdog@ff800000 { + compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; +- reg = <0xff800000 0x100>; ++ reg = <0x0 0xff800000 0x0 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = ; + status = "disabled"; +@@ -911,7 +911,7 @@ wdt: watchdog@ff800000 { + + spdif: sound@ff88b0000 { + compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; +- reg = <0xff8b0000 0x10000>; ++ reg = <0x0 0xff8b0000 0x0 0x10000>; + #sound-dai-cells = <0>; + clock-names = "hclk", "mclk"; + clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; +@@ -926,7 +926,7 @@ spdif: sound@ff88b0000 { + + i2s: i2s@ff890000 { + compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; +- reg = <0xff890000 0x10000>; ++ reg = <0x0 0xff890000 0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; +@@ -943,7 +943,7 @@ i2s: i2s@ff890000 { + + crypto: cypto-controller@ff8a0000 { + compatible = "rockchip,rk3288-crypto"; +- reg = <0xff8a0000 0x4000>; ++ reg = <0x0 0xff8a0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, + <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; +@@ -953,9 +953,28 @@ crypto: cypto-controller@ff8a0000 { + status = "okay"; + }; + ++ iep_mmu: iommu@ff900800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff900800 0x0 0x40>; ++ interrupts = ; ++ interrupt-names = "iep_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ isp_mmu: iommu@ff914000 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; ++ interrupts = ; ++ interrupt-names = "isp_mmu"; ++ #iommu-cells = <0>; ++ rockchip,disable-mmu-reset; ++ status = "disabled"; ++ }; ++ + vopb: vop@ff930000 { + compatible = "rockchip,rk3288-vop"; +- reg = <0xff930000 0x19c>; ++ reg = <0x0 0xff930000 0x0 0x19c>; + interrupts = ; + clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +@@ -988,7 +1007,7 @@ vopb_out_mipi: endpoint@2 { + + vopb_mmu: iommu@ff930300 { + compatible = "rockchip,iommu"; +- reg = <0xff930300 0x100>; ++ reg = <0x0 0xff930300 0x0 0x100>; + interrupts = ; + interrupt-names = "vopb_mmu"; + power-domains = <&power RK3288_PD_VIO>; +@@ -998,7 +1017,7 @@ vopb_mmu: iommu@ff930300 { + + vopl: vop@ff940000 { + compatible = "rockchip,rk3288-vop"; +- reg = <0xff940000 0x19c>; ++ reg = <0x0 0xff940000 0x0 0x19c>; + interrupts = ; + clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +@@ -1031,7 +1050,7 @@ vopl_out_mipi: endpoint@2 { + + vopl_mmu: iommu@ff940300 { + compatible = "rockchip,iommu"; +- reg = <0xff940300 0x100>; ++ reg = <0x0 0xff940300 0x0 0x100>; + interrupts = ; + interrupt-names = "vopl_mmu"; + power-domains = <&power RK3288_PD_VIO>; +@@ -1041,7 +1060,7 @@ vopl_mmu: iommu@ff940300 { + + mipi_dsi: mipi@ff960000 { + compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; +- reg = <0xff960000 0x4000>; ++ reg = <0x0 0xff960000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; + clock-names = "ref", "pclk"; +@@ -1069,7 +1088,7 @@ mipi_in_vopl: endpoint@1 { + + edp: dp@ff970000 { + compatible = "rockchip,rk3288-dp"; +- reg = <0xff970000 0x4000>; ++ reg = <0x0 0xff970000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; + clock-names = "dp", "pclk"; +@@ -1101,7 +1120,7 @@ edp_in_vopl: endpoint@1 { + + hdmi: hdmi@ff980000 { + compatible = "rockchip,rk3288-dw-hdmi"; +- reg = <0xff980000 0x20000>; ++ reg = <0x0 0xff980000 0x0 0x20000>; + reg-io-width = <4>; + rockchip,grf = <&grf>; + interrupts = ; +@@ -1126,9 +1145,27 @@ hdmi_in_vopl: endpoint@1 { + }; + }; + ++ vpu_mmu: iommu@ff9a0800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff9a0800 0x0 0x100>; ++ interrupts = ; ++ interrupt-names = "vpu_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ hevc_mmu: iommu@ff9c0440 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; ++ interrupts = ; ++ interrupt-names = "hevc_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ + gpu: gpu@ffa30000 { + compatible = "rockchip,rk3288-mali", "arm,mali-t760"; +- reg = <0xffa30000 0x10000>; ++ reg = <0x0 0xffa30000 0x0 0x10000>; + interrupts = , + , + ; +@@ -1170,72 +1207,72 @@ opp@600000000 { + + qos_gpu_r: qos@ffaa0000 { + compatible = "syscon"; +- reg = <0xffaa0000 0x20>; ++ reg = <0x0 0xffaa0000 0x0 0x20>; + }; + + qos_gpu_w: qos@ffaa0080 { + compatible = "syscon"; +- reg = <0xffaa0080 0x20>; ++ reg = <0x0 0xffaa0080 0x0 0x20>; + }; + + qos_vio1_vop: qos@ffad0000 { + compatible = "syscon"; +- reg = <0xffad0000 0x20>; ++ reg = <0x0 0xffad0000 0x0 0x20>; + }; + + qos_vio1_isp_w0: qos@ffad0100 { + compatible = "syscon"; +- reg = <0xffad0100 0x20>; ++ reg = <0x0 0xffad0100 0x0 0x20>; + }; + + qos_vio1_isp_w1: qos@ffad0180 { + compatible = "syscon"; +- reg = <0xffad0180 0x20>; ++ reg = <0x0 0xffad0180 0x0 0x20>; + }; + + qos_vio0_vop: qos@ffad0400 { + compatible = "syscon"; +- reg = <0xffad0400 0x20>; ++ reg = <0x0 0xffad0400 0x0 0x20>; + }; + + qos_vio0_vip: qos@ffad0480 { + compatible = "syscon"; +- reg = <0xffad0480 0x20>; ++ reg = <0x0 0xffad0480 0x0 0x20>; + }; + + qos_vio0_iep: qos@ffad0500 { + compatible = "syscon"; +- reg = <0xffad0500 0x20>; ++ reg = <0x0 0xffad0500 0x0 0x20>; + }; + + qos_vio2_rga_r: qos@ffad0800 { + compatible = "syscon"; +- reg = <0xffad0800 0x20>; ++ reg = <0x0 0xffad0800 0x0 0x20>; + }; + + qos_vio2_rga_w: qos@ffad0880 { + compatible = "syscon"; +- reg = <0xffad0880 0x20>; ++ reg = <0x0 0xffad0880 0x0 0x20>; + }; + + qos_vio1_isp_r: qos@ffad0900 { + compatible = "syscon"; +- reg = <0xffad0900 0x20>; ++ reg = <0x0 0xffad0900 0x0 0x20>; + }; + + qos_video: qos@ffae0000 { + compatible = "syscon"; +- reg = <0xffae0000 0x20>; ++ reg = <0x0 0xffae0000 0x0 0x20>; + }; + + qos_hevc_r: qos@ffaf0000 { + compatible = "syscon"; +- reg = <0xffaf0000 0x20>; ++ reg = <0x0 0xffaf0000 0x0 0x20>; + }; + + qos_hevc_w: qos@ffaf0080 { + compatible = "syscon"; +- reg = <0xffaf0080 0x20>; ++ reg = <0x0 0xffaf0080 0x0 0x20>; + }; + + gic: interrupt-controller@ffc01000 { +@@ -1244,16 +1281,16 @@ gic: interrupt-controller@ffc01000 { + #interrupt-cells = <3>; + #address-cells = <0>; + +- reg = <0xffc01000 0x1000>, +- <0xffc02000 0x2000>, +- <0xffc04000 0x2000>, +- <0xffc06000 0x2000>; ++ reg = <0x0 0xffc01000 0x0 0x1000>, ++ <0x0 0xffc02000 0x0 0x2000>, ++ <0x0 0xffc04000 0x0 0x2000>, ++ <0x0 0xffc06000 0x0 0x2000>; + interrupts = ; + }; + + efuse: efuse@ffb40000 { + compatible = "rockchip,rk3288-efuse"; +- reg = <0xffb40000 0x20>; ++ reg = <0x0 0xffb40000 0x0 0x20>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE256>; +@@ -1268,13 +1305,13 @@ pinctrl: pinctrl { + compatible = "rockchip,rk3288-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; +- #address-cells = <1>; +- #size-cells = <1>; ++ #address-cells = <2>; ++ #size-cells = <2>; + ranges; + + gpio0: gpio0@ff750000 { + compatible = "rockchip,gpio-bank"; +- reg = <0xff750000 0x100>; ++ reg = <0x0 0xff750000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + +@@ -1287,7 +1324,7 @@ gpio0: gpio0@ff750000 { + + gpio1: gpio1@ff780000 { + compatible = "rockchip,gpio-bank"; +- reg = <0xff780000 0x100>; ++ reg = <0x0 0xff780000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + +@@ -1300,7 +1337,7 @@ gpio1: gpio1@ff780000 { + + gpio2: gpio2@ff790000 { + compatible = "rockchip,gpio-bank"; +- reg = <0xff790000 0x100>; ++ reg = <0x0 0xff790000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + +@@ -1313,7 +1350,7 @@ gpio2: gpio2@ff790000 { + + gpio3: gpio3@ff7a0000 { + compatible = "rockchip,gpio-bank"; +- reg = <0xff7a0000 0x100>; ++ reg = <0x0 0xff7a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + +@@ -1326,7 +1363,7 @@ gpio3: gpio3@ff7a0000 { + + gpio4: gpio4@ff7b0000 { + compatible = "rockchip,gpio-bank"; +- reg = <0xff7b0000 0x100>; ++ reg = <0x0 0xff7b0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>; + +@@ -1339,7 +1376,7 @@ gpio4: gpio4@ff7b0000 { + + gpio5: gpio5@ff7c0000 { + compatible = "rockchip,gpio-bank"; +- reg = <0xff7c0000 0x100>; ++ reg = <0x0 0xff7c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO5>; + +@@ -1352,7 +1389,7 @@ gpio5: gpio5@ff7c0000 { + + gpio6: gpio6@ff7d0000 { + compatible = "rockchip,gpio-bank"; +- reg = <0xff7d0000 0x100>; ++ reg = <0x0 0xff7d0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO6>; + +@@ -1365,7 +1402,7 @@ gpio6: gpio6@ff7d0000 { + + gpio7: gpio7@ff7e0000 { + compatible = "rockchip,gpio-bank"; +- reg = <0xff7e0000 0x100>; ++ reg = <0x0 0xff7e0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO7>; + +@@ -1378,7 +1415,7 @@ gpio7: gpio7@ff7e0000 { + + gpio8: gpio8@ff7f0000 { + compatible = "rockchip,gpio-bank"; +- reg = <0xff7f0000 0x100>; ++ reg = <0x0 0xff7f0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO8>; + +diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts +index 58cf4ac079c3..86a57f823616 100644 +--- a/arch/arm/boot/dts/rv1108-evb.dts ++++ b/arch/arm/boot/dts/rv1108-evb.dts +@@ -54,6 +54,184 @@ memory@60000000 { + chosen { + stdout-path = "serial2:1500000n8"; + }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ brightness-levels = < ++ 0 1 2 3 4 5 6 7 ++ 8 9 10 11 12 13 14 15 ++ 16 17 18 19 20 21 22 23 ++ 24 25 26 27 28 29 30 31 ++ 32 33 34 35 36 37 38 39 ++ 40 41 42 43 44 45 46 47 ++ 48 49 50 51 52 53 54 55 ++ 56 57 58 59 60 61 62 63 ++ 64 65 66 67 68 69 70 71 ++ 72 73 74 75 76 77 78 79 ++ 80 81 82 83 84 85 86 87 ++ 88 89 90 91 92 93 94 95 ++ 96 97 98 99 100 101 102 103 ++ 104 105 106 107 108 109 110 111 ++ 112 113 114 115 116 117 118 119 ++ 120 121 122 123 124 125 126 127 ++ 128 129 130 131 132 133 134 135 ++ 136 137 138 139 140 141 142 143 ++ 144 145 146 147 148 149 150 151 ++ 152 153 154 155 156 157 158 159 ++ 160 161 162 163 164 165 166 167 ++ 168 169 170 171 172 173 174 175 ++ 176 177 178 179 180 181 182 183 ++ 184 185 186 187 188 189 190 191 ++ 192 193 194 195 196 197 198 199 ++ 200 201 202 203 204 205 206 207 ++ 208 209 210 211 212 213 214 215 ++ 216 217 218 219 220 221 222 223 ++ 224 225 226 227 228 229 230 231 ++ 232 233 234 235 236 237 238 239 ++ 240 241 242 243 244 245 246 247 ++ 248 249 250 251 252 253 254 255>; ++ default-brightness-level = <200>; ++ pwms = <&pwm0 0 25000 0>; ++ }; ++ ++ vcc_sys: vsys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vsys"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_core>; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ i2c-scl-rising-time-ns = <275>; ++ i2c-scl-falling-time-ns = <16>; ++ clock-frequency = <400000>; ++ ++ rk805: pmic@18 { ++ compatible = "rockchip,rk805"; ++ reg = <0x18>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ rockchip,system-power-controller; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_sys>; ++ vcc6-supply = <&vcc_sys>; ++ ++ regulators { ++ vdd_core: DCDC_REG1 { ++ regulator-name= "vdd_core"; ++ regulator-min-microvolt = <700000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-state-enabled; ++ regulator-state-uv = <900000>; ++ }; ++ }; ++ ++ vdd_cam: DCDC_REG2 { ++ regulator-name= "vdd_cam"; ++ regulator-min-microvolt = <700000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-state-mem { ++ regulator-state-disabled; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name= "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-state-enabled; ++ }; ++ }; ++ ++ vcc_io: DCDC_REG4 { ++ regulator-name= "vcc_io"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-state-enabled; ++ regulator-state-uv = <3300000>; ++ }; ++ }; ++ ++ vdd_10: LDO_REG1 { ++ regulator-name= "vdd_10"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-state-disabled; ++ }; ++ }; ++ ++ vcc_18: LDO_REG2 { ++ regulator-name= "vcc_18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-state-disabled; ++ }; ++ }; ++ ++ vdd10_pmu: LDO_REG3 { ++ regulator-name= "vdd10_pmu"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-state-enabled; ++ regulator-state-uv = <1000000>; ++ }; ++ }; ++ }; ++ }; ++ ++ bma250: accelerometer@19 { ++ compatible = "bosch,bma250e"; ++ reg = <0x19>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ }; ++}; ++ ++&pwm0 { ++ status = "okay"; ++}; ++ ++&sdmmc { ++ status = "okay"; ++}; ++ ++&u2phy { ++ status = "okay"; ++ ++ u2phy_host: host-port { ++ status = "okay"; ++ }; ++ ++ u2phy_otg: otg-port { ++ status = "okay"; ++ }; + }; + + &uart0 { +@@ -67,3 +245,15 @@ &uart1 { + &uart2 { + status = "okay"; + }; ++ ++&usb_host_ehci { ++ status = "okay"; ++}; ++ ++&usb_host_ohci { ++ status = "okay"; ++}; ++ ++&usb_otg { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi +index 437098b556eb..e7cd1315db1b 100644 +--- a/arch/arm/boot/dts/rv1108.dtsi ++++ b/arch/arm/boot/dts/rv1108.dtsi +@@ -52,6 +52,10 @@ / { + interrupt-parent = <&gic>; + + aliases { ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c2 = &i2c2; ++ i2c3 = &i2c3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; +@@ -65,6 +69,33 @@ cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; ++ clocks = <&cru ARMCLK>; ++ operating-points-v2 = <&cpu_opp_table>; ++ }; ++ }; ++ ++ cpu_opp_table: opp_table { ++ compatible = "operating-points-v2"; ++ ++ opp-408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <975000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <975000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <1025000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <1150000>; ++ clock-latency-ns = <40000>; + }; + }; + +@@ -154,9 +185,221 @@ uart0: serial@10230000 { + status = "disabled"; + }; + ++ i2c1: i2c@10240000 { ++ compatible = "rockchip,rv1108-i2c"; ++ reg = <0x10240000 0x1000>; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; ++ clock-names = "i2c", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_xfer>; ++ rockchip,grf = <&grf>; ++ status = "disabled"; ++ }; ++ ++ i2c2: i2c@10250000 { ++ compatible = "rockchip,rv1108-i2c"; ++ reg = <0x10250000 0x1000>; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; ++ clock-names = "i2c", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2m1_xfer>; ++ rockchip,grf = <&grf>; ++ status = "disabled"; ++ }; ++ ++ i2c3: i2c@10260000 { ++ compatible = "rockchip,rv1108-i2c"; ++ reg = <0x10260000 0x1000>; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; ++ clock-names = "i2c", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_xfer>; ++ rockchip,grf = <&grf>; ++ status = "disabled"; ++ }; ++ ++ spi: spi@10270000 { ++ compatible = "rockchip,rv1108-spi"; ++ reg = <0x10270000 0x1000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&pdma 8>, <&pdma 9>; ++ #dma-cells = <2>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pwm4: pwm@10280000 { ++ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; ++ reg = <0x10280000 0x10>; ++ interrupts = ; ++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm4_pin>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm5: pwm@10280010 { ++ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; ++ reg = <0x10280010 0x10>; ++ interrupts = ; ++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm5_pin>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm6: pwm@10280020 { ++ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; ++ reg = <0x10280020 0x10>; ++ interrupts = ; ++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm6_pin>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm7: pwm@10280030 { ++ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; ++ reg = <0x10280030 0x10>; ++ interrupts = ; ++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm7_pin>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + grf: syscon@10300000 { +- compatible = "rockchip,rv1108-grf", "syscon"; ++ compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; + reg = <0x10300000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ u2phy: usb2-phy@100 { ++ compatible = "rockchip,rv1108-usb2phy"; ++ reg = <0x100 0x0c>; ++ clocks = <&cru SCLK_USBPHY>; ++ clock-names = "phyclk"; ++ #clock-cells = <0>; ++ clock-output-names = "usbphy"; ++ rockchip,usbgrf = <&usbgrf>; ++ status = "disabled"; ++ ++ u2phy_otg: otg-port { ++ interrupts = ; ++ interrupt-names = "otg-mux"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ u2phy_host: host-port { ++ interrupts = ; ++ interrupt-names = "linestate"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ watchdog: wdt@10360000 { ++ compatible = "snps,dw-wdt"; ++ reg = <0x10360000 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_WDT>; ++ clock-names = "pclk_wdt"; ++ status = "disabled"; ++ }; ++ ++ adc: adc@1038c000 { ++ compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; ++ reg = <0x1038c000 0x100>; ++ interrupts = ; ++ #io-channel-cells = <1>; ++ clock-frequency = <1000000>; ++ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; ++ clock-names = "saradc", "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ i2c0: i2c@20000000 { ++ compatible = "rockchip,rv1108-i2c"; ++ reg = <0x20000000 0x1000>; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>; ++ clock-names = "i2c", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_xfer>; ++ rockchip,grf = <&grf>; ++ status = "disabled"; ++ }; ++ ++ pwm0: pwm@20040000 { ++ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; ++ reg = <0x20040000 0x10>; ++ interrupts = ; ++ clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pin>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm1: pwm@20040010 { ++ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; ++ reg = <0x20040010 0x10>; ++ interrupts = ; ++ clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm1_pin>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm2: pwm@20040020 { ++ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; ++ reg = <0x20040020 0x10>; ++ interrupts = ; ++ clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm2_pin>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm3: pwm@20040030 { ++ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; ++ reg = <0x20040030 0x10>; ++ interrupts = ; ++ clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm3_pin>; ++ #pwm-cells = <3>; ++ status = "disabled"; + }; + + pmugrf: syscon@20060000 { +@@ -164,6 +407,11 @@ pmugrf: syscon@20060000 { + reg = <0x20060000 0x1000>; + }; + ++ usbgrf: syscon@202a0000 { ++ compatible = "rockchip,rv1108-usbgrf", "syscon"; ++ reg = <0x202a0000 0x1000>; ++ }; ++ + cru: clock-controller@20200000 { + compatible = "rockchip,rv1108-cru"; + reg = <0x20200000 0x1000>; +@@ -174,37 +422,78 @@ cru: clock-controller@20200000 { + + emmc: dwmmc@30110000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; +- clock-freq-min-max = <400000 150000000>; ++ reg = <0x30110000 0x4000>; ++ interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; +- interrupts = ; +- reg = <0x30110000 0x4000>; ++ max-frequency = <150000000>; + status = "disabled"; + }; + + sdio: dwmmc@30120000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; +- clock-freq-min-max = <400000 150000000>; ++ reg = <0x30120000 0x4000>; ++ interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; +- interrupts = ; +- reg = <0x30120000 0x4000>; ++ max-frequency = <150000000>; + status = "disabled"; + }; + + sdmmc: dwmmc@30130000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; +- clock-freq-min-max = <400000 100000000>; ++ reg = <0x30130000 0x4000>; ++ interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; +- interrupts = ; +- reg = <0x30130000 0x4000>; ++ max-frequency = <100000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; ++ status = "disabled"; ++ }; ++ ++ usb_host_ehci: usb@30140000 { ++ compatible = "generic-ehci"; ++ reg = <0x30140000 0x20000>; ++ interrupts = ; ++ clocks = <&cru HCLK_HOST0>, <&u2phy>; ++ clock-names = "usbhost", "utmi"; ++ phys = <&u2phy_host>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ usb_host_ohci: usb@30160000 { ++ compatible = "generic-ohci"; ++ reg = <0x30160000 0x20000>; ++ interrupts = ; ++ clocks = <&cru HCLK_HOST0>, <&u2phy>; ++ clock-names = "usbhost", "utmi"; ++ phys = <&u2phy_host>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ usb_otg: usb@30180000 { ++ compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb", ++ "snps,dwc2"; ++ reg = <0x30180000 0x40000>; ++ interrupts = ; ++ clocks = <&cru HCLK_OTG>; ++ clock-names = "otg"; ++ dr_mode = "otg"; ++ g-np-tx-fifo-size = <16>; ++ g-rx-fifo-size = <280>; ++ g-tx-fifo-size = <256 128 128 64 32 16>; ++ g-use-dma; ++ phys = <&u2phy_otg>; ++ phy-names = "usb2-phy"; + status = "disabled"; + }; + +@@ -301,6 +590,11 @@ pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { + drive-strength = <12>; + }; + ++ pcfg_pull_none_smt: pcfg-pull-none-smt { ++ bias-disable; ++ input-schmitt-enable; ++ }; ++ + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; +@@ -328,6 +622,13 @@ pcfg_input_high: pcfg-input-high { + input-enable; + }; + ++ i2c0 { ++ i2c0_xfer: i2c0-xfer { ++ rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>, ++ <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>; ++ }; ++ }; ++ + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, +@@ -366,6 +667,54 @@ i2c3_xfer: i2c3-xfer { + }; + }; + ++ pwm0 { ++ pwm0_pin: pwm0-pin { ++ rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm1 { ++ pwm1_pin: pwm1-pin { ++ rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm2 { ++ pwm2_pin: pwm2-pin { ++ rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm3 { ++ pwm3_pin: pwm3-pin { ++ rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm4 { ++ pwm4_pin: pwm4-pin { ++ rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm5 { ++ pwm5_pin: pwm5-pin { ++ rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm6 { ++ pwm6_pin: pwm6-pin { ++ rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm7 { ++ pwm7_pin: pwm7-pin { ++ rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; ++ }; ++ }; ++ + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; +diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi +index 60e69aeacbdb..38d2216c7ead 100644 +--- a/arch/arm/boot/dts/sama5d2.dtsi ++++ b/arch/arm/boot/dts/sama5d2.dtsi +@@ -416,6 +416,17 @@ hlcdc_pwm: hlcdc-pwm { + }; + }; + ++ isc: isc@f0008000 { ++ compatible = "atmel,sama5d2-isc"; ++ reg = <0xf0008000 0x4000>; ++ interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; ++ clocks = <&isc_clk>, <&iscck>, <&isc_gclk>; ++ clock-names = "hclock", "iscck", "gck"; ++ #clock-cells = <0>; ++ clock-output-names = "isc-mck"; ++ status = "disabled"; ++ }; ++ + ramc0: ramc@f000c000 { + compatible = "atmel,sama5d3-ddramc"; + reg = <0xf000c000 0x200>; +@@ -494,6 +505,24 @@ plladiv: plladivck { + clocks = <&plla>; + }; + ++ audio_pll_frac: audiopll_fracck { ++ compatible = "atmel,sama5d2-clk-audio-pll-frac"; ++ #clock-cells = <0>; ++ clocks = <&main>; ++ }; ++ ++ audio_pll_pad: audiopll_padck { ++ compatible = "atmel,sama5d2-clk-audio-pll-pad"; ++ #clock-cells = <0>; ++ clocks = <&audio_pll_frac>; ++ }; ++ ++ audio_pll_pmc: audiopll_pmcck { ++ compatible = "atmel,sama5d2-clk-audio-pll-pmc"; ++ #clock-cells = <0>; ++ clocks = <&audio_pll_frac>; ++ }; ++ + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; +@@ -895,7 +924,7 @@ gck { + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; +- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; ++ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>; + + sdmmc0_gclk: sdmmc0_gclk { + #clock-cells = <0>; +@@ -925,6 +954,11 @@ pwm_gclk: pwm_gclk { + atmel,clk-output-range = <0 83000000>; + }; + ++ isc_gclk: isc_gclk { ++ #clock-cells = <0>; ++ reg = <46>; ++ }; ++ + pdmic_gclk: pdmic_gclk { + #clock-cells = <0>; + reg = <48>; +@@ -951,9 +985,37 @@ can1_gclk: can1_gclk { + reg = <57>; + atmel,clk-output-range = <0 80000000>; + }; ++ ++ classd_gclk: classd_gclk { ++ #clock-cells = <0>; ++ reg = <59>; ++ atmel,clk-output-range = <0 100000000>; ++ }; + }; + }; + ++ qspi0: spi@f0020000 { ++ compatible = "atmel,sama5d2-qspi"; ++ reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; ++ reg-names = "qspi_base", "qspi_mmap"; ++ interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; ++ clocks = <&qspi0_clk>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ qspi1: spi@f0024000 { ++ compatible = "atmel,sama5d2-qspi"; ++ reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; ++ reg-names = "qspi_base", "qspi_mmap"; ++ interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; ++ clocks = <&qspi1_clk>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + sha@f0028000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xf0028000 0x100>; +@@ -1406,6 +1468,19 @@ AT91_XDMAC_DT_PERID(28))>, + status = "okay"; + }; + ++ classd: classd@fc048000 { ++ compatible = "atmel,sama5d2-classd"; ++ reg = <0xfc048000 0x100>; ++ interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; ++ dmas = <&dma0 ++ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | ++ AT91_XDMAC_DT_PERID(47))>; ++ dma-names = "tx"; ++ clocks = <&classd_clk>, <&classd_gclk>; ++ clock-names = "pclk", "gclk"; ++ status = "disabled"; ++ }; ++ + can1: can@fc050000 { + compatible = "bosch,m_can"; + reg = <0xfc050000 0x4000>, <0x210000 0x4000>; +diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi +index 54bc6d3cf290..40f4ad3c34c6 100644 +--- a/arch/arm/boot/dts/spear1310.dtsi ++++ b/arch/arm/boot/dts/spear1310.dtsi +@@ -98,6 +98,7 @@ pcie0: pcie@b1000000 { + device_type = "pci"; + ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ ++ bus-range = <0x00 0xff>; + status = "disabled"; + }; + +@@ -116,6 +117,7 @@ pcie1: pcie@b1800000 { + device_type = "pci"; + ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ ++ bus-range = <0x00 0xff>; + status = "disabled"; + }; + +@@ -134,6 +136,7 @@ pcie2: pcie@b4000000 { + device_type = "pci"; + ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ ++ bus-range = <0x00 0xff>; + status = "disabled"; + }; + +diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi +index df2232d767ed..5f347054527d 100644 +--- a/arch/arm/boot/dts/spear1340.dtsi ++++ b/arch/arm/boot/dts/spear1340.dtsi +@@ -63,6 +63,7 @@ pcie0: pcie@b1000000 { + device_type = "pci"; + ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ ++ bus-range = <0x00 0xff>; + status = "disabled"; + }; + +diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi +index 6c5affe2d0f5..2310a4e97768 100644 +--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi ++++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi +@@ -37,6 +37,14 @@ CPU0: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x300>; ++ /* cpufreq controls */ ++ operating-points = <998400 0 ++ 800000 0 ++ 400000 0 ++ 200000 0>; ++ clocks = <&prcmu_clk PRCMU_ARMSS>; ++ clock-names = "cpu"; ++ clock-latency = <20000>; + }; + CPU1: cpu@301 { + device_type = "cpu"; +@@ -494,13 +502,6 @@ prcmu-timer-4@80157450 { + reg = <0x80157450 0xC>; + }; + +- cpufreq { +- compatible = "stericsson,cpufreq-ux500"; +- clocks = <&prcmu_clk PRCMU_ARMSS>; +- clock-names = "armss"; +- status = "disabled"; +- }; +- + thermal@801573c0 { + compatible = "stericsson,db8500-thermal"; + reg = <0x801573c0 0x40>; +diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts +index dcda0bbefe5b..97b1c2321ba9 100644 +--- a/arch/arm/boot/dts/stm32429i-eval.dts ++++ b/arch/arm/boot/dts/stm32429i-eval.dts +@@ -55,7 +55,7 @@ / { + compatible = "st,stm32429i-eval", "st,stm32f429"; + + chosen { +- bootargs = "root=/dev/ram rdinit=/linuxrc"; ++ bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + +diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts +index ae47cde7952f..c66d617e4245 100644 +--- a/arch/arm/boot/dts/stm32f429-disco.dts ++++ b/arch/arm/boot/dts/stm32f429-disco.dts +@@ -54,7 +54,7 @@ / { + compatible = "st,stm32f429i-disco", "st,stm32f429"; + + chosen { +- bootargs = "root=/dev/ram rdinit=/linuxrc"; ++ bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + +diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi +index a8113dc879cf..dd7e99b1f43b 100644 +--- a/arch/arm/boot/dts/stm32f429.dtsi ++++ b/arch/arm/boot/dts/stm32f429.dtsi +@@ -361,6 +361,31 @@ i2c1: i2c@40005400 { + status = "disabled"; + }; + ++ dac: dac@40007400 { ++ compatible = "st,stm32f4-dac-core"; ++ reg = <0x40007400 0x400>; ++ resets = <&rcc STM32F4_APB1_RESET(DAC)>; ++ clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>; ++ clock-names = "pclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ dac1: dac@1 { ++ compatible = "st,stm32-dac"; ++ #io-channels-cells = <1>; ++ reg = <1>; ++ status = "disabled"; ++ }; ++ ++ dac2: dac@2 { ++ compatible = "st,stm32-dac"; ++ #io-channels-cells = <1>; ++ reg = <2>; ++ status = "disabled"; ++ }; ++ }; ++ + usart7: serial@40007800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40007800 0x400>; +diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts +index 75470c34b92c..6ae1f037f3f0 100644 +--- a/arch/arm/boot/dts/stm32f469-disco.dts ++++ b/arch/arm/boot/dts/stm32f469-disco.dts +@@ -53,7 +53,7 @@ / { + compatible = "st,stm32f469i-disco", "st,stm32f469"; + + chosen { +- bootargs = "root=/dev/ram rdinit=/linuxrc"; ++ bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + +diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi +index 4506eb97a4ab..5633860037d2 100644 +--- a/arch/arm/boot/dts/stm32f746.dtsi ++++ b/arch/arm/boot/dts/stm32f746.dtsi +@@ -167,6 +167,15 @@ usart5: serial@40005000 { + status = "disabled"; + }; + ++ cec: cec@40006c00 { ++ compatible = "st,stm32-cec"; ++ reg = <0x40006C00 0x400>; ++ interrupts = <94>; ++ clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; ++ clock-names = "cec", "hdmi-cec"; ++ status = "disabled"; ++ }; ++ + usart7: serial@40007800 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40007800 0x400>; +@@ -336,6 +345,15 @@ gpiok: gpio@40022800 { + st,bank-name = "GPIOK"; + }; + ++ cec_pins_a: cec@0 { ++ pins { ++ pinmux = ; ++ slew-rate = <0>; ++ drive-open-drain; ++ bias-disable; ++ }; ++ }; ++ + usart1_pins_a: usart1@0 { + pins1 { + pinmux = ; +@@ -380,6 +398,39 @@ rcc: rcc@40023800 { + assigned-clocks = <&rcc 1 CLK_HSE_RTC>; + assigned-clock-rates = <1000000>; + }; ++ ++ dma1: dma@40026000 { ++ compatible = "st,stm32-dma"; ++ reg = <0x40026000 0x400>; ++ interrupts = <11>, ++ <12>, ++ <13>, ++ <14>, ++ <15>, ++ <16>, ++ <17>, ++ <47>; ++ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; ++ #dma-cells = <4>; ++ status = "disabled"; ++ }; ++ ++ dma2: dma@40026400 { ++ compatible = "st,stm32-dma"; ++ reg = <0x40026400 0x400>; ++ interrupts = <56>, ++ <57>, ++ <58>, ++ <59>, ++ <60>, ++ <68>, ++ <69>, ++ <70>; ++ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; ++ #dma-cells = <4>; ++ st,mem2mem; ++ status = "disabled"; ++ }; + }; + }; + +diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts +index 166728aeb166..4463ca13a740 100644 +--- a/arch/arm/boot/dts/stm32f769-disco.dts ++++ b/arch/arm/boot/dts/stm32f769-disco.dts +@@ -63,6 +63,12 @@ aliases { + + }; + ++&cec { ++ pinctrl-0 = <&cec_pins_a>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ + &clk_hse { + clock-frequency = <25000000>; + }; +diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi +index 36a99db0a3b4..58ec2275181e 100644 +--- a/arch/arm/boot/dts/stm32h743.dtsi ++++ b/arch/arm/boot/dts/stm32h743.dtsi +@@ -59,6 +59,45 @@ timer_clk: timer-clk { + }; + + soc { ++ timer5: timer@40000c00 { ++ compatible = "st,stm32-timer"; ++ reg = <0x40000c00 0x400>; ++ interrupts = <50>; ++ clocks = <&timer_clk>; ++ }; ++ ++ usart2: serial@40004400 { ++ compatible = "st,stm32f7-usart", "st,stm32f7-uart"; ++ reg = <0x40004400 0x400>; ++ interrupts = <38>; ++ status = "disabled"; ++ clocks = <&timer_clk>; ++ }; ++ ++ dac: dac@40007400 { ++ compatible = "st,stm32h7-dac-core"; ++ reg = <0x40007400 0x400>; ++ clocks = <&timer_clk>; ++ clock-names = "pclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ dac1: dac@1 { ++ compatible = "st,stm32-dac"; ++ #io-channels-cells = <1>; ++ reg = <1>; ++ status = "disabled"; ++ }; ++ ++ dac2: dac@2 { ++ compatible = "st,stm32-dac"; ++ #io-channels-cells = <1>; ++ reg = <2>; ++ status = "disabled"; ++ }; ++ }; ++ + usart1: serial@40011000 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40011000 0x400>; +@@ -68,19 +107,91 @@ usart1: serial@40011000 { + + }; + +- usart2: serial@40004400 { +- compatible = "st,stm32f7-usart", "st,stm32f7-uart"; +- reg = <0x40004400 0x400>; +- interrupts = <38>; ++ dma1: dma@40020000 { ++ compatible = "st,stm32-dma"; ++ reg = <0x40020000 0x400>; ++ interrupts = <11>, ++ <12>, ++ <13>, ++ <14>, ++ <15>, ++ <16>, ++ <17>, ++ <47>; ++ clocks = <&timer_clk>; ++ #dma-cells = <4>; ++ st,mem2mem; + status = "disabled"; ++ }; ++ ++ dma2: dma@40020400 { ++ compatible = "st,stm32-dma"; ++ reg = <0x40020400 0x400>; ++ interrupts = <56>, ++ <57>, ++ <58>, ++ <59>, ++ <60>, ++ <68>, ++ <69>, ++ <70>; + clocks = <&timer_clk>; ++ #dma-cells = <4>; ++ st,mem2mem; ++ status = "disabled"; + }; + +- timer5: timer@40000c00 { +- compatible = "st,stm32-timer"; +- reg = <0x40000c00 0x400>; +- interrupts = <50>; ++ adc_12: adc@40022000 { ++ compatible = "st,stm32h7-adc-core"; ++ reg = <0x40022000 0x400>; ++ interrupts = <18>; ++ clocks = <&timer_clk>; ++ clock-names = "bus"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ adc1: adc@0 { ++ compatible = "st,stm32h7-adc"; ++ #io-channel-cells = <1>; ++ reg = <0x0>; ++ interrupt-parent = <&adc_12>; ++ interrupts = <0>; ++ status = "disabled"; ++ }; ++ ++ adc2: adc@100 { ++ compatible = "st,stm32h7-adc"; ++ #io-channel-cells = <1>; ++ reg = <0x100>; ++ interrupt-parent = <&adc_12>; ++ interrupts = <1>; ++ status = "disabled"; ++ }; ++ }; ++ ++ adc_3: adc@58026000 { ++ compatible = "st,stm32h7-adc-core"; ++ reg = <0x58026000 0x400>; ++ interrupts = <127>; + clocks = <&timer_clk>; ++ clock-names = "bus"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ adc3: adc@0 { ++ compatible = "st,stm32h7-adc"; ++ #io-channel-cells = <1>; ++ reg = <0x0>; ++ interrupt-parent = <&adc_3>; ++ interrupts = <0>; ++ status = "disabled"; ++ }; + }; + }; + }; +diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts +index c6effbb36e4a..6c07786e7ddb 100644 +--- a/arch/arm/boot/dts/stm32h743i-eval.dts ++++ b/arch/arm/boot/dts/stm32h743i-eval.dts +@@ -60,6 +60,24 @@ memory { + aliases { + serial0 = &usart1; + }; ++ ++ vdda: regulator-vdda { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdda"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++}; ++ ++&adc_12 { ++ vref-supply = <&vdda>; ++ status = "okay"; ++ adc1: adc@0 { ++ /* potentiometer */ ++ st,adc-channels = <0>; ++ status = "okay"; ++ }; + }; + + &clk_hse { +diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi +index aebc3f9dc7b6..b147cb0dc14b 100644 +--- a/arch/arm/boot/dts/sun6i-a31.dtsi ++++ b/arch/arm/boot/dts/sun6i-a31.dtsi +@@ -1155,11 +1155,11 @@ rtc: rtc@01f00000 { + ; + }; + +- nmi_intc: interrupt-controller@01f00c0c { +- compatible = "allwinner,sun6i-a31-sc-nmi"; ++ nmi_intc: interrupt-controller@1f00c00 { ++ compatible = "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <2>; +- reg = <0x01f00c0c 0x38>; ++ reg = <0x01f00c00 0x400>; + interrupts = ; + }; + +diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +index bb510187602c..852a0aa24dce 100644 +--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts ++++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +@@ -271,6 +271,10 @@ &ac_power_supply { + status = "okay"; + }; + ++&battery_power_supply { ++ status = "okay"; ++}; ++ + ®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; +diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi +index a8b978d0f35b..ea50dda75adc 100644 +--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi ++++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi +@@ -519,11 +519,11 @@ rtc: rtc@01f00000 { + #clock-cells = <1>; + }; + +- nmi_intc: interrupt-controller@01f00c0c { +- compatible = "allwinner,sun6i-a31-sc-nmi"; ++ nmi_intc: interrupt-controller@1f00c00 { ++ compatible = "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <2>; +- reg = <0x01f00c0c 0x38>; ++ reg = <0x01f00c00 0x400>; + interrupts = ; + }; + +diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +index aecdeeb368ed..1f0d60afb25b 100644 +--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts ++++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +@@ -43,6 +43,7 @@ + + /dts-v1/; + #include "sun8i-a83t.dtsi" ++#include "sunxi-common-regulators.dtsi" + + / { + model = "Allwinner A83T H8Homlet Proto Dev Board v2.0"; +@@ -57,8 +58,92 @@ chosen { + }; + }; + ++&ehci0 { ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_vcc3v0>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ bus-width = <4>; ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_emmc_pins>; ++ vmmc-supply = <®_vcc3v0>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++®_usb0_vbus { ++ gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ ++ status = "okay"; ++}; ++ ++®_usb1_vbus { ++ gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ status = "okay"; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp81x: pmic@3a3 { ++ compatible = "x-powers,axp818", "x-powers,axp813"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ }; ++ ++ ac100: codec@e89 { ++ compatible = "x-powers,ac100"; ++ reg = <0xe89>; ++ ++ ac100_codec: codec { ++ compatible = "x-powers,ac100-codec"; ++ interrupt-parent = <&r_pio>; ++ interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ ++ #clock-cells = <0>; ++ clock-output-names = "4M_adda"; ++ }; ++ ++ ac100_rtc: rtc { ++ compatible = "x-powers,ac100-rtc"; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&ac100_codec>; ++ #clock-cells = <1>; ++ clock-output-names = "cko1_rtc", ++ "cko2_rtc", ++ "cko3_rtc"; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; + }; ++ ++&usbphy { ++ usb0_vbus-supply = <®_usb0_vbus>; ++ usb1_vbus-supply = <®_usb1_vbus>; ++ status = "okay"; ++}; ++ ++&usb_otg { ++ dr_mode = "host"; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +new file mode 100644 +index 000000000000..2bafd7e99ef7 +--- /dev/null ++++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +@@ -0,0 +1,148 @@ ++/* ++ * Copyright 2017 Chen-Yu Tsai ++ * ++ * Chen-Yu Tsai ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun8i-a83t.dtsi" ++#include "sunxi-common-regulators.dtsi" ++ ++#include ++ ++/ { ++ model = "Banana Pi BPI-M3"; ++ compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&ehci0 { ++ /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */ ++ status = "okay"; ++ ++ /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */ ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_emmc_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp81x: pmic@3a3 { ++ compatible = "x-powers,axp813"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ }; ++ ++ ac100: codec@e89 { ++ compatible = "x-powers,ac100"; ++ reg = <0xe89>; ++ ++ ac100_codec: codec { ++ compatible = "x-powers,ac100-codec"; ++ interrupt-parent = <&r_pio>; ++ interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ ++ #clock-cells = <0>; ++ clock-output-names = "4M_adda"; ++ }; ++ ++ ac100_rtc: rtc { ++ compatible = "x-powers,ac100-rtc"; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&ac100_codec>; ++ #clock-cells = <1>; ++ clock-output-names = "cko1_rtc", ++ "cko2_rtc", ++ "cko3_rtc"; ++ }; ++ }; ++}; ++ ++®_usb1_vbus { ++ gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ ++ status = "okay"; ++}; ++ ++®_vcc3v0 { ++ status = "disabled"; ++}; ++ ++®_vcc5v0 { ++ status = "disabled"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pb_pins>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_usb1_vbus>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +index cff33454fc24..716a205c6dbb 100644 +--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts ++++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +@@ -44,6 +44,7 @@ + + /dts-v1/; + #include "sun8i-a83t.dtsi" ++#include "sunxi-common-regulators.dtsi" + + #include + +@@ -83,6 +84,17 @@ green { + }; + }; + ++ usb-hub { ++ /* I2C is not connected */ ++ compatible = "smsc,usb3503"; ++ initial-mode = <1>; /* initialize in HUB mode */ ++ disabled-ports = <1>; ++ intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ ++ reset-gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */ ++ connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ ++ refclk-frequency = <19200000>; ++ }; ++ + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; +@@ -102,6 +114,89 @@ spdif_out: spdif-out { + }; + }; + ++&ehci0 { ++ /* GL830 USB-to-SATA bridge here */ ++ status = "okay"; ++}; ++ ++&ehci1 { ++ /* USB3503 HSIC USB 2.0 hub here */ ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_emmc_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp81x: pmic@3a3 { ++ compatible = "x-powers,axp818", "x-powers,axp813"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ }; ++ ++ ac100: codec@e89 { ++ compatible = "x-powers,ac100"; ++ reg = <0xe89>; ++ ++ ac100_codec: codec { ++ compatible = "x-powers,ac100-codec"; ++ interrupt-parent = <&r_pio>; ++ interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ ++ #clock-cells = <0>; ++ clock-output-names = "4M_adda"; ++ }; ++ ++ ac100_rtc: rtc { ++ compatible = "x-powers,ac100-rtc"; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&ac100_codec>; ++ #clock-cells = <1>; ++ clock-output-names = "cko1_rtc", ++ "cko2_rtc", ++ "cko3_rtc"; ++ }; ++ }; ++}; ++ ++®_usb1_vbus { ++ gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */ ++ status = "okay"; ++}; ++ ++®_usb2_vbus { ++ gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ status = "okay"; ++}; ++ ++®_vcc3v0 { ++ status = "disabled"; ++}; ++ ++®_vcc5v0 { ++ status = "disabled"; ++}; ++ + &spdif { + status = "okay"; + }; +@@ -111,3 +206,9 @@ &uart0 { + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; + }; ++ ++&usbphy { ++ usb1_vbus-supply = <®_usb1_vbus>; ++ usb2_vbus-supply = <®_usb2_vbus>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi +index 19a8f4fcfab5..f996bd343e50 100644 +--- a/arch/arm/boot/dts/sun8i-a83t.dtsi ++++ b/arch/arm/boot/dts/sun8i-a83t.dtsi +@@ -47,6 +47,7 @@ + #include + #include + #include ++#include + + / { + interrupt-parent = <&gic>; +@@ -182,6 +183,141 @@ dma: dma-controller@1c02000 { + #dma-cells = <1>; + }; + ++ mmc0: mmc@1c0f000 { ++ compatible = "allwinner,sun8i-a83t-mmc", ++ "allwinner,sun7i-a20-mmc"; ++ reg = <0x01c0f000 0x1000>; ++ clocks = <&ccu CLK_BUS_MMC0>, ++ <&ccu CLK_MMC0>, ++ <&ccu CLK_MMC0_OUTPUT>, ++ <&ccu CLK_MMC0_SAMPLE>; ++ clock-names = "ahb", ++ "mmc", ++ "output", ++ "sample"; ++ resets = <&ccu RST_BUS_MMC0>; ++ reset-names = "ahb"; ++ interrupts = ; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mmc1: mmc@1c10000 { ++ compatible = "allwinner,sun8i-a83t-mmc", ++ "allwinner,sun7i-a20-mmc"; ++ reg = <0x01c10000 0x1000>; ++ clocks = <&ccu CLK_BUS_MMC1>, ++ <&ccu CLK_MMC1>, ++ <&ccu CLK_MMC1_OUTPUT>, ++ <&ccu CLK_MMC1_SAMPLE>; ++ clock-names = "ahb", ++ "mmc", ++ "output", ++ "sample"; ++ resets = <&ccu RST_BUS_MMC1>; ++ reset-names = "ahb"; ++ interrupts = ; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mmc2: mmc@1c11000 { ++ compatible = "allwinner,sun8i-a83t-emmc"; ++ reg = <0x01c11000 0x1000>; ++ clocks = <&ccu CLK_BUS_MMC2>, ++ <&ccu CLK_MMC2>, ++ <&ccu CLK_MMC2_OUTPUT>, ++ <&ccu CLK_MMC2_SAMPLE>; ++ clock-names = "ahb", ++ "mmc", ++ "output", ++ "sample"; ++ resets = <&ccu RST_BUS_MMC2>; ++ reset-names = "ahb"; ++ interrupts = ; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ usb_otg: usb@01c19000 { ++ compatible = "allwinner,sun8i-a83t-musb", ++ "allwinner,sun8i-a33-musb"; ++ reg = <0x01c19000 0x0400>; ++ clocks = <&ccu CLK_BUS_OTG>; ++ resets = <&ccu RST_BUS_OTG>; ++ interrupts = ; ++ interrupt-names = "mc"; ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ extcon = <&usbphy 0>; ++ status = "disabled"; ++ }; ++ ++ usbphy: phy@1c19400 { ++ compatible = "allwinner,sun8i-a83t-usb-phy"; ++ reg = <0x01c19400 0x10>, ++ <0x01c1a800 0x14>, ++ <0x01c1b800 0x14>; ++ reg-names = "phy_ctrl", ++ "pmu1", ++ "pmu2"; ++ clocks = <&ccu CLK_USB_PHY0>, ++ <&ccu CLK_USB_PHY1>, ++ <&ccu CLK_USB_HSIC>, ++ <&ccu CLK_USB_HSIC_12M>; ++ clock-names = "usb0_phy", ++ "usb1_phy", ++ "usb2_phy", ++ "usb2_hsic_12M"; ++ resets = <&ccu RST_USB_PHY0>, ++ <&ccu RST_USB_PHY1>, ++ <&ccu RST_USB_HSIC>; ++ reset-names = "usb0_reset", ++ "usb1_reset", ++ "usb2_reset"; ++ status = "disabled"; ++ #phy-cells = <1>; ++ }; ++ ++ ehci0: usb@1c1a000 { ++ compatible = "allwinner,sun8i-a83t-ehci", ++ "generic-ehci"; ++ reg = <0x01c1a000 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_EHCI0>; ++ resets = <&ccu RST_BUS_EHCI0>; ++ phys = <&usbphy 1>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci0: usb@1c1a400 { ++ compatible = "allwinner,sun8i-a83t-ohci", ++ "generic-ohci"; ++ reg = <0x01c1a400 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; ++ resets = <&ccu RST_BUS_OHCI0>; ++ phys = <&usbphy 1>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ehci1: usb@1c1b000 { ++ compatible = "allwinner,sun8i-a83t-ehci", ++ "generic-ehci"; ++ reg = <0x01c1b000 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_EHCI1>; ++ resets = <&ccu RST_BUS_EHCI1>; ++ phys = <&usbphy 2>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ + ccu: clock@1c20000 { + compatible = "allwinner,sun8i-a83t-ccu"; + reg = <0x01c20000 0x400>; +@@ -212,6 +348,15 @@ mmc0_pins: mmc0-pins { + bias-pull-up; + }; + ++ mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { ++ pins = "PC5", "PC6", "PC8", "PC9", ++ "PC10", "PC11", "PC12", "PC13", ++ "PC14", "PC15", "PC16"; ++ function = "mmc2"; ++ drive-strength = <30>; ++ bias-pull-up; ++ }; ++ + spdif_tx_pin: spdif-tx-pin { + pins = "PE18"; + function = "spdif"; +@@ -281,6 +426,15 @@ gic: interrupt-controller@1c81000 { + interrupts = ; + }; + ++ r_intc: interrupt-controller@1f00c00 { ++ compatible = "allwinner,sun8i-a83t-r-intc", ++ "allwinner,sun6i-a31-r-intc"; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ reg = <0x01f00c00 0x400>; ++ interrupts = ; ++ }; ++ + r_ccu: clock@1f01400 { + compatible = "allwinner,sun8i-a83t-r-ccu"; + reg = <0x01f01400 0x400>; +@@ -302,6 +456,28 @@ r_pio: pinctrl@1f02c00 { + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; ++ ++ r_rsb_pins: r-rsb-pins { ++ pins = "PL0", "PL1"; ++ function = "s_rsb"; ++ drive-strength = <20>; ++ bias-pull-up; ++ }; ++ }; ++ ++ r_rsb: rsb@1f03400 { ++ compatible = "allwinner,sun8i-a83t-rsb", ++ "allwinner,sun8i-a23-rsb"; ++ reg = <0x01f03400 0x400>; ++ interrupts = ; ++ clocks = <&r_ccu CLK_APB0_RSB>; ++ clock-frequency = <3000000>; ++ resets = <&r_ccu RST_APB0_RSB>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_rsb_pins>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +index e7fae65eb5d3..10da56e86ab8 100644 +--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts ++++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +@@ -100,6 +100,10 @@ spdif_out: spdif-out { + }; + }; + ++&ehci0 { ++ status = "okay"; ++}; ++ + &ehci1 { + status = "okay"; + }; +@@ -147,10 +151,19 @@ &mmc2 { + status = "okay"; + }; + ++&ohci0 { ++ status = "okay"; ++}; ++ + &ohci1 { + status = "okay"; + }; + ++®_usb0_vbus { ++ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ ++ status = "okay"; ++}; ++ + &spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pins_a>; +@@ -163,7 +176,14 @@ &uart0 { + status = "okay"; + }; + ++&usb_otg { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ + &usbphy { +- /* USB VBUS is on as long as VCC-IO is on */ ++ /* USB VBUS is always on except for the OTG port */ + status = "okay"; ++ usb0_id_det-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA07 */ ++ usb0_vbus-supply = <®_usb0_vbus>; + }; +diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts +new file mode 100644 +index 000000000000..eaf09666720d +--- /dev/null ++++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts +@@ -0,0 +1,321 @@ ++/* ++ * Copyright (c) 2017 Free Electrons ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun8i-a33.dtsi" ++ ++#include ++ ++/ { ++ model = "BananaPi M2 Magic"; ++ compatible = "sinovoip,bananapi-m2m", "allwinner,sun8i-a33"; ++ ++ aliases { ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c2 = &i2c2; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ blue { ++ label = "bpi-m2m:blue:usr"; ++ gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ green { ++ label = "bpi-m2m:green:usr"; ++ gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; ++ }; ++ ++ red { ++ label = "bpi-m2m:red:power"; ++ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; ++ default-state = "on"; ++ }; ++ }; ++ ++ reg_vcc5v0: vcc5v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ ++ }; ++}; ++ ++&codec { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_dcdc3>; ++}; ++ ++&cpu0_opp_table { ++ opp@1104000000 { ++ opp-hz = /bits/ 64 <1104000000>; ++ opp-microvolt = <1320000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp@1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1320000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++}; ++ ++&dai { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++/* This is the i2c bus exposed on the DSI connector for the touch panel */ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins_a>; ++ status = "disabled"; ++}; ++ ++/* This is the i2c bus exposed on the GPIO header */ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins_a>; ++ status = "disabled"; ++}; ++ ++/* This is the i2c bus exposed on the CSI connector to control the sensor */ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins_a>; ++ status = "disabled"; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_a>; ++ vmmc-supply = <®_dcdc1>; ++ bus-width = <4>; ++ cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins_a>; ++ vmmc-supply = <®_aldo1>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_dcdc1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp22x: pmic@3a3 { ++ compatible = "x-powers,axp223"; ++ reg = <0x3a3>; ++ interrupt-parent = <&nmi_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ eldoin-supply = <®_dcdc1>; ++ x-powers,drive-vbus-en; ++ }; ++}; ++ ++#include "axp223.dtsi" ++ ++&ac_power_supply { ++ status = "okay"; ++}; ++ ++®_aldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-io"; ++}; ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; ++ regulator-name = "vdd-dll"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "avcc"; ++}; ++ ++®_dc1sw { ++ regulator-name = "vcc-lcd"; ++}; ++ ++®_dc5ldo { ++ regulator-always-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-3v0"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_dcdc3 { ++ regulator-always-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-name = "vdd-cpu"; ++}; ++ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vcc-dram"; ++}; ++ ++/* ++ * Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same ++ * time, with the two being in sync. Since this is not really ++ * supported right now, just use the two as always on, and we will fix ++ * it later. ++ */ ++®_dldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi0"; ++}; ++ ++®_dldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi1"; ++}; ++ ++®_drivevbus { ++ regulator-name = "usb0-vbus"; ++ status = "okay"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; ++ ++&sound { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_b>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins_a>, <&uart1_pins_cts_rts_a>; ++ status = "okay"; ++}; ++ ++&usb_otg { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&usb_power_supply { ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ ++ usb0_vbus_power-supply = <&usb_power_supply>; ++ usb0_vbus-supply = <®_drivevbus>; ++ usb1_vbus-supply = <®_vcc5v0>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts +index 1444fbd543e7..5af4dd321952 100644 +--- a/arch/arm/boot/dts/tegra114-dalmore.dts ++++ b/arch/arm/boot/dts/tegra114-dalmore.dts +@@ -1122,6 +1122,16 @@ sdhci@78000600 { + non-removable; + }; + ++ usb@7d000000 { ++ compatible = "nvidia,tegra114-udc"; ++ status = "okay"; ++ dr_mode = "peripheral"; ++ }; ++ ++ usb-phy@7d000000 { ++ status = "okay"; ++ }; ++ + usb@7d008000 { + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts +index 7bacb2954f58..61873d642a45 100644 +--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts ++++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts +@@ -1722,7 +1722,7 @@ usb2 { + + lanes { + usb2-0 { +- nvidia,function = "xusb"; ++ nvidia,function = "snps"; + status = "okay"; + }; + +@@ -1829,6 +1829,16 @@ i2s@70301100 { + }; + }; + ++ usb@7d000000 { ++ compatible = "nvidia,tegra124-udc"; ++ status = "okay"; ++ dr_mode = "peripheral"; ++ }; ++ ++ usb-phy@7d000000 { ++ status = "okay"; ++ }; ++ + /* mini-PCIe USB */ + usb@7d004000 { + status = "okay"; +diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi +index 1b10b14a6abd..8baf00b89efb 100644 +--- a/arch/arm/boot/dts/tegra124.dtsi ++++ b/arch/arm/boot/dts/tegra124.dtsi +@@ -87,6 +87,7 @@ host1x@50000000 { + clocks = <&tegra_car TEGRA124_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; ++ iommus = <&mc TEGRA_SWGROUP_HC>; + + #address-cells = <2>; + #size-cells = <2>; +diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts +index b4bfa5586c23..bfa9421fcf94 100644 +--- a/arch/arm/boot/dts/tegra20-paz00.dts ++++ b/arch/arm/boot/dts/tegra20-paz00.dts +@@ -452,7 +452,9 @@ pmc@7000e400 { + }; + + usb@c5000000 { ++ compatible = "nvidia,tegra20-udc"; + status = "okay"; ++ dr_mode = "peripheral"; + }; + + usb-phy@c5000000 { +diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts +index 4f41b18d9547..3e104ddeb220 100644 +--- a/arch/arm/boot/dts/tegra30-beaver.dts ++++ b/arch/arm/boot/dts/tegra30-beaver.dts +@@ -1927,6 +1927,16 @@ sdhci@78000600 { + non-removable; + }; + ++ usb@7d000000 { ++ compatible = "nvidia,tegra30-udc"; ++ status = "okay"; ++ dr_mode = "peripheral"; ++ }; ++ ++ usb-phy@7d000000 { ++ status = "okay"; ++ }; ++ + usb@7d004000 { + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi +index 02de56b55823..399baaa0a2ab 100644 +--- a/arch/arm/boot/dts/tps65217.dtsi ++++ b/arch/arm/boot/dts/tps65217.dtsi +@@ -18,11 +18,14 @@ &tps { + + charger { + compatible = "ti,tps65217-charger"; ++ interrupts = <0>, <1>; ++ interrupt-names = "USB", "AC"; + status = "disabled"; + }; + + pwrbutton { + compatible = "ti,tps65217-pwrbutton"; ++ interrupts = <2>; + status = "disabled"; + }; + +diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts +index 4817ebb28eb2..b3aaab354f3e 100644 +--- a/arch/arm/boot/dts/uniphier-ld4-ref.dts ++++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts +@@ -8,9 +8,9 @@ + */ + + /dts-v1/; +-/include/ "uniphier-ld4.dtsi" +-/include/ "uniphier-ref-daughter.dtsi" +-/include/ "uniphier-support-card.dtsi" ++#include "uniphier-ld4.dtsi" ++#include "uniphier-ref-daughter.dtsi" ++#include "uniphier-support-card.dtsi" + + / { + model = "UniPhier LD4 Reference Board"; +@@ -64,3 +64,7 @@ &usb0 { + &usb1 { + status = "okay"; + }; ++ ++&nand { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi +index fb2fd9605b9d..79183db5b386 100644 +--- a/arch/arm/boot/dts/uniphier-ld4.dtsi ++++ b/arch/arm/boot/dts/uniphier-ld4.dtsi +@@ -270,6 +270,13 @@ intc: interrupt-controller@60001000 { + interrupt-controller; + }; + ++ aidet: aidet@61830000 { ++ compatible = "socionext,uniphier-ld4-aidet"; ++ reg = <0x61830000 0x200>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ + sysctrl@61840000 { + compatible = "socionext,uniphier-ld4-sysctrl", + "simple-mfd", "syscon"; +@@ -285,7 +292,18 @@ sys_rst: reset { + #reset-cells = <1>; + }; + }; ++ ++ nand: nand@68000000 { ++ compatible = "socionext,uniphier-denali-nand-v5a"; ++ status = "disabled"; ++ reg-names = "nand_data", "denali_reg"; ++ reg = <0x68000000 0x20>, <0x68100000 0x1000>; ++ interrupts = <0 65 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_nand2cs>; ++ clocks = <&sys_clk 2>; ++ }; + }; + }; + +-/include/ "uniphier-pinctrl.dtsi" ++#include "uniphier-pinctrl.dtsi" +diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts +index 96db4abc02c3..2188d114d79b 100644 +--- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts ++++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts +@@ -8,9 +8,9 @@ + */ + + /dts-v1/; +-/include/ "uniphier-ld6b.dtsi" +-/include/ "uniphier-ref-daughter.dtsi" +-/include/ "uniphier-support-card.dtsi" ++#include "uniphier-ld6b.dtsi" ++#include "uniphier-ref-daughter.dtsi" ++#include "uniphier-support-card.dtsi" + + / { + model = "UniPhier LD6b Reference Board"; +@@ -58,3 +58,7 @@ &serial2 { + &i2c0 { + status = "okay"; + }; ++ ++&nand { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/uniphier-ld6b.dtsi b/arch/arm/boot/dts/uniphier-ld6b.dtsi +index 8b9a79731bd3..9a7b25cc8233 100644 +--- a/arch/arm/boot/dts/uniphier-ld6b.dtsi ++++ b/arch/arm/boot/dts/uniphier-ld6b.dtsi +@@ -12,7 +12,7 @@ + * The D-chip (digital chip) is the same as the PXs2 die. + * Reuse the PXs2 device tree with some properties overridden. + */ +-/include/ "uniphier-pxs2.dtsi" ++#include "uniphier-pxs2.dtsi" + + / { + compatible = "socionext,uniphier-ld6b"; +diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi +index 246f35ffb638..be82cddc4072 100644 +--- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi ++++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi +@@ -4,51 +4,35 @@ + * Copyright (C) 2015-2017 Socionext Inc. + * Author: Masahiro Yamada + * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. ++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + + &pinctrl { ++ pinctrl_aout: aout_grp { ++ groups = "aout"; ++ function = "aout"; ++ }; ++ + pinctrl_emmc: emmc_grp { + groups = "emmc", "emmc_dat8"; + function = "emmc"; + }; + ++ pinctrl_ether_mii: ether_mii_grp { ++ groups = "ether_mii"; ++ function = "ether_mii"; ++ }; ++ ++ pinctrl_ether_rgmii: ether_rgmii_grp { ++ groups = "ether_rgmii"; ++ function = "ether_rgmii"; ++ }; ++ ++ pinctrl_ether_rmii: ether_rmii_grp { ++ groups = "ether_rmii"; ++ function = "ether_rmii"; ++ }; ++ + pinctrl_i2c0: i2c0_grp { + groups = "i2c0"; + function = "i2c0"; +diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts +index 11690b57931c..089419cee273 100644 +--- a/arch/arm/boot/dts/uniphier-pro4-ace.dts ++++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts +@@ -8,7 +8,7 @@ + */ + + /dts-v1/; +-/include/ "uniphier-pro4.dtsi" ++#include "uniphier-pro4.dtsi" + + / { + model = "UniPhier Pro4 Ace Board"; +diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts +index 4cf539245f2e..903df6348e77 100644 +--- a/arch/arm/boot/dts/uniphier-pro4-ref.dts ++++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts +@@ -8,9 +8,9 @@ + */ + + /dts-v1/; +-/include/ "uniphier-pro4.dtsi" +-/include/ "uniphier-ref-daughter.dtsi" +-/include/ "uniphier-support-card.dtsi" ++#include "uniphier-pro4.dtsi" ++#include "uniphier-ref-daughter.dtsi" ++#include "uniphier-support-card.dtsi" + + / { + model = "UniPhier Pro4 Reference Board"; +@@ -66,3 +66,7 @@ &usb2 { + &usb3 { + status = "okay"; + }; ++ ++&nand { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-pro4-sanji.dts +index 2763cebcd76a..adef212b45b2 100644 +--- a/arch/arm/boot/dts/uniphier-pro4-sanji.dts ++++ b/arch/arm/boot/dts/uniphier-pro4-sanji.dts +@@ -8,7 +8,7 @@ + */ + + /dts-v1/; +-/include/ "uniphier-pro4.dtsi" ++#include "uniphier-pro4.dtsi" + + / { + model = "UniPhier Pro4 Sanji Board"; +diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi +index 37400becf4ba..b3dbbd9b6e39 100644 +--- a/arch/arm/boot/dts/uniphier-pro4.dtsi ++++ b/arch/arm/boot/dts/uniphier-pro4.dtsi +@@ -268,6 +268,13 @@ pinctrl: pinctrl { + }; + }; + ++ aidet: aidet@5fc20000 { ++ compatible = "socionext,uniphier-pro4-aidet"; ++ reg = <0x5fc20000 0x200>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; +@@ -305,7 +312,18 @@ sys_rst: reset { + #reset-cells = <1>; + }; + }; ++ ++ nand: nand@68000000 { ++ compatible = "socionext,uniphier-denali-nand-v5a"; ++ status = "disabled"; ++ reg-names = "nand_data", "denali_reg"; ++ reg = <0x68000000 0x20>, <0x68100000 0x1000>; ++ interrupts = <0 65 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_nand>; ++ clocks = <&sys_clk 2>; ++ }; + }; + }; + +-/include/ "uniphier-pinctrl.dtsi" ++#include "uniphier-pinctrl.dtsi" +diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi +index 9577769a0add..b026bcd42a06 100644 +--- a/arch/arm/boot/dts/uniphier-pro5.dtsi ++++ b/arch/arm/boot/dts/uniphier-pro5.dtsi +@@ -4,43 +4,7 @@ + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. ++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + + / { +@@ -328,7 +292,7 @@ smpctrl@59801000 { + sdctrl@59810000 { + compatible = "socionext,uniphier-pro5-sdctrl", + "simple-mfd", "syscon"; +- reg = <0x59810000 0x800>; ++ reg = <0x59810000 0x400>; + + sd_clk: clock { + compatible = "socionext,uniphier-pro5-sd-clock"; +@@ -367,6 +331,13 @@ pinctrl: pinctrl { + }; + }; + ++ aidet: aidet@5fc20000 { ++ compatible = "socionext,uniphier-pro5-aidet"; ++ reg = <0x5fc20000 0x200>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; +@@ -404,7 +375,18 @@ sys_rst: reset { + #reset-cells = <1>; + }; + }; ++ ++ nand: nand@68000000 { ++ compatible = "socionext,uniphier-denali-nand-v5b"; ++ status = "disabled"; ++ reg-names = "nand_data", "denali_reg"; ++ reg = <0x68000000 0x20>, <0x68100000 0x1000>; ++ interrupts = <0 65 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_nand2cs>; ++ clocks = <&sys_clk 2>; ++ }; + }; + }; + +-/include/ "uniphier-pinctrl.dtsi" ++#include "uniphier-pinctrl.dtsi" +diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts +index 81560f75bfa7..7dfae2667f50 100644 +--- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts ++++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts +@@ -8,7 +8,7 @@ + */ + + /dts-v1/; +-/include/ "uniphier-pxs2.dtsi" ++#include "uniphier-pxs2.dtsi" + + / { + model = "UniPhier PXs2 Gentil Board"; +diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts +index dc2d0579c666..0cf615463a82 100644 +--- a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts ++++ b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts +@@ -8,7 +8,7 @@ + */ + + /dts-v1/; +-/include/ "uniphier-pxs2.dtsi" ++#include "uniphier-pxs2.dtsi" + + / { + model = "UniPhier PXs2 Vodka Board"; +diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi +index bace751d4023..90b020c95083 100644 +--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi ++++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi +@@ -276,7 +276,7 @@ smpctrl@59801000 { + sdctrl@59810000 { + compatible = "socionext,uniphier-pxs2-sdctrl", + "simple-mfd", "syscon"; +- reg = <0x59810000 0x800>; ++ reg = <0x59810000 0x400>; + + sd_clk: clock { + compatible = "socionext,uniphier-pxs2-sd-clock"; +@@ -315,6 +315,13 @@ pinctrl: pinctrl { + }; + }; + ++ aidet: aidet@5fc20000 { ++ compatible = "socionext,uniphier-pxs2-aidet"; ++ reg = <0x5fc20000 0x200>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; +@@ -352,7 +359,18 @@ sys_rst: reset { + #reset-cells = <1>; + }; + }; ++ ++ nand: nand@68000000 { ++ compatible = "socionext,uniphier-denali-nand-v5b"; ++ status = "disabled"; ++ reg-names = "nand_data", "denali_reg"; ++ reg = <0x68000000 0x20>, <0x68100000 0x1000>; ++ interrupts = <0 65 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_nand2cs>; ++ clocks = <&sys_clk 2>; ++ }; + }; + }; + +-/include/ "uniphier-pinctrl.dtsi" ++#include "uniphier-pinctrl.dtsi" +diff --git a/arch/arm/boot/dts/uniphier-sld3-ref.dts b/arch/arm/boot/dts/uniphier-sld3-ref.dts +deleted file mode 100644 +index 70cda39a3dd2..000000000000 +--- a/arch/arm/boot/dts/uniphier-sld3-ref.dts ++++ /dev/null +@@ -1,75 +0,0 @@ +-/* +- * Device Tree Source for UniPhier sLD3 Reference Board +- * +- * Copyright (C) 2015-2016 Socionext Inc. +- * Author: Masahiro Yamada +- * +- * SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- */ +- +-/dts-v1/; +-/include/ "uniphier-sld3.dtsi" +-/include/ "uniphier-ref-daughter.dtsi" +-/include/ "uniphier-support-card.dtsi" +- +-/ { +- model = "UniPhier sLD3 Reference Board"; +- compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- serial2 = &serial2; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2c2 = &i2c2; +- i2c3 = &i2c3; +- i2c4 = &i2c4; +- }; +- +- memory@8000000 { +- device_type = "memory"; +- reg = <0x80000000 0x20000000 +- 0xc0000000 0x20000000>; +- }; +-}; +- +-ðsc { +- interrupts = <0 49 4>; +-}; +- +-&serial0 { +- status = "okay"; +-}; +- +-&serial1 { +- status = "okay"; +-}; +- +-&serial2 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&usb0 { +- status = "okay"; +-}; +- +-&usb1 { +- status = "okay"; +-}; +- +-&usb2 { +- status = "okay"; +-}; +- +-&usb3 { +- status = "okay"; +-}; +diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi +deleted file mode 100644 +index 408287936613..000000000000 +--- a/arch/arm/boot/dts/uniphier-sld3.dtsi ++++ /dev/null +@@ -1,260 +0,0 @@ +-/* +- * Device Tree Source for UniPhier sLD3 SoC +- * +- * Copyright (C) 2015-2016 Socionext Inc. +- * Author: Masahiro Yamada +- * +- * SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- */ +- +-/ { +- compatible = "socionext,uniphier-sld3"; +- #address-cells = <1>; +- #size-cells = <1>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <0>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- }; +- +- cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a9"; +- reg = <1>; +- enable-method = "psci"; +- next-level-cache = <&l2>; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2"; +- method = "smc"; +- }; +- +- clocks { +- refclk: ref { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24576000>; +- }; +- +- arm_timer_clk: arm_timer_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <50000000>; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- interrupt-parent = <&intc>; +- +- timer@20000200 { +- compatible = "arm,cortex-a9-global-timer"; +- reg = <0x20000200 0x20>; +- interrupts = <1 11 0x304>; +- clocks = <&arm_timer_clk>; +- }; +- +- timer@20000600 { +- compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x20000600 0x20>; +- interrupts = <1 13 0x304>; +- clocks = <&arm_timer_clk>; +- }; +- +- intc: interrupt-controller@20001000 { +- compatible = "arm,cortex-a9-gic"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x20001000 0x1000>, +- <0x20000100 0x100>; +- }; +- +- l2: l2-cache@500c0000 { +- compatible = "socionext,uniphier-system-cache"; +- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, +- <0x506c0000 0x400>; +- interrupts = <0 174 4>, <0 175 4>; +- cache-unified; +- cache-size = <(512 * 1024)>; +- cache-sets = <256>; +- cache-line-size = <128>; +- cache-level = <2>; +- }; +- +- serial0: serial@54006800 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006800 0x40>; +- interrupts = <0 33 4>; +- clocks = <&sys_clk 0>; +- }; +- +- serial1: serial@54006900 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006900 0x40>; +- interrupts = <0 35 4>; +- clocks = <&sys_clk 0>; +- }; +- +- serial2: serial@54006a00 { +- compatible = "socionext,uniphier-uart"; +- status = "disabled"; +- reg = <0x54006a00 0x40>; +- interrupts = <0 37 4>; +- clocks = <&sys_clk 0>; +- }; +- +- i2c0: i2c@58400000 { +- compatible = "socionext,uniphier-i2c"; +- status = "disabled"; +- reg = <0x58400000 0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 41 1>; +- clocks = <&sys_clk 1>; +- clock-frequency = <100000>; +- }; +- +- i2c1: i2c@58480000 { +- compatible = "socionext,uniphier-i2c"; +- status = "disabled"; +- reg = <0x58480000 0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 42 1>; +- clocks = <&sys_clk 1>; +- clock-frequency = <100000>; +- }; +- +- i2c2: i2c@58500000 { +- compatible = "socionext,uniphier-i2c"; +- status = "disabled"; +- reg = <0x58500000 0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 43 1>; +- clocks = <&sys_clk 1>; +- clock-frequency = <100000>; +- }; +- +- i2c3: i2c@58580000 { +- compatible = "socionext,uniphier-i2c"; +- status = "disabled"; +- reg = <0x58580000 0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 44 1>; +- clocks = <&sys_clk 1>; +- clock-frequency = <100000>; +- }; +- +- /* chip-internal connection for DMD */ +- i2c4: i2c@58600000 { +- compatible = "socionext,uniphier-i2c"; +- reg = <0x58600000 0x40>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = <0 45 1>; +- clocks = <&sys_clk 1>; +- clock-frequency = <400000>; +- }; +- +- system_bus: system-bus@58c00000 { +- compatible = "socionext,uniphier-system-bus"; +- status = "disabled"; +- reg = <0x58c00000 0x400>; +- #address-cells = <2>; +- #size-cells = <1>; +- }; +- +- smpctrl@59801000 { +- compatible = "socionext,uniphier-smpctrl"; +- reg = <0x59801000 0x400>; +- }; +- +- mioctrl@59810000 { +- compatible = "socionext,uniphier-sld3-mioctrl", +- "simple-mfd", "syscon"; +- reg = <0x59810000 0x800>; +- +- mio_clk: clock { +- compatible = "socionext,uniphier-sld3-mio-clock"; +- #clock-cells = <1>; +- }; +- +- mio_rst: reset { +- compatible = "socionext,uniphier-sld3-mio-reset"; +- #reset-cells = <1>; +- }; +- }; +- +- usb0: usb@5a800100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a800100 0x100>; +- interrupts = <0 80 4>; +- clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, +- <&mio_rst 12>; +- }; +- +- usb1: usb@5a810100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a810100 0x100>; +- interrupts = <0 81 4>; +- clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, +- <&mio_rst 13>; +- }; +- +- usb2: usb@5a820100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a820100 0x100>; +- interrupts = <0 82 4>; +- clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, +- <&mio_rst 14>; +- }; +- +- usb3: usb@5a830100 { +- compatible = "socionext,uniphier-ehci", "generic-ehci"; +- status = "disabled"; +- reg = <0x5a830100 0x100>; +- interrupts = <0 83 4>; +- clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>; +- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>, +- <&mio_rst 15>; +- }; +- +- sysctrl@f1840000 { +- compatible = "socionext,uniphier-sld3-sysctrl", +- "simple-mfd", "syscon"; +- reg = <0xf1840000 0x10000>; +- +- sys_clk: clock { +- compatible = "socionext,uniphier-sld3-clock"; +- #clock-cells = <1>; +- }; +- +- sys_rst: reset { +- compatible = "socionext,uniphier-sld3-reset"; +- #reset-cells = <1>; +- }; +- }; +- }; +-}; +diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts +index 4536d5b71297..5accd3cc76e4 100644 +--- a/arch/arm/boot/dts/uniphier-sld8-ref.dts ++++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts +@@ -8,9 +8,9 @@ + */ + + /dts-v1/; +-/include/ "uniphier-sld8.dtsi" +-/include/ "uniphier-ref-daughter.dtsi" +-/include/ "uniphier-support-card.dtsi" ++#include "uniphier-sld8.dtsi" ++#include "uniphier-ref-daughter.dtsi" ++#include "uniphier-support-card.dtsi" + + / { + model = "UniPhier sLD8 Reference Board"; +@@ -68,3 +68,7 @@ &usb1 { + &usb2 { + status = "okay"; + }; ++ ++&nand { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi +index 9fb9167f2db4..b08390332971 100644 +--- a/arch/arm/boot/dts/uniphier-sld8.dtsi ++++ b/arch/arm/boot/dts/uniphier-sld8.dtsi +@@ -270,6 +270,13 @@ intc: interrupt-controller@60001000 { + interrupt-controller; + }; + ++ aidet: aidet@61830000 { ++ compatible = "socionext,uniphier-sld8-aidet"; ++ reg = <0x61830000 0x200>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ + sysctrl@61840000 { + compatible = "socionext,uniphier-sld8-sysctrl", + "simple-mfd", "syscon"; +@@ -285,7 +292,18 @@ sys_rst: reset { + #reset-cells = <1>; + }; + }; ++ ++ nand: nand@68000000 { ++ compatible = "socionext,uniphier-denali-nand-v5a"; ++ status = "disabled"; ++ reg-names = "nand_data", "denali_reg"; ++ reg = <0x68000000 0x20>, <0x68100000 0x1000>; ++ interrupts = <0 65 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_nand2cs>; ++ clocks = <&sys_clk 2>; ++ }; + }; + }; + +-/include/ "uniphier-pinctrl.dtsi" ++#include "uniphier-pinctrl.dtsi" +diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts +index 06e2331f666d..9abe26028c8b 100644 +--- a/arch/arm/boot/dts/versatile-pb.dts ++++ b/arch/arm/boot/dts/versatile-pb.dts +@@ -39,7 +39,7 @@ gpio3: gpio@101e7000 { + clock-names = "apb_pclk"; + }; + +- pci-controller@10001000 { ++ pci@10001000 { + compatible = "arm,versatile-pci"; + device_type = "pci"; + reg = <0x10001000 0x1000 +diff --git a/arch/arm/boot/dts/zx296702-ad1.dts b/arch/arm/boot/dts/zx296702-ad1.dts +index 081f980cfbe6..b0183c3a1d7c 100644 +--- a/arch/arm/boot/dts/zx296702-ad1.dts ++++ b/arch/arm/boot/dts/zx296702-ad1.dts +@@ -18,7 +18,6 @@ memory { + }; + + &mmc0 { +- num-slots = <1>; + supports-highspeed; + non-removable; + disable-wp; +@@ -31,7 +30,6 @@ slot@0 { + }; + + &mmc1 { +- num-slots = <1>; + supports-highspeed; + non-removable; + disable-wp; +diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi +index f3ac9bfe580e..0f79fe1ccd9d 100644 +--- a/arch/arm/boot/dts/zynq-7000.dtsi ++++ b/arch/arm/boot/dts/zynq-7000.dtsi +@@ -42,6 +42,14 @@ cpu1: cpu@1 { + }; + }; + ++ fpga_full: fpga-full { ++ compatible = "fpga-region"; ++ fpga-mgr = <&devcfg>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ + pmu@f8891000 { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 5 4>, <0 6 4>; +diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts +index 64a6390fc501..0144acfa9793 100644 +--- a/arch/arm/boot/dts/zynq-parallella.dts ++++ b/arch/arm/boot/dts/zynq-parallella.dts +@@ -34,7 +34,7 @@ memory@0 { + }; + + chosen { +- bootargs = "earlycon root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait"; ++ bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait"; + stdout-path = "serial0:115200n8"; + }; + }; +@@ -54,6 +54,7 @@ ethernet_phy: ethernet-phy@0 { + compatible = "ethernet-phy-id0141.0e90", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; ++ device_type = "ethernet-phy"; + marvell,reg-init = <0x3 0x10 0xff00 0x1e>, + <0x3 0x11 0xfff0 0xa>; + }; +diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts +index 0cdad2cc8b78..34e8277fce0d 100644 +--- a/arch/arm/boot/dts/zynq-zc702.dts ++++ b/arch/arm/boot/dts/zynq-zc702.dts +@@ -12,7 +12,7 @@ + * GNU General Public License for more details. + */ + /dts-v1/; +-/include/ "zynq-7000.dtsi" ++#include "zynq-7000.dtsi" + + / { + model = "Zynq ZC702 Development Board"; +@@ -30,7 +30,7 @@ memory@0 { + }; + + chosen { +- bootargs = "earlycon"; ++ bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + +@@ -97,6 +97,7 @@ &gem0 { + + ethernet_phy: ethernet-phy@7 { + reg = <7>; ++ device_type = "ethernet-phy"; + }; + }; + +@@ -131,6 +132,21 @@ si570: clock-generator@5d { + }; + }; + ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ adv7511: hdmi-tx@39 { ++ compatible = "adi,adv7511"; ++ reg = <0x39>; ++ adi,input-depth = <8>; ++ adi,input-colorspace = "yuv422"; ++ adi,input-clock = "1x"; ++ adi,input-style = <3>; ++ adi,input-justification = "right"; ++ }; ++ }; ++ + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; +diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts +index ad4bb06dba25..7ebc8c5ae39d 100644 +--- a/arch/arm/boot/dts/zynq-zc706.dts ++++ b/arch/arm/boot/dts/zynq-zc706.dts +@@ -12,7 +12,7 @@ + * GNU General Public License for more details. + */ + /dts-v1/; +-/include/ "zynq-7000.dtsi" ++#include "zynq-7000.dtsi" + + / { + model = "Zynq ZC706 Development Board"; +@@ -30,7 +30,7 @@ memory@0 { + }; + + chosen { +- bootargs = "earlycon"; ++ bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + +@@ -53,6 +53,7 @@ &gem0 { + + ethernet_phy: ethernet-phy@7 { + reg = <7>; ++ device_type = "ethernet-phy"; + }; + }; + +@@ -87,6 +88,21 @@ si570: clock-generator@5d { + }; + }; + ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ adv7511: hdmi-tx@39 { ++ compatible = "adi,adv7511"; ++ reg = <0x39>; ++ adi,input-depth = <8>; ++ adi,input-colorspace = "yuv422"; ++ adi,input-clock = "1x"; ++ adi,input-style = <3>; ++ adi,input-justification = "evenly"; ++ }; ++ }; ++ + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; +diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts +index 325379f7983c..5e44dc12fd60 100644 +--- a/arch/arm/boot/dts/zynq-zed.dts ++++ b/arch/arm/boot/dts/zynq-zed.dts +@@ -12,7 +12,7 @@ + * GNU General Public License for more details. + */ + /dts-v1/; +-/include/ "zynq-7000.dtsi" ++#include "zynq-7000.dtsi" + + / { + model = "Zynq Zed Development Board"; +@@ -29,7 +29,7 @@ memory@0 { + }; + + chosen { +- bootargs = "earlycon"; ++ bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + +@@ -50,6 +50,7 @@ &gem0 { + + ethernet_phy: ethernet-phy@0 { + reg = <0>; ++ device_type = "ethernet-phy"; + }; + }; + +diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts +index 590ec24b8749..e40cafc5ee5b 100644 +--- a/arch/arm/boot/dts/zynq-zybo.dts ++++ b/arch/arm/boot/dts/zynq-zybo.dts +@@ -12,7 +12,7 @@ + * GNU General Public License for more details. + */ + /dts-v1/; +-/include/ "zynq-7000.dtsi" ++#include "zynq-7000.dtsi" + + / { + model = "Zynq ZYBO Development Board"; +@@ -29,7 +29,7 @@ memory@0 { + }; + + chosen { +- bootargs = "earlycon"; ++ bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + +@@ -51,6 +51,7 @@ &gem0 { + + ethernet_phy: ethernet-phy@0 { + reg = <0>; ++ device_type = "ethernet-phy"; + }; + }; + +diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms +index b65a7e876a26..6b54ee8c1262 100644 +--- a/arch/arm64/Kconfig.platforms ++++ b/arch/arm64/Kconfig.platforms +@@ -184,6 +184,12 @@ config ARCH_R8A7796 + help + This enables support for the Renesas R-Car M3-W SoC. + ++config ARCH_R8A77995 ++ bool "Renesas R-Car D3 SoC Platform" ++ depends on ARCH_RENESAS ++ help ++ This enables support for the Renesas R-Car D3 SoC. ++ + config ARCH_STRATIX10 + bool "Altera's Stratix 10 SoCFPGA Family" + help +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index 108f12ce6d1d..19c3fbd75eda 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -1,4 +1,6 @@ + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb +diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi +new file mode 100644 +index 000000000000..ff8af52743ff +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi +@@ -0,0 +1,150 @@ ++/* ++ * Copyright 2017 Icenowy Zheng ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/* ++ * AXP803 Integrated Power Management Chip ++ * http://files.pine64.org/doc/datasheet/pine64/AXP803_Datasheet_V1.0.pdf ++ */ ++ ++&axp803 { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ ++ regulators { ++ /* Default work frequency for buck regulators */ ++ x-powers,dcdc-freq = <3000>; ++ ++ reg_aldo1: aldo1 { ++ regulator-name = "aldo1"; ++ }; ++ ++ reg_aldo2: aldo2 { ++ regulator-name = "aldo2"; ++ }; ++ ++ reg_aldo3: aldo3 { ++ regulator-name = "aldo3"; ++ }; ++ ++ reg_dc1sw: dc1sw { ++ regulator-name = "dc1sw"; ++ }; ++ ++ reg_dcdc1: dcdc1 { ++ regulator-name = "dcdc1"; ++ }; ++ ++ reg_dcdc2: dcdc2 { ++ regulator-name = "dcdc2"; ++ }; ++ ++ reg_dcdc3: dcdc3 { ++ regulator-name = "dcdc3"; ++ }; ++ ++ reg_dcdc4: dcdc4 { ++ regulator-name = "dcdc4"; ++ }; ++ ++ reg_dcdc5: dcdc5 { ++ regulator-name = "dcdc5"; ++ }; ++ ++ reg_dcdc6: dcdc6 { ++ regulator-name = "dcdc6"; ++ }; ++ ++ reg_dldo1: dldo1 { ++ regulator-name = "dldo1"; ++ }; ++ ++ reg_dldo2: dldo2 { ++ regulator-name = "dldo2"; ++ }; ++ ++ reg_dldo3: dldo3 { ++ regulator-name = "dldo3"; ++ }; ++ ++ reg_dldo4: dldo4 { ++ regulator-name = "dldo4"; ++ }; ++ ++ reg_eldo1: eldo1 { ++ regulator-name = "eldo1"; ++ }; ++ ++ reg_eldo2: eldo2 { ++ regulator-name = "eldo2"; ++ }; ++ ++ reg_eldo3: eldo3 { ++ regulator-name = "eldo3"; ++ }; ++ ++ reg_fldo1: fldo1 { ++ regulator-name = "fldo1"; ++ }; ++ ++ reg_fldo2: fldo2 { ++ regulator-name = "fldo2"; ++ }; ++ ++ reg_ldo_io0: ldo-io0 { ++ regulator-name = "ldo-io0"; ++ status = "disabled"; ++ }; ++ ++ reg_ldo_io1: ldo-io1 { ++ regulator-name = "ldo-io1"; ++ status = "disabled"; ++ }; ++ ++ reg_rtc_ldo: rtc-ldo { ++ /* RTC_LDO is a fixed, always-on regulator */ ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "rtc-ldo"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +index 6872135d7f84..d347f52e27f6 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +@@ -59,14 +59,16 @@ chosen { + stdout-path = "serial0:115200n8"; + }; + +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + }; + }; + ++&ehci1 { ++ status = "okay"; ++}; ++ + &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +@@ -80,7 +82,7 @@ &i2c1_pins { + &mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; +- vmmc-supply = <®_vcc3v3>; ++ vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + cd-inverted; + disable-wp; +@@ -91,22 +93,143 @@ &mmc0 { + &mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <®_vcc3v3>; ++ vmmc-supply = <®_dldo2>; ++ vqmmc-supply = <®_dldo4>; ++ mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; ++ ++ brcmf: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&r_pio>; ++ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ ++ interrupt-names = "host-wake"; ++ }; + }; + + &mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; +- vmmc-supply = <®_vcc3v3>; ++ vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; + }; + ++&ohci1 { ++ status = "okay"; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp803: pmic@3a3 { ++ compatible = "x-powers,axp803"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++#include "axp803.dtsi" ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-pll-avcc"; ++}; ++ ++®_dc1sw { ++ regulator-name = "vcc-phy"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-3v3"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1040000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-name = "vdd-cpux"; ++}; ++ ++/* DCDC3 is polyphased with DCDC2 */ ++ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vcc-dram"; ++}; ++ ++®_dcdc6 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_dldo1 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-hdmi-dsi"; ++}; ++ ++®_dldo2 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi"; ++}; ++ ++®_dldo4 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi-io"; ++}; ++ ++®_eldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "cpvdd"; ++}; ++ ++®_fldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-1v2-hsic"; ++}; ++ ++/* ++ * The A64 chip cannot work without this regulator off, although ++ * it seems to be only driving the AR100 core. ++ * Maybe we don't still know well about CPUs domain. ++ */ ++®_fldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; +@@ -118,3 +241,7 @@ &uart1 { + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + status = "okay"; + }; ++ ++&usbphy { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +new file mode 100644 +index 000000000000..2beef9e6cb88 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +@@ -0,0 +1,207 @@ ++/* ++ * Copyright (C) 2017 Jagan Teki ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64.dtsi" ++ ++#include ++ ++/ { ++ model = "FriendlyARM NanoPi A64"; ++ compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++/* i2c1 connected with gpio headers like pine64, bananapi */ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "disabled"; ++}; ++ ++&i2c1_pins { ++ bias-pull-up; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_dcdc1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; ++ cd-inverted; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp803: pmic@3a3 { ++ compatible = "x-powers,axp803"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++#include "axp803.dtsi" ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-pll-avcc"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-3v"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1040000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-name = "vdd-cpux"; ++}; ++ ++/* DCDC3 is polyphased with DCDC2 */ ++ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vcc-dram"; ++}; ++ ++®_dcdc6 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_dldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-hdmi-dsi"; ++}; ++ ++®_dldo4 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-pg-wifi-io"; ++}; ++ ++®_eldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "cpvdd"; ++}; ++ ++®_fldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-1v2-hsic"; ++}; ++ ++/* ++ * The A64 chip cannot work without this regulator off, although ++ * it seems to be only driving the AR100 core. ++ * Maybe we don't still know well about CPUs domain. ++ */ ++®_fldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +new file mode 100644 +index 000000000000..338e786155b1 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +@@ -0,0 +1,199 @@ ++/* ++ * Copyright (C) 2017 Jagan Teki ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64.dtsi" ++ ++#include ++ ++/ { ++ model = "Olimex A64-Olinuxino"; ++ compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_dcdc1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; ++ cd-inverted; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp803: pmic@3a3 { ++ compatible = "x-powers,axp803"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++#include "axp803.dtsi" ++ ++®_aldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "vcc-pe"; ++}; ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-pll-avcc"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-3v3"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1040000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-name = "vdd-cpux"; ++}; ++ ++/* DCDC3 is polyphased with DCDC2 */ ++ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vcc-ddr3"; ++}; ++ ++®_dcdc6 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_dldo1 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-hdmi"; ++}; ++ ++®_dldo2 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-mipi"; ++}; ++ ++®_dldo3 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "vcc-avdd-csi"; ++}; ++ ++®_dldo4 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi-io"; ++}; ++ ++®_eldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "cpvdd"; ++}; ++ ++®_eldo2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-dvdd-csi"; ++}; ++ ++®_fldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-1v2-hsic"; ++}; ++ ++/* ++ * The A64 chip cannot work without this regulator off, although ++ * it seems to be only driving the AR100 core. ++ * Maybe we don't still know well about CPUs domain. ++ */ ++®_fldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +index 7c533b6d4ba9..caf8b6fbe5e3 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +@@ -107,6 +107,118 @@ &ohci1 { + status = "okay"; + }; + ++&r_rsb { ++ status = "okay"; ++ ++ axp803: pmic@3a3 { ++ compatible = "x-powers,axp803"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++#include "axp803.dtsi" ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-pll-avcc"; ++}; ++ ++®_dc1sw { ++ regulator-name = "vcc-phy"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-3v3"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1040000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-name = "vdd-cpux"; ++}; ++ ++/* DCDC3 is polyphased with DCDC2 */ ++ ++/* ++ * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can ++ * work at 1.35V with less power consumption. ++ * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead. ++ */ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1360000>; ++ regulator-max-microvolt = <1360000>; ++ regulator-name = "vcc-dram"; ++}; ++ ++®_dcdc6 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_dldo1 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-hdmi"; ++}; ++ ++®_dldo2 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-mipi"; ++}; ++ ++®_dldo4 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi"; ++}; ++ ++®_eldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "cpvdd"; ++}; ++ ++®_fldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-1v2-hsic"; ++}; ++ ++/* ++ * The A64 chip cannot work without this regulator off, although ++ * it seems to be only driving the AR100 core. ++ * Maybe we don't still know well about CPUs domain. ++ */ ++®_fldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; ++ + /* On Exp and Euler connectors */ + &uart0 { + pinctrl-names = "default"; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +index d891a1a27f6c..17ccc12b58df 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +@@ -95,6 +95,28 @@ &ohci1 { + status = "okay"; + }; + ++®_dc1sw { ++ regulator-name = "vcc-phy"; ++}; ++ ++®_dldo1 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-hdmi"; ++}; ++ ++®_dldo2 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-mipi"; ++}; ++ ++®_dldo4 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +index 475518b031dd..a5da18a6f286 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +@@ -63,3 +63,89 @@ &mmc0 { + bus-width = <4>; + status = "okay"; + }; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp803: pmic@3a3 { ++ compatible = "x-powers,axp803"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++#include "axp803.dtsi" ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-pll-avcc"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-3v3"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1040000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-name = "vdd-cpux"; ++}; ++ ++/* DCDC3 is polyphased with DCDC2 */ ++ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-dram"; ++}; ++ ++®_dcdc6 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_eldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vdd-1v8-lpddr"; ++}; ++ ++®_fldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-1v2-hsic"; ++}; ++ ++/* ++ * The A64 chip cannot work without this regulator off, although ++ * it seems to be only driving the AR100 core. ++ * Maybe we don't still know well about CPUs domain. ++ */ ++®_fldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 68aadc9b96dc..8c8db1b057df 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -467,6 +467,15 @@ rtc: rtc@1f00000 { + ; + }; + ++ r_intc: interrupt-controller@1f00c00 { ++ compatible = "allwinner,sun50i-a64-r-intc", ++ "allwinner,sun6i-a31-r-intc"; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ reg = <0x01f00c00 0x400>; ++ interrupts = ; ++ }; ++ + r_ccu: clock@1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi +index dc478d094c11..c89010e56488 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi +@@ -121,6 +121,13 @@ hdmi_connector_in: endpoint { + }; + }; + ++&cec_AO { ++ status = "okay"; ++ pinctrl-0 = <&ao_cec_pins>; ++ pinctrl-names = "default"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ + &cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +index 738ed689ff69..f175db846286 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +@@ -225,7 +225,7 @@ reset: reset-controller@4404 { + }; + + uart_A: serial@84c0 { +- compatible = "amlogic,meson-uart"; ++ compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; + reg = <0x0 0x84c0 0x0 0x14>; + interrupts = ; + clocks = <&xtal>; +@@ -233,7 +233,7 @@ uart_A: serial@84c0 { + }; + + uart_B: serial@84dc { +- compatible = "amlogic,meson-uart"; ++ compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; + reg = <0x0 0x84dc 0x0 0x14>; + interrupts = ; + clocks = <&xtal>; +@@ -279,7 +279,7 @@ pwm_ef: pwm@86c0 { + }; + + uart_C: serial@8700 { +- compatible = "amlogic,meson-uart"; ++ compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; + reg = <0x0 0x8700 0x0 0x14>; + interrupts = ; + clocks = <&xtal>; +@@ -367,26 +367,40 @@ aobus: aobus@c8100000 { + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; + +- clkc_AO: clock-controller@040 { +- compatible = "amlogic,gx-aoclkc", "amlogic,gxbb-aoclkc"; +- reg = <0x0 0x00040 0x0 0x4>; +- #clock-cells = <1>; +- #reset-cells = <1>; ++ sysctrl_AO: sys-ctrl@0 { ++ compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; ++ reg = <0x0 0x0 0x0 0x100>; ++ ++ clkc_AO: clock-controller { ++ compatible = "amlogic,meson-gx-aoclkc"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ }; ++ ++ cec_AO: cec@100 { ++ compatible = "amlogic,meson-gx-ao-cec"; ++ reg = <0x0 0x00100 0x0 0x14>; ++ interrupts = ; ++ }; ++ ++ sec_AO: ao-secure@140 { ++ compatible = "amlogic,meson-gx-ao-secure", "syscon"; ++ reg = <0x0 0x140 0x0 0x140>; ++ amlogic,has-chip-id; + }; + + uart_AO: serial@4c0 { +- compatible = "amlogic,meson-uart"; ++ compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart"; + reg = <0x0 0x004c0 0x0 0x14>; + interrupts = ; +- clocks = <&xtal>; + status = "disabled"; + }; + + uart_AO_B: serial@4e0 { +- compatible = "amlogic,meson-uart"; ++ compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart"; + reg = <0x0 0x004e0 0x0 0x14>; + interrupts = ; +- clocks = <&xtal>; + status = "disabled"; + }; + +@@ -437,9 +451,9 @@ hiubus: hiubus@c883c000 { + mailbox: mailbox@404 { + compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; + reg = <0 0x404 0 0x4c>; +- interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, +- <0 209 IRQ_TYPE_EDGE_RISING>, +- <0 210 IRQ_TYPE_EDGE_RISING>; ++ interrupts = , ++ , ++ ; + #mbox-cells = <1>; + }; + }; +@@ -448,7 +462,7 @@ ethmac: ethernet@c9410000 { + compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac"; + reg = <0x0 0xc9410000 0x0 0x10000 + 0x0 0xc8834540 0x0 0x4>; +- interrupts = <0 8 1>; ++ interrupts = ; + interrupt-names = "macirq"; + status = "disabled"; + }; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +index fa462831ccaf..9697a7a79464 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +@@ -175,6 +175,64 @@ &ir { + pinctrl-names = "default"; + }; + ++&pinctrl_aobus { ++ gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In", ++ "VCCK En", "CON1 Header Pin31", ++ "I2S Header Pin6", "IR In", "I2S Header Pin7", ++ "I2S Header Pin3", "I2S Header Pin4", ++ "I2S Header Pin5", "HDMI CEC", "SYS LED"; ++}; ++ ++&pinctrl_periphs { ++ gpio-line-names = /* Bank GPIOZ */ ++ "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", ++ "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", ++ "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En", ++ "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3", ++ "Eth PHY nRESET", "Eth PHY Intc", ++ /* Bank GPIOH */ ++ "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", ++ "CON1 Header Pin33", ++ /* Bank BOOT */ ++ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4", ++ "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk", ++ "eMMC Reset", "eMMC CMD", ++ "", "", "", "", "eMMC DS", ++ "", "", ++ /* Bank CARD */ ++ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", ++ "SDCard D3", "SDCard D2", "SDCard Det", ++ /* Bank GPIODV */ ++ "", "", "", "", "", "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", "", "", "", ++ "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", ++ "VDDEE Regulator", "VCCK Regulator", ++ /* Bank GPIOY */ ++ "CON1 Header Pin7", "CON1 Header Pin11", ++ "CON1 Header Pin13", "CON1 Header Pin15", ++ "CON1 Header Pin18", "CON1 Header Pin19", ++ "CON1 Header Pin22", "CON1 Header Pin21", ++ "CON1 Header Pin24", "CON1 Header Pin23", ++ "CON1 Header Pin26", "CON1 Header Pin29", ++ "CON1 Header Pin32", "CON1 Header Pin8", ++ "CON1 Header Pin10", "CON1 Header Pin16", ++ "CON1 Header Pin12", ++ /* Bank GPIOX */ ++ "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2", ++ "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD", ++ "WIFI Power Enable", "WIFI WAKE HOST", ++ "Bluetooth PCM DOUT", "Bluetooth PCM DIN", ++ "Bluetooth PCM SYNC", "Bluetooth PCM CLK", ++ "Bluetooth UART TX", "Bluetooth UART RX", ++ "Bluetooth UART CTS", "Bluetooth UART RTS", ++ "", "", "", "WIFI 32K", "Bluetooth Enable", ++ "Bluetooth WAKE HOST", ++ /* Bank GPIOCLK */ ++ "", "CON1 Header Pin35", "", "", ++ /* GPIO_TEST_N */ ++ ""; ++}; ++ + &pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +index a1078b3e1c76..9c59c3c6d1b6 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +@@ -171,6 +171,13 @@ cvbs_vdac_out: endpoint { + }; + }; + ++&cec_AO { ++ status = "okay"; ++ pinctrl-0 = <&ao_cec_pins>; ++ pinctrl-names = "default"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ + ðmac { + status = "okay"; + pinctrl-0 = <ð_rmii_pins>; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +index d904deb1018c..81ffc689a5bf 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +@@ -84,6 +84,9 @@ vddio_card: gpio-regulator { + /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ + states = <1800000 0 + 3300000 1>; ++ ++ regulator-settling-time-up-us = <10000>; ++ regulator-settling-time-down-us = <150000>; + }; + + vddio_boot: regulator-vddio_boot { +@@ -148,6 +151,13 @@ hdmi_connector_in: endpoint { + }; + }; + ++&cec_AO { ++ status = "okay"; ++ pinctrl-0 = <&ao_cec_pins>; ++ pinctrl-names = "default"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ + &cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +index e76ac313fef9..f7144fd5e03f 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +@@ -108,6 +108,12 @@ hdmi_connector_in: endpoint { + }; + }; + ++&cec_AO { ++ status = "okay"; ++ pinctrl-0 = <&ao_cec_pins>; ++ pinctrl-names = "default"; ++ hdmi-phandle = <&hdmi_tx>; ++}; + + &cvbs_vdac_port { + cvbs_vdac_out: endpoint { +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +index 17d3efdf1469..52f1687e7a09 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +@@ -307,6 +307,15 @@ spifc: spi@8c80 { + }; + }; + ++&cec_AO { ++ clocks = <&clkc_AO CLKID_AO_CEC_32K>; ++ clock-names = "core"; ++}; ++ ++&clkc_AO { ++ compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; ++}; ++ + ðmac { + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_FCLK_DIV2>, +@@ -682,6 +691,31 @@ &spifc { + clocks = <&clkc CLKID_SPI>; + }; + ++&uart_A { ++ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; ++ clock-names = "xtal", "pclk", "baud"; ++}; ++ ++&uart_AO { ++ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; ++ clock-names = "xtal", "pclk", "baud"; ++}; ++ ++&uart_AO_B { ++ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; ++ clock-names = "xtal", "pclk", "baud"; ++}; ++ ++&uart_B { ++ clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; ++ clock-names = "xtal", "core", "baud"; ++}; ++ ++&uart_C { ++ clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; ++ clock-names = "xtal", "core", "baud"; ++}; ++ + &vpu { + compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; + }; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +index 3e0c023d6abd..6827f235d7cf 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +@@ -97,6 +97,13 @@ hdmi_connector_in: endpoint { + }; + }; + ++&cec_AO { ++ status = "okay"; ++ pinctrl-0 = <&ao_cec_pins>; ++ pinctrl-names = "default"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ + /* P230 has exclusive choice between internal or external PHY */ + ðmac { + pinctrl-0 = <ð_pins>; +@@ -124,7 +131,6 @@ external_phy: ethernet-phy@0 { + }; + }; + +- + &hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +index 94567eb17875..edc512ad0bac 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +@@ -67,6 +67,13 @@ hdmi_connector_in: endpoint { + }; + }; + ++&cec_AO { ++ status = "okay"; ++ pinctrl-0 = <&ao_cec_pins>; ++ pinctrl-names = "default"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ + &hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; +@@ -105,6 +112,62 @@ &ir { + linux,rc-map-name = "rc-geekbox"; + }; + ++&pinctrl_aobus { ++ gpio-line-names = "UART TX", ++ "UART RX", ++ "Power Key In", ++ "J9 Header Pin35", ++ "J9 Header Pin16", ++ "J9 Header Pin15", ++ "J9 Header Pin33", ++ "IR In", ++ "HDMI CEC", ++ "SYS LED"; ++}; ++ ++&pinctrl_periphs { ++ gpio-line-names = /* Bank GPIOZ */ ++ "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", ++ "Power OFF", ++ "VCCK Enable", ++ /* Bank GPIOH */ ++ "HDMI HPD", "HDMI SDA", "HDMI SCL", ++ "HDMI_5V_EN", "SPDIF", ++ "J9 Header Pin37", ++ "J9 Header Pin30", ++ "J9 Header Pin29", ++ "J9 Header Pin32", ++ "J9 Header Pin31", ++ /* Bank BOOT */ ++ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", ++ "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", ++ "eMMC Clk", "eMMC Reset", "eMMC CMD", ++ "", "BOOT_MODE", "", "", "eMMC Data Strobe", ++ /* Bank CARD */ ++ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", ++ "SDCard D3", "SDCard D2", "SDCard Det", ++ /* Bank GPIODV */ ++ "", "", "", "", "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", "", "", "", "", ++ "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", ++ "VCCK Regulator", "VDDEE Regulator", ++ /* Bank GPIOX */ ++ "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2", ++ "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD", ++ "WIFI Power Enable", "WIFI WAKE HOST", ++ "Bluetooth PCM DOUT", "Bluetooth PCM DIN", ++ "Bluetooth PCM SYNC", "Bluetooth PCM CLK", ++ "Bluetooth UART TX", "Bluetooth UART RX", ++ "Bluetooth UART CTS", "Bluetooth UART RTS", ++ "WIFI 32K", "Bluetooth Enable", ++ "Bluetooth WAKE HOST", ++ /* Bank GPIOCLK */ ++ "", "J9 Header Pin39", ++ /* GPIO_TEST_N */ ++ ""; ++}; ++ + &pwm_AO_ab { + status = "okay"; + pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts +index 266fbcf3e47f..69ca14ac10fa 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts +@@ -101,6 +101,13 @@ vddio_boot: regulator-vddio_boot { + }; + }; + ++&cec_AO { ++ status = "okay"; ++ pinctrl-0 = <&ao_cec_pins>; ++ pinctrl-names = "default"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ + &cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; +@@ -129,6 +136,63 @@ hdmi_tx_tmds_out: endpoint { + }; + }; + ++&pinctrl_aobus { ++ gpio-line-names = "UART TX", ++ "UART RX", ++ "Blue LED", ++ "SDCard Voltage Switch", ++ "7J1 Header Pin5", ++ "7J1 Header Pin3", ++ "7J1 Header Pin12", ++ "IR In", ++ "9J3 Switch HDMI CEC/7J1 Header Pin11", ++ "7J1 Header Pin13"; ++}; ++ ++&pinctrl_periphs { ++ gpio-line-names = /* Bank GPIOZ */ ++ "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", ++ "Eth Link LED", "Eth Activity LED", ++ /* Bank GPIOH */ ++ "HDMI HPD", "HDMI SDA", "HDMI SCL", ++ "HDMI_5V_EN", "9J1 Header Pin2", ++ "Analog Audio Mute", ++ "2J3 Header Pin6", ++ "2J3 Header Pin5", ++ "2J3 Header Pin4", ++ "2J3 Header Pin3", ++ /* Bank BOOT */ ++ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", ++ "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", ++ "eMMC Clk", "eMMC Reset", "eMMC CMD", ++ "ALT BOOT MODE", "", "", "", "eMMC Data Strobe", ++ /* Bank CARD */ ++ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", ++ "SDCard D3", "SDCard D2", "SDCard Det", ++ /* Bank GPIODV */ ++ "", "", "", "", "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", "", "", "", "", ++ "Green LED", "VCCK Enable", ++ "7J1 Header Pin27", "7J1 Header Pin28", ++ "VCCK Regulator", "VDDEE Regulator", ++ /* Bank GPIOX */ ++ "7J1 Header Pin22", "7J1 Header Pin26", ++ "7J1 Header Pin36", "7J1 Header Pin38", ++ "7J1 Header Pin40", "7J1 Header Pin37", ++ "7J1 Header Pin33", "7J1 Header Pin35", ++ "7J1 Header Pin19", "7J1 Header Pin21", ++ "7J1 Header Pin24", "7J1 Header Pin23", ++ "7J1 Header Pin8", "7J1 Header Pin10", ++ "7J1 Header Pin16", "7J1 Header Pin18", ++ "7J1 Header Pin32", "7J1 Header Pin29", ++ "7J1 Header Pin31", ++ /* Bank GPIOCLK */ ++ "7J1 Header Pin7", "", ++ /* GPIO_TEST_N */ ++ "7J1 Header Pin15"; ++}; ++ + /* SD card */ + &sd_emmc_b { + status = "okay"; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts +index 6633a5d8fdd3..4c2ac7650fcd 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts +@@ -140,6 +140,13 @@ hdmi_connector_in: endpoint { + }; + }; + ++&cec_AO { ++ status = "okay"; ++ pinctrl-0 = <&ao_cec_pins>; ++ pinctrl-names = "default"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ + &cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts +index 6ab17c1eeefd..6e2bf858291c 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts +@@ -71,6 +71,13 @@ hdmi_connector_in: endpoint { + }; + }; + ++&cec_AO { ++ status = "okay"; ++ pinctrl-0 = <&ao_cec_pins>; ++ pinctrl-names = "default"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ + &cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +index 8d4f3160a0ee..d6876e64979e 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +@@ -43,6 +43,7 @@ + + #include "meson-gx.dtsi" + #include ++#include + #include + #include + +@@ -207,6 +208,15 @@ mux { + }; + }; + ++&cec_AO { ++ clocks = <&clkc_AO CLKID_AO_CEC_32K>; ++ clock-names = "core"; ++}; ++ ++&clkc_AO { ++ compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc"; ++}; ++ + &hdmi_tx { + compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; + resets = <&reset RESET_HDMITX_CAPB3>, +@@ -623,6 +633,31 @@ &spifc { + clocks = <&clkc CLKID_SPI>; + }; + ++&uart_A { ++ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; ++ clock-names = "xtal", "core", "baud"; ++}; ++ ++&uart_AO { ++ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; ++ clock-names = "xtal", "pclk", "baud"; ++}; ++ ++&uart_AO_B { ++ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; ++ clock-names = "xtal", "pclk", "baud"; ++}; ++ ++&uart_B { ++ clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; ++ clock-names = "xtal", "core", "baud"; ++}; ++ ++&uart_C { ++ clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; ++ clock-names = "xtal", "core", "baud"; ++}; ++ + &vpu { + compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu"; + }; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +index 5f626d683088..9b10c5f4f8c0 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +@@ -113,6 +113,13 @@ hdmi_connector_in: endpoint { + }; + }; + ++&cec_AO { ++ status = "okay"; ++ pinctrl-0 = <&ao_cec_pins>; ++ pinctrl-names = "default"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ + &cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +index fe451cce93e7..19a798d2ae2f 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +@@ -117,6 +117,10 @@ cpu7: cpu@103 { + }; + }; + ++&clkc_AO { ++ compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc"; ++}; ++ + &saradc { + compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc"; + }; +diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +index 72720e9132a1..c9ffffb96e43 100644 +--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi ++++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +@@ -626,6 +626,7 @@ pcie0: pcie@1f2b0000 { + 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4 + 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4 +@@ -651,6 +652,7 @@ pcie1: pcie@1f2c0000 { + 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4 + 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4 +diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi +index 63be8e51eaa8..c09a36fed917 100644 +--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi ++++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi +@@ -626,6 +626,7 @@ pcie0: pcie@1f2b0000 { + 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4 + 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4 +@@ -651,6 +652,7 @@ pcie1: pcie@1f2c0000 { + 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4 + 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4 +@@ -676,6 +678,7 @@ pcie2: pcie@1f2d0000 { + 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4 + 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4 +@@ -701,6 +704,7 @@ pcie3: pcie@1f500000 { + 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4 + 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4 +@@ -726,6 +730,7 @@ pcie4: pcie@1f510000 { + 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4 + 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4 +diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi +index 7cfa8e414e7f..8ecdd4331980 100644 +--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi ++++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi +@@ -226,7 +226,7 @@ v2m_serial3: uart@0c0000 { + clock-names = "uartclk", "apb_pclk"; + }; + +- virtio_block@0130000 { ++ virtio-block@0130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x200>; + interrupts = <42>; +diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi +index e8b7413ec890..fbafe62d6b22 100644 +--- a/arch/arm64/boot/dts/arm/juno-base.dtsi ++++ b/arch/arm64/boot/dts/arm/juno-base.dtsi +@@ -201,7 +201,7 @@ stm_out_port: endpoint { + }; + }; + +- cpu_debug0: cpu_debug@22010000 { ++ cpu_debug0: cpu-debug@22010000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0x22010000 0x0 0x1000>; + +@@ -260,7 +260,7 @@ cluster0_funnel_in_port1: endpoint { + }; + }; + +- cpu_debug1: cpu_debug@22110000 { ++ cpu_debug1: cpu-debug@22110000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0x22110000 0x0 0x1000>; + +@@ -283,7 +283,7 @@ cluster0_etm1_out_port: endpoint { + }; + }; + +- cpu_debug2: cpu_debug@23010000 { ++ cpu_debug2: cpu-debug@23010000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0x23010000 0x0 0x1000>; + +@@ -356,7 +356,7 @@ cluster1_funnel_in_port3: endpoint { + }; + }; + +- cpu_debug3: cpu_debug@23110000 { ++ cpu_debug3: cpu-debug@23110000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0x23110000 0x0 0x1000>; + +@@ -379,7 +379,7 @@ cluster1_etm1_out_port: endpoint { + }; + }; + +- cpu_debug4: cpu_debug@23210000 { ++ cpu_debug4: cpu-debug@23210000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0x23210000 0x0 0x1000>; + +@@ -402,7 +402,7 @@ cluster1_etm2_out_port: endpoint { + }; + }; + +- cpu_debug5: cpu_debug@23310000 { ++ cpu_debug5: cpu-debug@23310000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0x23310000 0x0 0x1000>; + +@@ -426,7 +426,7 @@ cluster1_etm3_out_port: endpoint { + }; + + replicator@20120000 { +- compatible = "qcom,coresight-replicator1x", "arm,primecell"; ++ compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x20120000 0 0x1000>; + + clocks = <&soc_smc50mhz>; +diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +index 161ac98418a3..528875c75598 100644 +--- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi ++++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +@@ -219,7 +219,7 @@ panel-timing { + }; + }; + +- virtio_block@0130000 { ++ virtio-block@0130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x200>; + interrupts = <42>; +diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile +index f11bdd6689ea..3eaef3895d66 100644 +--- a/arch/arm64/boot/dts/broadcom/Makefile ++++ b/arch/arm64/boot/dts/broadcom/Makefile +@@ -1,7 +1,7 @@ + dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb +-dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb + +-dts-dirs := stingray ++dts-dirs += northstar2 ++dts-dirs += stingray + always := $(dtb-y) + subdir-y := $(dts-dirs) + clean-files := *.dtb +diff --git a/arch/arm64/boot/dts/broadcom/bcm2835-rpi.dtsi b/arch/arm64/boot/dts/broadcom/bcm2835-rpi.dtsi +deleted file mode 120000 +index 3937b77cb310..000000000000 +--- a/arch/arm64/boot/dts/broadcom/bcm2835-rpi.dtsi ++++ /dev/null +@@ -1 +0,0 @@ +-../../../../arm/boot/dts/bcm2835-rpi.dtsi +\ No newline at end of file +diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts +index 972f14db28ac..699d340a3437 100644 +--- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts ++++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts +@@ -1,41 +1 @@ +-/dts-v1/; +-#include "bcm2837.dtsi" +-#include "bcm2835-rpi.dtsi" +-#include "bcm283x-rpi-smsc9514.dtsi" +-#include "bcm283x-rpi-usb-host.dtsi" +- +-/ { +- compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; +- model = "Raspberry Pi 3 Model B"; +- +- memory { +- reg = <0 0x40000000>; +- }; +- +- leds { +- act { +- gpios = <&gpio 47 0>; +- }; +- }; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-/* SDHCI is used to control the SDIO for wireless */ +-&sdhci { +- pinctrl-names = "default"; +- pinctrl-0 = <&emmc_gpio34>; +- status = "okay"; +- bus-width = <4>; +- non-removable; +-}; +- +-/* SDHOST is used to drive the SD card */ +-&sdhost { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdhost_gpio48>; +- status = "okay"; +- bus-width = <4>; +-}; ++#include "arm/bcm2837-rpi-3-b.dts" +diff --git a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi +deleted file mode 100644 +index 2d5de6f0f78d..000000000000 +--- a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi ++++ /dev/null +@@ -1,86 +0,0 @@ +-#include "bcm283x.dtsi" +- +-/ { +- compatible = "brcm,bcm2837"; +- +- soc { +- ranges = <0x7e000000 0x3f000000 0x1000000>, +- <0x40000000 0x40000000 0x00001000>; +- dma-ranges = <0xc0000000 0x00000000 0x3f000000>; +- +- local_intc: local_intc { +- compatible = "brcm,bcm2836-l1-intc"; +- reg = <0x40000000 0x100>; +- interrupt-controller; +- #interrupt-cells = <1>; +- interrupt-parent = <&local_intc>; +- }; +- }; +- +- timer { +- compatible = "arm,armv7-timer"; +- interrupt-parent = <&local_intc>; +- interrupts = <0>, // PHYS_SECURE_PPI +- <1>, // PHYS_NONSECURE_PPI +- <3>, // VIRT_PPI +- <2>; // HYP_PPI +- always-on; +- }; +- +- cpus: cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x000000d8>; +- }; +- +- cpu1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <1>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x000000e0>; +- }; +- +- cpu2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <2>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x000000e8>; +- }; +- +- cpu3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <3>; +- enable-method = "spin-table"; +- cpu-release-addr = <0x0 0x000000f0>; +- }; +- }; +-}; +- +-/* Make the BCM2835-style global interrupt controller be a child of the +- * CPU-local interrupt controller. +- */ +-&intc { +- compatible = "brcm,bcm2836-armctrl-ic"; +- reg = <0x7e00b200 0x200>; +- interrupt-parent = <&local_intc>; +- interrupts = <8>; +-}; +- +-&cpu_thermal { +- coefficients = <(-538) 412000>; +-}; +- +-/* enable thermal sensor with the correct compatible property set */ +-&thermal { +- compatible = "brcm,bcm2837-thermal"; +- status = "okay"; +-}; +diff --git a/arch/arm64/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi +deleted file mode 120000 +index dca7c057d5a5..000000000000 +--- a/arch/arm64/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi ++++ /dev/null +@@ -1 +0,0 @@ +-../../../../arm/boot/dts/bcm283x-rpi-smsc9514.dtsi +\ No newline at end of file +diff --git a/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi +deleted file mode 120000 +index cbeebe312ff8..000000000000 +--- a/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi ++++ /dev/null +@@ -1 +0,0 @@ +-../../../../arm/boot/dts/bcm283x-rpi-usb-host.dtsi +\ No newline at end of file +diff --git a/arch/arm64/boot/dts/broadcom/bcm283x.dtsi b/arch/arm64/boot/dts/broadcom/bcm283x.dtsi +deleted file mode 120000 +index 5f54e4cab99b..000000000000 +--- a/arch/arm64/boot/dts/broadcom/bcm283x.dtsi ++++ /dev/null +@@ -1 +0,0 @@ +-../../../../arm/boot/dts/bcm283x.dtsi +\ No newline at end of file +diff --git a/arch/arm64/boot/dts/broadcom/northstar2/Makefile b/arch/arm64/boot/dts/broadcom/northstar2/Makefile +new file mode 100644 +index 000000000000..e01a1485b813 +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/northstar2/Makefile +@@ -0,0 +1,6 @@ ++dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ++dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-xmc.dtb ++ ++always := $(dtb-y) ++subdir-y := $(dts-dirs) ++clean-files := *.dtb +diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi +new file mode 100644 +index 000000000000..99009fdf10a4 +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi +@@ -0,0 +1,105 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright (c) 2016 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++ ++ osc: oscillator { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <25000000>; ++ }; ++ ++ lcpll_ddr: lcpll_ddr@6501d058 { ++ #clock-cells = <1>; ++ compatible = "brcm,ns2-lcpll-ddr"; ++ reg = <0x6501d058 0x20>, ++ <0x6501c020 0x4>, ++ <0x6501d04c 0x4>; ++ clocks = <&osc>; ++ clock-output-names = "lcpll_ddr", "pcie_sata_usb", ++ "ddr", "ddr_ch2_unused", ++ "ddr_ch3_unused", "ddr_ch4_unused", ++ "ddr_ch5_unused"; ++ }; ++ ++ lcpll_ports: lcpll_ports@6501d078 { ++ #clock-cells = <1>; ++ compatible = "brcm,ns2-lcpll-ports"; ++ reg = <0x6501d078 0x20>, ++ <0x6501c020 0x4>, ++ <0x6501d054 0x4>; ++ clocks = <&osc>; ++ clock-output-names = "lcpll_ports", "wan", "rgmii", ++ "ports_ch2_unused", ++ "ports_ch3_unused", ++ "ports_ch4_unused", ++ "ports_ch5_unused"; ++ }; ++ ++ genpll_scr: genpll_scr@6501d098 { ++ #clock-cells = <1>; ++ compatible = "brcm,ns2-genpll-scr"; ++ reg = <0x6501d098 0x32>, ++ <0x6501c020 0x4>, ++ <0x6501d044 0x4>; ++ clocks = <&osc>; ++ clock-output-names = "genpll_scr", "scr", "fs", ++ "audio_ref", "scr_ch3_unused", ++ "scr_ch4_unused", "scr_ch5_unused"; ++ }; ++ ++ iprocmed: iprocmed { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; ++ clock-div = <2>; ++ clock-mult = <1>; ++ }; ++ ++ iprocslow: iprocslow { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; ++ clock-div = <4>; ++ clock-mult = <1>; ++ }; ++ ++ genpll_sw: genpll_sw@6501d0c4 { ++ #clock-cells = <1>; ++ compatible = "brcm,ns2-genpll-sw"; ++ reg = <0x6501d0c4 0x32>, ++ <0x6501c020 0x4>, ++ <0x6501d044 0x4>; ++ clocks = <&osc>; ++ clock-output-names = "genpll_sw", "rpe", "250", "nic", ++ "chimp", "port", "sdio"; ++ }; +diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +new file mode 100644 +index 000000000000..ec19fbf928a1 +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +@@ -0,0 +1,236 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++#include "ns2.dtsi" ++ ++/ { ++ model = "Broadcom NS2 SVK"; ++ compatible = "brcm,ns2-svk", "brcm,ns2"; ++ ++ aliases { ++ serial0 = &uart3; ++ serial1 = &uart0; ++ serial2 = &uart1; ++ serial3 = &uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ bootargs = "earlycon=uart8250,mmio32,0x66130000"; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x000000000 0x80000000 0x00000000 0x40000000>; ++ }; ++}; ++ ++&enet { ++ status = "okay"; ++}; ++ ++&pci_phy0 { ++ status = "okay"; ++}; ++ ++&pci_phy1 { ++ status = "okay"; ++}; ++ ++&pcie0 { ++ status = "okay"; ++}; ++ ++&pcie4 { ++ status = "okay"; ++}; ++ ++&pcie8 { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++}; ++ ++&i2c1 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&uart3 { ++ status = "okay"; ++}; ++ ++&ssp0 { ++ status = "okay"; ++ ++ slic@0 { ++ compatible = "silabs,si3226x"; ++ reg = <0>; ++ spi-max-frequency = <5000000>; ++ spi-cpha = <1>; ++ spi-cpol = <1>; ++ pl022,hierarchy = <0>; ++ pl022,interface = <0>; ++ pl022,slave-tx-disable = <0>; ++ pl022,com-mode = <0>; ++ pl022,rx-level-trig = <1>; ++ pl022,tx-level-trig = <1>; ++ pl022,ctrl-len = <11>; ++ pl022,wait-state = <0>; ++ pl022,duplex = <0>; ++ }; ++}; ++ ++&ssp1 { ++ status = "okay"; ++ ++ at25@0 { ++ compatible = "atmel,at25"; ++ reg = <0>; ++ spi-max-frequency = <5000000>; ++ at25,byte-len = <0x8000>; ++ at25,addr-mode = <2>; ++ at25,page-size = <64>; ++ spi-cpha = <1>; ++ spi-cpol = <1>; ++ pl022,hierarchy = <0>; ++ pl022,interface = <0>; ++ pl022,slave-tx-disable = <0>; ++ pl022,com-mode = <0>; ++ pl022,rx-level-trig = <1>; ++ pl022,tx-level-trig = <1>; ++ pl022,ctrl-len = <11>; ++ pl022,wait-state = <0>; ++ pl022,duplex = <0>; ++ }; ++}; ++ ++&sata_phy0 { ++ status = "okay"; ++}; ++ ++&sata_phy1 { ++ status = "okay"; ++}; ++ ++&sata { ++ status = "okay"; ++}; ++ ++&sdio0 { ++ status = "okay"; ++}; ++ ++&sdio1 { ++ status = "okay"; ++}; ++ ++&nand { ++ nandcs@0 { ++ compatible = "brcm,nandcs"; ++ reg = <0>; ++ nand-ecc-mode = "hw"; ++ nand-ecc-strength = <8>; ++ nand-ecc-step-size = <512>; ++ nand-bus-width = <16>; ++ brcm,nand-oob-sector-size = <16>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++}; ++ ++&mdio_mux_iproc { ++ mdio@10 { ++ gphy0: eth-phy@10 { ++ enet-phy-lane-swap; ++ reg = <0x10>; ++ }; ++ }; ++}; ++ ++&pinctrl { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&nand_sel>; ++ nand_sel: nand_sel { ++ function = "nand"; ++ groups = "nand_grp"; ++ }; ++}; ++ ++&qspi { ++ bspi-sel = <0>; ++ flash: m25p80@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "m25p80"; ++ reg = <0x0>; ++ spi-max-frequency = <12500000>; ++ m25p,fast-read; ++ spi-cpol; ++ spi-cpha; ++ ++ partition@0 { ++ label = "boot"; ++ reg = <0x00000000 0x000a0000>; ++ }; ++ ++ partition@a0000 { ++ label = "env"; ++ reg = <0x000a0000 0x00060000>; ++ }; ++ ++ partition@100000 { ++ label = "system"; ++ reg = <0x00100000 0x00600000>; ++ }; ++ ++ partition@700000 { ++ label = "rootfs"; ++ reg = <0x00700000 0x01900000>; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts +new file mode 100644 +index 000000000000..ab4ae1a32fab +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts +@@ -0,0 +1,191 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2016 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++#include "ns2.dtsi" ++ ++/ { ++ model = "Broadcom NS2 XMC"; ++ compatible = "brcm,ns2-xmc", "brcm,ns2"; ++ ++ aliases { ++ serial0 = &uart3; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ bootargs = "earlycon=uart8250,mmio32,0x66130000"; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x000000000 0x80000000 0x00000001 0x00000000>; ++ }; ++}; ++ ++&enet { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++}; ++ ++&i2c1 { ++ status = "okay"; ++}; ++ ++&mdio_mux_iproc { ++ mdio@10 { ++ gphy0: eth-phy@10 { ++ reg = <0x10>; ++ }; ++ }; ++}; ++ ++&nand { ++ nandcs@0 { ++ compatible = "brcm,nandcs"; ++ reg = <0>; ++ nand-ecc-mode = "hw"; ++ nand-ecc-strength = <8>; ++ nand-ecc-step-size = <512>; ++ nand-bus-width = <16>; ++ brcm,nand-oob-sector-size = <16>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "nboot"; ++ reg = <0x00000000 0x00280000>; /* 2.5MB */ ++ read-only; ++ }; ++ ++ partition@280000 { ++ label = "nenv"; ++ reg = <0x00280000 0x00040000>; /* 0.25MB */ ++ read-only; ++ }; ++ ++ partition@2c0000 { ++ label = "ndtb"; ++ reg = <0x002c0000 0x00040000>; /* 0.25MB */ ++ read-only; ++ }; ++ ++ partition@300000 { ++ label = "nsystem"; ++ reg = <0x00300000 0x03d00000>; /* 61MB */ ++ read-only; ++ }; ++ ++ partition@4000000 { ++ label = "nrootfs"; ++ reg = <0x04000000 0x06400000>; /* 100MB */ ++ }; ++ ++ partition@0a400000{ ++ label = "ncustfs"; ++ reg = <0x0a400000 0x35c00000>; /* 860MB */ ++ }; ++ }; ++}; ++ ++&pci_phy0 { ++ status = "okay"; ++}; ++ ++&pcie0 { ++ status = "okay"; ++}; ++ ++&pcie8 { ++ status = "okay"; ++}; ++ ++&sata_phy0 { ++ status = "okay"; ++}; ++ ++&sata_phy1 { ++ status = "okay"; ++}; ++ ++&sata { ++ status = "okay"; ++}; ++ ++&qspi { ++ flash: m25p80@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "m25p80"; ++ spi-max-frequency = <62500000>; ++ m25p,default-addr-width = <3>; ++ reg = <0x0 0x0>; ++ ++ partition@0 { ++ label = "bl0"; ++ reg = <0x00000000 0x00080000>; /* 512KB */ ++ }; ++ ++ partition@80000 { ++ label = "fip"; ++ reg = <0x00080000 0x00150000>; /* 1344KB */ ++ }; ++ ++ partition@1e0000 { ++ label = "env"; ++ reg = <0x001e0000 0x00010000>;/* 64KB */ ++ }; ++ ++ partition@1f0000 { ++ label = "dtb"; ++ reg = <0x001f0000 0x00010000>; /* 64KB */ ++ }; ++ ++ partition@200000 { ++ label = "kernel"; ++ reg = <0x00200000 0x00e00000>; /* 14MB */ ++ }; ++ ++ partition@1000000 { ++ label = "rootfs"; ++ reg = <0x01000000 0x01000000>; /* 16MB */ ++ }; ++ }; ++}; ++ ++&uart3 { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +new file mode 100644 +index 000000000000..35c8457e3d1f +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +@@ -0,0 +1,765 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright (c) 2015 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/memreserve/ 0x81000000 0x00200000; ++ ++#include ++#include ++ ++/ { ++ compatible = "brcm,ns2"; ++ interrupt-parent = <&gic>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ cpus { ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ A57_0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a57", "arm,armv8"; ++ reg = <0 0>; ++ enable-method = "psci"; ++ next-level-cache = <&CLUSTER0_L2>; ++ }; ++ ++ A57_1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a57", "arm,armv8"; ++ reg = <0 1>; ++ enable-method = "psci"; ++ next-level-cache = <&CLUSTER0_L2>; ++ }; ++ ++ A57_2: cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a57", "arm,armv8"; ++ reg = <0 2>; ++ enable-method = "psci"; ++ next-level-cache = <&CLUSTER0_L2>; ++ }; ++ ++ A57_3: cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a57", "arm,armv8"; ++ reg = <0 3>; ++ enable-method = "psci"; ++ next-level-cache = <&CLUSTER0_L2>; ++ }; ++ ++ CLUSTER0_L2: l2-cache@000 { ++ compatible = "cache"; ++ }; ++ }; ++ ++ psci { ++ compatible = "arm,psci-1.0"; ++ method = "smc"; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ pmu { ++ compatible = "arm,armv8-pmuv3"; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-affinity = <&A57_0>, ++ <&A57_1>, ++ <&A57_2>, ++ <&A57_3>; ++ }; ++ ++ pcie0: pcie@20020000 { ++ compatible = "brcm,iproc-pcie"; ++ reg = <0 0x20020000 0 0x1000>; ++ dma-coherent; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_NONE>; ++ ++ linux,pci-domain = <0>; ++ ++ bus-range = <0x00 0xff>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>; ++ ++ brcm,pcie-ob; ++ brcm,pcie-ob-oarr-size; ++ brcm,pcie-ob-axi-offset = <0x00000000>; ++ brcm,pcie-ob-window-size = <256>; ++ ++ status = "disabled"; ++ ++ phys = <&pci_phy0>; ++ phy-names = "pcie-phy"; ++ ++ msi-parent = <&v2m0>; ++ }; ++ ++ pcie4: pcie@50020000 { ++ compatible = "brcm,iproc-pcie"; ++ reg = <0 0x50020000 0 0x1000>; ++ dma-coherent; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_NONE>; ++ ++ linux,pci-domain = <4>; ++ ++ bus-range = <0x00 0xff>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>; ++ ++ brcm,pcie-ob; ++ brcm,pcie-ob-oarr-size; ++ brcm,pcie-ob-axi-offset = <0x30000000>; ++ brcm,pcie-ob-window-size = <256>; ++ ++ status = "disabled"; ++ ++ phys = <&pci_phy1>; ++ phy-names = "pcie-phy"; ++ ++ msi-parent = <&v2m0>; ++ }; ++ ++ pcie8: pcie@60c00000 { ++ compatible = "brcm,iproc-pcie-paxc"; ++ reg = <0 0x60c00000 0 0x1000>; ++ dma-coherent; ++ linux,pci-domain = <8>; ++ ++ bus-range = <0x0 0x1>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>; ++ ++ status = "disabled"; ++ ++ msi-parent = <&v2m0>; ++ }; ++ ++ soc: soc { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0 0xffffffff>; ++ ++ #include "ns2-clock.dtsi" ++ ++ enet: ethernet@61000000 { ++ compatible = "brcm,ns2-amac"; ++ reg = <0x61000000 0x1000>, ++ <0x61090000 0x1000>, ++ <0x61030000 0x100>; ++ reg-names = "amac_base", "idm_base", "nicpm_base"; ++ interrupts = ; ++ dma-coherent; ++ phy-handle = <&gphy0>; ++ phy-mode = "rgmii"; ++ status = "disabled"; ++ }; ++ ++ pdc0: iproc-pdc0@612c0000 { ++ compatible = "brcm,iproc-pdc-mbox"; ++ reg = <0x612c0000 0x445>; /* PDC FS0 regs */ ++ interrupts = ; ++ #mbox-cells = <1>; ++ dma-coherent; ++ brcm,rx-status-len = <32>; ++ brcm,use-bcm-hdr; ++ }; ++ ++ crypto0: crypto@612d0000 { ++ compatible = "brcm,spum-crypto"; ++ reg = <0x612d0000 0x900>; ++ mboxes = <&pdc0 0>; ++ }; ++ ++ pdc1: iproc-pdc1@612e0000 { ++ compatible = "brcm,iproc-pdc-mbox"; ++ reg = <0x612e0000 0x445>; /* PDC FS1 regs */ ++ interrupts = ; ++ #mbox-cells = <1>; ++ dma-coherent; ++ brcm,rx-status-len = <32>; ++ brcm,use-bcm-hdr; ++ }; ++ ++ crypto1: crypto@612f0000 { ++ compatible = "brcm,spum-crypto"; ++ reg = <0x612f0000 0x900>; ++ mboxes = <&pdc1 0>; ++ }; ++ ++ pdc2: iproc-pdc2@61300000 { ++ compatible = "brcm,iproc-pdc-mbox"; ++ reg = <0x61300000 0x445>; /* PDC FS2 regs */ ++ interrupts = ; ++ #mbox-cells = <1>; ++ dma-coherent; ++ brcm,rx-status-len = <32>; ++ brcm,use-bcm-hdr; ++ }; ++ ++ crypto2: crypto@61310000 { ++ compatible = "brcm,spum-crypto"; ++ reg = <0x61310000 0x900>; ++ mboxes = <&pdc2 0>; ++ }; ++ ++ pdc3: iproc-pdc3@61320000 { ++ compatible = "brcm,iproc-pdc-mbox"; ++ reg = <0x61320000 0x445>; /* PDC FS3 regs */ ++ interrupts = ; ++ #mbox-cells = <1>; ++ dma-coherent; ++ brcm,rx-status-len = <32>; ++ brcm,use-bcm-hdr; ++ }; ++ ++ crypto3: crypto@61330000 { ++ compatible = "brcm,spum-crypto"; ++ reg = <0x61330000 0x900>; ++ mboxes = <&pdc3 0>; ++ }; ++ ++ dma0: dma@61360000 { ++ compatible = "arm,pl330", "arm,primecell"; ++ reg = <0x61360000 0x1000>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ #dma-cells = <1>; ++ #dma-channels = <8>; ++ #dma-requests = <32>; ++ clocks = <&iprocslow>; ++ clock-names = "apb_pclk"; ++ }; ++ ++ smmu: mmu@64000000 { ++ compatible = "arm,mmu-500"; ++ reg = <0x64000000 0x40000>; ++ #global-interrupts = <2>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ #iommu-cells = <1>; ++ }; ++ ++ pinctrl: pinctrl@6501d130 { ++ compatible = "brcm,ns2-pinmux"; ++ reg = <0x6501d130 0x08>, ++ <0x660a0028 0x04>, ++ <0x660009b0 0x40>; ++ }; ++ ++ gpio_aon: gpio@65024800 { ++ compatible = "brcm,iproc-gpio"; ++ reg = <0x65024800 0x50>, ++ <0x65024008 0x18>; ++ ngpios = <6>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ }; ++ ++ gic: interrupt-controller@65210000 { ++ compatible = "arm,gic-400"; ++ #interrupt-cells = <3>; ++ interrupt-controller; ++ reg = <0x65210000 0x1000>, ++ <0x65220000 0x1000>, ++ <0x65240000 0x2000>, ++ <0x65260000 0x1000>; ++ interrupts = ; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x652e0000 0x80000>; ++ ++ v2m0: v2m@00000 { ++ compatible = "arm,gic-v2m-frame"; ++ interrupt-parent = <&gic>; ++ msi-controller; ++ reg = <0x00000 0x1000>; ++ arm,msi-base-spi = <72>; ++ arm,msi-num-spis = <16>; ++ }; ++ ++ v2m1: v2m@10000 { ++ compatible = "arm,gic-v2m-frame"; ++ interrupt-parent = <&gic>; ++ msi-controller; ++ reg = <0x10000 0x1000>; ++ arm,msi-base-spi = <88>; ++ arm,msi-num-spis = <16>; ++ }; ++ ++ v2m2: v2m@20000 { ++ compatible = "arm,gic-v2m-frame"; ++ interrupt-parent = <&gic>; ++ msi-controller; ++ reg = <0x20000 0x1000>; ++ arm,msi-base-spi = <104>; ++ arm,msi-num-spis = <16>; ++ }; ++ ++ v2m3: v2m@30000 { ++ compatible = "arm,gic-v2m-frame"; ++ interrupt-parent = <&gic>; ++ msi-controller; ++ reg = <0x30000 0x1000>; ++ arm,msi-base-spi = <120>; ++ arm,msi-num-spis = <16>; ++ }; ++ ++ v2m4: v2m@40000 { ++ compatible = "arm,gic-v2m-frame"; ++ interrupt-parent = <&gic>; ++ msi-controller; ++ reg = <0x40000 0x1000>; ++ arm,msi-base-spi = <136>; ++ arm,msi-num-spis = <16>; ++ }; ++ ++ v2m5: v2m@50000 { ++ compatible = "arm,gic-v2m-frame"; ++ interrupt-parent = <&gic>; ++ msi-controller; ++ reg = <0x50000 0x1000>; ++ arm,msi-base-spi = <152>; ++ arm,msi-num-spis = <16>; ++ }; ++ ++ v2m6: v2m@60000 { ++ compatible = "arm,gic-v2m-frame"; ++ interrupt-parent = <&gic>; ++ msi-controller; ++ reg = <0x60000 0x1000>; ++ arm,msi-base-spi = <168>; ++ arm,msi-num-spis = <16>; ++ }; ++ ++ v2m7: v2m@70000 { ++ compatible = "arm,gic-v2m-frame"; ++ interrupt-parent = <&gic>; ++ msi-controller; ++ reg = <0x70000 0x1000>; ++ arm,msi-base-spi = <184>; ++ arm,msi-num-spis = <16>; ++ }; ++ }; ++ ++ cci@65590000 { ++ compatible = "arm,cci-400"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0x65590000 0x1000>; ++ ranges = <0 0x65590000 0x10000>; ++ ++ pmu@9000 { ++ compatible = "arm,cci-400-pmu,r1", ++ "arm,cci-400-pmu"; ++ reg = <0x9000 0x4000>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ ; ++ }; ++ }; ++ ++ usbdrd_phy: phy@66000960 { ++ #phy-cells = <0>; ++ compatible = "brcm,ns2-drd-phy"; ++ reg = <0x66000960 0x24>, ++ <0x67012800 0x4>, ++ <0x6501d148 0x4>, ++ <0x664d0700 0x4>; ++ reg-names = "icfg", "rst-ctrl", ++ "crmu-ctrl", "usb2-strap"; ++ id-gpios = <&gpio_g 30 0>; ++ vbus-gpios = <&gpio_g 31 0>; ++ status = "disabled"; ++ }; ++ ++ pwm: pwm@66010000 { ++ compatible = "brcm,iproc-pwm"; ++ reg = <0x66010000 0x28>; ++ clocks = <&osc>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ mdio_mux_iproc: mdio-mux@6602023c { ++ compatible = "brcm,mdio-mux-iproc"; ++ reg = <0x6602023c 0x14>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ mdio@0 { ++ reg = <0x0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pci_phy0: pci-phy@0 { ++ compatible = "brcm,ns2-pcie-phy"; ++ reg = <0x0>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ ++ mdio@7 { ++ reg = <0x7>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pci_phy1: pci-phy@0 { ++ compatible = "brcm,ns2-pcie-phy"; ++ reg = <0x0>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ ++ mdio@10 { ++ reg = <0x10>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ ++ timer0: timer@66030000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x66030000 0x1000>; ++ interrupts = ; ++ clocks = <&iprocslow>, ++ <&iprocslow>, ++ <&iprocslow>; ++ clock-names = "timer1", "timer2", "apb_pclk"; ++ }; ++ ++ timer1: timer@66040000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x66040000 0x1000>; ++ interrupts = ; ++ clocks = <&iprocslow>, ++ <&iprocslow>, ++ <&iprocslow>; ++ clock-names = "timer1", "timer2", "apb_pclk"; ++ }; ++ ++ timer2: timer@66050000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x66050000 0x1000>; ++ interrupts = ; ++ clocks = <&iprocslow>, ++ <&iprocslow>, ++ <&iprocslow>; ++ clock-names = "timer1", "timer2", "apb_pclk"; ++ }; ++ ++ timer3: timer@66060000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x66060000 0x1000>; ++ interrupts = ; ++ clocks = <&iprocslow>, ++ <&iprocslow>, ++ <&iprocslow>; ++ clock-names = "timer1", "timer2", "apb_pclk"; ++ }; ++ ++ i2c0: i2c@66080000 { ++ compatible = "brcm,iproc-i2c"; ++ reg = <0x66080000 0x100>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ clock-frequency = <100000>; ++ status = "disabled"; ++ }; ++ ++ wdt0: watchdog@66090000 { ++ compatible = "arm,sp805", "arm,primecell"; ++ reg = <0x66090000 0x1000>; ++ interrupts = ; ++ clocks = <&iprocslow>, <&iprocslow>; ++ clock-names = "wdogclk", "apb_pclk"; ++ }; ++ ++ gpio_g: gpio@660a0000 { ++ compatible = "brcm,iproc-gpio"; ++ reg = <0x660a0000 0x50>; ++ ngpios = <32>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ interrupt-controller; ++ interrupts = ; ++ }; ++ ++ i2c1: i2c@660b0000 { ++ compatible = "brcm,iproc-i2c"; ++ reg = <0x660b0000 0x100>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ clock-frequency = <100000>; ++ status = "disabled"; ++ }; ++ ++ uart0: serial@66100000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x66100000 0x100>; ++ interrupts = ; ++ clocks = <&iprocslow>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ uart1: serial@66110000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x66110000 0x100>; ++ interrupts = ; ++ clocks = <&iprocslow>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ uart2: serial@66120000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x66120000 0x100>; ++ interrupts = ; ++ clocks = <&iprocslow>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ uart3: serial@66130000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x66130000 0x100>; ++ interrupts = ; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&osc>; ++ status = "disabled"; ++ }; ++ ++ ssp0: ssp@66180000 { ++ compatible = "arm,pl022", "arm,primecell"; ++ reg = <0x66180000 0x1000>; ++ interrupts = ; ++ clocks = <&iprocslow>, <&iprocslow>; ++ clock-names = "spiclk", "apb_pclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ ssp1: ssp@66190000 { ++ compatible = "arm,pl022", "arm,primecell"; ++ reg = <0x66190000 0x1000>; ++ interrupts = ; ++ clocks = <&iprocslow>, <&iprocslow>; ++ clock-names = "spiclk", "apb_pclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ hwrng: hwrng@66220000 { ++ compatible = "brcm,iproc-rng200"; ++ reg = <0x66220000 0x28>; ++ }; ++ ++ sata_phy: sata_phy@663f0100 { ++ compatible = "brcm,iproc-ns2-sata-phy"; ++ reg = <0x663f0100 0x1f00>, ++ <0x663f004c 0x10>; ++ reg-names = "phy", "phy-ctrl"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ sata_phy0: sata-phy@0 { ++ reg = <0>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ sata_phy1: sata-phy@1 { ++ reg = <1>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ ++ sata: ahci@663f2000 { ++ compatible = "brcm,iproc-ahci", "generic-ahci"; ++ reg = <0x663f2000 0x1000>; ++ dma-coherent; ++ reg-names = "ahci"; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata0: sata-port@0 { ++ reg = <0>; ++ phys = <&sata_phy0>; ++ phy-names = "sata-phy"; ++ }; ++ ++ sata1: sata-port@1 { ++ reg = <1>; ++ phys = <&sata_phy1>; ++ phy-names = "sata-phy"; ++ }; ++ }; ++ ++ sdio0: sdhci@66420000 { ++ compatible = "brcm,sdhci-iproc-cygnus"; ++ reg = <0x66420000 0x100>; ++ interrupts = ; ++ dma-coherent; ++ bus-width = <8>; ++ clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; ++ status = "disabled"; ++ }; ++ ++ sdio1: sdhci@66430000 { ++ compatible = "brcm,sdhci-iproc-cygnus"; ++ reg = <0x66430000 0x100>; ++ interrupts = ; ++ dma-coherent; ++ bus-width = <8>; ++ clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; ++ status = "disabled"; ++ }; ++ ++ nand: nand@66460000 { ++ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; ++ reg = <0x66460000 0x600>, ++ <0x67015408 0x600>, ++ <0x66460f00 0x20>; ++ reg-names = "nand", "iproc-idm", "iproc-ext"; ++ interrupts = ; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ brcm,nand-has-wp; ++ }; ++ ++ qspi: spi@66470200 { ++ compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"; ++ reg = <0x66470200 0x184>, ++ <0x66470000 0x124>, ++ <0x67017408 0x004>, ++ <0x664703a0 0x01c>; ++ reg-names = "mspi", "bspi", "intr_regs", ++ "intr_status_reg"; ++ interrupts = ; ++ interrupt-names = "spi_l1_intr"; ++ clocks = <&iprocmed>; ++ clock-names = "iprocmed"; ++ num-cs = <2>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ }; ++}; +diff --git a/arch/arm64/boot/dts/broadcom/ns2-clock.dtsi b/arch/arm64/boot/dts/broadcom/ns2-clock.dtsi +deleted file mode 100644 +index 99009fdf10a4..000000000000 +--- a/arch/arm64/boot/dts/broadcom/ns2-clock.dtsi ++++ /dev/null +@@ -1,105 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright (c) 2016 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-#include +- +- osc: oscillator { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <25000000>; +- }; +- +- lcpll_ddr: lcpll_ddr@6501d058 { +- #clock-cells = <1>; +- compatible = "brcm,ns2-lcpll-ddr"; +- reg = <0x6501d058 0x20>, +- <0x6501c020 0x4>, +- <0x6501d04c 0x4>; +- clocks = <&osc>; +- clock-output-names = "lcpll_ddr", "pcie_sata_usb", +- "ddr", "ddr_ch2_unused", +- "ddr_ch3_unused", "ddr_ch4_unused", +- "ddr_ch5_unused"; +- }; +- +- lcpll_ports: lcpll_ports@6501d078 { +- #clock-cells = <1>; +- compatible = "brcm,ns2-lcpll-ports"; +- reg = <0x6501d078 0x20>, +- <0x6501c020 0x4>, +- <0x6501d054 0x4>; +- clocks = <&osc>; +- clock-output-names = "lcpll_ports", "wan", "rgmii", +- "ports_ch2_unused", +- "ports_ch3_unused", +- "ports_ch4_unused", +- "ports_ch5_unused"; +- }; +- +- genpll_scr: genpll_scr@6501d098 { +- #clock-cells = <1>; +- compatible = "brcm,ns2-genpll-scr"; +- reg = <0x6501d098 0x32>, +- <0x6501c020 0x4>, +- <0x6501d044 0x4>; +- clocks = <&osc>; +- clock-output-names = "genpll_scr", "scr", "fs", +- "audio_ref", "scr_ch3_unused", +- "scr_ch4_unused", "scr_ch5_unused"; +- }; +- +- iprocmed: iprocmed { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; +- clock-div = <2>; +- clock-mult = <1>; +- }; +- +- iprocslow: iprocslow { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; +- clock-div = <4>; +- clock-mult = <1>; +- }; +- +- genpll_sw: genpll_sw@6501d0c4 { +- #clock-cells = <1>; +- compatible = "brcm,ns2-genpll-sw"; +- reg = <0x6501d0c4 0x32>, +- <0x6501c020 0x4>, +- <0x6501d044 0x4>; +- clocks = <&osc>; +- clock-output-names = "genpll_sw", "rpe", "250", "nic", +- "chimp", "port", "sdio"; +- }; +diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts +deleted file mode 100644 +index ec19fbf928a1..000000000000 +--- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts ++++ /dev/null +@@ -1,236 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2015 Broadcom Corporation. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "ns2.dtsi" +- +-/ { +- model = "Broadcom NS2 SVK"; +- compatible = "brcm,ns2-svk", "brcm,ns2"; +- +- aliases { +- serial0 = &uart3; +- serial1 = &uart0; +- serial2 = &uart1; +- serial3 = &uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x66130000"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x000000000 0x80000000 0x00000000 0x40000000>; +- }; +-}; +- +-&enet { +- status = "okay"; +-}; +- +-&pci_phy0 { +- status = "okay"; +-}; +- +-&pci_phy1 { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie4 { +- status = "okay"; +-}; +- +-&pcie8 { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&uart0 { +- status = "okay"; +-}; +- +-&uart1 { +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- +-&uart3 { +- status = "okay"; +-}; +- +-&ssp0 { +- status = "okay"; +- +- slic@0 { +- compatible = "silabs,si3226x"; +- reg = <0>; +- spi-max-frequency = <5000000>; +- spi-cpha = <1>; +- spi-cpol = <1>; +- pl022,hierarchy = <0>; +- pl022,interface = <0>; +- pl022,slave-tx-disable = <0>; +- pl022,com-mode = <0>; +- pl022,rx-level-trig = <1>; +- pl022,tx-level-trig = <1>; +- pl022,ctrl-len = <11>; +- pl022,wait-state = <0>; +- pl022,duplex = <0>; +- }; +-}; +- +-&ssp1 { +- status = "okay"; +- +- at25@0 { +- compatible = "atmel,at25"; +- reg = <0>; +- spi-max-frequency = <5000000>; +- at25,byte-len = <0x8000>; +- at25,addr-mode = <2>; +- at25,page-size = <64>; +- spi-cpha = <1>; +- spi-cpol = <1>; +- pl022,hierarchy = <0>; +- pl022,interface = <0>; +- pl022,slave-tx-disable = <0>; +- pl022,com-mode = <0>; +- pl022,rx-level-trig = <1>; +- pl022,tx-level-trig = <1>; +- pl022,ctrl-len = <11>; +- pl022,wait-state = <0>; +- pl022,duplex = <0>; +- }; +-}; +- +-&sata_phy0 { +- status = "okay"; +-}; +- +-&sata_phy1 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&sdio0 { +- status = "okay"; +-}; +- +-&sdio1 { +- status = "okay"; +-}; +- +-&nand { +- nandcs@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- nand-bus-width = <16>; +- brcm,nand-oob-sector-size = <16>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&mdio_mux_iproc { +- mdio@10 { +- gphy0: eth-phy@10 { +- enet-phy-lane-swap; +- reg = <0x10>; +- }; +- }; +-}; +- +-&pinctrl { +- pinctrl-names = "default"; +- pinctrl-0 = <&nand_sel>; +- nand_sel: nand_sel { +- function = "nand"; +- groups = "nand_grp"; +- }; +-}; +- +-&qspi { +- bspi-sel = <0>; +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p80"; +- reg = <0x0>; +- spi-max-frequency = <12500000>; +- m25p,fast-read; +- spi-cpol; +- spi-cpha; +- +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x000a0000>; +- }; +- +- partition@a0000 { +- label = "env"; +- reg = <0x000a0000 0x00060000>; +- }; +- +- partition@100000 { +- label = "system"; +- reg = <0x00100000 0x00600000>; +- }; +- +- partition@700000 { +- label = "rootfs"; +- reg = <0x00700000 0x01900000>; +- }; +- }; +-}; +diff --git a/arch/arm64/boot/dts/broadcom/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/ns2-xmc.dts +deleted file mode 100644 +index ab4ae1a32fab..000000000000 +--- a/arch/arm64/boot/dts/broadcom/ns2-xmc.dts ++++ /dev/null +@@ -1,191 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright(c) 2016 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/dts-v1/; +- +-#include "ns2.dtsi" +- +-/ { +- model = "Broadcom NS2 XMC"; +- compatible = "brcm,ns2-xmc", "brcm,ns2"; +- +- aliases { +- serial0 = &uart3; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x66130000"; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x000000000 0x80000000 0x00000001 0x00000000>; +- }; +-}; +- +-&enet { +- status = "okay"; +-}; +- +-&i2c0 { +- status = "okay"; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&mdio_mux_iproc { +- mdio@10 { +- gphy0: eth-phy@10 { +- reg = <0x10>; +- }; +- }; +-}; +- +-&nand { +- nandcs@0 { +- compatible = "brcm,nandcs"; +- reg = <0>; +- nand-ecc-mode = "hw"; +- nand-ecc-strength = <8>; +- nand-ecc-step-size = <512>; +- nand-bus-width = <16>; +- brcm,nand-oob-sector-size = <16>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- partition@0 { +- label = "nboot"; +- reg = <0x00000000 0x00280000>; /* 2.5MB */ +- read-only; +- }; +- +- partition@280000 { +- label = "nenv"; +- reg = <0x00280000 0x00040000>; /* 0.25MB */ +- read-only; +- }; +- +- partition@2c0000 { +- label = "ndtb"; +- reg = <0x002c0000 0x00040000>; /* 0.25MB */ +- read-only; +- }; +- +- partition@300000 { +- label = "nsystem"; +- reg = <0x00300000 0x03d00000>; /* 61MB */ +- read-only; +- }; +- +- partition@4000000 { +- label = "nrootfs"; +- reg = <0x04000000 0x06400000>; /* 100MB */ +- }; +- +- partition@0a400000{ +- label = "ncustfs"; +- reg = <0x0a400000 0x35c00000>; /* 860MB */ +- }; +- }; +-}; +- +-&pci_phy0 { +- status = "okay"; +-}; +- +-&pcie0 { +- status = "okay"; +-}; +- +-&pcie8 { +- status = "okay"; +-}; +- +-&sata_phy0 { +- status = "okay"; +-}; +- +-&sata_phy1 { +- status = "okay"; +-}; +- +-&sata { +- status = "okay"; +-}; +- +-&qspi { +- flash: m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "m25p80"; +- spi-max-frequency = <62500000>; +- m25p,default-addr-width = <3>; +- reg = <0x0 0x0>; +- +- partition@0 { +- label = "bl0"; +- reg = <0x00000000 0x00080000>; /* 512KB */ +- }; +- +- partition@80000 { +- label = "fip"; +- reg = <0x00080000 0x00150000>; /* 1344KB */ +- }; +- +- partition@1e0000 { +- label = "env"; +- reg = <0x001e0000 0x00010000>;/* 64KB */ +- }; +- +- partition@1f0000 { +- label = "dtb"; +- reg = <0x001f0000 0x00010000>; /* 64KB */ +- }; +- +- partition@200000 { +- label = "kernel"; +- reg = <0x00200000 0x00e00000>; /* 14MB */ +- }; +- +- partition@1000000 { +- label = "rootfs"; +- reg = <0x01000000 0x01000000>; /* 16MB */ +- }; +- }; +-}; +- +-&uart3 { +- status = "okay"; +-}; +diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi +deleted file mode 100644 +index 35c8457e3d1f..000000000000 +--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi ++++ /dev/null +@@ -1,765 +0,0 @@ +-/* +- * BSD LICENSE +- * +- * Copyright (c) 2015 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * +- * * Redistributions of source code must retain the above copyright +- * notice, this list of conditions and the following disclaimer. +- * * Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in +- * the documentation and/or other materials provided with the +- * distribution. +- * * Neither the name of Broadcom Corporation nor the names of its +- * contributors may be used to endorse or promote products derived +- * from this software without specific prior written permission. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +-/memreserve/ 0x81000000 0x00200000; +- +-#include +-#include +- +-/ { +- compatible = "brcm,ns2"; +- interrupt-parent = <&gic>; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <2>; +- #size-cells = <0>; +- +- A57_0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57", "arm,armv8"; +- reg = <0 0>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER0_L2>; +- }; +- +- A57_1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57", "arm,armv8"; +- reg = <0 1>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER0_L2>; +- }; +- +- A57_2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57", "arm,armv8"; +- reg = <0 2>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER0_L2>; +- }; +- +- A57_3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a57", "arm,armv8"; +- reg = <0 3>; +- enable-method = "psci"; +- next-level-cache = <&CLUSTER0_L2>; +- }; +- +- CLUSTER0_L2: l2-cache@000 { +- compatible = "cache"; +- }; +- }; +- +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = , +- , +- , +- ; +- interrupt-affinity = <&A57_0>, +- <&A57_1>, +- <&A57_2>, +- <&A57_3>; +- }; +- +- pcie0: pcie@20020000 { +- compatible = "brcm,iproc-pcie"; +- reg = <0 0x20020000 0 0x1000>; +- dma-coherent; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_NONE>; +- +- linux,pci-domain = <0>; +- +- bus-range = <0x00 0xff>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>; +- +- brcm,pcie-ob; +- brcm,pcie-ob-oarr-size; +- brcm,pcie-ob-axi-offset = <0x00000000>; +- brcm,pcie-ob-window-size = <256>; +- +- status = "disabled"; +- +- phys = <&pci_phy0>; +- phy-names = "pcie-phy"; +- +- msi-parent = <&v2m0>; +- }; +- +- pcie4: pcie@50020000 { +- compatible = "brcm,iproc-pcie"; +- reg = <0 0x50020000 0 0x1000>; +- dma-coherent; +- +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_NONE>; +- +- linux,pci-domain = <4>; +- +- bus-range = <0x00 0xff>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>; +- +- brcm,pcie-ob; +- brcm,pcie-ob-oarr-size; +- brcm,pcie-ob-axi-offset = <0x30000000>; +- brcm,pcie-ob-window-size = <256>; +- +- status = "disabled"; +- +- phys = <&pci_phy1>; +- phy-names = "pcie-phy"; +- +- msi-parent = <&v2m0>; +- }; +- +- pcie8: pcie@60c00000 { +- compatible = "brcm,iproc-pcie-paxc"; +- reg = <0 0x60c00000 0 0x1000>; +- dma-coherent; +- linux,pci-domain = <8>; +- +- bus-range = <0x0 0x1>; +- +- #address-cells = <3>; +- #size-cells = <2>; +- device_type = "pci"; +- ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>; +- +- status = "disabled"; +- +- msi-parent = <&v2m0>; +- }; +- +- soc: soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0 0 0xffffffff>; +- +- #include "ns2-clock.dtsi" +- +- enet: ethernet@61000000 { +- compatible = "brcm,ns2-amac"; +- reg = <0x61000000 0x1000>, +- <0x61090000 0x1000>, +- <0x61030000 0x100>; +- reg-names = "amac_base", "idm_base", "nicpm_base"; +- interrupts = ; +- dma-coherent; +- phy-handle = <&gphy0>; +- phy-mode = "rgmii"; +- status = "disabled"; +- }; +- +- pdc0: iproc-pdc0@612c0000 { +- compatible = "brcm,iproc-pdc-mbox"; +- reg = <0x612c0000 0x445>; /* PDC FS0 regs */ +- interrupts = ; +- #mbox-cells = <1>; +- dma-coherent; +- brcm,rx-status-len = <32>; +- brcm,use-bcm-hdr; +- }; +- +- crypto0: crypto@612d0000 { +- compatible = "brcm,spum-crypto"; +- reg = <0x612d0000 0x900>; +- mboxes = <&pdc0 0>; +- }; +- +- pdc1: iproc-pdc1@612e0000 { +- compatible = "brcm,iproc-pdc-mbox"; +- reg = <0x612e0000 0x445>; /* PDC FS1 regs */ +- interrupts = ; +- #mbox-cells = <1>; +- dma-coherent; +- brcm,rx-status-len = <32>; +- brcm,use-bcm-hdr; +- }; +- +- crypto1: crypto@612f0000 { +- compatible = "brcm,spum-crypto"; +- reg = <0x612f0000 0x900>; +- mboxes = <&pdc1 0>; +- }; +- +- pdc2: iproc-pdc2@61300000 { +- compatible = "brcm,iproc-pdc-mbox"; +- reg = <0x61300000 0x445>; /* PDC FS2 regs */ +- interrupts = ; +- #mbox-cells = <1>; +- dma-coherent; +- brcm,rx-status-len = <32>; +- brcm,use-bcm-hdr; +- }; +- +- crypto2: crypto@61310000 { +- compatible = "brcm,spum-crypto"; +- reg = <0x61310000 0x900>; +- mboxes = <&pdc2 0>; +- }; +- +- pdc3: iproc-pdc3@61320000 { +- compatible = "brcm,iproc-pdc-mbox"; +- reg = <0x61320000 0x445>; /* PDC FS3 regs */ +- interrupts = ; +- #mbox-cells = <1>; +- dma-coherent; +- brcm,rx-status-len = <32>; +- brcm,use-bcm-hdr; +- }; +- +- crypto3: crypto@61330000 { +- compatible = "brcm,spum-crypto"; +- reg = <0x61330000 0x900>; +- mboxes = <&pdc3 0>; +- }; +- +- dma0: dma@61360000 { +- compatible = "arm,pl330", "arm,primecell"; +- reg = <0x61360000 0x1000>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- ; +- #dma-cells = <1>; +- #dma-channels = <8>; +- #dma-requests = <32>; +- clocks = <&iprocslow>; +- clock-names = "apb_pclk"; +- }; +- +- smmu: mmu@64000000 { +- compatible = "arm,mmu-500"; +- reg = <0x64000000 0x40000>; +- #global-interrupts = <2>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- , +- ; +- #iommu-cells = <1>; +- }; +- +- pinctrl: pinctrl@6501d130 { +- compatible = "brcm,ns2-pinmux"; +- reg = <0x6501d130 0x08>, +- <0x660a0028 0x04>, +- <0x660009b0 0x40>; +- }; +- +- gpio_aon: gpio@65024800 { +- compatible = "brcm,iproc-gpio"; +- reg = <0x65024800 0x50>, +- <0x65024008 0x18>; +- ngpios = <6>; +- #gpio-cells = <2>; +- gpio-controller; +- }; +- +- gic: interrupt-controller@65210000 { +- compatible = "arm,gic-400"; +- #interrupt-cells = <3>; +- interrupt-controller; +- reg = <0x65210000 0x1000>, +- <0x65220000 0x1000>, +- <0x65240000 0x2000>, +- <0x65260000 0x1000>; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x652e0000 0x80000>; +- +- v2m0: v2m@00000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x00000 0x1000>; +- arm,msi-base-spi = <72>; +- arm,msi-num-spis = <16>; +- }; +- +- v2m1: v2m@10000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x10000 0x1000>; +- arm,msi-base-spi = <88>; +- arm,msi-num-spis = <16>; +- }; +- +- v2m2: v2m@20000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x20000 0x1000>; +- arm,msi-base-spi = <104>; +- arm,msi-num-spis = <16>; +- }; +- +- v2m3: v2m@30000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x30000 0x1000>; +- arm,msi-base-spi = <120>; +- arm,msi-num-spis = <16>; +- }; +- +- v2m4: v2m@40000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x40000 0x1000>; +- arm,msi-base-spi = <136>; +- arm,msi-num-spis = <16>; +- }; +- +- v2m5: v2m@50000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x50000 0x1000>; +- arm,msi-base-spi = <152>; +- arm,msi-num-spis = <16>; +- }; +- +- v2m6: v2m@60000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x60000 0x1000>; +- arm,msi-base-spi = <168>; +- arm,msi-num-spis = <16>; +- }; +- +- v2m7: v2m@70000 { +- compatible = "arm,gic-v2m-frame"; +- interrupt-parent = <&gic>; +- msi-controller; +- reg = <0x70000 0x1000>; +- arm,msi-base-spi = <184>; +- arm,msi-num-spis = <16>; +- }; +- }; +- +- cci@65590000 { +- compatible = "arm,cci-400"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x65590000 0x1000>; +- ranges = <0 0x65590000 0x10000>; +- +- pmu@9000 { +- compatible = "arm,cci-400-pmu,r1", +- "arm,cci-400-pmu"; +- reg = <0x9000 0x4000>; +- interrupts = , +- , +- , +- , +- , +- ; +- }; +- }; +- +- usbdrd_phy: phy@66000960 { +- #phy-cells = <0>; +- compatible = "brcm,ns2-drd-phy"; +- reg = <0x66000960 0x24>, +- <0x67012800 0x4>, +- <0x6501d148 0x4>, +- <0x664d0700 0x4>; +- reg-names = "icfg", "rst-ctrl", +- "crmu-ctrl", "usb2-strap"; +- id-gpios = <&gpio_g 30 0>; +- vbus-gpios = <&gpio_g 31 0>; +- status = "disabled"; +- }; +- +- pwm: pwm@66010000 { +- compatible = "brcm,iproc-pwm"; +- reg = <0x66010000 0x28>; +- clocks = <&osc>; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- mdio_mux_iproc: mdio-mux@6602023c { +- compatible = "brcm,mdio-mux-iproc"; +- reg = <0x6602023c 0x14>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- mdio@0 { +- reg = <0x0>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pci_phy0: pci-phy@0 { +- compatible = "brcm,ns2-pcie-phy"; +- reg = <0x0>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- mdio@7 { +- reg = <0x7>; +- #address-cells = <1>; +- #size-cells = <0>; +- +- pci_phy1: pci-phy@0 { +- compatible = "brcm,ns2-pcie-phy"; +- reg = <0x0>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- mdio@10 { +- reg = <0x10>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- }; +- +- timer0: timer@66030000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x66030000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, +- <&iprocslow>, +- <&iprocslow>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- timer1: timer@66040000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x66040000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, +- <&iprocslow>, +- <&iprocslow>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- timer2: timer@66050000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x66050000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, +- <&iprocslow>, +- <&iprocslow>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- timer3: timer@66060000 { +- compatible = "arm,sp804", "arm,primecell"; +- reg = <0x66060000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, +- <&iprocslow>, +- <&iprocslow>; +- clock-names = "timer1", "timer2", "apb_pclk"; +- }; +- +- i2c0: i2c@66080000 { +- compatible = "brcm,iproc-i2c"; +- reg = <0x66080000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <100000>; +- status = "disabled"; +- }; +- +- wdt0: watchdog@66090000 { +- compatible = "arm,sp805", "arm,primecell"; +- reg = <0x66090000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, <&iprocslow>; +- clock-names = "wdogclk", "apb_pclk"; +- }; +- +- gpio_g: gpio@660a0000 { +- compatible = "brcm,iproc-gpio"; +- reg = <0x660a0000 0x50>; +- ngpios = <32>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- interrupts = ; +- }; +- +- i2c1: i2c@660b0000 { +- compatible = "brcm,iproc-i2c"; +- reg = <0x660b0000 0x100>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- clock-frequency = <100000>; +- status = "disabled"; +- }; +- +- uart0: serial@66100000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x66100000 0x100>; +- interrupts = ; +- clocks = <&iprocslow>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart1: serial@66110000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x66110000 0x100>; +- interrupts = ; +- clocks = <&iprocslow>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart2: serial@66120000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x66120000 0x100>; +- interrupts = ; +- clocks = <&iprocslow>; +- reg-shift = <2>; +- reg-io-width = <4>; +- status = "disabled"; +- }; +- +- uart3: serial@66130000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x66130000 0x100>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&osc>; +- status = "disabled"; +- }; +- +- ssp0: ssp@66180000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x66180000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, <&iprocslow>; +- clock-names = "spiclk", "apb_pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- ssp1: ssp@66190000 { +- compatible = "arm,pl022", "arm,primecell"; +- reg = <0x66190000 0x1000>; +- interrupts = ; +- clocks = <&iprocslow>, <&iprocslow>; +- clock-names = "spiclk", "apb_pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- hwrng: hwrng@66220000 { +- compatible = "brcm,iproc-rng200"; +- reg = <0x66220000 0x28>; +- }; +- +- sata_phy: sata_phy@663f0100 { +- compatible = "brcm,iproc-ns2-sata-phy"; +- reg = <0x663f0100 0x1f00>, +- <0x663f004c 0x10>; +- reg-names = "phy", "phy-ctrl"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- sata_phy0: sata-phy@0 { +- reg = <0>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- sata_phy1: sata-phy@1 { +- reg = <1>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- }; +- +- sata: ahci@663f2000 { +- compatible = "brcm,iproc-ahci", "generic-ahci"; +- reg = <0x663f2000 0x1000>; +- dma-coherent; +- reg-names = "ahci"; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- sata0: sata-port@0 { +- reg = <0>; +- phys = <&sata_phy0>; +- phy-names = "sata-phy"; +- }; +- +- sata1: sata-port@1 { +- reg = <1>; +- phys = <&sata_phy1>; +- phy-names = "sata-phy"; +- }; +- }; +- +- sdio0: sdhci@66420000 { +- compatible = "brcm,sdhci-iproc-cygnus"; +- reg = <0x66420000 0x100>; +- interrupts = ; +- dma-coherent; +- bus-width = <8>; +- clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; +- status = "disabled"; +- }; +- +- sdio1: sdhci@66430000 { +- compatible = "brcm,sdhci-iproc-cygnus"; +- reg = <0x66430000 0x100>; +- interrupts = ; +- dma-coherent; +- bus-width = <8>; +- clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; +- status = "disabled"; +- }; +- +- nand: nand@66460000 { +- compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; +- reg = <0x66460000 0x600>, +- <0x67015408 0x600>, +- <0x66460f00 0x20>; +- reg-names = "nand", "iproc-idm", "iproc-ext"; +- interrupts = ; +- +- #address-cells = <1>; +- #size-cells = <0>; +- +- brcm,nand-has-wp; +- }; +- +- qspi: spi@66470200 { +- compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"; +- reg = <0x66470200 0x184>, +- <0x66470000 0x124>, +- <0x67017408 0x004>, +- <0x664703a0 0x01c>; +- reg-names = "mspi", "bspi", "intr_regs", +- "intr_status_reg"; +- interrupts = ; +- interrupt-names = "spi_l1_intr"; +- clocks = <&iprocmed>; +- clock-names = "iprocmed"; +- num-cs = <2>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- }; +-}; +diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi +index 5dca7d10253b..8862ec907fd8 100644 +--- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi ++++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi +@@ -72,6 +72,78 @@ &memory { /* Default DRAM banks */ + <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */ + }; + ++&sata0 { ++ status = "okay"; ++}; ++ ++&sata_phy0{ ++ status = "okay"; ++}; ++ ++&sata1 { ++ status = "okay"; ++}; ++ ++&sata_phy1{ ++ status = "okay"; ++}; ++ ++&sata2 { ++ status = "okay"; ++}; ++ ++&sata_phy2{ ++ status = "okay"; ++}; ++ ++&sata3 { ++ status = "okay"; ++}; ++ ++&sata_phy3{ ++ status = "okay"; ++}; ++ ++&sata4 { ++ status = "okay"; ++}; ++ ++&sata_phy4{ ++ status = "okay"; ++}; ++ ++&sata5 { ++ status = "okay"; ++}; ++ ++&sata_phy5{ ++ status = "okay"; ++}; ++ ++&sata6 { ++ status = "okay"; ++}; ++ ++&sata_phy6{ ++ status = "okay"; ++}; ++ ++&sata7 { ++ status = "okay"; ++}; ++ ++&sata_phy7{ ++ status = "okay"; ++}; ++ ++&mdio_mux_iproc { ++ mdio@10 { ++ gphy0: eth-phy@10 { ++ reg = <0x10>; ++ }; ++ }; ++}; ++ + &uart1 { + status = "okay"; + }; +@@ -102,6 +174,12 @@ pcf8574: pcf8574@20 { + }; + }; + ++&enet { ++ phy-mode = "rgmii-id"; ++ phy-handle = <&gphy0>; ++ status = "okay"; ++}; ++ + &nand { + status = "ok"; + nandcs@0 { +diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts +index 5671669ba348..eb6f08cdbd79 100644 +--- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts ++++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts +@@ -39,6 +39,10 @@ / { + model = "Stingray Combo SVK (BCM958742K)"; + }; + ++&gphy0 { ++ enet-phy-lane-swap; ++}; ++ + &uart2 { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts +index 6ebe399fda6a..5084b037320f 100644 +--- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts ++++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts +@@ -38,3 +38,7 @@ / { + compatible = "brcm,bcm958742t", "brcm,stingray"; + model = "Stingray SST100 (BCM958742T)"; + }; ++ ++&gphy0 { ++ enet-phy-lane-swap; ++}; +diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi +new file mode 100644 +index 000000000000..8bf1dc6b46ca +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi +@@ -0,0 +1,118 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2016-2017 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ fs4: fs4 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0x67000000 0x00800000>; ++ ++ crypto_mbox: crypto_mbox@00000000 { ++ compatible = "brcm,iproc-flexrm-mbox"; ++ reg = <0x00000000 0x200000>; ++ msi-parent = <&gic_its 0x4100>; ++ #mbox-cells = <3>; ++ dma-coherent; ++ }; ++ ++ raid_mbox: raid_mbox@00400000 { ++ compatible = "brcm,iproc-flexrm-mbox"; ++ reg = <0x00400000 0x200000>; ++ dma-coherent; ++ msi-parent = <&gic_its 0x4300>; ++ #mbox-cells = <3>; ++ }; ++ ++ raid0: raid@0 { ++ compatible = "brcm,iproc-sba-v2"; ++ mboxes = <&raid_mbox 0 0x1 0xff00>, ++ <&raid_mbox 1 0x1 0xff00>, ++ <&raid_mbox 2 0x1 0xff00>, ++ <&raid_mbox 3 0x1 0xff00>; ++ }; ++ ++ raid1: raid@1 { ++ compatible = "brcm,iproc-sba-v2"; ++ mboxes = <&raid_mbox 4 0x1 0xff00>, ++ <&raid_mbox 5 0x1 0xff00>, ++ <&raid_mbox 6 0x1 0xff00>, ++ <&raid_mbox 7 0x1 0xff00>; ++ }; ++ ++ raid2: raid@2 { ++ compatible = "brcm,iproc-sba-v2"; ++ mboxes = <&raid_mbox 8 0x1 0xff00>, ++ <&raid_mbox 9 0x1 0xff00>, ++ <&raid_mbox 10 0x1 0xff00>, ++ <&raid_mbox 11 0x1 0xff00>; ++ }; ++ ++ raid3: raid@3 { ++ compatible = "brcm,iproc-sba-v2"; ++ mboxes = <&raid_mbox 12 0x1 0xff00>, ++ <&raid_mbox 13 0x1 0xff00>, ++ <&raid_mbox 14 0x1 0xff00>, ++ <&raid_mbox 15 0x1 0xff00>; ++ }; ++ ++ raid4: raid@4 { ++ compatible = "brcm,iproc-sba-v2"; ++ mboxes = <&raid_mbox 16 0x1 0xff00>, ++ <&raid_mbox 17 0x1 0xff00>, ++ <&raid_mbox 18 0x1 0xff00>, ++ <&raid_mbox 19 0x1 0xff00>; ++ }; ++ ++ raid5: raid@5 { ++ compatible = "brcm,iproc-sba-v2"; ++ mboxes = <&raid_mbox 20 0x1 0xff00>, ++ <&raid_mbox 21 0x1 0xff00>, ++ <&raid_mbox 22 0x1 0xff00>, ++ <&raid_mbox 23 0x1 0xff00>; ++ }; ++ ++ raid6: raid@6 { ++ compatible = "brcm,iproc-sba-v2"; ++ mboxes = <&raid_mbox 24 0x1 0xff00>, ++ <&raid_mbox 25 0x1 0xff00>, ++ <&raid_mbox 26 0x1 0xff00>, ++ <&raid_mbox 27 0x1 0xff00>; ++ }; ++ ++ raid7: raid@7 { ++ compatible = "brcm,iproc-sba-v2"; ++ mboxes = <&raid_mbox 28 0x1 0xff00>, ++ <&raid_mbox 29 0x1 0xff00>, ++ <&raid_mbox 30 0x1 0xff00>, ++ <&raid_mbox 31 0x1 0xff00>; ++ }; ++ }; +diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi +new file mode 100644 +index 000000000000..a774709388df +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi +@@ -0,0 +1,278 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2016-2017 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ sata { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0x67d00000 0x00800000>; ++ ++ sata0: ahci@00210000 { ++ compatible = "brcm,iproc-ahci", "generic-ahci"; ++ reg = <0x00210000 0x1000>; ++ reg-names = "ahci"; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata0_port0: sata-port@0 { ++ reg = <0>; ++ phys = <&sata0_phy0>; ++ phy-names = "sata-phy"; ++ }; ++ }; ++ ++ sata_phy0: sata_phy@00212100 { ++ compatible = "brcm,iproc-sr-sata-phy"; ++ reg = <0x00212100 0x1000>; ++ reg-names = "phy"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata0_phy0: sata-phy@0 { ++ reg = <0>; ++ #phy-cells = <0>; ++ }; ++ }; ++ ++ sata1: ahci@00310000 { ++ compatible = "brcm,iproc-ahci", "generic-ahci"; ++ reg = <0x00310000 0x1000>; ++ reg-names = "ahci"; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata1_port0: sata-port@0 { ++ reg = <0>; ++ phys = <&sata1_phy0>; ++ phy-names = "sata-phy"; ++ }; ++ }; ++ ++ sata_phy1: sata_phy@00312100 { ++ compatible = "brcm,iproc-sr-sata-phy"; ++ reg = <0x00312100 0x1000>; ++ reg-names = "phy"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata1_phy0: sata-phy@0 { ++ reg = <0>; ++ #phy-cells = <0>; ++ }; ++ }; ++ ++ sata2: ahci@00120000 { ++ compatible = "brcm,iproc-ahci", "generic-ahci"; ++ reg = <0x00120000 0x1000>; ++ reg-names = "ahci"; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata2_port0: sata-port@0 { ++ reg = <0>; ++ phys = <&sata2_phy0>; ++ phy-names = "sata-phy"; ++ }; ++ }; ++ ++ sata_phy2: sata_phy@00122100 { ++ compatible = "brcm,iproc-sr-sata-phy"; ++ reg = <0x00122100 0x1000>; ++ reg-names = "phy"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata2_phy0: sata-phy@0 { ++ reg = <0>; ++ #phy-cells = <0>; ++ }; ++ }; ++ ++ sata3: ahci@00130000 { ++ compatible = "brcm,iproc-ahci", "generic-ahci"; ++ reg = <0x00130000 0x1000>; ++ reg-names = "ahci"; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata3_port0: sata-port@0 { ++ reg = <0>; ++ phys = <&sata3_phy0>; ++ phy-names = "sata-phy"; ++ }; ++ }; ++ ++ sata_phy3: sata_phy@00132100 { ++ compatible = "brcm,iproc-sr-sata-phy"; ++ reg = <0x00132100 0x1000>; ++ reg-names = "phy"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata3_phy0: sata-phy@0 { ++ reg = <0>; ++ #phy-cells = <0>; ++ }; ++ }; ++ ++ sata4: ahci@00330000 { ++ compatible = "brcm,iproc-ahci", "generic-ahci"; ++ reg = <0x00330000 0x1000>; ++ reg-names = "ahci"; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata4_port0: sata-port@0 { ++ reg = <0>; ++ phys = <&sata4_phy0>; ++ phy-names = "sata-phy"; ++ }; ++ }; ++ ++ sata_phy4: sata_phy@00332100 { ++ compatible = "brcm,iproc-sr-sata-phy"; ++ reg = <0x00332100 0x1000>; ++ reg-names = "phy"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata4_phy0: sata-phy@0 { ++ reg = <0>; ++ #phy-cells = <0>; ++ }; ++ }; ++ ++ sata5: ahci@00400000 { ++ compatible = "brcm,iproc-ahci", "generic-ahci"; ++ reg = <0x00400000 0x1000>; ++ reg-names = "ahci"; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata5_port0: sata-port@0 { ++ reg = <0>; ++ phys = <&sata5_phy0>; ++ phy-names = "sata-phy"; ++ }; ++ }; ++ ++ sata_phy5: sata_phy@00402100 { ++ compatible = "brcm,iproc-sr-sata-phy"; ++ reg = <0x00402100 0x1000>; ++ reg-names = "phy"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata5_phy0: sata-phy@0 { ++ reg = <0>; ++ #phy-cells = <0>; ++ }; ++ }; ++ ++ sata6: ahci@00410000 { ++ compatible = "brcm,iproc-ahci", "generic-ahci"; ++ reg = <0x00410000 0x1000>; ++ reg-names = "ahci"; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata6_port0: sata-port@0 { ++ reg = <0>; ++ phys = <&sata6_phy0>; ++ phy-names = "sata-phy"; ++ }; ++ }; ++ ++ sata_phy6: sata_phy@00412100 { ++ compatible = "brcm,iproc-sr-sata-phy"; ++ reg = <0x00412100 0x1000>; ++ reg-names = "phy"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata6_phy0: sata-phy@0 { ++ reg = <0>; ++ #phy-cells = <0>; ++ }; ++ }; ++ ++ sata7: ahci@00420000 { ++ compatible = "brcm,iproc-ahci", "generic-ahci"; ++ reg = <0x00420000 0x1000>; ++ reg-names = "ahci"; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata7_port0: sata-port@0 { ++ reg = <0>; ++ phys = <&sata7_phy0>; ++ phy-names = "sata-phy"; ++ }; ++ }; ++ ++ sata_phy7: sata_phy@00422100 { ++ compatible = "brcm,iproc-sr-sata-phy"; ++ reg = <0x00422100 0x1000>; ++ reg-names = "phy"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ sata7_phy0: sata-phy@0 { ++ reg = <0>; ++ #phy-cells = <0>; ++ }; ++ }; ++ }; +diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +index 49933cf16c92..e6f75c633623 100644 +--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi ++++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +@@ -152,6 +152,12 @@ scr { + #size-cells = <1>; + ranges = <0x0 0x0 0x61000000 0x05000000>; + ++ ccn: ccn@00000000 { ++ compatible = "arm,ccn-502"; ++ reg = <0x00000000 0x900000>; ++ interrupts = ; ++ }; ++ + gic: interrupt-controller@02c00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; +@@ -261,6 +267,9 @@ gpio_crmu: gpio@00024800 { + }; + }; + ++ #include "stingray-fs4.dtsi" ++ #include "stingray-sata.dtsi" ++ + hsls { + compatible = "simple-bus"; + #address-cells = <1>; +@@ -269,6 +278,37 @@ hsls { + + #include "stingray-pinctrl.dtsi" + ++ mdio_mux_iproc: mdio-mux@0002023c { ++ compatible = "brcm,mdio-mux-iproc"; ++ reg = <0x0002023c 0x14>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ mdio@0 { /* PCIe serdes */ ++ reg = <0x0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@2 { /* SATA */ ++ reg = <0x2>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@3 { /* USB */ ++ reg = <0x3>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@10 { /* RGMII */ ++ reg = <0x10>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ + pwm: pwm@00010000 { + compatible = "brcm,iproc-pwm"; + reg = <0x00010000 0x1000>; +@@ -277,6 +317,93 @@ pwm: pwm@00010000 { + status = "disabled"; + }; + ++ timer0: timer@00030000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x00030000 0x1000>; ++ interrupts = ; ++ clocks = <&hsls_25m_div2_clk>, ++ <&hsls_25m_div2_clk>, ++ <&hsls_div4_clk>; ++ clock-names = "timer1", "timer2", "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ timer1: timer@00040000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x00040000 0x1000>; ++ interrupts = ; ++ clocks = <&hsls_25m_div2_clk>, ++ <&hsls_25m_div2_clk>, ++ <&hsls_div4_clk>; ++ clock-names = "timer1", "timer2", "apb_pclk"; ++ }; ++ ++ timer2: timer@00050000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x00050000 0x1000>; ++ interrupts = ; ++ clocks = <&hsls_25m_div2_clk>, ++ <&hsls_25m_div2_clk>, ++ <&hsls_div4_clk>; ++ clock-names = "timer1", "timer2", "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ timer3: timer@00060000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x00060000 0x1000>; ++ interrupts = ; ++ clocks = <&hsls_25m_div2_clk>, ++ <&hsls_25m_div2_clk>, ++ <&hsls_div4_clk>; ++ clock-names = "timer1", "timer2", "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ timer4: timer@00070000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x00070000 0x1000>; ++ interrupts = ; ++ clocks = <&hsls_25m_div2_clk>, ++ <&hsls_25m_div2_clk>, ++ <&hsls_div4_clk>; ++ clock-names = "timer1", "timer2", "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ timer5: timer@00080000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x00080000 0x1000>; ++ interrupts = ; ++ clocks = <&hsls_25m_div2_clk>, ++ <&hsls_25m_div2_clk>, ++ <&hsls_div4_clk>; ++ clock-names = "timer1", "timer2", "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ timer6: timer@00090000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x00090000 0x1000>; ++ interrupts = ; ++ clocks = <&hsls_25m_div2_clk>, ++ <&hsls_25m_div2_clk>, ++ <&hsls_div4_clk>; ++ clock-names = "timer1", "timer2", "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ timer7: timer@000a0000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x000a0000 0x1000>; ++ interrupts = ; ++ clocks = <&hsls_25m_div2_clk>, ++ <&hsls_25m_div2_clk>, ++ <&hsls_div4_clk>; ++ clock-names = "timer1", "timer2", "apb_pclk"; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@000b0000 { + compatible = "brcm,iproc-i2c"; + reg = <0x000b0000 0x100>; +@@ -424,6 +551,15 @@ dma0: dma@00310000 { + iommus = <&smmu 0x6000 0x0000>; + }; + ++ enet: ethernet@00340000{ ++ compatible = "brcm,amac"; ++ reg = <0x00340000 0x1000>; ++ reg-names = "amac_base"; ++ dma-coherent; ++ interrupts = ; ++ status= "disabled"; ++ }; ++ + nand: nand@00360000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x00360000 0x600>, +diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +index 105b2938082f..297597442c44 100644 +--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi ++++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +@@ -307,20 +307,6 @@ &dsi { + samsung,pll-clock-frequency = <24000000>; + pinctrl-names = "default"; + pinctrl-0 = <&te_irq>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@1 { +- reg = <1>; +- +- dsi_out: endpoint { +- samsung,burst-clock-frequency = <512000000>; +- samsung,esc-clock-frequency = <16000000>; +- }; +- }; +- }; + }; + + &hdmi { +@@ -843,7 +829,6 @@ &i2s0 { + + &mshc_0 { + status = "okay"; +- num-slots = <1>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; +@@ -865,7 +850,6 @@ &mshc_0 { + + &mshc_2 { + status = "okay"; +- num-slots = <1>; + cap-sd-highspeed; + disable-wp; + cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>; +@@ -1210,8 +1194,9 @@ &usbdrd30 { + status = "okay"; + }; + +-&usbdrd_dwc3_0 { ++&usbdrd_dwc3 { + dr_mode = "otg"; ++ extcon = <&muic>; + }; + + &usbdrd30_phy { +diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi +index 727f36abf3d4..7fe994b750da 100644 +--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi ++++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi +@@ -1367,7 +1367,7 @@ usbdrd30: usbdrd { + ranges; + status = "disabled"; + +- dwc3@15400000 { ++ usbdrd_dwc3: dwc3@15400000 { + compatible = "snps,dwc3"; + reg = <0x15400000 0x10000>; + interrupts = ; +@@ -1414,7 +1414,7 @@ usbhost30: usbhost { + ranges; + status = "disabled"; + +- usbdrd_dwc3_0: dwc3@15a00000 { ++ usbhost_dwc3: dwc3@15a00000 { + compatible = "snps,dwc3"; + reg = <0x15a00000 0x10000>; + interrupts = ; +diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +index e5892bb0ae6e..4a8b1fb51243 100644 +--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts ++++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +@@ -359,7 +359,6 @@ pmic_irq: pmic-irq { + + &mmc_0 { + status = "okay"; +- num-slots = <1>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; +@@ -375,7 +374,6 @@ &mmc_0 { + + &mmc_2 { + status = "okay"; +- num-slots = <1>; + cap-sd-highspeed; + card-detect-delay = <200>; + clock-frequency = <400000000>; +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +index b1554cbd2c54..df83915d6ea6 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +@@ -444,6 +444,15 @@ edma0: edma@2c00000 { + <&clockgen 4 3>; + }; + ++ usb0: usb3@2f00000 { ++ compatible = "snps,dwc3"; ++ reg = <0x0 0x2f00000 0x0 0x10000>; ++ interrupts = <0 60 0x4>; ++ dr_mode = "host"; ++ snps,quirk-frame-length-adjustment = <0x20>; ++ snps,dis_rxdet_inp3_quirk; ++ }; ++ + sata: sata@3200000 { + compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>, +@@ -454,5 +463,13 @@ sata: sata@3200000 { + dma-coherent; + status = "disabled"; + }; ++ ++ usb1: usb2@8600000 { ++ compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; ++ reg = <0x0 0x8600000 0x0 0x1000>; ++ interrupts = <0 139 0x4>; ++ dr_mode = "host"; ++ phy_type = "ulpi"; ++ }; + }; + }; +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +index 213abb72de93..0f6fcda36b9e 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +@@ -49,7 +49,7 @@ + #include "fsl-ls1088a.dtsi" + + / { +- model = "L1088A RDB Board"; ++ model = "LS1088A RDB Board"; + compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; + }; + +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +index c144d06a6e33..33797b373674 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +@@ -52,6 +52,10 @@ / { + #address-cells = <2>; + #size-cells = <2>; + ++ aliases { ++ crypto = &crypto; ++ }; ++ + cpus { + #address-cells = <1>; + #size-cells = <0>; +@@ -62,6 +66,7 @@ cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x0>; + clocks = <&clockgen 1 0>; ++ cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + +@@ -70,6 +75,7 @@ cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x1>; + clocks = <&clockgen 1 0>; ++ cpu-idle-states = <&CPU_PH20>; + }; + + cpu2: cpu@2 { +@@ -77,6 +83,7 @@ cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x2>; + clocks = <&clockgen 1 0>; ++ cpu-idle-states = <&CPU_PH20>; + }; + + cpu3: cpu@3 { +@@ -84,6 +91,7 @@ cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x3>; + clocks = <&clockgen 1 0>; ++ cpu-idle-states = <&CPU_PH20>; + }; + + cpu4: cpu@100 { +@@ -91,6 +99,7 @@ cpu4: cpu@100 { + compatible = "arm,cortex-a53"; + reg = <0x100>; + clocks = <&clockgen 1 1>; ++ cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + +@@ -99,6 +108,7 @@ cpu5: cpu@101 { + compatible = "arm,cortex-a53"; + reg = <0x101>; + clocks = <&clockgen 1 1>; ++ cpu-idle-states = <&CPU_PH20>; + }; + + cpu6: cpu@102 { +@@ -106,6 +116,7 @@ cpu6: cpu@102 { + compatible = "arm,cortex-a53"; + reg = <0x102>; + clocks = <&clockgen 1 1>; ++ cpu-idle-states = <&CPU_PH20>; + }; + + cpu7: cpu@103 { +@@ -113,6 +124,16 @@ cpu7: cpu@103 { + compatible = "arm,cortex-a53"; + reg = <0x103>; + clocks = <&clockgen 1 1>; ++ cpu-idle-states = <&CPU_PH20>; ++ }; ++ ++ CPU_PH20: cpu-ph20 { ++ compatible = "arm,idle-state"; ++ idle-state-name = "PH20"; ++ arm,psci-suspend-param = <0x00010000>; ++ entry-latency-us = <1000>; ++ exit-latency-us = <1000>; ++ min-residency-us = <3000>; + }; + }; + +@@ -136,6 +157,11 @@ timer { + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ + }; + ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; +@@ -369,6 +395,45 @@ sata: sata@3200000 { + dma-coherent; + status = "disabled"; + }; ++ ++ crypto: crypto@8000000 { ++ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; ++ fsl,sec-era = <8>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x00 0x8000000 0x100000>; ++ reg = <0x00 0x8000000 0x0 0x100000>; ++ interrupts = ; ++ dma-coherent; ++ ++ sec_jr0: jr@10000 { ++ compatible = "fsl,sec-v5.0-job-ring", ++ "fsl,sec-v4.0-job-ring"; ++ reg = <0x10000 0x10000>; ++ interrupts = ; ++ }; ++ ++ sec_jr1: jr@20000 { ++ compatible = "fsl,sec-v5.0-job-ring", ++ "fsl,sec-v4.0-job-ring"; ++ reg = <0x20000 0x10000>; ++ interrupts = ; ++ }; ++ ++ sec_jr2: jr@30000 { ++ compatible = "fsl,sec-v5.0-job-ring", ++ "fsl,sec-v4.0-job-ring"; ++ reg = <0x30000 0x10000>; ++ interrupts = ; ++ }; ++ ++ sec_jr3: jr@40000 { ++ compatible = "fsl,sec-v5.0-job-ring", ++ "fsl,sec-v4.0-job-ring"; ++ reg = <0x40000 0x10000>; ++ interrupts = ; ++ }; ++ }; + }; + + }; +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts +index ed209cd57283..3c99608b9b45 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts +@@ -55,11 +55,6 @@ / { + model = "Freescale Layerscape 2080a QDS Board"; + compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; + +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- }; +- + chosen { + stdout-path = "serial0:115200n8"; + }; +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts +index 67ec3f9c81a1..a4e7de9f70d8 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts +@@ -55,11 +55,6 @@ / { + model = "Freescale Layerscape 2080a RDB Board"; + compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; + +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- }; +- + chosen { + stdout-path = "serial1:115200n8"; + }; +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts +index 3ee718f0aaf8..fbbb73e571c0 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts +@@ -52,11 +52,6 @@ / { + model = "Freescale Layerscape 2080a software Simulator model"; + compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; + +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- }; +- + ethernet@2210000 { + compatible = "smsc,lan91c111"; + reg = <0x0 0x2210000 0x0 0x100>; +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +index d789c6814e6a..8d739301e7b8 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +@@ -53,6 +53,7 @@ cpu0: cpu@0 { + compatible = "arm,cortex-a57"; + reg = <0x0>; + clocks = <&clockgen 1 0>; ++ cpu-idle-states = <&CPU_PW20>; + next-level-cache = <&cluster0_l2>; + #cooling-cells = <2>; + }; +@@ -62,6 +63,7 @@ cpu1: cpu@1 { + compatible = "arm,cortex-a57"; + reg = <0x1>; + clocks = <&clockgen 1 0>; ++ cpu-idle-states = <&CPU_PW20>; + next-level-cache = <&cluster0_l2>; + }; + +@@ -70,6 +72,7 @@ cpu2: cpu@100 { + compatible = "arm,cortex-a57"; + reg = <0x100>; + clocks = <&clockgen 1 1>; ++ cpu-idle-states = <&CPU_PW20>; + next-level-cache = <&cluster1_l2>; + #cooling-cells = <2>; + }; +@@ -79,6 +82,7 @@ cpu3: cpu@101 { + compatible = "arm,cortex-a57"; + reg = <0x101>; + clocks = <&clockgen 1 1>; ++ cpu-idle-states = <&CPU_PW20>; + next-level-cache = <&cluster1_l2>; + }; + +@@ -87,6 +91,7 @@ cpu4: cpu@200 { + compatible = "arm,cortex-a57"; + reg = <0x200>; + clocks = <&clockgen 1 2>; ++ cpu-idle-states = <&CPU_PW20>; + next-level-cache = <&cluster2_l2>; + #cooling-cells = <2>; + }; +@@ -96,6 +101,7 @@ cpu5: cpu@201 { + compatible = "arm,cortex-a57"; + reg = <0x201>; + clocks = <&clockgen 1 2>; ++ cpu-idle-states = <&CPU_PW20>; + next-level-cache = <&cluster2_l2>; + }; + +@@ -105,6 +111,7 @@ cpu6: cpu@300 { + reg = <0x300>; + clocks = <&clockgen 1 3>; + next-level-cache = <&cluster3_l2>; ++ cpu-idle-states = <&CPU_PW20>; + #cooling-cells = <2>; + }; + +@@ -113,6 +120,7 @@ cpu7: cpu@301 { + compatible = "arm,cortex-a57"; + reg = <0x301>; + clocks = <&clockgen 1 3>; ++ cpu-idle-states = <&CPU_PW20>; + next-level-cache = <&cluster3_l2>; + }; + +@@ -131,6 +139,15 @@ cluster2_l2: l2-cache2 { + cluster3_l2: l2-cache3 { + compatible = "cache"; + }; ++ ++ CPU_PW20: cpu-pw20 { ++ compatible = "arm,idle-state"; ++ idle-state-name = "PW20"; ++ arm,psci-suspend-param = <0x00010000>; ++ entry-latency-us = <2000>; ++ exit-latency-us = <2000>; ++ min-residency-us = <6000>; ++ }; + }; + + &pcie1 { +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts +index 4a1df5ce3229..eaee5b1c3a44 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts +@@ -54,11 +54,6 @@ / { + model = "Freescale Layerscape 2088A QDS Board"; + compatible = "fsl,ls2088a-qds", "fsl,ls2088a"; + +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- }; +- + chosen { + stdout-path = "serial0:115200n8"; + }; +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +index a76d4b4debd1..c411442cac62 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +@@ -54,11 +54,6 @@ / { + model = "Freescale Layerscape 2088A RDB Board"; + compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; + +- aliases { +- serial0 = &serial0; +- serial1 = &serial1; +- }; +- + chosen { + stdout-path = "serial1:115200n8"; + }; +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +index 5c695c658056..6aa319dae396 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +@@ -53,6 +53,7 @@ cpu0: cpu@0 { + compatible = "arm,cortex-a72"; + reg = <0x0>; + clocks = <&clockgen 1 0>; ++ cpu-idle-states = <&CPU_PW20>; + next-level-cache = <&cluster0_l2>; + #cooling-cells = <2>; + }; +@@ -62,6 +63,7 @@ cpu1: cpu@1 { + compatible = "arm,cortex-a72"; + reg = <0x1>; + clocks = <&clockgen 1 0>; ++ cpu-idle-states = <&CPU_PW20>; + next-level-cache = <&cluster0_l2>; + }; + +@@ -70,6 +72,7 @@ cpu2: cpu@100 { + compatible = "arm,cortex-a72"; + reg = <0x100>; + clocks = <&clockgen 1 1>; ++ cpu-idle-states = <&CPU_PW20>; + next-level-cache = <&cluster1_l2>; + #cooling-cells = <2>; + }; +@@ -79,6 +82,7 @@ cpu3: cpu@101 { + compatible = "arm,cortex-a72"; + reg = <0x101>; + clocks = <&clockgen 1 1>; ++ cpu-idle-states = <&CPU_PW20>; + next-level-cache = <&cluster1_l2>; + }; + +@@ -88,6 +92,7 @@ cpu4: cpu@200 { + reg = <0x200>; + clocks = <&clockgen 1 2>; + next-level-cache = <&cluster2_l2>; ++ cpu-idle-states = <&CPU_PW20>; + #cooling-cells = <2>; + }; + +@@ -96,6 +101,7 @@ cpu5: cpu@201 { + compatible = "arm,cortex-a72"; + reg = <0x201>; + clocks = <&clockgen 1 2>; ++ cpu-idle-states = <&CPU_PW20>; + next-level-cache = <&cluster2_l2>; + }; + +@@ -104,6 +110,7 @@ cpu6: cpu@300 { + compatible = "arm,cortex-a72"; + reg = <0x300>; + clocks = <&clockgen 1 3>; ++ cpu-idle-states = <&CPU_PW20>; + next-level-cache = <&cluster3_l2>; + #cooling-cells = <2>; + }; +@@ -113,6 +120,7 @@ cpu7: cpu@301 { + compatible = "arm,cortex-a72"; + reg = <0x301>; + clocks = <&clockgen 1 3>; ++ cpu-idle-states = <&CPU_PW20>; + next-level-cache = <&cluster3_l2>; + }; + +@@ -131,6 +139,15 @@ cluster2_l2: l2-cache2 { + cluster3_l2: l2-cache3 { + compatible = "cache"; + }; ++ ++ CPU_PW20: cpu-pw20 { ++ compatible = "arm,idle-state"; ++ idle-state-name = "PW20"; ++ arm,psci-suspend-param = <0x00010000>; ++ entry-latency-us = <2000>; ++ exit-latency-us = <2000>; ++ min-residency-us = <6000>; ++ }; + }; + + &pcie1 { +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +index 94cdd3045037..4fb9a0966a84 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +@@ -46,6 +46,7 @@ + */ + + #include ++#include + + / { + compatible = "fsl,ls2080a"; +@@ -53,6 +54,12 @@ / { + #address-cells = <2>; + #size-cells = <2>; + ++ aliases { ++ crypto = &crypto; ++ serial0 = &serial0; ++ serial1 = &serial1; ++ }; ++ + cpu: cpus { + #address-cells = <1>; + #size-cells = <0>; +@@ -118,6 +125,11 @@ pmu { + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ + }; + ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ + soc { + compatible = "simple-bus"; + #address-cells = <2>; +@@ -301,6 +313,45 @@ cluster4_core1_watchdog: wdt@c310000 { + clock-names = "apb_pclk", "wdog_clk"; + }; + ++ crypto: crypto@8000000 { ++ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; ++ fsl,sec-era = <8>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x00 0x8000000 0x100000>; ++ reg = <0x00 0x8000000 0x0 0x100000>; ++ interrupts = ; ++ dma-coherent; ++ ++ sec_jr0: jr@10000 { ++ compatible = "fsl,sec-v5.0-job-ring", ++ "fsl,sec-v4.0-job-ring"; ++ reg = <0x10000 0x10000>; ++ interrupts = ; ++ }; ++ ++ sec_jr1: jr@20000 { ++ compatible = "fsl,sec-v5.0-job-ring", ++ "fsl,sec-v4.0-job-ring"; ++ reg = <0x20000 0x10000>; ++ interrupts = ; ++ }; ++ ++ sec_jr2: jr@30000 { ++ compatible = "fsl,sec-v5.0-job-ring", ++ "fsl,sec-v4.0-job-ring"; ++ reg = <0x30000 0x10000>; ++ interrupts = ; ++ }; ++ ++ sec_jr3: jr@40000 { ++ compatible = "fsl,sec-v5.0-job-ring", ++ "fsl,sec-v4.0-job-ring"; ++ reg = <0x40000 0x10000>; ++ interrupts = ; ++ }; ++ }; ++ + fsl_mc: fsl-mc@80c000000 { + compatible = "fsl,qoriq-mc"; + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ +diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +index 6609b0fe7a8b..fd4705c451e2 100644 +--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts ++++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +@@ -39,6 +39,34 @@ memory@0 { + reg = <0x0 0x0 0x0 0x0>; + }; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ ramoops@32000000 { ++ compatible = "ramoops"; ++ reg = <0x0 0x32000000 0x0 0x00100000>; ++ record-size = <0x00020000>; ++ console-size = <0x00020000>; ++ ftrace-size = <0x00020000>; ++ }; ++ }; ++ ++ reboot-mode-syscon@32100000 { ++ compatible = "syscon", "simple-mfd"; ++ reg = <0x0 0x32100000 0x0 0x00001000>; ++ ++ reboot-mode { ++ compatible = "syscon-reboot-mode"; ++ offset = <0x0>; ++ ++ mode-normal = <0x77665501>; ++ mode-bootloader = <0x77665500>; ++ mode-recovery = <0x77665502>; ++ }; ++ }; ++ + keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; +@@ -159,6 +187,13 @@ wlan_en: wlan-en-1-8v { + startup-delay-us = <70000>; + enable-active-high; + }; ++ ++ firmware { ++ optee { ++ compatible = "linaro,optee-tz"; ++ method = "smc"; ++ }; ++ }; + }; + + &i2c0 { +@@ -195,7 +230,7 @@ &uart4 { + bluetooth { + compatible = "ti,wl1837-st"; + enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>; +- max-speed = <921600>; ++ max-speed = <3000000>; + }; + }; + +diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +index c6a1961e8d55..b7a90d632959 100644 +--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi ++++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +@@ -58,6 +58,8 @@ cpu0: cpu@0 { + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; ++ next-level-cache = <&A53_L2>; ++ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + }; + + cpu1: cpu@1 { +@@ -65,6 +67,8 @@ cpu1: cpu@1 { + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; ++ next-level-cache = <&A53_L2>; ++ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + }; + + cpu2: cpu@2 { +@@ -72,6 +76,8 @@ cpu2: cpu@2 { + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; ++ next-level-cache = <&A53_L2>; ++ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + }; + + cpu3: cpu@3 { +@@ -79,6 +85,8 @@ cpu3: cpu@3 { + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; ++ next-level-cache = <&A53_L2>; ++ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + }; + + cpu4: cpu@100 { +@@ -86,6 +94,12 @@ cpu4: cpu@100 { + device_type = "cpu"; + reg = <0x0 0x100>; + enable-method = "psci"; ++ next-level-cache = <&A73_L2>; ++ cpu-idle-states = < ++ &CPU_NAP ++ &CPU_SLEEP ++ &CLUSTER_SLEEP_1 ++ >; + }; + + cpu5: cpu@101 { +@@ -93,6 +107,12 @@ cpu5: cpu@101 { + device_type = "cpu"; + reg = <0x0 0x101>; + enable-method = "psci"; ++ next-level-cache = <&A73_L2>; ++ cpu-idle-states = < ++ &CPU_NAP ++ &CPU_SLEEP ++ &CLUSTER_SLEEP_1 ++ >; + }; + + cpu6: cpu@102 { +@@ -100,6 +120,12 @@ cpu6: cpu@102 { + device_type = "cpu"; + reg = <0x0 0x102>; + enable-method = "psci"; ++ next-level-cache = <&A73_L2>; ++ cpu-idle-states = < ++ &CPU_NAP ++ &CPU_SLEEP ++ &CLUSTER_SLEEP_1 ++ >; + }; + + cpu7: cpu@103 { +@@ -107,6 +133,59 @@ cpu7: cpu@103 { + device_type = "cpu"; + reg = <0x0 0x103>; + enable-method = "psci"; ++ next-level-cache = <&A73_L2>; ++ cpu-idle-states = < ++ &CPU_NAP ++ &CPU_SLEEP ++ &CLUSTER_SLEEP_1 ++ >; ++ }; ++ ++ idle-states { ++ entry-method = "psci"; ++ ++ CPU_NAP: cpu-nap { ++ compatible = "arm,idle-state"; ++ arm,psci-suspend-param = <0x0000001>; ++ entry-latency-us = <7>; ++ exit-latency-us = <2>; ++ min-residency-us = <15>; ++ }; ++ ++ CPU_SLEEP: cpu-sleep { ++ compatible = "arm,idle-state"; ++ local-timer-stop; ++ arm,psci-suspend-param = <0x0010000>; ++ entry-latency-us = <40>; ++ exit-latency-us = <70>; ++ min-residency-us = <3000>; ++ }; ++ ++ CLUSTER_SLEEP_0: cluster-sleep-0 { ++ compatible = "arm,idle-state"; ++ local-timer-stop; ++ arm,psci-suspend-param = <0x1010000>; ++ entry-latency-us = <500>; ++ exit-latency-us = <5000>; ++ min-residency-us = <20000>; ++ }; ++ ++ CLUSTER_SLEEP_1: cluster-sleep-1 { ++ compatible = "arm,idle-state"; ++ local-timer-stop; ++ arm,psci-suspend-param = <0x1010000>; ++ entry-latency-us = <1000>; ++ exit-latency-us = <5000>; ++ min-residency-us = <20000>; ++ }; ++ }; ++ ++ A53_L2: l2-cache0 { ++ compatible = "cache"; ++ }; ++ ++ A73_L2: l2-cache1 { ++ compatible = "cache"; + }; + }; + +@@ -123,6 +202,26 @@ gic: interrupt-controller@e82b0000 { + IRQ_TYPE_LEVEL_HIGH)>; + }; + ++ pmu { ++ compatible = "arm,armv8-pmuv3"; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-affinity = <&cpu0>, ++ <&cpu1>, ++ <&cpu2>, ++ <&cpu3>, ++ <&cpu4>, ++ <&cpu5>, ++ <&cpu6>, ++ <&cpu7>; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; +@@ -337,6 +436,19 @@ uart6: serial@fff32000 { + status = "disabled"; + }; + ++ dma0: dma@fdf30000 { ++ compatible = "hisilicon,k3-dma-1.0"; ++ reg = <0x0 0xfdf30000 0x0 0x1000>; ++ #dma-cells = <1>; ++ dma-channels = <16>; ++ dma-requests = <32>; ++ dma-min-chan = <1>; ++ interrupts = ; ++ clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; ++ dma-no-cci; ++ dma-type = "hi3660_dma"; ++ }; ++ + rtc0: rtc@fff04000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0Xfff04000 0x0 0x1000>; +@@ -810,6 +922,7 @@ dwmmc1: dwmmc1@ff37f000 { + clock-names = "ciu", "biu"; + clock-frequency = <3200000>; + resets = <&crg_rst 0x94 18>; ++ reset-names = "reset"; + cd-gpios = <&gpio25 3 0>; + hisilicon,peripheral-syscon = <&sctrl>; + pinctrl-names = "default"; +@@ -839,6 +952,7 @@ dwmmc2: dwmmc2@ff3ff000 { + <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; + clock-names = "ciu", "biu"; + resets = <&crg_rst 0x94 20>; ++ reset-names = "reset"; + card-detect-delay = <200>; + supports-highspeed; + keep-power-in-suspend; +@@ -848,5 +962,21 @@ &sdio_clk_cfg_func + &sdio_cfg_func>; + status = "disabled"; + }; ++ ++ watchdog0: watchdog@e8a06000 { ++ compatible = "arm,sp805-wdt", "arm,primecell"; ++ reg = <0x0 0xe8a06000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&crg_ctrl HI3660_OSC32K>; ++ clock-names = "apb_pclk"; ++ }; ++ ++ watchdog1: watchdog@e8a07000 { ++ compatible = "arm,sp805-wdt", "arm,primecell"; ++ reg = <0x0 0xe8a07000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&crg_ctrl HI3660_OSC32K>; ++ clock-names = "apb_pclk"; ++ }; + }; + }; +diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +index eacbe0db5bc2..02a3aa4b2165 100644 +--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi ++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +@@ -262,6 +262,12 @@ pm_ctrl: pm_ctrl@f7032000 { + #clock-cells = <1>; + }; + ++ acpu_sctrl: acpu_sctrl@f6504000 { ++ compatible = "hisilicon,hi6220-acpu-sctrl", "syscon"; ++ reg = <0x0 0xf6504000 0x0 0x1000>; ++ #clock-cells = <1>; ++ }; ++ + medianoc_ade: medianoc_ade@f4520000 { + compatible = "syscon"; + reg = <0x0 0xf4520000 0x0 0x4000>; +@@ -755,7 +761,8 @@ usb: usb@f72c0000 { + dr_mode = "otg"; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <128>; +- g-tx-fifo-size = <128 128 128 128 128 128>; ++ g-tx-fifo-size = <128 128 128 128 128 128 128 128 ++ 16 16 16 16 16 16 16>; + interrupts = <0 77 0x4>; + }; + +diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts +index f5d7f0889b41..fe7c16c36025 100644 +--- a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts ++++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts +@@ -84,3 +84,7 @@ ð3 { + &sas1 { + status = "ok"; + }; ++ ++&p0_pcie2_a { ++ status = "ok"; ++}; +diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi +index 283d7b532e16..2c01a21c3665 100644 +--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi ++++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi +@@ -1534,5 +1534,27 @@ sas2: sas@a3000000 { + <637 1>,<638 1>,<639 1>; + status = "disabled"; + }; ++ ++ p0_pcie2_a: pcie@a00a0000 { ++ compatible = "hisilicon,hip07-pcie-ecam"; ++ reg = <0 0xaf800000 0 0x800000>, ++ <0 0xa00a0000 0 0x10000>; ++ bus-range = <0xf8 0xff>; ++ msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>; ++ msi-map-mask = <0xffff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ dma-coherent; ++ ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000 ++ 0x01000000 0 0 0 0xaf7f0000 0 0x10000>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0xf800 0 0 7>; ++ interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4 ++ 0x0 0 0 2 &mbigen_pcie2_a 671 4 ++ 0x0 0 0 3 &mbigen_pcie2_a 671 4 ++ 0x0 0 0 4 &mbigen_pcie2_a 671 4>; ++ status = "disabled"; ++ }; + }; + }; +diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile +index 3e6ce6c15a74..6cff81eeaae2 100644 +--- a/arch/arm64/boot/dts/marvell/Makefile ++++ b/arch/arm64/boot/dts/marvell/Makefile +@@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb + dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb + dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb + dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb ++dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb + + always := $(dtb-y) + subdir-y := $(dts-dirs) +diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +index e3a136ed77b0..2ce52ba74f73 100644 +--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts ++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +@@ -45,6 +45,7 @@ + + /dts-v1/; + ++#include + #include "armada-372x.dtsi" + + / { +@@ -59,6 +60,20 @@ memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; ++ ++ vcc_sd_reg1: regulator { ++ compatible = "regulator-gpio"; ++ regulator-name = "vcc_sd1"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ ++ gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>; ++ gpios-states = <0>; ++ states = <1800000 0x1 ++ 3300000 0x0>; ++ enable-active-high; ++ }; + }; + + /* J9 */ +@@ -71,6 +86,16 @@ &sata { + status = "okay"; + }; + ++/* J1 */ ++&sdhci1 { ++ wp-inverted; ++ bus-width = <4>; ++ cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>; ++ marvell,pad-type = "sd"; ++ vqmmc-supply = <&vcc_sd_reg1>; ++ status = "okay"; ++}; ++ + /* Exported on the micro USB connector J5 through an FTDI */ + &uart0 { + status = "okay"; +@@ -81,6 +106,11 @@ &usb3 { + status = "okay"; + }; + ++/* J8 */ ++&usb2 { ++ status = "okay"; ++}; ++ + &mdio { + switch0: switch0@1 { + compatible = "marvell,mv88e6085"; +diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +index 51763d674050..8c0cf7efac65 100644 +--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi ++++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +@@ -81,6 +81,11 @@ timer { + ; + }; + ++ pmu { ++ compatible = "arm,armv8-pmuv3"; ++ interrupts = ; ++ }; ++ + soc { + compatible = "simple-bus"; + #address-cells = <2>; +@@ -322,7 +327,11 @@ gic: interrupt-controller@1d00000 { + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1d00000 0x10000>, /* GICD */ +- <0x1d40000 0x40000>; /* GICR */ ++ <0x1d40000 0x40000>, /* GICR */ ++ <0x1d80000 0x2000>, /* GICC */ ++ <0x1d90000 0x2000>, /* GICH */ ++ <0x1da0000 0x20000>; /* GICV */ ++ interrupts = ; + }; + }; + +diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts +index 92c761c380d3..9c3bdf87e543 100644 +--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts ++++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts +@@ -44,6 +44,7 @@ + * Device Tree file for Marvell Armada 7040 Development board platform + */ + ++#include + #include "armada-7040.dtsi" + + / { +@@ -59,6 +60,34 @@ memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; ++ ++ cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb3h0-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb3h1-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ cpm_usb3_0_phy: cpm-usb3-0-phy { ++ compatible = "usb-nop-xceiv"; ++ vcc-supply = <&cpm_reg_usb3_0_vbus>; ++ }; ++ ++ cpm_usb3_1_phy: cpm-usb3-1-phy { ++ compatible = "usb-nop-xceiv"; ++ vcc-supply = <&cpm_reg_usb3_1_vbus>; ++ }; + }; + + &i2c0 { +@@ -105,6 +134,14 @@ &cpm_pcie2 { + &cpm_i2c0 { + status = "okay"; + clock-frequency = <100000>; ++ ++ expander0: pca9555@21 { ++ compatible = "nxp,pca9555"; ++ pinctrl-names = "default"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ reg = <0x21>; ++ }; + }; + + &cpm_spi1 { +@@ -140,10 +177,12 @@ &cpm_sata0 { + }; + + &cpm_usb3_0 { ++ usb-phy = <&cpm_usb3_0_phy>; + status = "okay"; + }; + + &cpm_usb3_1 { ++ usb-phy = <&cpm_usb3_1_phy>; + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts +index 1e8f7242ed6f..0d7b2ae46610 100644 +--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts ++++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts +@@ -44,6 +44,7 @@ + * Device Tree file for Marvell Armada 8040 Development board platform + */ + ++#include + #include "armada-8040.dtsi" + + / { +@@ -59,6 +60,48 @@ memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; ++ ++ cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "cpm-usb3h0-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "cpm-usb3h1-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ cpm_usb3_0_phy: cpm-usb3-0-phy { ++ compatible = "usb-nop-xceiv"; ++ vcc-supply = <&cpm_reg_usb3_0_vbus>; ++ }; ++ ++ cpm_usb3_1_phy: cpm-usb3-1-phy { ++ compatible = "usb-nop-xceiv"; ++ vcc-supply = <&cpm_reg_usb3_1_vbus>; ++ }; ++ ++ cps_reg_usb3_0_vbus: cps-usb3-0-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "cps-usb3h0-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&expander1 0 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ cps_usb3_0_phy: cps-usb3-0-phy { ++ compatible = "usb-nop-xceiv"; ++ vcc-supply = <&cps_reg_usb3_0_vbus>; ++ }; + }; + + &i2c0 { +@@ -107,6 +150,25 @@ &cpm_pcie2 { + &cpm_i2c0 { + status = "okay"; + clock-frequency = <100000>; ++ ++ /* U31 */ ++ expander0: pca9555@21 { ++ compatible = "nxp,pca9555"; ++ pinctrl-names = "default"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ reg = <0x21>; ++ }; ++ ++ /* U25 */ ++ expander1: pca9555@25 { ++ compatible = "nxp,pca9555"; ++ pinctrl-names = "default"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ reg = <0x25>; ++ }; ++ + }; + + /* CON4 on CP0 expansion */ +@@ -116,11 +178,13 @@ &cpm_sata0 { + + /* CON9 on CP0 expansion */ + &cpm_usb3_0 { ++ usb-phy = <&cpm_usb3_0_phy>; + status = "okay"; + }; + + /* CON10 on CP0 expansion */ + &cpm_usb3_1 { ++ usb-phy = <&cpm_usb3_1_phy>; + status = "okay"; + }; + +@@ -159,6 +223,7 @@ &cps_sata0 { + + /* CON9 on CP1 expansion */ + &cps_usb3_0 { ++ usb-phy = <&cps_usb3_0_phy>; + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +index 4968e731de61..acf5c7d16d79 100644 +--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts ++++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +@@ -46,11 +46,17 @@ + + #include "armada-8040.dtsi" + ++#include ++ + / { + model = "Marvell 8040 MACHIATOBin"; + compatible = "marvell,armada8040-mcbin", "marvell,armada8040", + "marvell,armada-ap806-quad", "marvell,armada-ap806"; + ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; +@@ -77,11 +83,13 @@ v_vddo_h: regulator-1-8v { + + v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { + compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&cpm_gpio2 15 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cpm_xhci_vbus_pins>; + regulator-name = "v_5v0_usb3_hst_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; +- /* actually GPIO controlled, but 8k has no GPIO support yet */ +- regulator-always-on; + status = "okay"; + }; + +@@ -112,10 +120,44 @@ &ap_sdhci0 { + + &cpm_i2c0 { + clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cpm_i2c0_pins>; + status = "okay"; + }; + ++&cpm_i2c1 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cpm_i2c1_pins>; ++ status = "okay"; ++ ++ i2c-switch@70 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x70>; ++ ++ sfpp0_i2c: i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ }; ++ sfpp1_i2c: i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ }; ++ sfp_1g_i2c: i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ }; ++ }; ++}; ++ + &cpm_mdio { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cpm_ge_mdio_pins>; + status = "okay"; + + ge_phy: ethernet-phy@0 { +@@ -123,6 +165,67 @@ ge_phy: ethernet-phy@0 { + }; + }; + ++&cpm_pcie0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cpm_pcie_pins>; ++ num-lanes = <4>; ++ num-viewport = <8>; ++ reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&cpm_pinctrl { ++ cpm_ge_mdio_pins: ge-mdio-pins { ++ marvell,pins = "mpp32", "mpp34"; ++ marvell,function = "ge"; ++ }; ++ cpm_i2c1_pins: i2c1-pins { ++ marvell,pins = "mpp35", "mpp36"; ++ marvell,function = "i2c1"; ++ }; ++ cpm_i2c0_pins: i2c0-pins { ++ marvell,pins = "mpp37", "mpp38"; ++ marvell,function = "i2c0"; ++ }; ++ cpm_xhci_vbus_pins: xhci0-vbus-pins { ++ marvell,pins = "mpp47"; ++ marvell,function = "gpio"; ++ }; ++ cpm_pcie_pins: pcie-pins { ++ marvell,pins = "mpp52"; ++ marvell,function = "gpio"; ++ }; ++ cpm_sdhci_pins: sdhci-pins { ++ marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", ++ "mpp60", "mpp61"; ++ marvell,function = "sdio"; ++ }; ++}; ++ ++&cpm_xmdio { ++ status = "okay"; ++ ++ phy0: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <0>; ++ }; ++ ++ phy8: ethernet-phy@8 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <8>; ++ }; ++}; ++ ++&cpm_ethernet { ++ status = "okay"; ++}; ++ ++&cpm_eth0 { ++ status = "okay"; ++ phy = <&phy0>; ++ phy-mode = "10gbase-kr"; ++}; ++ + &cpm_sata0 { + /* CPM Lane 0 - U29 */ + status = "okay"; +@@ -132,6 +235,8 @@ &cpm_sdhci0 { + /* U6 */ + broken-cd; + bus-width = <4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cpm_sdhci_pins>; + status = "okay"; + vqmmc-supply = <&v_3_3>; + }; +@@ -150,6 +255,12 @@ &cps_ethernet { + status = "okay"; + }; + ++&cps_eth0 { ++ status = "okay"; ++ phy = <&phy8>; ++ phy-mode = "10gbase-kr"; ++}; ++ + &cps_eth1 { + /* CPS Lane 0 - J5 (Gigabit RJ45) */ + status = "okay"; +@@ -157,6 +268,13 @@ &cps_eth1 { + phy-mode = "sgmii"; + }; + ++&cps_pinctrl { ++ cps_spi1_pins: spi1-pins { ++ marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16"; ++ marvell,function = "spi1"; ++ }; ++}; ++ + &cps_sata0 { + /* CPS Lane 1 - U32 */ + /* CPS Lane 3 - U31 */ +@@ -164,6 +282,8 @@ &cps_sata0 { + }; + + &cps_spi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cps_spi1_pins>; + status = "okay"; + + spi-flash@0 { +diff --git a/arch/arm64/boot/dts/marvell/armada-8080-db.dts b/arch/arm64/boot/dts/marvell/armada-8080-db.dts +new file mode 100644 +index 000000000000..707af833832b +--- /dev/null ++++ b/arch/arm64/boot/dts/marvell/armada-8080-db.dts +@@ -0,0 +1,67 @@ ++/* ++ * Copyright (C) 2017 Marvell Technology Group Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPLv2 or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/* ++ * Device Tree file for Marvell Armada-8080 Development board platform ++ */ ++ ++#include "armada-8080.dtsi" ++ ++/ { ++ model = "Marvell 8080 board"; ++ compatible = "marvell,armada-8080-db", "marvell,armada-8080", ++ "marvell,armada-ap810-octa", "marvell,armada-ap810"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@00000000 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x80000000>; ++ }; ++}; ++ ++&uart0_ap0 { ++ clock-frequency = <384000>; ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/marvell/armada-8080.dtsi b/arch/arm64/boot/dts/marvell/armada-8080.dtsi +new file mode 100644 +index 000000000000..d5535b716735 +--- /dev/null ++++ b/arch/arm64/boot/dts/marvell/armada-8080.dtsi +@@ -0,0 +1,53 @@ ++/* ++ * Copyright (C) 2017 Marvell Technology Group Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPLv2 or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/* ++ * Device Tree file for Marvell Armada-8080 SoC, made of an AP810 OCTA. ++ */ ++ ++#include "armada-ap810-ap0-octa-core.dtsi" ++ ++/ { ++ model = "Marvell 8080 board"; ++ compatible = "marvell,armada-8080", "marvell,armada-ap810-octa", ++ "marvell,armada-ap810"; ++}; +diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi +new file mode 100644 +index 000000000000..bf1b22b70384 +--- /dev/null ++++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi +@@ -0,0 +1,104 @@ ++/* ++ * Copyright (C) 2017 Marvell Technology Group Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPLv2 or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/* ++ * Device Tree file for Marvell Armada AP810 OCTA cores. ++ */ ++ ++#include "armada-ap810-ap0.dtsi" ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "marvell,armada-ap810-octa"; ++ ++ cpu@000 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72", "arm,armv8"; ++ reg = <0x000>; ++ enable-method = "psci"; ++ }; ++ cpu@001 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72", "arm,armv8"; ++ reg = <0x001>; ++ enable-method = "psci"; ++ }; ++ cpu@100 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72", "arm,armv8"; ++ reg = <0x100>; ++ enable-method = "psci"; ++ }; ++ cpu@101 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72", "arm,armv8"; ++ reg = <0x101>; ++ enable-method = "psci"; ++ }; ++ cpu@200 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72", "arm,armv8"; ++ reg = <0x200>; ++ enable-method = "psci"; ++ }; ++ cpu@201 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72", "arm,armv8"; ++ reg = <0x201>; ++ enable-method = "psci"; ++ }; ++ cpu@300 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72", "arm,armv8"; ++ reg = <0x300>; ++ enable-method = "psci"; ++ }; ++ cpu@301 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72", "arm,armv8"; ++ reg = <0x301>; ++ enable-method = "psci"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi +new file mode 100644 +index 000000000000..7e6f039f0f80 +--- /dev/null ++++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi +@@ -0,0 +1,163 @@ ++/* ++ * Copyright (C) 2017 Marvell Technology Group Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPLv2 or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/* ++ * Device Tree file for Marvell Armada AP810. ++ */ ++ ++#include ++ ++/dts-v1/; ++ ++/ { ++ model = "Marvell Armada AP810"; ++ compatible = "marvell,armada-ap810"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ aliases { ++ serial0 = &uart0_ap0; ++ serial1 = &uart1_ap0; ++ }; ++ ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ ap810-ap0 { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ compatible = "simple-bus"; ++ interrupt-parent = <&gic>; ++ ranges; ++ ++ config-space@e8000000 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "simple-bus"; ++ ranges = <0x0 0x0 0xe8000000 0x4000000>; ++ interrupt-parent = <&gic>; ++ ++ gic: interrupt-controller@3000000 { ++ compatible = "arm,gic-v3"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ interrupts = ; ++ ranges; ++ ++ reg = <0x3000000 0x10000>, /* GICD */ ++ <0x3060000 0x100000>, /* GICR */ ++ <0x00c0000 0x2000>, /* GICC */ ++ <0x00d0000 0x1000>, /* GICH */ ++ <0x00e0000 0x2000>; /* GICV */ ++ ++ gic_its_ap0: interrupt-controller@3040000 { ++ compatible = "arm,gic-v3-its"; ++ msi-controller; ++ #msi-cells = <1>; ++ reg = <0x3040000 0x20000>; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ xor@400000 { ++ compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; ++ reg = <0x400000 0x1000>, ++ <0x410000 0x1000>; ++ msi-parent = <&gic_its_ap0 0xa0>; ++ dma-coherent; ++ }; ++ ++ xor@420000 { ++ compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; ++ reg = <0x420000 0x1000>, ++ <0x430000 0x1000>; ++ msi-parent = <&gic_its_ap0 0xa1>; ++ dma-coherent; ++ }; ++ ++ xor@440000 { ++ compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; ++ reg = <0x440000 0x1000>, ++ <0x450000 0x1000>; ++ msi-parent = <&gic_its_ap0 0xa2>; ++ dma-coherent; ++ }; ++ ++ xor@460000 { ++ compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; ++ reg = <0x460000 0x1000>, ++ <0x470000 0x1000>; ++ msi-parent = <&gic_its_ap0 0xa3>; ++ dma-coherent; ++ }; ++ ++ uart0_ap0: serial@512000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x512000 0x100>; ++ reg-shift = <2>; ++ interrupts = ; ++ reg-io-width = <1>; ++ status = "disabled"; ++ }; ++ ++ uart1_ap0: serial@512100 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x512100 0x100>; ++ reg-shift = <2>; ++ interrupts = ; ++ reg-io-width = <1>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +index 4c68605675a8..8263a8a504a8 100644 +--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi ++++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +@@ -65,25 +65,44 @@ cpm_ethernet: ethernet@0 { + reg = <0x0 0x100000>, <0x129000 0xb000>; + clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>; + clock-names = "pp_clk", "gop_clk", "mg_clk"; ++ marvell,system-controller = <&cpm_syscon0>; + status = "disabled"; + dma-coherent; + + cpm_eth0: eth0 { +- interrupts = ; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", ++ "tx-cpu3", "rx-shared"; + port-id = <0>; + gop-port-id = <0>; + status = "disabled"; + }; + + cpm_eth1: eth1 { +- interrupts = ; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", ++ "tx-cpu3", "rx-shared"; + port-id = <1>; + gop-port-id = <2>; + status = "disabled"; + }; + + cpm_eth2: eth2 { +- interrupts = ; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", ++ "tx-cpu3", "rx-shared"; + port-id = <2>; + gop-port-id = <3>; + status = "disabled"; +@@ -115,6 +134,13 @@ cpm_icu: interrupt-controller@1e0000 { + msi-parent = <&gicp>; + }; + ++ cpm_rtc: rtc@284000 { ++ compatible = "marvell,armada-8k-rtc"; ++ reg = <0x284000 0x20>, <0x284080 0x24>; ++ reg-names = "rtc", "rtc-soc"; ++ interrupts = ; ++ }; ++ + cpm_syscon0: system-controller@440000 { + compatible = "syscon", "simple-mfd"; + reg = <0x440000 0x1000>; +@@ -131,8 +157,12 @@ cpm_gpio1: gpio@100 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&cpm_pinctrl 0 0 32>; ++ interrupt-controller; ++ interrupts = , ++ , ++ , ++ ; + status = "disabled"; +- + }; + + cpm_gpio2: gpio@140 { +@@ -142,26 +172,15 @@ cpm_gpio2: gpio@140 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&cpm_pinctrl 0 32 31>; ++ interrupt-controller; ++ interrupts = , ++ , ++ , ++ ; + status = "disabled"; + }; + }; + +- cpm_rtc: rtc@284000 { +- compatible = "marvell,armada-8k-rtc"; +- reg = <0x284000 0x20>, <0x284080 0x24>; +- reg-names = "rtc", "rtc-soc"; +- interrupts = ; +- }; +- +- cpm_sata0: sata@540000 { +- compatible = "marvell,armada-8k-ahci", +- "generic-ahci"; +- reg = <0x540000 0x30000>; +- interrupts = ; +- clocks = <&cpm_clk 1 15>; +- status = "disabled"; +- }; +- + cpm_usb3_0: usb3@500000 { + compatible = "marvell,armada-8k-xhci", + "generic-xhci"; +@@ -182,6 +201,15 @@ cpm_usb3_1: usb3@510000 { + status = "disabled"; + }; + ++ cpm_sata0: sata@540000 { ++ compatible = "marvell,armada-8k-ahci", ++ "generic-ahci"; ++ reg = <0x540000 0x30000>; ++ interrupts = ; ++ clocks = <&cpm_clk 1 15>; ++ status = "disabled"; ++ }; ++ + cpm_xor0: xor@6a0000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x6a0000 0x1000>, +@@ -240,6 +268,21 @@ cpm_i2c1: i2c@701100 { + status = "disabled"; + }; + ++ cpm_nand: nand@720000 { ++ /* ++ * Due to the limiation of the pin available ++ * this controller is only usable on the CPM ++ * for A7K and on the CPS for A8K. ++ */ ++ compatible = "marvell,armada370-nand"; ++ reg = <0x720000 0x54>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupts = ; ++ clocks = <&cpm_clk 1 2>; ++ status = "disabled"; ++ }; ++ + cpm_trng: trng@760000 { + compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; + reg = <0x760000 0x7d>; +diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +index 923f354b02f0..b71ee6c83668 100644 +--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi ++++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +@@ -60,37 +60,49 @@ config-space@f4000000 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0xf4000000 0x2000000>; + +- cps_rtc: rtc@284000 { +- compatible = "marvell,armada-8k-rtc"; +- reg = <0x284000 0x20>, <0x284080 0x24>; +- reg-names = "rtc", "rtc-soc"; +- interrupts = ; +- }; +- + cps_ethernet: ethernet@0 { + compatible = "marvell,armada-7k-pp22"; + reg = <0x0 0x100000>, <0x129000 0xb000>; + clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>; + clock-names = "pp_clk", "gop_clk", "mg_clk"; ++ marvell,system-controller = <&cps_syscon0>; + status = "disabled"; + dma-coherent; + + cps_eth0: eth0 { +- interrupts = ; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", ++ "tx-cpu3", "rx-shared"; + port-id = <0>; + gop-port-id = <0>; + status = "disabled"; + }; + + cps_eth1: eth1 { +- interrupts = ; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", ++ "tx-cpu3", "rx-shared"; + port-id = <1>; + gop-port-id = <2>; + status = "disabled"; + }; + + cps_eth2: eth2 { +- interrupts = ; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", ++ "tx-cpu3", "rx-shared"; + port-id = <2>; + gop-port-id = <3>; + status = "disabled"; +@@ -122,6 +134,13 @@ cps_icu: interrupt-controller@1e0000 { + msi-parent = <&gicp>; + }; + ++ cps_rtc: rtc@284000 { ++ compatible = "marvell,armada-8k-rtc"; ++ reg = <0x284000 0x20>, <0x284080 0x24>; ++ reg-names = "rtc", "rtc-soc"; ++ interrupts = ; ++ }; ++ + cps_syscon0: system-controller@440000 { + compatible = "syscon", "simple-mfd"; + reg = <0x440000 0x1000>; +@@ -138,8 +157,12 @@ cps_gpio1: gpio@100 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&cps_pinctrl 0 0 32>; ++ interrupt-controller; ++ interrupts = , ++ , ++ , ++ ; + status = "disabled"; +- + }; + + cps_gpio2: gpio@140 { +@@ -149,20 +172,16 @@ cps_gpio2: gpio@140 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&cps_pinctrl 0 32 31>; ++ interrupt-controller; ++ interrupts = , ++ , ++ , ++ ; + status = "disabled"; + }; + + }; + +- cps_sata0: sata@540000 { +- compatible = "marvell,armada-8k-ahci", +- "generic-ahci"; +- reg = <0x540000 0x30000>; +- interrupts = ; +- clocks = <&cps_clk 1 15>; +- status = "disabled"; +- }; +- + cps_usb3_0: usb3@500000 { + compatible = "marvell,armada-8k-xhci", + "generic-xhci"; +@@ -183,6 +202,15 @@ cps_usb3_1: usb3@510000 { + status = "disabled"; + }; + ++ cps_sata0: sata@540000 { ++ compatible = "marvell,armada-8k-ahci", ++ "generic-ahci"; ++ reg = <0x540000 0x30000>; ++ interrupts = ; ++ clocks = <&cps_clk 1 15>; ++ status = "disabled"; ++ }; ++ + cps_xor0: xor@6a0000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x6a0000 0x1000>, +@@ -241,6 +269,21 @@ cps_i2c1: i2c@701100 { + status = "disabled"; + }; + ++ cps_nand: nand@720000 { ++ /* ++ * Due to the limiation of the pin available ++ * this controller is only usable on the CPM ++ * for A7K and on the CPS for A8K. ++ */ ++ compatible = "marvell,armada370-nand"; ++ reg = <0x720000 0x54>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupts = ; ++ clocks = <&cps_clk 1 2>; ++ status = "disabled"; ++ }; ++ + cps_trng: trng@760000 { + compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; + reg = <0x760000 0x7d>; +diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile +index 015eb072ddef..151723b5c733 100644 +--- a/arch/arm64/boot/dts/mediatek/Makefile ++++ b/arch/arm64/boot/dts/mediatek/Makefile +@@ -1,6 +1,8 @@ ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb + + always := $(dtb-y) +diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +new file mode 100644 +index 000000000000..8c804df3da4e +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +@@ -0,0 +1,32 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: YT Shen ++ * ++ * SPDX-License-Identifier: (GPL-2.0 OR MIT) ++ */ ++ ++/dts-v1/; ++#include "mt2712e.dtsi" ++ ++/ { ++ model = "MediaTek MT2712 evaluation board"; ++ compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0 0x40000000 0 0x80000000>; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:921600n8"; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ +diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +new file mode 100644 +index 000000000000..57d0396b7faa +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +@@ -0,0 +1,171 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: YT Shen ++ * ++ * SPDX-License-Identifier: (GPL-2.0 OR MIT) ++ */ ++ ++#include ++#include ++ ++/ { ++ compatible = "mediatek,mt2712"; ++ interrupt-parent = <&sysirq>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu-map { ++ cluster0 { ++ core0 { ++ cpu = <&cpu0>; ++ }; ++ core1 { ++ cpu = <&cpu1>; ++ }; ++ }; ++ ++ cluster1 { ++ core0 { ++ cpu = <&cpu2>; ++ }; ++ }; ++ }; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a35"; ++ reg = <0x000>; ++ }; ++ ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a35"; ++ reg = <0x001>; ++ enable-method = "psci"; ++ }; ++ ++ cpu2: cpu@200 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72"; ++ reg = <0x200>; ++ enable-method = "psci"; ++ }; ++ }; ++ ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ baud_clk: dummy26m { ++ compatible = "fixed-clock"; ++ clock-frequency = <26000000>; ++ #clock-cells = <0>; ++ }; ++ ++ sys_clk: dummyclk { ++ compatible = "fixed-clock"; ++ clock-frequency = <26000000>; ++ #clock-cells = <0>; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupt-parent = <&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ uart5: serial@1000f000 { ++ compatible = "mediatek,mt2712-uart", ++ "mediatek,mt6577-uart"; ++ reg = <0 0x1000f000 0 0x400>; ++ interrupts = ; ++ clocks = <&baud_clk>, <&sys_clk>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++ ++ sysirq: interrupt-controller@10220a80 { ++ compatible = "mediatek,mt2712-sysirq", ++ "mediatek,mt6577-sysirq"; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ interrupt-parent = <&gic>; ++ reg = <0 0x10220a80 0 0x40>; ++ }; ++ ++ gic: interrupt-controller@10510000 { ++ compatible = "arm,gic-400"; ++ #interrupt-cells = <3>; ++ interrupt-parent = <&gic>; ++ interrupt-controller; ++ reg = <0 0x10510000 0 0x10000>, ++ <0 0x10520000 0 0x20000>, ++ <0 0x10540000 0 0x20000>, ++ <0 0x10560000 0 0x20000>; ++ interrupts = ; ++ }; ++ ++ uart0: serial@11002000 { ++ compatible = "mediatek,mt2712-uart", ++ "mediatek,mt6577-uart"; ++ reg = <0 0x11002000 0 0x400>; ++ interrupts = ; ++ clocks = <&baud_clk>, <&sys_clk>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++ ++ uart1: serial@11003000 { ++ compatible = "mediatek,mt2712-uart", ++ "mediatek,mt6577-uart"; ++ reg = <0 0x11003000 0 0x400>; ++ interrupts = ; ++ clocks = <&baud_clk>, <&sys_clk>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++ ++ uart2: serial@11004000 { ++ compatible = "mediatek,mt2712-uart", ++ "mediatek,mt6577-uart"; ++ reg = <0 0x11004000 0 0x400>; ++ interrupts = ; ++ clocks = <&baud_clk>, <&sys_clk>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++ ++ uart3: serial@11005000 { ++ compatible = "mediatek,mt2712-uart", ++ "mediatek,mt6577-uart"; ++ reg = <0 0x11005000 0 0x400>; ++ interrupts = ; ++ clocks = <&baud_clk>, <&sys_clk>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++ ++ uart4: serial@11019000 { ++ compatible = "mediatek,mt2712-uart", ++ "mediatek,mt6577-uart"; ++ reg = <0 0x11019000 0 0x400>; ++ interrupts = ; ++ clocks = <&baud_clk>, <&sys_clk>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++}; ++ +diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi +index 31088a9f71de..4beaa71107d7 100644 +--- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi +@@ -108,13 +108,6 @@ clk26m: oscillator@0 { + clock-output-names = "clk26m"; + }; + +- clk32k: oscillator@1 { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <32000>; +- clock-output-names = "clk32k"; +- }; +- + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; +@@ -147,6 +140,11 @@ scpsys: scpsys@10006000 { + infracfg = <&infrasys>; + }; + ++ watchdog: watchdog@10007000 { ++ compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt"; ++ reg = <0 0x10007000 0 0x100>; ++ }; ++ + apmixedsys: apmixed@1000c000 { + compatible = "mediatek,mt6797-apmixedsys"; + reg = <0 0x1000c000 0 0x1000>; +diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +new file mode 100644 +index 000000000000..c08309df2cc7 +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -0,0 +1,27 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Ming Huang ++ * Sean Wang ++ * ++ * SPDX-License-Identifier: (GPL-2.0 OR MIT) ++ */ ++ ++/dts-v1/; ++#include "mt7622.dtsi" ++ ++/ { ++ model = "MediaTek MT7622 RFB1 board"; ++ compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n1"; ++ }; ++ ++ memory { ++ reg = <0 0x40000000 0 0x3F000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +new file mode 100644 +index 000000000000..b111fec2ed9d +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -0,0 +1,110 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Ming Huang ++ * Sean Wang ++ * ++ * SPDX-License-Identifier: (GPL-2.0 OR MIT) ++ */ ++ ++#include ++#include ++ ++/ { ++ compatible = "mediatek,mt7622"; ++ interrupt-parent = <&sysirq>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ cpus { ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ reg = <0x0 0x0>; ++ enable-method = "psci"; ++ clock-frequency = <1300000000>; ++ }; ++ ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ reg = <0x0 0x1>; ++ enable-method = "psci"; ++ clock-frequency = <1300000000>; ++ }; ++ }; ++ ++ uart_clk: dummy25m { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <25000000>; ++ }; ++ ++ bus_clk: dummy280m { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <280000000>; ++ }; ++ ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ ++ secmon_reserved: secmon@43000000 { ++ reg = <0 0x43000000 0 0x30000>; ++ no-map; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupt-parent = <&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ sysirq: interrupt-controller@10200620 { ++ compatible = "mediatek,mt7622-sysirq", ++ "mediatek,mt6577-sysirq"; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ interrupt-parent = <&gic>; ++ reg = <0 0x10200620 0 0x20>; ++ }; ++ ++ gic: interrupt-controller@10300000 { ++ compatible = "arm,gic-400"; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ interrupt-parent = <&gic>; ++ reg = <0 0x10310000 0 0x1000>, ++ <0 0x10320000 0 0x1000>, ++ <0 0x10340000 0 0x2000>, ++ <0 0x10360000 0 0x2000>; ++ }; ++ ++ uart0: serial@11002000 { ++ compatible = "mediatek,mt7622-uart", ++ "mediatek,mt6577-uart"; ++ reg = <0 0x11002000 0 0x400>; ++ interrupts = ; ++ clocks = <&uart_clk>, <&bus_clk>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile +index cc0f02d9dd02..ff81d7e5805e 100644 +--- a/arch/arm64/boot/dts/qcom/Makefile ++++ b/arch/arm64/boot/dts/qcom/Makefile +@@ -1,5 +1,6 @@ + dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb + dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb +diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi +index d94640812194..790b7775b901 100644 +--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi ++++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi +@@ -17,6 +17,7 @@ pinconf { + function = PMIC_GPIO_FUNC_NORMAL; + power-source = ; + input-disable; ++ output-high; + }; + }; + +diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +index bd310ac1967a..1d63e6b879de 100644 +--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi ++++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +@@ -88,6 +88,8 @@ adv_bridge: bridge@39 { + interrupts = <31 2>; + + adi,dsi-lanes = <4>; ++ clocks = <&rpmcc RPM_SMD_BB_CLK2>; ++ clock-names = "cec"; + + pd-gpios = <&msmgpio 32 0>; + +@@ -213,11 +215,14 @@ sdhci@07864000 { + }; + + usb@78d9000 { +- extcon = <&usb_id>, <&usb_id>; ++ extcon = <&usb_id>; + status = "okay"; + adp-disable; + hnp-disable; + srp-disable; ++ dr_mode = "host"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb_sw_sel_pm>; + ulpi { + phy { + v1p8-supply = <&pm8916_l7>; +@@ -337,19 +342,11 @@ usb2513 { + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; +- id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>; ++ vbus-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_default>; + }; + +- usb-switch { +- compatible = "toshiba,tc7usb40mu"; +- switch-gpios = <&pm8916_gpios 4 GPIO_ACTIVE_HIGH>; +- extcon = <&usb_id>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_sw_sel_pm>; +- }; +- + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; +diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi +index b1142c45fdc9..8e379782597a 100644 +--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi ++++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi +@@ -24,4 +24,28 @@ pinconf { + power-source = ; // 1.8V + }; + }; ++ ++ usb3_vbus_det_gpio: pm8996_gpio22 { ++ pinconf { ++ pins = "gpio22"; ++ function = PMIC_GPIO_FUNC_NORMAL; ++ input-enable; ++ bias-pull-down; ++ qcom,drive-strength = ; ++ power-source = ; // 1.8V ++ }; ++ }; ++}; ++ ++&pmi8994_gpios { ++ usb2_vbus_det_gpio: pmi8996_gpio6 { ++ pinconf { ++ pins = "gpio6"; ++ function = PMIC_GPIO_FUNC_NORMAL; ++ input-enable; ++ bias-pull-down; ++ qcom,drive-strength = ; ++ power-source = ; // 1.8V ++ }; ++ }; + }; +diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +index d2196fc6d739..789f3e87321e 100644 +--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi ++++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +@@ -13,6 +13,7 @@ + + #include "msm8996.dtsi" + #include "pm8994.dtsi" ++#include "pmi8994.dtsi" + #include "apq8096-db820c-pins.dtsi" + #include "apq8096-db820c-pmic-pins.dtsi" + #include +@@ -88,6 +89,55 @@ sdhci@74a4900 { + cd-gpios = <&msmgpio 38 0x1>; + status = "okay"; + }; ++ ++ phy@34000 { ++ status = "okay"; ++ }; ++ ++ phy@7410000 { ++ status = "okay"; ++ }; ++ ++ phy@7411000 { ++ status = "okay"; ++ }; ++ ++ phy@7412000 { ++ status = "okay"; ++ }; ++ ++ usb@6a00000 { ++ status = "okay"; ++ ++ dwc3@6a00000 { ++ extcon = <&usb3_id>; ++ dr_mode = "otg"; ++ }; ++ }; ++ ++ usb3_id: usb3-id { ++ compatible = "linux,extcon-usb-gpio"; ++ id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb3_vbus_det_gpio>; ++ }; ++ ++ usb@7600000 { ++ status = "okay"; ++ ++ dwc3@7600000 { ++ extcon = <&usb2_id>; ++ dr_mode = "otg"; ++ maximum-speed = "high-speed"; ++ }; ++ }; ++ ++ usb2_id: usb2-id { ++ compatible = "linux,extcon-usb-gpio"; ++ id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb2_vbus_det_gpio>; ++ }; + }; + + +@@ -106,4 +156,152 @@ button@0 { + gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; + }; + }; ++ ++ rpm-glink { ++ rpm_requests { ++ pm8994-regulators { ++ vdd_l1-supply = <&pm8994_s3>; ++ vdd_l2_l26_l28-supply = <&pm8994_s3>; ++ vdd_l3_l11-supply = <&pm8994_s3>; ++ vdd_l4_l27_l31-supply = <&pm8994_s3>; ++ vdd_l5_l7-supply = <&pm8994_s5>; ++ vdd_l14_l15-supply = <&pm8994_s5>; ++ vdd_l20_l21-supply = <&pm8994_s5>; ++ vdd_l25-supply = <&pm8994_s3>; ++ ++ s3 { ++ regulator-min-microvolt = <1300000>; ++ regulator-max-microvolt = <1300000>; ++ }; ++ s4 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ s5 { ++ regulator-min-microvolt = <2150000>; ++ regulator-max-microvolt = <2150000>; ++ }; ++ s7 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ }; ++ ++ l1 { ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ }; ++ l2 { ++ regulator-min-microvolt = <1250000>; ++ regulator-max-microvolt = <1250000>; ++ }; ++ l3 { ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ }; ++ l4 { ++ regulator-min-microvolt = <1225000>; ++ regulator-max-microvolt = <1225000>; ++ }; ++ l6 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ }; ++ l8 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ l9 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ l10 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ l11 { ++ regulator-min-microvolt = <1150000>; ++ regulator-max-microvolt = <1150000>; ++ }; ++ l12 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ l13 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <2950000>; ++ }; ++ l14 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ l15 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ l16 { ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <2700000>; ++ }; ++ l17 { ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; ++ }; ++ l18 { ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <2900000>; ++ }; ++ l19 { ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ }; ++ l20 { ++ regulator-min-microvolt = <2950000>; ++ regulator-max-microvolt = <2950000>; ++ regulator-allow-set-load; ++ }; ++ l21 { ++ regulator-min-microvolt = <2950000>; ++ regulator-max-microvolt = <2950000>; ++ }; ++ l22 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ l23 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ }; ++ l24 { ++ regulator-min-microvolt = <3075000>; ++ regulator-max-microvolt = <3075000>; ++ }; ++ l25 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-allow-set-load; ++ }; ++ l27 { ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ }; ++ l28 { ++ regulator-min-microvolt = <925000>; ++ regulator-max-microvolt = <925000>; ++ regulator-allow-set-load; ++ }; ++ l29 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ }; ++ l30 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ l32 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ }; ++ }; ++ }; + }; +diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +new file mode 100644 +index 000000000000..6a838b5d321e +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +@@ -0,0 +1,52 @@ ++/dts-v1/; ++/* Copyright (c) 2017, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++#include "ipq8074.dtsi" ++ ++/ { ++ #address-cells = <0x2>; ++ #size-cells = <0x2>; ++ model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; ++ compatible = "qcom,ipq8074-hk01", "qcom,ipq8074"; ++ interrupt-parent = <&intc>; ++ ++ aliases { ++ serial0 = &blsp1_uart5; ++ }; ++ ++ chosen { ++ stdout-path = "serial0"; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x0 0x40000000 0x0 0x20000000>; ++ }; ++ ++ soc { ++ pinctrl@1000000 { ++ serial_4_pins: serial4_pinmux { ++ mux { ++ pins = "gpio23", "gpio24"; ++ function = "blsp4_uart1"; ++ bias-disable; ++ }; ++ }; ++ }; ++ ++ serial@78b3000 { ++ pinctrl-0 = <&serial_4_pins>; ++ pinctrl-names = "default"; ++ status = "ok"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +new file mode 100644 +index 000000000000..2bc5dec5614d +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -0,0 +1,194 @@ ++/* ++ * Copyright (c) 2017, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++ ++/ { ++ model = "Qualcomm Technologies, Inc. IPQ8074"; ++ compatible = "qcom,ipq8074"; ++ ++ soc: soc { ++ #address-cells = <0x1>; ++ #size-cells = <0x1>; ++ ranges = <0 0 0 0xffffffff>; ++ compatible = "simple-bus"; ++ ++ pinctrl@1000000 { ++ compatible = "qcom,ipq8074-pinctrl"; ++ reg = <0x1000000 0x300000>; ++ interrupts = ; ++ gpio-controller; ++ #gpio-cells = <0x2>; ++ interrupt-controller; ++ #interrupt-cells = <0x2>; ++ }; ++ ++ intc: interrupt-controller@b000000 { ++ compatible = "qcom,msm-qgic2"; ++ interrupt-controller; ++ #interrupt-cells = <0x3>; ++ reg = <0xb000000 0x1000>, <0xb002000 0x1000>; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ timer@b120000 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ compatible = "arm,armv7-timer-mem"; ++ reg = <0xb120000 0x1000>; ++ clock-frequency = <19200000>; ++ ++ frame@b120000 { ++ frame-number = <0>; ++ interrupts = , ++ ; ++ reg = <0xb121000 0x1000>, ++ <0xb122000 0x1000>; ++ }; ++ ++ frame@b123000 { ++ frame-number = <1>; ++ interrupts = ; ++ reg = <0xb123000 0x1000>; ++ status = "disabled"; ++ }; ++ ++ frame@b124000 { ++ frame-number = <2>; ++ interrupts = ; ++ reg = <0xb124000 0x1000>; ++ status = "disabled"; ++ }; ++ ++ frame@b125000 { ++ frame-number = <3>; ++ interrupts = ; ++ reg = <0xb125000 0x1000>; ++ status = "disabled"; ++ }; ++ ++ frame@b126000 { ++ frame-number = <4>; ++ interrupts = ; ++ reg = <0xb126000 0x1000>; ++ status = "disabled"; ++ }; ++ ++ frame@b127000 { ++ frame-number = <5>; ++ interrupts = ; ++ reg = <0xb127000 0x1000>; ++ status = "disabled"; ++ }; ++ ++ frame@b128000 { ++ frame-number = <6>; ++ interrupts = ; ++ reg = <0xb128000 0x1000>; ++ status = "disabled"; ++ }; ++ }; ++ ++ gcc: gcc@1800000 { ++ compatible = "qcom,gcc-ipq8074"; ++ reg = <0x1800000 0x80000>; ++ #clock-cells = <0x1>; ++ #reset-cells = <0x1>; ++ }; ++ ++ blsp1_uart5: serial@78b3000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x78b3000 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ }; ++ ++ cpus { ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ ++ CPU0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ reg = <0x0>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ CPU1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ enable-method = "psci"; ++ reg = <0x1>; ++ next-level-cache = <&L2_0>; ++ }; ++ ++ CPU2: cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ enable-method = "psci"; ++ reg = <0x2>; ++ next-level-cache = <&L2_0>; ++ }; ++ ++ CPU3: cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ enable-method = "psci"; ++ reg = <0x3>; ++ next-level-cache = <&L2_0>; ++ }; ++ ++ L2_0: l2-cache { ++ compatible = "cache"; ++ cache-level = <0x2>; ++ }; ++ }; ++ ++ psci { ++ compatible = "arm,psci-1.0"; ++ method = "smc"; ++ }; ++ ++ pmu { ++ compatible = "arm,armv8-pmuv3"; ++ interrupts = ; ++ }; ++ ++ clocks { ++ sleep_clk: sleep_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++ #clock-cells = <0>; ++ }; ++ ++ xo: xo { ++ compatible = "fixed-clock"; ++ clock-frequency = <19200000>; ++ #clock-cells = <0>; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi +index 039991f80831..dc3817593e14 100644 +--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi ++++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi +@@ -88,6 +88,11 @@ wcnss_mem: wcnss@89300000 { + no-map; + }; + ++ venus_mem: venus@89900000 { ++ reg = <0x0 0x89900000 0x0 0x600000>; ++ no-map; ++ }; ++ + mba_mem: mba@8ea00000 { + no-map; + reg = <0 0x8ea00000 0 0x100000>; +@@ -204,6 +209,17 @@ cpu_crit1: trip1 { + + }; + ++ gpu_opp_table: opp_table { ++ compatible = "operating-points-v2"; ++ ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ }; ++ opp-19200000 { ++ opp-hz = /bits/ 64 <19200000>; ++ }; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupts = , +@@ -694,6 +710,84 @@ tsens: thermal-sensor@4a8000 { + #thermal-sensor-cells = <1>; + }; + ++ apps_iommu: iommu@1ef0000 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ #iommu-cells = <1>; ++ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; ++ ranges = <0 0x1e20000 0x40000>; ++ reg = <0x1ef0000 0x3000>; ++ clocks = <&gcc GCC_SMMU_CFG_CLK>, ++ <&gcc GCC_APSS_TCU_CLK>; ++ clock-names = "iface", "bus"; ++ qcom,iommu-secure-id = <17>; ++ ++ // mdp_0: ++ iommu-ctx@4000 { ++ compatible = "qcom,msm-iommu-v1-ns"; ++ reg = <0x4000 0x1000>; ++ interrupts = ; ++ }; ++ ++ // venus_ns: ++ iommu-ctx@5000 { ++ compatible = "qcom,msm-iommu-v1-sec"; ++ reg = <0x5000 0x1000>; ++ interrupts = ; ++ }; ++ }; ++ ++ gpu_iommu: iommu@1f08000 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ #iommu-cells = <1>; ++ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; ++ ranges = <0 0x1f08000 0x10000>; ++ clocks = <&gcc GCC_SMMU_CFG_CLK>, ++ <&gcc GCC_GFX_TCU_CLK>; ++ clock-names = "iface", "bus"; ++ qcom,iommu-secure-id = <18>; ++ ++ // gfx3d_user: ++ iommu-ctx@1000 { ++ compatible = "qcom,msm-iommu-v1-ns"; ++ reg = <0x1000 0x1000>; ++ interrupts = ; ++ }; ++ ++ // gfx3d_priv: ++ iommu-ctx@2000 { ++ compatible = "qcom,msm-iommu-v1-ns"; ++ reg = <0x2000 0x1000>; ++ interrupts = ; ++ }; ++ }; ++ ++ gpu@1c00000 { ++ compatible = "qcom,adreno-306.0", "qcom,adreno"; ++ reg = <0x01c00000 0x20000>; ++ reg-names = "kgsl_3d0_reg_memory"; ++ interrupts = ; ++ interrupt-names = "kgsl_3d0_irq"; ++ clock-names = ++ "core", ++ "iface", ++ "mem", ++ "mem_iface", ++ "alt_mem_iface", ++ "gfx3d"; ++ clocks = ++ <&gcc GCC_OXILI_GFX3D_CLK>, ++ <&gcc GCC_OXILI_AHB_CLK>, ++ <&gcc GCC_OXILI_GMEM_CLK>, ++ <&gcc GCC_BIMC_GFX_CLK>, ++ <&gcc GCC_BIMC_GPU_CLK>, ++ <&gcc GFX3D_CLK_SRC>; ++ power-domains = <&gcc OXILI_GDSC>; ++ operating-points-v2 = <&gpu_opp_table>; ++ iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; ++ }; ++ + mdss: mdss@1a00000 { + compatible = "qcom,mdss"; + reg = <0x1a00000 0x1000>, +@@ -735,6 +829,8 @@ mdp: mdp@1a01000 { + "core_clk", + "vsync_clk"; + ++ iommus = <&apps_iommu 4>; ++ + ports { + #address-cells = <1>; + #size-cells = <0>; +@@ -990,7 +1086,7 @@ funnel0_out: endpoint { + }; + + replicator@824000 { +- compatible = "qcom,coresight-replicator1x", "arm,primecell"; ++ compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x824000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; +@@ -1207,6 +1303,28 @@ etm3_out: endpoint { + }; + }; + }; ++ ++ venus: video-codec@1d00000 { ++ compatible = "qcom,msm8916-venus"; ++ reg = <0x01d00000 0xff000>; ++ interrupts = ; ++ power-domains = <&gcc VENUS_GDSC>; ++ clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, ++ <&gcc GCC_VENUS0_AHB_CLK>, ++ <&gcc GCC_VENUS0_AXI_CLK>; ++ clock-names = "core", "iface", "bus"; ++ iommus = <&apps_iommu 5>; ++ memory-region = <&venus_mem>; ++ status = "okay"; ++ ++ video-decoder { ++ compatible = "venus-decoder"; ++ }; ++ ++ video-encoder { ++ compatible = "venus-encoder"; ++ }; ++ }; + }; + + smd { +diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi +index 8f085716e258..887b61c872dd 100644 +--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi ++++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi +@@ -276,12 +276,83 @@ smem { + hwlocks = <&tcsr_mutex 3>; + }; + ++ rpm-glink { ++ compatible = "qcom,glink-rpm"; ++ ++ interrupts = ; ++ ++ qcom,rpm-msg-ram = <&rpm_msg_ram>; ++ ++ mboxes = <&apcs_glb 0>; ++ ++ rpm_requests { ++ compatible = "qcom,rpm-msm8996"; ++ qcom,glink-channels = "rpm_requests"; ++ ++ pm8994-regulators { ++ compatible = "qcom,rpm-pm8994-regulators"; ++ ++ pm8994_s1: s1 {}; ++ pm8994_s2: s2 {}; ++ pm8994_s3: s3 {}; ++ pm8994_s4: s4 {}; ++ pm8994_s5: s5 {}; ++ pm8994_s6: s6 {}; ++ pm8994_s7: s7 {}; ++ pm8994_s8: s8 {}; ++ pm8994_s9: s9 {}; ++ pm8994_s10: s10 {}; ++ pm8994_s11: s11 {}; ++ pm8994_s12: s12 {}; ++ ++ pm8994_l1: l1 {}; ++ pm8994_l2: l2 {}; ++ pm8994_l3: l3 {}; ++ pm8994_l4: l4 {}; ++ pm8994_l5: l5 {}; ++ pm8994_l6: l6 {}; ++ pm8994_l7: l7 {}; ++ pm8994_l8: l8 {}; ++ pm8994_l9: l9 {}; ++ pm8994_l10: l10 {}; ++ pm8994_l11: l11 {}; ++ pm8994_l12: l12 {}; ++ pm8994_l13: l13 {}; ++ pm8994_l14: l14 {}; ++ pm8994_l15: l15 {}; ++ pm8994_l16: l16 {}; ++ pm8994_l17: l17 {}; ++ pm8994_l18: l18 {}; ++ pm8994_l19: l19 {}; ++ pm8994_l20: l20 {}; ++ pm8994_l21: l21 {}; ++ pm8994_l22: l22 {}; ++ pm8994_l23: l23 {}; ++ pm8994_l24: l24 {}; ++ pm8994_l25: l25 {}; ++ pm8994_l26: l26 {}; ++ pm8994_l27: l27 {}; ++ pm8994_l28: l28 {}; ++ pm8994_l29: l29 {}; ++ pm8994_l30: l30 {}; ++ pm8994_l31: l31 {}; ++ pm8994_l32: l32 {}; ++ }; ++ ++ }; ++ }; ++ + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + ++ rpm_msg_ram: memory@68000 { ++ compatible = "qcom,rpm-msg-ram"; ++ reg = <0x68000 0x6000>; ++ }; ++ + tcsr_mutex_regs: syscon@740000 { + compatible = "syscon"; + reg = <0x740000 0x20000>; +@@ -303,6 +374,13 @@ apcs: syscon@9820000 { + reg = <0x9820000 0x1000>; + }; + ++ apcs_glb: mailbox@9820000 { ++ compatible = "qcom,msm8996-apcs-hmss-global"; ++ reg = <0x9820000 0x1000>; ++ ++ #mbox-cells = <1>; ++ }; ++ + gcc: clock-controller@300000 { + compatible = "qcom,gcc-msm8996"; + #clock-cells = <1>; +@@ -538,6 +616,209 @@ mmcc: clock-controller@8c0000 { + <960000000>, + <825000000>; + }; ++ ++ qfprom@74000 { ++ compatible = "qcom,qfprom"; ++ reg = <0x74000 0x8ff>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ qusb2p_hstx_trim: hstx_trim@24e { ++ reg = <0x24e 0x2>; ++ bits = <5 4>; ++ }; ++ ++ qusb2s_hstx_trim: hstx_trim@24f { ++ reg = <0x24f 0x1>; ++ bits = <1 4>; ++ }; ++ }; ++ ++ phy@34000 { ++ compatible = "qcom,msm8996-qmp-pcie-phy"; ++ reg = <0x34000 0x488>; ++ #clock-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, ++ <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, ++ <&gcc GCC_PCIE_CLKREF_CLK>; ++ clock-names = "aux", "cfg_ahb", "ref"; ++ ++ vdda-phy-supply = <&pm8994_l28>; ++ vdda-pll-supply = <&pm8994_l12>; ++ ++ resets = <&gcc GCC_PCIE_PHY_BCR>, ++ <&gcc GCC_PCIE_PHY_COM_BCR>, ++ <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; ++ reset-names = "phy", "common", "cfg"; ++ status = "disabled"; ++ ++ pciephy_0: lane@35000 { ++ reg = <0x035000 0x130>, ++ <0x035200 0x200>, ++ <0x035400 0x1dc>; ++ #phy-cells = <0>; ++ ++ clock-output-names = "pcie_0_pipe_clk_src"; ++ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; ++ clock-names = "pipe0"; ++ resets = <&gcc GCC_PCIE_0_PHY_BCR>; ++ reset-names = "lane0"; ++ }; ++ ++ pciephy_1: lane@36000 { ++ reg = <0x036000 0x130>, ++ <0x036200 0x200>, ++ <0x036400 0x1dc>; ++ #phy-cells = <0>; ++ ++ clock-output-names = "pcie_1_pipe_clk_src"; ++ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; ++ clock-names = "pipe1"; ++ resets = <&gcc GCC_PCIE_1_PHY_BCR>; ++ reset-names = "lane1"; ++ }; ++ ++ pciephy_2: lane@37000 { ++ reg = <0x037000 0x130>, ++ <0x037200 0x200>, ++ <0x037400 0x1dc>; ++ #phy-cells = <0>; ++ ++ clock-output-names = "pcie_2_pipe_clk_src"; ++ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; ++ clock-names = "pipe2"; ++ resets = <&gcc GCC_PCIE_2_PHY_BCR>; ++ reset-names = "lane2"; ++ }; ++ }; ++ ++ phy@7410000 { ++ compatible = "qcom,msm8996-qmp-usb3-phy"; ++ reg = <0x7410000 0x1c4>; ++ #clock-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, ++ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, ++ <&gcc GCC_USB3_CLKREF_CLK>; ++ clock-names = "aux", "cfg_ahb", "ref"; ++ ++ vdda-phy-supply = <&pm8994_l28>; ++ vdda-pll-supply = <&pm8994_l12>; ++ ++ resets = <&gcc GCC_USB3_PHY_BCR>, ++ <&gcc GCC_USB3PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ status = "disabled"; ++ ++ ssusb_phy_0: lane@7410200 { ++ reg = <0x7410200 0x200>, ++ <0x7410400 0x130>, ++ <0x7410600 0x1a8>; ++ #phy-cells = <0>; ++ ++ clock-output-names = "usb3_phy_pipe_clk_src"; ++ clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; ++ clock-names = "pipe0"; ++ }; ++ }; ++ ++ hsusb_phy1: phy@7411000 { ++ compatible = "qcom,msm8996-qusb2-phy"; ++ reg = <0x7411000 0x180>; ++ #phy-cells = <0>; ++ ++ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, ++ <&gcc GCC_RX1_USB2_CLKREF_CLK>; ++ clock-names = "cfg_ahb", "ref"; ++ ++ vdda-pll-supply = <&pm8994_l12>; ++ vdda-phy-dpdm-supply = <&pm8994_l24>; ++ ++ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; ++ nvmem-cells = <&qusb2p_hstx_trim>; ++ status = "disabled"; ++ }; ++ ++ hsusb_phy2: phy@7412000 { ++ compatible = "qcom,msm8996-qusb2-phy"; ++ reg = <0x7412000 0x180>; ++ #phy-cells = <0>; ++ ++ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, ++ <&gcc GCC_RX2_USB2_CLKREF_CLK>; ++ clock-names = "cfg_ahb", "ref"; ++ ++ vdda-pll-supply = <&pm8994_l12>; ++ vdda-phy-dpdm-supply = <&pm8994_l24>; ++ ++ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; ++ nvmem-cells = <&qusb2s_hstx_trim>; ++ status = "disabled"; ++ }; ++ ++ usb2: usb@7600000 { ++ compatible = "qcom,dwc3"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, ++ <&gcc GCC_USB20_MASTER_CLK>, ++ <&gcc GCC_USB20_MOCK_UTMI_CLK>, ++ <&gcc GCC_USB20_SLEEP_CLK>, ++ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; ++ ++ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, ++ <&gcc GCC_USB20_MASTER_CLK>; ++ assigned-clock-rates = <19200000>, <60000000>; ++ ++ power-domains = <&gcc USB30_GDSC>; ++ status = "disabled"; ++ ++ dwc3@7600000 { ++ compatible = "snps,dwc3"; ++ reg = <0x7600000 0xcc00>; ++ interrupts = <0 138 0>; ++ phys = <&hsusb_phy2>; ++ phy-names = "usb2-phy"; ++ }; ++ }; ++ ++ usb3: usb@6a00000 { ++ compatible = "qcom,dwc3"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, ++ <&gcc GCC_USB30_MASTER_CLK>, ++ <&gcc GCC_AGGRE2_USB3_AXI_CLK>, ++ <&gcc GCC_USB30_MOCK_UTMI_CLK>, ++ <&gcc GCC_USB30_SLEEP_CLK>, ++ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; ++ ++ assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, ++ <&gcc GCC_USB30_MASTER_CLK>; ++ assigned-clock-rates = <19200000>, <120000000>; ++ ++ power-domains = <&gcc USB30_GDSC>; ++ status = "disabled"; ++ ++ dwc3@6a00000 { ++ compatible = "snps,dwc3"; ++ reg = <0x6a00000 0xcc00>; ++ interrupts = <0 131 0>; ++ phys = <&hsusb_phy1>, <&ssusb_phy_0>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ }; ++ }; + }; + + adsp-pil { +@@ -558,6 +839,15 @@ adsp-pil { + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; ++ ++ smd-edge { ++ interrupts = ; ++ ++ label = "lpass"; ++ qcom,ipc = <&apcs 16 8>; ++ qcom,smd-edge = <1>; ++ qcom,remote-pid = <2>; ++ }; + }; + + adsp-smp2p { +@@ -584,6 +874,30 @@ adsp_smp2p_in: slave-kernel { + }; + }; + ++ modem-smp2p { ++ compatible = "qcom,smp2p"; ++ qcom,smem = <435>, <428>; ++ ++ interrupts = ; ++ ++ qcom,ipc = <&apcs 16 14>; ++ ++ qcom,local-pid = <0>; ++ qcom,remote-pid = <1>; ++ ++ modem_smp2p_out: master-kernel { ++ qcom,entry-name = "master-kernel"; ++ #qcom,smem-state-cells = <1>; ++ }; ++ ++ modem_smp2p_in: slave-kernel { ++ qcom,entry-name = "slave-kernel"; ++ ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ }; ++ + smp2p-slpi { + compatible = "qcom,smp2p"; + qcom,smem = <481>, <430>; +diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi +index d3879a4e8076..57673f92805d 100644 +--- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi ++++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi +@@ -8,6 +8,23 @@ pmic@2 { + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; ++ ++ pmi8994_gpios: gpios@c000 { ++ compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio"; ++ reg = <0xc000>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupts = <2 0xc0 0 IRQ_TYPE_NONE>, ++ <2 0xc1 0 IRQ_TYPE_NONE>, ++ <2 0xc2 0 IRQ_TYPE_NONE>, ++ <2 0xc3 0 IRQ_TYPE_NONE>, ++ <2 0xc4 0 IRQ_TYPE_NONE>, ++ <2 0xc5 0 IRQ_TYPE_NONE>, ++ <2 0xc6 0 IRQ_TYPE_NONE>, ++ <2 0xc7 0 IRQ_TYPE_NONE>, ++ <2 0xc8 0 IRQ_TYPE_NONE>, ++ <2 0xc9 0 IRQ_TYPE_NONE>; ++ }; + }; + + pmic@3 { +diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile +index acc4bb30d485..381928bc1358 100644 +--- a/arch/arm64/boot/dts/renesas/Makefile ++++ b/arch/arm64/boot/dts/renesas/Makefile +@@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb + dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb + dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb + dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb ++dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb + + always := $(dtb-y) + clean-files := *.dtb +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts +index 95fe207cb6a3..dd4f9b6a4254 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts +@@ -9,8 +9,6 @@ + * kind, whether express or implied. + */ + +-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 +- + /dts-v1/; + #include "r8a7795-es1.dtsi" + #include "ulcb.dtsi" +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts +index b84c156ed696..3f7d5f51e428 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts +@@ -8,8 +8,6 @@ + * kind, whether express or implied. + */ + +-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 +- + /dts-v1/; + #include "r8a7795-es1.dtsi" + #include "salvator-x.dtsi" +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +index a0ba7bd21ea3..aaa5e67a963e 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +@@ -21,6 +21,14 @@ xhci1: usb@ee0400000 { + status = "disabled"; + }; + ++ /delete-node/ usb-phy@ee0e0200; ++ /delete-node/ usb@ee0e0100; ++ /delete-node/ usb@ee0e0000; ++ /delete-node/ usb@e659c000; ++ ++ /delete-node/ dma-controller@e6460000; ++ /delete-node/ dma-controller@e6470000; ++ + fcpf2: fcp@fe952000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe952000 0 0x200>; +@@ -79,6 +87,5 @@ fdp1@fe948000 { + }; + + &du { +- compatible = "renesas,du-r8a7795"; + vsps = <&vspd0 &vspd1 &vspd2 &vspd3>; + }; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +index 0426f41765f0..0afe777973de 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +@@ -9,8 +9,6 @@ + * kind, whether express or implied. + */ + +-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 +- + /dts-v1/; + #include "r8a7795.dtsi" + #include "ulcb.dtsi" +@@ -40,3 +38,17 @@ memory@700000000 { + reg = <0x7 0x00000000 0x0 0x40000000>; + }; + }; ++ ++&du { ++ clocks = <&cpg CPG_MOD 724>, ++ <&cpg CPG_MOD 723>, ++ <&cpg CPG_MOD 722>, ++ <&cpg CPG_MOD 721>, ++ <&cpg CPG_MOD 727>, ++ <&versaclock5 1>, ++ <&versaclock5 3>, ++ <&versaclock5 4>, ++ <&versaclock5 2>; ++ clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", ++ "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +index 684fb3b9d154..17953070f38d 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +@@ -8,8 +8,6 @@ + * kind, whether express or implied. + */ + +-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 +- + /dts-v1/; + #include "r8a7795.dtsi" + #include "salvator-x.dtsi" +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts +index de354957144b..7675de5d4f2c 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts +@@ -8,8 +8,6 @@ + * kind, whether express or implied. + */ + +-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 +- + /dts-v1/; + #include "r8a7795.dtsi" + #include "salvator-xs.dtsi" +@@ -46,10 +44,12 @@ &du { + <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 721>, + <&cpg CPG_MOD 727>, ++ <&versaclock6 1>, + <&x21_clk>, +- <&x22_clk>; ++ <&x22_clk>, ++ <&versaclock6 2>; + clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", +- "dclkin.1", "dclkin.2"; ++ "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; + }; + + &ehci2 { +diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +index e31c1b660b3f..2938195b9571 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -12,6 +12,8 @@ + #include + #include + ++#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 ++ + / { + compatible = "renesas,r8a7795"; + #address-cells = <2>; +@@ -691,6 +693,126 @@ channel1 { + }; + }; + ++ drif00: rif@e6f40000 { ++ compatible = "renesas,r8a7795-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6f40000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 515>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x20>, <&dmac2 0x20>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 515>; ++ renesas,bonding = <&drif01>; ++ status = "disabled"; ++ }; ++ ++ drif01: rif@e6f50000 { ++ compatible = "renesas,r8a7795-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6f50000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 514>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x22>, <&dmac2 0x22>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 514>; ++ renesas,bonding = <&drif00>; ++ status = "disabled"; ++ }; ++ ++ drif10: rif@e6f60000 { ++ compatible = "renesas,r8a7795-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6f60000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 513>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x24>, <&dmac2 0x24>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 513>; ++ renesas,bonding = <&drif11>; ++ status = "disabled"; ++ }; ++ ++ drif11: rif@e6f70000 { ++ compatible = "renesas,r8a7795-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6f70000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 512>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x26>, <&dmac2 0x26>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 512>; ++ renesas,bonding = <&drif10>; ++ status = "disabled"; ++ }; ++ ++ drif20: rif@e6f80000 { ++ compatible = "renesas,r8a7795-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6f80000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 511>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x28>, <&dmac2 0x28>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 511>; ++ renesas,bonding = <&drif21>; ++ status = "disabled"; ++ }; ++ ++ drif21: rif@e6f90000 { ++ compatible = "renesas,r8a7795-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6f90000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 510>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 510>; ++ renesas,bonding = <&drif20>; ++ status = "disabled"; ++ }; ++ ++ drif30: rif@e6fa0000 { ++ compatible = "renesas,r8a7795-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6fa0000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 509>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 509>; ++ renesas,bonding = <&drif31>; ++ status = "disabled"; ++ }; ++ ++ drif31: rif@e6fb0000 { ++ compatible = "renesas,r8a7795-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6fb0000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 508>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 508>; ++ renesas,bonding = <&drif30>; ++ status = "disabled"; ++ }; ++ + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", +@@ -776,6 +898,68 @@ hscif4: serial@e66b0000 { + status = "disabled"; + }; + ++ msiof0: spi@e6e90000 { ++ compatible = "renesas,msiof-r8a7795", ++ "renesas,rcar-gen3-msiof"; ++ reg = <0 0xe6e90000 0 0x0064>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 211>; ++ dmas = <&dmac1 0x41>, <&dmac1 0x40>, ++ <&dmac2 0x41>, <&dmac2 0x40>; ++ dma-names = "tx", "rx", "tx", "rx"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 211>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ msiof1: spi@e6ea0000 { ++ compatible = "renesas,msiof-r8a7795", ++ "renesas,rcar-gen3-msiof"; ++ reg = <0 0xe6ea0000 0 0x0064>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 210>; ++ dmas = <&dmac1 0x43>, <&dmac1 0x42>, ++ <&dmac2 0x43>, <&dmac2 0x42>; ++ dma-names = "tx", "rx", "tx", "rx"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 210>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ msiof2: spi@e6c00000 { ++ compatible = "renesas,msiof-r8a7795", ++ "renesas,rcar-gen3-msiof"; ++ reg = <0 0xe6c00000 0 0x0064>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 209>; ++ dmas = <&dmac0 0x45>, <&dmac0 0x44>; ++ dma-names = "tx", "rx"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 209>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ msiof3: spi@e6c10000 { ++ compatible = "renesas,msiof-r8a7795", ++ "renesas,rcar-gen3-msiof"; ++ reg = <0 0xe6c10000 0 0x0064>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 208>; ++ dmas = <&dmac0 0x47>, <&dmac0 0x46>; ++ dma-names = "tx", "rx"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 208>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; +@@ -1267,7 +1451,8 @@ ssi9: ssi-9 { + }; + + sata: sata@ee300000 { +- compatible = "renesas,sata-r8a7795"; ++ compatible = "renesas,sata-r8a7795", ++ "renesas,rcar-gen3-sata"; + reg = <0 0xee300000 0 0x200000>; + interrupts = ; + clocks = <&cpg CPG_MOD 815>; +@@ -1314,6 +1499,34 @@ usb_dmac1: dma-controller@e65b0000 { + dma-channels = <2>; + }; + ++ usb_dmac2: dma-controller@e6460000 { ++ compatible = "renesas,r8a7795-usb-dmac", ++ "renesas,usb-dmac"; ++ reg = <0 0xe6460000 0 0x100>; ++ interrupts = ; ++ interrupt-names = "ch0", "ch1"; ++ clocks = <&cpg CPG_MOD 326>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 326>; ++ #dma-cells = <1>; ++ dma-channels = <2>; ++ }; ++ ++ usb_dmac3: dma-controller@e6470000 { ++ compatible = "renesas,r8a7795-usb-dmac", ++ "renesas,usb-dmac"; ++ reg = <0 0xe6470000 0 0x100>; ++ interrupts = ; ++ interrupt-names = "ch0", "ch1"; ++ clocks = <&cpg CPG_MOD 329>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 329>; ++ #dma-cells = <1>; ++ dma-channels = <2>; ++ }; ++ + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7795"; + reg = <0 0xee100000 0 0x2000>; +@@ -1392,6 +1605,18 @@ usb2_phy2: usb-phy@ee0c0200 { + status = "disabled"; + }; + ++ usb2_phy3: usb-phy@ee0e0200 { ++ compatible = "renesas,usb2-phy-r8a7795", ++ "renesas,rcar-gen3-usb2-phy"; ++ reg = <0 0xee0e0200 0 0x700>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 700>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 700>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; +@@ -1399,6 +1624,7 @@ ehci0: usb@ee080100 { + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; ++ companion = <&ohci0>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; +@@ -1411,6 +1637,7 @@ ehci1: usb@ee0a0100 { + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; ++ companion = <&ohci1>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; +@@ -1423,11 +1650,25 @@ ehci2: usb@ee0c0100 { + clocks = <&cpg CPG_MOD 701>; + phys = <&usb2_phy2>; + phy-names = "usb"; ++ companion = <&ohci2>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 701>; + status = "disabled"; + }; + ++ ehci3: usb@ee0e0100 { ++ compatible = "generic-ehci"; ++ reg = <0 0xee0e0100 0 0x100>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 700>; ++ phys = <&usb2_phy3>; ++ phy-names = "usb"; ++ companion = <&ohci3>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 700>; ++ status = "disabled"; ++ }; ++ + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; +@@ -1464,6 +1705,18 @@ ohci2: usb@ee0c0000 { + status = "disabled"; + }; + ++ ohci3: usb@ee0e0000 { ++ compatible = "generic-ohci"; ++ reg = <0 0xee0e0000 0 0x100>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 700>; ++ phys = <&usb2_phy3>; ++ phy-names = "usb"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 700>; ++ status = "disabled"; ++ }; ++ + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7795", + "renesas,rcar-gen3-usbhs"; +@@ -1481,6 +1734,23 @@ hsusb: usb@e6590000 { + status = "disabled"; + }; + ++ hsusb3: usb@e659c000 { ++ compatible = "renesas,usbhs-r8a7795", ++ "renesas,rcar-gen3-usbhs"; ++ reg = <0 0xe659c000 0 0x100>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 705>; ++ dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, ++ <&usb_dmac3 0>, <&usb_dmac3 1>; ++ dma-names = "ch0", "ch1", "ch2", "ch3"; ++ renesas,buswait = <11>; ++ phys = <&usb2_phy3>; ++ phy-names = "usb"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 705>; ++ status = "disabled"; ++ }; ++ + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a7795", + "renesas,pcie-rcar-gen3"; +@@ -1535,6 +1805,46 @@ pciec1: pcie@ee800000 { + status = "disabled"; + }; + ++ imr-lx4@fe860000 { ++ compatible = "renesas,r8a7795-imr-lx4", ++ "renesas,imr-lx4"; ++ reg = <0 0xfe860000 0 0x2000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 823>; ++ power-domains = <&sysc R8A7795_PD_A3VC>; ++ resets = <&cpg 823>; ++ }; ++ ++ imr-lx4@fe870000 { ++ compatible = "renesas,r8a7795-imr-lx4", ++ "renesas,imr-lx4"; ++ reg = <0 0xfe870000 0 0x2000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 822>; ++ power-domains = <&sysc R8A7795_PD_A3VC>; ++ resets = <&cpg 822>; ++ }; ++ ++ imr-lx4@fe880000 { ++ compatible = "renesas,r8a7795-imr-lx4", ++ "renesas,imr-lx4"; ++ reg = <0 0xfe880000 0 0x2000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 821>; ++ power-domains = <&sysc R8A7795_PD_A3VC>; ++ resets = <&cpg 821>; ++ }; ++ ++ imr-lx4@fe890000 { ++ compatible = "renesas,r8a7795-imr-lx4", ++ "renesas,imr-lx4"; ++ reg = <0 0xfe890000 0 0x2000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 820>; ++ power-domains = <&sysc R8A7795_PD_A3VC>; ++ resets = <&cpg 820>; ++ }; ++ + vspbc: vsp@fe920000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe920000 0 0x8000>; +@@ -1755,6 +2065,7 @@ port@1 { + }; + + du: display@feb00000 { ++ compatible = "renesas,du-r8a7795"; + reg = <0 0xfeb00000 0 0x80000>, + <0 0xfeb90000 0 0x14>; + reg-names = "du", "lvds.0"; +@@ -1768,6 +2079,7 @@ du: display@feb00000 { + <&cpg CPG_MOD 721>, + <&cpg CPG_MOD 727>; + clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0"; ++ vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>; + status = "disabled"; + + ports { +diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +index 38b58b7fca4b..daee1f1a3f68 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +@@ -9,8 +9,6 @@ + * kind, whether express or implied. + */ + +-#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4 +- + /dts-v1/; + #include "r8a7796.dtsi" + #include "ulcb.dtsi" +@@ -30,3 +28,15 @@ memory@600000000 { + reg = <0x6 0x00000000 0x0 0x40000000>; + }; + }; ++ ++&du { ++ clocks = <&cpg CPG_MOD 724>, ++ <&cpg CPG_MOD 723>, ++ <&cpg CPG_MOD 722>, ++ <&cpg CPG_MOD 727>, ++ <&versaclock5 1>, ++ <&versaclock5 3>, ++ <&versaclock5 2>; ++ clock-names = "du.0", "du.1", "du.2", "lvds.0", ++ "dclkin.0", "dclkin.1", "dclkin.2"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +index db4f162d6bdd..b317be03306e 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +@@ -8,8 +8,6 @@ + * kind, whether express or implied. + */ + +-#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4 +- + /dts-v1/; + #include "r8a7796.dtsi" + #include "salvator-x.dtsi" +@@ -29,3 +27,32 @@ memory@600000000 { + reg = <0x6 0x00000000 0x0 0x80000000>; + }; + }; ++ ++&du { ++ clocks = <&cpg CPG_MOD 724>, ++ <&cpg CPG_MOD 723>, ++ <&cpg CPG_MOD 722>, ++ <&cpg CPG_MOD 727>, ++ <&versaclock5 1>, ++ <&x21_clk>, ++ <&versaclock5 2>; ++ clock-names = "du.0", "du.1", "du.2", "lvds.0", ++ "dclkin.0", "dclkin.1", "dclkin.2"; ++}; ++ ++&hdmi0 { ++ status = "okay"; ++ ++ ports { ++ port@1 { ++ reg = <1>; ++ rcar_dw_hdmi0_out: endpoint { ++ remote-endpoint = <&hdmi0_con>; ++ }; ++ }; ++ }; ++}; ++ ++&hdmi0_con { ++ remote-endpoint = <&rcar_dw_hdmi0_out>; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index 1f6710912045..369092e17e34 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -12,6 +12,8 @@ + #include + #include + ++#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4 ++ + / { + compatible = "renesas,r8a7796"; + #address-cells = <2>; +@@ -639,6 +641,126 @@ channel1 { + }; + }; + ++ drif00: rif@e6f40000 { ++ compatible = "renesas,r8a7796-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6f40000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 515>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x20>, <&dmac2 0x20>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 515>; ++ renesas,bonding = <&drif01>; ++ status = "disabled"; ++ }; ++ ++ drif01: rif@e6f50000 { ++ compatible = "renesas,r8a7796-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6f50000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 514>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x22>, <&dmac2 0x22>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 514>; ++ renesas,bonding = <&drif00>; ++ status = "disabled"; ++ }; ++ ++ drif10: rif@e6f60000 { ++ compatible = "renesas,r8a7796-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6f60000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 513>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x24>, <&dmac2 0x24>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 513>; ++ renesas,bonding = <&drif11>; ++ status = "disabled"; ++ }; ++ ++ drif11: rif@e6f70000 { ++ compatible = "renesas,r8a7796-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6f70000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 512>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x26>, <&dmac2 0x26>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 512>; ++ renesas,bonding = <&drif10>; ++ status = "disabled"; ++ }; ++ ++ drif20: rif@e6f80000 { ++ compatible = "renesas,r8a7796-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6f80000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 511>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x28>, <&dmac2 0x28>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 511>; ++ renesas,bonding = <&drif21>; ++ status = "disabled"; ++ }; ++ ++ drif21: rif@e6f90000 { ++ compatible = "renesas,r8a7796-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6f90000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 510>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 510>; ++ renesas,bonding = <&drif20>; ++ status = "disabled"; ++ }; ++ ++ drif30: rif@e6fa0000 { ++ compatible = "renesas,r8a7796-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6fa0000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 509>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 509>; ++ renesas,bonding = <&drif31>; ++ status = "disabled"; ++ }; ++ ++ drif31: rif@e6fb0000 { ++ compatible = "renesas,r8a7796-drif", ++ "renesas,rcar-gen3-drif"; ++ reg = <0 0xe6fb0000 0 0x64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 508>; ++ clock-names = "fck"; ++ dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; ++ dma-names = "rx", "rx"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 508>; ++ renesas,bonding = <&drif30>; ++ status = "disabled"; ++ }; ++ + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7796", + "renesas,etheravb-rcar-gen3"; +@@ -877,7 +999,7 @@ msiof0: spi@e6e90000 { + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; +- dma-names = "tx", "rx"; ++ dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; +@@ -893,7 +1015,7 @@ msiof1: spi@e6ea0000 { + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; +- dma-names = "tx", "rx"; ++ dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; +@@ -1101,36 +1223,133 @@ GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH + dma-channels = <16>; + }; + ++ usb_dmac0: dma-controller@e65a0000 { ++ compatible = "renesas,r8a7796-usb-dmac", ++ "renesas,usb-dmac"; ++ reg = <0 0xe65a0000 0 0x100>; ++ interrupts = ; ++ interrupt-names = "ch0", "ch1"; ++ clocks = <&cpg CPG_MOD 330>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 330>; ++ #dma-cells = <1>; ++ dma-channels = <2>; ++ }; ++ ++ usb_dmac1: dma-controller@e65b0000 { ++ compatible = "renesas,r8a7796-usb-dmac", ++ "renesas,usb-dmac"; ++ reg = <0 0xe65b0000 0 0x100>; ++ interrupts = ; ++ interrupt-names = "ch0", "ch1"; ++ clocks = <&cpg CPG_MOD 331>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 331>; ++ #dma-cells = <1>; ++ dma-channels = <2>; ++ }; ++ + hsusb: usb@e6590000 { +- /* placeholder */ ++ compatible = "renesas,usbhs-r8a7796", ++ "renesas,rcar-gen3-usbhs"; ++ reg = <0 0xe6590000 0 0x100>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 704>; ++ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, ++ <&usb_dmac1 0>, <&usb_dmac1 1>; ++ dma-names = "ch0", "ch1", "ch2", "ch3"; ++ renesas,buswait = <11>; ++ phys = <&usb2_phy0>; ++ phy-names = "usb"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 704>; ++ status = "disabled"; + }; + + xhci0: usb@ee000000 { +- /* placeholder */ ++ compatible = "renesas,xhci-r8a7796", ++ "renesas,rcar-gen3-xhci"; ++ reg = <0 0xee000000 0 0xc00>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 328>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 328>; ++ status = "disabled"; + }; + + ohci0: usb@ee080000 { +- /* placeholder */ ++ compatible = "generic-ohci"; ++ reg = <0 0xee080000 0 0x100>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 703>; ++ phys = <&usb2_phy0>; ++ phy-names = "usb"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 703>; ++ status = "disabled"; + }; + + ehci0: usb@ee080100 { +- /* placeholder */ ++ compatible = "generic-ehci"; ++ reg = <0 0xee080100 0 0x100>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 703>; ++ phys = <&usb2_phy0>; ++ phy-names = "usb"; ++ companion= <&ohci0>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 703>; ++ status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { +- /* placeholder */ ++ compatible = "renesas,usb2-phy-r8a7796", ++ "renesas,rcar-gen3-usb2-phy"; ++ reg = <0 0xee080200 0 0x700>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 703>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 703>; ++ #phy-cells = <0>; ++ status = "disabled"; + }; + + ohci1: usb@ee0a0000 { +- /* placeholder */ ++ compatible = "generic-ohci"; ++ reg = <0 0xee0a0000 0 0x100>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 702>; ++ phys = <&usb2_phy1>; ++ phy-names = "usb"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 702>; ++ status = "disabled"; + }; + + ehci1: usb@ee0a0100 { +- /* placeholder */ ++ compatible = "generic-ehci"; ++ reg = <0 0xee0a0100 0 0x100>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 702>; ++ phys = <&usb2_phy1>; ++ phy-names = "usb"; ++ companion= <&ohci1>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 702>; ++ status = "disabled"; + }; + + usb2_phy1: usb-phy@ee0a0200 { +- /* placeholder */ ++ compatible = "renesas,usb2-phy-r8a7796", ++ "renesas,rcar-gen3-usb2-phy"; ++ reg = <0 0xee0a0200 0 0x700>; ++ clocks = <&cpg CPG_MOD 702>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 702>; ++ #phy-cells = <0>; ++ status = "disabled"; + }; + + sdhi0: sd@ee100000 { +@@ -1440,8 +1659,150 @@ pciec1: pcie@ee800000 { + /* placeholder */ + }; + ++ fcpf0: fcp@fe950000 { ++ compatible = "renesas,fcpf"; ++ reg = <0 0xfe950000 0 0x200>; ++ clocks = <&cpg CPG_MOD 615>; ++ power-domains = <&sysc R8A7796_PD_A3VC>; ++ resets = <&cpg 615>; ++ }; ++ ++ vspb: vsp@fe960000 { ++ compatible = "renesas,vsp2"; ++ reg = <0 0xfe960000 0 0x8000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 626>; ++ power-domains = <&sysc R8A7796_PD_A3VC>; ++ resets = <&cpg 626>; ++ ++ renesas,fcp = <&fcpvb0>; ++ }; ++ ++ fcpvb0: fcp@fe96f000 { ++ compatible = "renesas,fcpv"; ++ reg = <0 0xfe96f000 0 0x200>; ++ clocks = <&cpg CPG_MOD 607>; ++ power-domains = <&sysc R8A7796_PD_A3VC>; ++ resets = <&cpg 607>; ++ }; ++ ++ vspi0: vsp@fe9a0000 { ++ compatible = "renesas,vsp2"; ++ reg = <0 0xfe9a0000 0 0x8000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 631>; ++ power-domains = <&sysc R8A7796_PD_A3VC>; ++ resets = <&cpg 631>; ++ ++ renesas,fcp = <&fcpvi0>; ++ }; ++ ++ fcpvi0: fcp@fe9af000 { ++ compatible = "renesas,fcpv"; ++ reg = <0 0xfe9af000 0 0x200>; ++ clocks = <&cpg CPG_MOD 611>; ++ power-domains = <&sysc R8A7796_PD_A3VC>; ++ resets = <&cpg 611>; ++ }; ++ ++ vspd0: vsp@fea20000 { ++ compatible = "renesas,vsp2"; ++ reg = <0 0xfea20000 0 0x4000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 623>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 623>; ++ ++ renesas,fcp = <&fcpvd0>; ++ }; ++ ++ fcpvd0: fcp@fea27000 { ++ compatible = "renesas,fcpv"; ++ reg = <0 0xfea27000 0 0x200>; ++ clocks = <&cpg CPG_MOD 603>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 603>; ++ }; ++ ++ vspd1: vsp@fea28000 { ++ compatible = "renesas,vsp2"; ++ reg = <0 0xfea28000 0 0x4000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 622>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 622>; ++ ++ renesas,fcp = <&fcpvd1>; ++ }; ++ ++ fcpvd1: fcp@fea2f000 { ++ compatible = "renesas,fcpv"; ++ reg = <0 0xfea2f000 0 0x200>; ++ clocks = <&cpg CPG_MOD 602>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 602>; ++ }; ++ ++ vspd2: vsp@fea30000 { ++ compatible = "renesas,vsp2"; ++ reg = <0 0xfea30000 0 0x4000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 621>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 621>; ++ ++ renesas,fcp = <&fcpvd2>; ++ }; ++ ++ fcpvd2: fcp@fea37000 { ++ compatible = "renesas,fcpv"; ++ reg = <0 0xfea37000 0 0x200>; ++ clocks = <&cpg CPG_MOD 601>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 601>; ++ }; ++ ++ hdmi0: hdmi@fead0000 { ++ compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi"; ++ reg = <0 0xfead0000 0 0x10000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>; ++ clock-names = "iahb", "isfr"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 729>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ dw_hdmi0_in: endpoint { ++ remote-endpoint = <&du_out_hdmi0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ + du: display@feb00000 { +- /* placeholder */ ++ compatible = "renesas,du-r8a7796"; ++ reg = <0 0xfeb00000 0 0x70000>, ++ <0 0xfeb90000 0 0x14>; ++ reg-names = "du", "lvds.0"; ++ interrupts = , ++ , ++ ; ++ clocks = <&cpg CPG_MOD 724>, ++ <&cpg CPG_MOD 723>, ++ <&cpg CPG_MOD 722>, ++ <&cpg CPG_MOD 727>; ++ clock-names = "du.0", "du.1", "du.2", "lvds.0"; ++ status = "disabled"; ++ ++ vsps = <&vspd0 &vspd1 &vspd2>; + + ports { + #address-cells = <1>; +@@ -1452,7 +1813,38 @@ port@0 { + du_out_rgb: endpoint { + }; + }; ++ port@1 { ++ reg = <1>; ++ du_out_hdmi0: endpoint { ++ remote-endpoint = <&dw_hdmi0_in>; ++ }; ++ }; ++ port@2 { ++ reg = <2>; ++ du_out_lvds0: endpoint { ++ }; ++ }; + }; + }; ++ ++ imr-lx4@fe860000 { ++ compatible = "renesas,r8a7796-imr-lx4", ++ "renesas,imr-lx4"; ++ reg = <0 0xfe860000 0 0x2000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 823>; ++ power-domains = <&sysc R8A7796_PD_A3VC>; ++ resets = <&cpg 823>; ++ }; ++ ++ imr-lx4@fe870000 { ++ compatible = "renesas,r8a7796-imr-lx4", ++ "renesas,imr-lx4"; ++ reg = <0 0xfe870000 0 0x2000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 822>; ++ power-domains = <&sysc R8A7796_PD_A3VC>; ++ resets = <&cpg 822>; ++ }; + }; + }; +diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +new file mode 100644 +index 000000000000..d144370051d5 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +@@ -0,0 +1,46 @@ ++/* ++ * Device Tree Source for the Draak board ++ * ++ * Copyright (C) 2016 Renesas Electronics Corp. ++ * Copyright (C) 2017 Glider bvba ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++#include "r8a77995.dtsi" ++ ++/ { ++ model = "Renesas Draak board based on r8a77995"; ++ compatible = "renesas,draak", "renesas,r8a77995"; ++ ++ aliases { ++ serial0 = &scif2; ++ }; ++ ++ chosen { ++ bootargs = "ignore_loglevel"; ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@48000000 { ++ device_type = "memory"; ++ /* first 128MB is reserved for secure area. */ ++ reg = <0x0 0x48000000 0x0 0x18000000>; ++ }; ++}; ++ ++&extal_clk { ++ clock-frequency = <48000000>; ++}; ++ ++&scif2 { ++ status = "okay"; ++}; ++ ++&rwdt { ++ timeout-sec = <60>; ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi +new file mode 100644 +index 000000000000..d0f95b78c022 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi +@@ -0,0 +1,155 @@ ++/* ++ * Device Tree Source for the r8a77995 SoC ++ * ++ * Copyright (C) 2016 Renesas Electronics Corp. ++ * Copyright (C) 2017 Glider bvba ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include ++#include ++ ++/ { ++ compatible = "renesas,r8a77995"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ psci { ++ compatible = "arm,psci-1.0", "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ a53_0: cpu@0 { ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ reg = <0x0>; ++ device_type = "cpu"; ++ power-domains = <&sysc 5>; ++ next-level-cache = <&L2_CA53>; ++ enable-method = "psci"; ++ }; ++ ++ L2_CA53: cache-controller-1 { ++ compatible = "cache"; ++ power-domains = <&sysc 21>; ++ cache-unified; ++ cache-level = <2>; ++ }; ++ }; ++ ++ extal_clk: extal { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ /* This value must be overridden by the board */ ++ clock-frequency = <0>; ++ }; ++ ++ scif_clk: scif { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <0>; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&gic>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ gic: interrupt-controller@f1010000 { ++ compatible = "arm,gic-400"; ++ #interrupt-cells = <3>; ++ #address-cells = <0>; ++ interrupt-controller; ++ reg = <0x0 0xf1010000 0 0x1000>, ++ <0x0 0xf1020000 0 0x20000>, ++ <0x0 0xf1040000 0 0x20000>, ++ <0x0 0xf1060000 0 0x20000>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 408>; ++ clock-names = "clk"; ++ power-domains = <&sysc 32>; ++ resets = <&cpg 408>; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ rwdt: watchdog@e6020000 { ++ compatible = "renesas,r8a77995-wdt", ++ "renesas,rcar-gen3-wdt"; ++ reg = <0 0xe6020000 0 0x0c>; ++ clocks = <&cpg CPG_MOD 402>; ++ power-domains = <&sysc 32>; ++ resets = <&cpg 402>; ++ status = "disabled"; ++ }; ++ ++ pmu_a53 { ++ compatible = "arm,cortex-a53-pmu"; ++ interrupts = ; ++ }; ++ ++ cpg: clock-controller@e6150000 { ++ compatible = "renesas,r8a77995-cpg-mssr"; ++ reg = <0 0xe6150000 0 0x1000>; ++ clocks = <&extal_clk>; ++ clock-names = "extal"; ++ #clock-cells = <2>; ++ #power-domain-cells = <0>; ++ #reset-cells = <1>; ++ }; ++ ++ rst: reset-controller@e6160000 { ++ compatible = "renesas,r8a77995-rst"; ++ reg = <0 0xe6160000 0 0x0200>; ++ }; ++ ++ pfc: pfc@e6060000 { ++ compatible = "renesas,pfc-r8a77995"; ++ reg = <0 0xe6060000 0 0x508>; ++ }; ++ ++ prr: chipid@fff00044 { ++ compatible = "renesas,prr"; ++ reg = <0 0xfff00044 0 4>; ++ }; ++ ++ sysc: system-controller@e6180000 { ++ compatible = "renesas,r8a77995-sysc"; ++ reg = <0 0xe6180000 0 0x0400>; ++ #power-domain-cells = <1>; ++ }; ++ ++ scif2: serial@e6e88000 { ++ compatible = "renesas,scif-r8a77995", ++ "renesas,rcar-gen3-scif", "renesas,scif"; ++ reg = <0 0xe6e88000 0 64>; ++ interrupts = ; ++ clocks = <&cpg CPG_MOD 310>, ++ <&cpg CPG_CORE 16>, ++ <&scif_clk>; ++ clock-names = "fck", "brg_int", "scif_clk"; ++ power-domains = <&sysc 32>; ++ resets = <&cpg 310>; ++ status = "disabled"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi +index f903957da504..4786c67b5e65 100644 +--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi ++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi +@@ -268,10 +268,6 @@ endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; +- port@3 { +- lvds_connector: endpoint { +- }; +- }; + }; + }; + +diff --git a/arch/arm64/boot/dts/renesas/salvator-xs.dtsi b/arch/arm64/boot/dts/renesas/salvator-xs.dtsi +index 81227e3c2c6f..bf4d200fb546 100644 +--- a/arch/arm64/boot/dts/renesas/salvator-xs.dtsi ++++ b/arch/arm64/boot/dts/renesas/salvator-xs.dtsi +@@ -18,3 +18,13 @@ / { + &extal_clk { + clock-frequency = <16640000>; + }; ++ ++&i2c4 { ++ versaclock6: clock-generator@6a { ++ compatible = "idt,5p49v6901"; ++ reg = <0x6a>; ++ #clock-cells = <1>; ++ clocks = <&x23_clk>; ++ clock-names = "xin"; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi +index d1a3f3b7a0ab..1b868df2393f 100644 +--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi ++++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi +@@ -34,6 +34,16 @@ audio_clkout: audio-clkout { + clock-frequency = <11289600>; + }; + ++ hdmi0-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi0_con: endpoint { ++ }; ++ }; ++ }; ++ + keyboard { + compatible = "gpio-keys"; + +@@ -120,6 +130,12 @@ x12_clk: x12 { + #clock-cells = <0>; + clock-frequency = <24576000>; + }; ++ ++ x23_clk: x23-clock { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <25000000>; ++ }; + }; + + &audio_clk_a { +@@ -153,6 +169,23 @@ &extalr_clk { + clock-frequency = <32768>; + }; + ++&hdmi0 { ++ status = "okay"; ++ ++ ports { ++ port@1 { ++ reg = <1>; ++ rcar_dw_hdmi0_out: endpoint { ++ remote-endpoint = <&hdmi0_con>; ++ }; ++ }; ++ }; ++}; ++ ++&hdmi0_con { ++ remote-endpoint = <&rcar_dw_hdmi0_out>; ++}; ++ + &i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; +@@ -189,6 +222,24 @@ cs2000: clk-multiplier@4f { + }; + }; + ++&i2c4 { ++ status = "okay"; ++ ++ clock-frequency = <400000>; ++ ++ versaclock5: clock-generator@6a { ++ compatible = "idt,5p49v5925"; ++ reg = <0x6a>; ++ #clock-cells = <1>; ++ clocks = <&x23_clk>; ++ clock-names = "xin"; ++ }; ++}; ++ ++&i2c_dvfs { ++ status = "okay"; ++}; ++ + &ohci1 { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index bcfa53b1e6b7..f1c9b13cea5c 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -1,4 +1,5 @@ + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb +@@ -7,6 +8,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb + + always := $(dtb-y) + subdir-y := $(dts-dirs) +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts +index b9f36dad17e6..8e6a65431756 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts +@@ -51,6 +51,25 @@ chosen { + stdout-path = "serial2:1500000n8"; + }; + ++ dc_12v: dc-12v { ++ compatible = "regulator-fixed"; ++ regulator-name = "dc_12v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ vcc_sys: vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&dc_12v>; ++ }; ++ + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; +@@ -69,6 +88,151 @@ &gmac2phy { + status = "okay"; + }; + ++&i2c1 { ++ status = "okay"; ++ ++ rk805: rk805@18 { ++ compatible = "rockchip,rk805"; ++ reg = <0x18>; ++ interrupt-parent = <&gpio2>; ++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk805-clkout2"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_io>; ++ vcc6-supply = <&vcc_io>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ ++ vdd_arm: DCDC_REG2 { ++ regulator-name = "vdd_arm"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <950000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_io: DCDC_REG4 { ++ regulator-name = "vcc_io"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_18: LDO_REG1 { ++ regulator-name = "vcc_18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc18_emmc: LDO_REG2 { ++ regulator-name = "vcc18_emmc"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_10: LDO_REG3 { ++ regulator-name = "vdd_10"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&pinctrl { ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ + &uart2 { + status = "okay"; + }; ++ ++&u2phy { ++ status = "okay"; ++}; ++ ++&u2phy_host { ++ status = "okay"; ++}; ++ ++&u2phy_otg { ++ status = "okay"; ++}; ++ ++&usb20_otg { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +new file mode 100644 +index 000000000000..d4f80786e7c2 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +@@ -0,0 +1,333 @@ ++/* ++ * Copyright (c) 2017 PINE64 ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "rk3328.dtsi" ++ ++/ { ++ model = "Pine64 Rock64"; ++ compatible = "pine64,rock64", "rockchip,rk3328"; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gmac_clkin: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ vcc_sd: sdmmc-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0m1_gpio>; ++ regulator-name = "vcc_sd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_io>; ++ }; ++ ++ vcc_host_5v: vcc-host-5v-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb30_host_drv>; ++ regulator-name = "vcc_host_5v"; ++ regulator-always-on; ++ vin-supply = <&vcc_sys>; ++ }; ++ ++ vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb20_host_drv>; ++ regulator-name = "vcc_host1_5v"; ++ regulator-always-on; ++ vin-supply = <&vcc_sys>; ++ }; ++ ++ vcc_sys: vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&emmc { ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; ++ vmmc-supply = <&vcc_io>; ++ vqmmc-supply = <&vcc18_emmc>; ++ status = "okay"; ++}; ++ ++&gmac2io { ++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; ++ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc_io>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmiim1_pins>; ++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x26>; ++ rx_delay = <0x11>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ rk805: rk805@18 { ++ compatible = "rockchip,rk805"; ++ reg = <0x18>; ++ interrupt-parent = <&gpio2>; ++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk805-clkout2"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_io>; ++ vcc6-supply = <&vcc_sys>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ ++ vdd_arm: DCDC_REG2 { ++ regulator-name = "vdd_arm"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <950000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_io: DCDC_REG4 { ++ regulator-name = "vcc_io"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_18: LDO_REG1 { ++ regulator-name = "vdd_18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc18_emmc: LDO_REG2 { ++ regulator-name = "vcc_18emmc"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_10: LDO_REG3 { ++ regulator-name = "vdd_10"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&io_domains { ++ status = "okay"; ++ ++ vccio1-supply = <&vcc_io>; ++ vccio2-supply = <&vcc18_emmc>; ++ vccio3-supply = <&vcc_io>; ++ vccio4-supply = <&vcc_18>; ++ vccio5-supply = <&vcc_io>; ++ vccio6-supply = <&vcc_io>; ++ pmuio-supply = <&vcc_io>; ++}; ++ ++&pinctrl { ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb2 { ++ usb20_host_drv: usb20-host-drv { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb3 { ++ usb30_host_drv: usb30-host-drv { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; ++ vmmc-supply = <&vcc_sd>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <0>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&u2phy { ++ status = "okay"; ++ ++ u2phy_host: host-port { ++ status = "okay"; ++ }; ++ ++ u2phy_otg: otg-port { ++ status = "okay"; ++ }; ++}; ++ ++&usb20_otg { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index d48bf5d9f8bd..6d615cb6e64d 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -47,6 +47,7 @@ + #include + #include + #include ++#include + + / { + compatible = "rockchip,rk3328"; +@@ -76,8 +77,11 @@ cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + clocks = <&cru ARMCLK>; ++ #cooling-cells = <2>; ++ dynamic-power-coefficient = <120>; + enable-method = "psci"; + next-level-cache = <&l2>; ++ operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu1: cpu@1 { +@@ -85,8 +89,10 @@ cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + clocks = <&cru ARMCLK>; ++ dynamic-power-coefficient = <120>; + enable-method = "psci"; + next-level-cache = <&l2>; ++ operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu2: cpu@2 { +@@ -94,8 +100,10 @@ cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + clocks = <&cru ARMCLK>; ++ dynamic-power-coefficient = <120>; + enable-method = "psci"; + next-level-cache = <&l2>; ++ operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu3: cpu@3 { +@@ -103,8 +111,10 @@ cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + clocks = <&cru ARMCLK>; ++ dynamic-power-coefficient = <120>; + enable-method = "psci"; + next-level-cache = <&l2>; ++ operating-points-v2 = <&cpu0_opp_table>; + }; + + l2: l2-cache0 { +@@ -112,6 +122,43 @@ l2: l2-cache0 { + }; + }; + ++ cpu0_opp_table: opp_table0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <950000>; ++ clock-latency-ns = <40000>; ++ opp-suspend; ++ }; ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <1100000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1225000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1296000000 { ++ opp-hz = /bits/ 64 <1296000000>; ++ opp-microvolt = <1300000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ + amba { + compatible = "simple-bus"; + #address-cells = <2>; +@@ -158,12 +205,84 @@ xin24m: xin24m { + clock-output-names = "xin24m"; + }; + ++ i2s0: i2s@ff000000 { ++ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; ++ reg = <0x0 0xff000000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; ++ clock-names = "i2s_clk", "i2s_hclk"; ++ dmas = <&dmac 11>, <&dmac 12>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ i2s1: i2s@ff010000 { ++ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; ++ reg = <0x0 0xff010000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; ++ clock-names = "i2s_clk", "i2s_hclk"; ++ dmas = <&dmac 14>, <&dmac 15>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ i2s2: i2s@ff020000 { ++ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; ++ reg = <0x0 0xff020000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; ++ clock-names = "i2s_clk", "i2s_hclk"; ++ dmas = <&dmac 0>, <&dmac 1>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ spdif: spdif@ff030000 { ++ compatible = "rockchip,rk3328-spdif"; ++ reg = <0x0 0xff030000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; ++ clock-names = "mclk", "hclk"; ++ dmas = <&dmac 10>; ++ dma-names = "tx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdifm2_tx>; ++ status = "disabled"; ++ }; ++ ++ pdm: pdm@ff040000 { ++ compatible = "rockchip,pdm"; ++ reg = <0x0 0xff040000 0x0 0x1000>; ++ clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; ++ clock-names = "pdm_clk", "pdm_hclk"; ++ dmas = <&dmac 16>; ++ dma-names = "rx"; ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&pdmm0_clk ++ &pdmm0_sdi0 ++ &pdmm0_sdi1 ++ &pdmm0_sdi2 ++ &pdmm0_sdi3>; ++ pinctrl-1 = <&pdmm0_clk_sleep ++ &pdmm0_sdi0_sleep ++ &pdmm0_sdi1_sleep ++ &pdmm0_sdi2_sleep ++ &pdmm0_sdi3_sleep>; ++ status = "disabled"; ++ }; ++ + grf: syscon@ff100000 { + compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff100000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ++ io_domains: io-domains { ++ compatible = "rockchip,rk3328-io-voltage-domain"; ++ status = "disabled"; ++ }; ++ + power: power-controller { + compatible = "rockchip,rk3328-power-controller"; + #power-domain-cells = <1>; +@@ -310,6 +429,108 @@ wdt: watchdog@ff1a0000 { + interrupts = ; + }; + ++ pwm0: pwm@ff1b0000 { ++ compatible = "rockchip,rk3328-pwm"; ++ reg = <0x0 0xff1b0000 0x0 0x10>; ++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pin>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm1: pwm@ff1b0010 { ++ compatible = "rockchip,rk3328-pwm"; ++ reg = <0x0 0xff1b0010 0x0 0x10>; ++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm1_pin>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm2: pwm@ff1b0020 { ++ compatible = "rockchip,rk3328-pwm"; ++ reg = <0x0 0xff1b0020 0x0 0x10>; ++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm2_pin>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm3: pwm@ff1b0030 { ++ compatible = "rockchip,rk3328-pwm"; ++ reg = <0x0 0xff1b0030 0x0 0x10>; ++ interrupts = ; ++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwmir_pin>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ thermal-zones { ++ soc_thermal: soc-thermal { ++ polling-delay-passive = <20>; ++ polling-delay = <1000>; ++ sustainable-power = <1000>; ++ ++ thermal-sensors = <&tsadc 0>; ++ ++ trips { ++ threshold: trip-point0 { ++ temperature = <70000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ target: trip-point1 { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ soc_crit: soc-crit { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&target>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ contribution = <4096>; ++ }; ++ }; ++ }; ++ ++ }; ++ ++ tsadc: tsadc@ff250000 { ++ compatible = "rockchip,rk3328-tsadc"; ++ reg = <0x0 0xff250000 0x0 0x100>; ++ interrupts = ; ++ assigned-clocks = <&cru SCLK_TSADC>; ++ assigned-clock-rates = <50000>; ++ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; ++ clock-names = "tsadc", "apb_pclk"; ++ pinctrl-names = "init", "default", "sleep"; ++ pinctrl-0 = <&otp_gpio>; ++ pinctrl-1 = <&otp_out>; ++ pinctrl-2 = <&otp_gpio>; ++ resets = <&cru SRST_TSADC>; ++ reset-names = "tsadc-apb"; ++ rockchip,grf = <&grf>; ++ rockchip,hw-tshut-temp = <100000>; ++ #thermal-sensor-cells = <1>; ++ status = "disabled"; ++ }; ++ + saradc: adc@ff280000 { + compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; + reg = <0x0 0xff280000 0x0 0x100>; +@@ -322,6 +543,51 @@ saradc: adc@ff280000 { + status = "disabled"; + }; + ++ h265e_mmu: iommu@ff330200 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff330200 0 0x100>; ++ interrupts = ; ++ interrupt-names = "h265e_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ vepu_mmu: iommu@ff340800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff340800 0x0 0x40>; ++ interrupts = ; ++ interrupt-names = "vepu_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ vpu_mmu: iommu@ff350800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff350800 0x0 0x40>; ++ interrupts = ; ++ interrupt-names = "vpu_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ rkvdec_mmu: iommu@ff360480 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; ++ interrupts = ; ++ interrupt-names = "rkvdec_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ vop_mmu: iommu@ff373f00 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff373f00 0x0 0x100>; ++ interrupts = ; ++ interrupt-names = "vop_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ + cru: clock-controller@ff440000 { + compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; + reg = <0x0 0xff440000 0x0 0x1000>; +@@ -374,6 +640,43 @@ cru: clock-controller@ff440000 { + <32768>; + }; + ++ usb2phy_grf: syscon@ff450000 { ++ compatible = "rockchip,rk3328-usb2phy-grf", "syscon", ++ "simple-mfd"; ++ reg = <0x0 0xff450000 0x0 0x10000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ u2phy: usb2-phy@100 { ++ compatible = "rockchip,rk3328-usb2phy"; ++ reg = <0x100 0x10>; ++ clocks = <&xin24m>; ++ clock-names = "phyclk"; ++ clock-output-names = "usb480m_phy"; ++ #clock-cells = <0>; ++ assigned-clocks = <&cru USB480M>; ++ assigned-clock-parents = <&u2phy>; ++ status = "disabled"; ++ ++ u2phy_otg: otg-port { ++ #phy-cells = <0>; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "otg-bvalid", "otg-id", ++ "linestate"; ++ status = "disabled"; ++ }; ++ ++ u2phy_host: host-port { ++ #phy-cells = <0>; ++ interrupts = ; ++ interrupt-names = "linestate"; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ + sdmmc: dwmmc@ff500000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff500000 0x0 0x4000>; +@@ -463,6 +766,45 @@ phy: phy@0 { + }; + }; + ++ usb20_otg: usb@ff580000 { ++ compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", ++ "snps,dwc2"; ++ reg = <0x0 0xff580000 0x0 0x40000>; ++ interrupts = ; ++ clocks = <&cru HCLK_OTG>; ++ clock-names = "otg"; ++ dr_mode = "otg"; ++ g-np-tx-fifo-size = <16>; ++ g-rx-fifo-size = <280>; ++ g-tx-fifo-size = <256 128 128 64 32 16>; ++ g-use-dma; ++ phys = <&u2phy_otg>; ++ phy-names = "usb2-phy"; ++ status = "disabled"; ++ }; ++ ++ usb_host0_ehci: usb@ff5c0000 { ++ compatible = "generic-ehci"; ++ reg = <0x0 0xff5c0000 0x0 0x10000>; ++ interrupts = ; ++ clocks = <&cru HCLK_HOST0>, <&u2phy>; ++ clock-names = "usbhost", "utmi"; ++ phys = <&u2phy_host>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ usb_host0_ohci: usb@ff5d0000 { ++ compatible = "generic-ohci"; ++ reg = <0x0 0xff5d0000 0x0 0x10000>; ++ interrupts = ; ++ clocks = <&cru HCLK_HOST0>, <&u2phy>; ++ clock-names = "usbhost", "utmi"; ++ phys = <&u2phy_host>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ + gic: interrupt-controller@ff811000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; +@@ -649,6 +991,62 @@ hdmii2c_xfer: hdmii2c-xfer { + }; + }; + ++ pdm-0 { ++ pdmm0_clk: pdmm0-clk { ++ rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; ++ }; ++ ++ pdmm0_fsync: pdmm0-fsync { ++ rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; ++ }; ++ ++ pdmm0_sdi0: pdmm0-sdi0 { ++ rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; ++ }; ++ ++ pdmm0_sdi1: pdmm0-sdi1 { ++ rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; ++ }; ++ ++ pdmm0_sdi2: pdmm0-sdi2 { ++ rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; ++ }; ++ ++ pdmm0_sdi3: pdmm0-sdi3 { ++ rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; ++ }; ++ ++ pdmm0_clk_sleep: pdmm0-clk-sleep { ++ rockchip,pins = ++ <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; ++ }; ++ ++ pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { ++ rockchip,pins = ++ <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; ++ }; ++ ++ pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { ++ rockchip,pins = ++ <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; ++ }; ++ ++ pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { ++ rockchip,pins = ++ <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; ++ }; ++ ++ pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { ++ rockchip,pins = ++ <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; ++ }; ++ ++ pdmm0_fsync_sleep: pdmm0-fsync-sleep { ++ rockchip,pins = ++ <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; ++ }; ++ }; ++ + tsadc { + otp_gpio: otp-gpio { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi +index 4772917c5f7e..a37220a9387c 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi +@@ -156,7 +156,6 @@ &emmc { + disable-wp; + mmc-pwrseq = <&emmc_pwrseq>; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +diff --git a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts +index e631d424f08e..5e4d3a7015f5 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts +@@ -117,7 +117,6 @@ &emmc { + clock-frequency = <150000000>; + disable-wp; + non-removable; +- num-slots = <1>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_flash>; + pinctrl-names = "default"; +diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts +index fac116acc12f..d3f6c8e0d206 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts +@@ -203,7 +203,6 @@ &emmc { + mmc-hs200-1_2v; + mmc-hs200-1_8v; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +@@ -347,7 +346,6 @@ &sdmmc { + max-frequency = <50000000>; + cap-sd-highspeed; + card-detect-delay = <200>; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts +index ff48edd8e348..13a9e22f5d2d 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts +@@ -86,12 +86,10 @@ &emmc { + cap-mmc-highspeed; + clock-frequency = <150000000>; + disable-wp; +- keep-power-in-suspend; + mmc-hs200-1_8v; + no-sdio; + no-sd; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; +@@ -281,7 +279,6 @@ &sdmmc { + card-detect-delay = <200>; + no-emmc; + no-sdio; +- num-slots = <1>; + sd-uhs-sdr12; + sd-uhs-sdr25; + pinctrl-names = "default"; +diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts +index 7134181f1dc2..b3510d56517a 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts +@@ -189,7 +189,6 @@ &emmc { + disable-wp; + mmc-pwrseq = <&emmc_pwrseq>; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +@@ -254,7 +253,6 @@ &sdio0 { + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; +- num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; + vmmc-supply = <&vcc_io>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi +index 6d5dc0587e59..e0518b4bc6c2 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi +@@ -113,7 +113,8 @@ cpu_l0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; +- ++ clocks = <&cru ARMCLKL>; ++ operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; /* min followed by max */ + }; + +@@ -122,6 +123,8 @@ cpu_l1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; ++ clocks = <&cru ARMCLKL>; ++ operating-points-v2 = <&cluster0_opp>; + }; + + cpu_l2: cpu@2 { +@@ -129,6 +132,8 @@ cpu_l2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; ++ clocks = <&cru ARMCLKL>; ++ operating-points-v2 = <&cluster0_opp>; + }; + + cpu_l3: cpu@3 { +@@ -136,6 +141,8 @@ cpu_l3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; ++ clocks = <&cru ARMCLKL>; ++ operating-points-v2 = <&cluster0_opp>; + }; + + cpu_b0: cpu@100 { +@@ -143,7 +150,8 @@ cpu_b0: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; +- ++ clocks = <&cru ARMCLKB>; ++ operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; /* min followed by max */ + }; + +@@ -152,6 +160,8 @@ cpu_b1: cpu@101 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; ++ clocks = <&cru ARMCLKB>; ++ operating-points-v2 = <&cluster1_opp>; + }; + + cpu_b2: cpu@102 { +@@ -159,6 +169,8 @@ cpu_b2: cpu@102 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; ++ clocks = <&cru ARMCLKB>; ++ operating-points-v2 = <&cluster1_opp>; + }; + + cpu_b3: cpu@103 { +@@ -166,6 +178,62 @@ cpu_b3: cpu@103 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; ++ clocks = <&cru ARMCLKB>; ++ operating-points-v2 = <&cluster1_opp>; ++ }; ++ }; ++ ++ cluster0_opp: opp-table0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <312000000>; ++ opp-microvolt = <950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <950000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <950000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <1025000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <1125000>; ++ }; ++ }; ++ ++ cluster1_opp: opp-table1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <312000000>; ++ opp-microvolt = <950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <950000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <950000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <975000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <1050000>; + }; + }; + +@@ -700,6 +768,19 @@ timer@ff810000 { + interrupts = ; + }; + ++ spdif: spdif@ff880000 { ++ compatible = "rockchip,rk3368-spdif"; ++ reg = <0x0 0xff880000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; ++ clock-names = "mclk", "hclk"; ++ dmas = <&dmac_bus 3>; ++ dma-names = "tx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdif_tx>; ++ status = "disabled"; ++ }; ++ + i2s_2ch: i2s-2ch@ff890000 { + compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff890000 0x0 0x1000>; +@@ -724,6 +805,55 @@ i2s_8ch: i2s-8ch@ff898000 { + status = "disabled"; + }; + ++ iep_mmu: iommu@ff900800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff900800 0x0 0x100>; ++ interrupts = ; ++ interrupt-names = "iep_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ isp_mmu: iommu@ff914000 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff914000 0x0 0x100>, ++ <0x0 0xff915000 0x0 0x100>; ++ interrupts = ; ++ interrupt-names = "isp_mmu"; ++ #iommu-cells = <0>; ++ rockchip,disable-mmu-reset; ++ status = "disabled"; ++ }; ++ ++ vop_mmu: iommu@ff930300 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff930300 0x0 0x100>; ++ interrupts = ; ++ interrupt-names = "vop_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ hevc_mmu: iommu@ff9a0440 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff9a0440 0x0 0x40>, ++ <0x0 0xff9a0480 0x0 0x40>; ++ interrupts = ; ++ interrupt-names = "hevc_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ vpu_mmu: iommu@ff9a0800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff9a0800 0x0 0x100>; ++ interrupts = , ++ ; ++ interrupt-names = "vepu_mmu", "vdpu_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ + gic: interrupt-controller@ffb71000 { + compatible = "arm,gic-400"; + interrupt-controller; +@@ -1024,6 +1154,12 @@ sdmmc_bus4: sdmmc-bus4 { + }; + }; + ++ spdif { ++ spdif_tx: spdif-tx { ++ rockchip,pins = <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; ++ }; ++ }; ++ + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts +index 42033bcc614c..56533c344ef2 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts +@@ -199,7 +199,7 @@ &pcie0 { + ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; +- pinctrl-0 = <&pcie_clkreqn>; ++ pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "disabled"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +index ba1d9810ad1e..7fd4bfcaa38e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +@@ -43,6 +43,7 @@ + /dts-v1/; + #include + #include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" + + / { + model = "Firefly-RK3399 Board"; +@@ -550,7 +551,7 @@ &pcie0 { + ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; +- pinctrl-0 = <&pcie_clkreqn>; ++ pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; + }; + +@@ -630,9 +631,20 @@ &saradc { + status = "okay"; + }; + ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; ++ status = "okay"; ++}; ++ + &sdhci { + bus-width = <8>; +- keep-power-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +index 7bd31066399b..a3d3cea7dc4f 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +@@ -264,6 +264,50 @@ touchscreen@4b { + }; + }; + ++&ppvar_bigcpu_pwm { ++ regulator-min-microvolt = <798674>; ++ regulator-max-microvolt = <1302172>; ++}; ++ ++&ppvar_bigcpu { ++ regulator-min-microvolt = <798674>; ++ regulator-max-microvolt = <1302172>; ++ ctrl-voltage-range = <798674 1302172>; ++}; ++ ++&ppvar_litcpu_pwm { ++ regulator-min-microvolt = <799065>; ++ regulator-max-microvolt = <1303738>; ++}; ++ ++&ppvar_litcpu { ++ regulator-min-microvolt = <799065>; ++ regulator-max-microvolt = <1303738>; ++ ctrl-voltage-range = <799065 1303738>; ++}; ++ ++&ppvar_gpu_pwm { ++ regulator-min-microvolt = <785782>; ++ regulator-max-microvolt = <1217729>; ++}; ++ ++&ppvar_gpu { ++ regulator-min-microvolt = <785782>; ++ regulator-max-microvolt = <1217729>; ++ ctrl-voltage-range = <785782 1217729>; ++}; ++ ++&ppvar_centerlogic_pwm { ++ regulator-min-microvolt = <800069>; ++ regulator-max-microvolt = <1049692>; ++}; ++ ++&ppvar_centerlogic { ++ regulator-min-microvolt = <800069>; ++ regulator-max-microvolt = <1049692>; ++ ctrl-voltage-range = <800069 1049692>; ++}; ++ + &saradc { + status = "okay"; + vref-supply = <&pp1800_ap_io>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +index eb5059344023..199a5118b20d 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +@@ -164,14 +164,9 @@ pp5000: pp5000 { + vin-supply = <&ppvar_sys>; + }; + +- ppvar_bigcpu: ppvar-bigcpu { ++ ppvar_bigcpu_pwm: ppvar-bigcpu-pwm { + compatible = "pwm-regulator"; +- regulator-name = "ppvar_bigcpu"; +- /* +- * OVP circuit requires special handling which is not yet +- * represented. Keep disabled for now. +- */ +- status = "disabled"; ++ regulator-name = "ppvar_bigcpu_pwm"; + + pwms = <&pwm1 0 3337 0>; + pwm-supply = <&ppvar_sys>; +@@ -181,18 +176,28 @@ ppvar_bigcpu: ppvar-bigcpu { + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; +- regulator-min-microvolt = <798674>; +- regulator-max-microvolt = <1302172>; ++ regulator-min-microvolt = <800107>; ++ regulator-max-microvolt = <1302232>; + }; + +- ppvar_litcpu: ppvar-litcpu { ++ ppvar_bigcpu: ppvar-bigcpu { ++ compatible = "vctrl-regulator"; ++ regulator-name = "ppvar_bigcpu"; ++ ++ regulator-min-microvolt = <800107>; ++ regulator-max-microvolt = <1302232>; ++ ++ ctrl-supply = <&ppvar_bigcpu_pwm>; ++ ctrl-voltage-range = <800107 1302232>; ++ ++ regulator-settling-time-up-us = <322>; ++ min-slew-down-rate = <225>; ++ ovp-threshold-percent = <16>; ++ }; ++ ++ ppvar_litcpu_pwm: ppvar-litcpu-pwm { + compatible = "pwm-regulator"; +- regulator-name = "ppvar_litcpu"; +- /* +- * OVP circuit requires special handling which is not yet +- * represented. Keep disabled for now. +- */ +- status = "disabled"; ++ regulator-name = "ppvar_litcpu_pwm"; + + pwms = <&pwm2 0 3337 0>; + pwm-supply = <&ppvar_sys>; +@@ -202,18 +207,28 @@ ppvar_litcpu: ppvar-litcpu { + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; +- regulator-min-microvolt = <799065>; +- regulator-max-microvolt = <1303738>; ++ regulator-min-microvolt = <797743>; ++ regulator-max-microvolt = <1307837>; + }; + +- ppvar_gpu: ppvar-gpu { ++ ppvar_litcpu: ppvar-litcpu { ++ compatible = "vctrl-regulator"; ++ regulator-name = "ppvar_litcpu"; ++ ++ regulator-min-microvolt = <797743>; ++ regulator-max-microvolt = <1307837>; ++ ++ ctrl-supply = <&ppvar_litcpu_pwm>; ++ ctrl-voltage-range = <797743 1307837>; ++ ++ regulator-settling-time-up-us = <384>; ++ min-slew-down-rate = <225>; ++ ovp-threshold-percent = <16>; ++ }; ++ ++ ppvar_gpu_pwm: ppvar-gpu-pwm { + compatible = "pwm-regulator"; +- regulator-name = "ppvar_gpu"; +- /* +- * OVP circuit requires special handling which is not yet +- * represented. Keep disabled for now. +- */ +- status = "disabled"; ++ regulator-name = "ppvar_gpu_pwm"; + + pwms = <&pwm0 0 3337 0>; + pwm-supply = <&ppvar_sys>; +@@ -223,18 +238,28 @@ ppvar_gpu: ppvar-gpu { + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; +- regulator-min-microvolt = <785782>; +- regulator-max-microvolt = <1217729>; ++ regulator-min-microvolt = <786384>; ++ regulator-max-microvolt = <1217747>; + }; + +- ppvar_centerlogic: ppvar-centerlogic { ++ ppvar_gpu: ppvar-gpu { ++ compatible = "vctrl-regulator"; ++ regulator-name = "ppvar_gpu"; ++ ++ regulator-min-microvolt = <786384>; ++ regulator-max-microvolt = <1217747>; ++ ++ ctrl-supply = <&ppvar_gpu_pwm>; ++ ctrl-voltage-range = <786384 1217747>; ++ ++ regulator-settling-time-up-us = <390>; ++ min-slew-down-rate = <225>; ++ ovp-threshold-percent = <16>; ++ }; ++ ++ ppvar_centerlogic_pwm: ppvar-centerlogic-pwm { + compatible = "pwm-regulator"; +- regulator-name = "ppvar_centerlogic"; +- /* +- * OVP circuit requires special handling which is not yet +- * represented. Keep disabled for now. +- */ +- status = "disabled"; ++ regulator-name = "ppvar_centerlogic_pwm"; + + pwms = <&pwm3 0 3337 0>; + pwm-supply = <&ppvar_sys>; +@@ -244,8 +269,23 @@ ppvar_centerlogic: ppvar-centerlogic { + /* EC turns on w/ ppvar_centerlogic_en; always on for AP */ + regulator-always-on; + regulator-boot-on; +- regulator-min-microvolt = <800069>; +- regulator-max-microvolt = <1049692>; ++ regulator-min-microvolt = <799434>; ++ regulator-max-microvolt = <1049925>; ++ }; ++ ++ ppvar_centerlogic: ppvar-centerlogic { ++ compatible = "vctrl-regulator"; ++ regulator-name = "ppvar_centerlogic"; ++ ++ regulator-min-microvolt = <799434>; ++ regulator-max-microvolt = <1049925>; ++ ++ ctrl-supply = <&ppvar_centerlogic_pwm>; ++ ctrl-voltage-range = <799434 1049925>; ++ ++ regulator-settling-time-up-us = <378>; ++ min-slew-down-rate = <225>; ++ ovp-threshold-percent = <16>; + }; + + /* Schematics call this PPVAR even though it's fixed */ +@@ -555,6 +595,11 @@ &emmc_phy { + status = "okay"; + }; + ++&gpu { ++ mali-supply = <&ppvar_gpu>; ++ status = "okay"; ++}; ++ + ap_i2c_mic: &i2c1 { + status = "okay"; + +@@ -567,12 +612,7 @@ ap_i2c_mic: &i2c1 { + headsetcodec: rt5514@57 { + compatible = "realtek,rt5514"; + reg = <0x57>; +- interrupt-parent = <&gpio1>; +- interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mic_int>; +- realtek,dmic-init-delay = <20>; +- wakeup-source; ++ realtek,dmic-init-delay-ms = <20>; + }; + }; + +@@ -781,9 +821,13 @@ &spi2 { + wacky_spi_audio: spi2@0 { + compatible = "realtek,rt5514"; + reg = <0>; +- ++ interrupt-parent = <&gpio1>; ++ interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mic_int>; + /* May run faster once verified. */ + spi-max-frequency = <10000000>; ++ wakeup-source; + }; + }; + +@@ -1031,7 +1075,7 @@ sdmmc_cmd: sdmmc-cmd { + * hurt and dw_mmc will ignore it. We make sure to disable + * the pull though so we don't burn needless power. + */ +- sdmmc_cd: sdmcc-cd { ++ sdmmc_cd: sdmmc-cd { + rockchip,pins = + <0 7 RK_FUNC_1 &pcfg_pull_none>; + }; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi +index be7fe635f7c1..d8a120f945c8 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi +@@ -118,6 +118,35 @@ opp08 { + opp-microvolt = <1250000>; + }; + }; ++ ++ gpu_opp_table: opp-table2 { ++ compatible = "operating-points-v2"; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <200000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <297000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <825000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <925000>; ++ }; ++ opp05 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <1075000>; ++ }; ++ }; + }; + + &cpu_l0 { +@@ -143,3 +172,7 @@ &cpu_b0 { + &cpu_b1 { + operating-points-v2 = <&cluster1_opp>; + }; ++ ++&gpu { ++ operating-points-v2 = <&gpu_opp_table>; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi +index c83460db130a..81617bcf2522 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi +@@ -110,6 +110,35 @@ opp07 { + opp-microvolt = <1200000>; + }; + }; ++ ++ gpu_opp_table: opp-table2 { ++ compatible = "operating-points-v2"; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <200000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <297000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <825000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <875000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <925000>; ++ }; ++ opp05 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <1100000>; ++ }; ++ }; + }; + + &cpu_l0 { +@@ -135,3 +164,7 @@ &cpu_b0 { + &cpu_b1 { + operating-points-v2 = <&cluster1_opp>; + }; ++ ++&gpu { ++ operating-points-v2 = <&gpu_opp_table>; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts +new file mode 100644 +index 000000000000..9a7486058455 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts +@@ -0,0 +1,228 @@ ++/* ++ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "rk3399-puma.dtsi" ++ ++/ { ++ model = "Theobroma Systems RK3399-Q7 SoM"; ++ compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ pinctrl-0 = <&led_pin_module>, <&led_sd_haikou>; ++ ++ sd-card-led { ++ label = "sd_card_led"; ++ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "mmc0"; ++ }; ++ }; ++ ++ dc_12v: dc-12v { ++ compatible = "regulator-fixed"; ++ regulator-name = "dc_12v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ vcc3v3_baseboard: vcc3v3-baseboard { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_baseboard"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&dc_12v>; ++ }; ++ ++ vcc5v0_otg: vcc5v0-otg-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&otg_vbus_drv>; ++ regulator-name = "vcc5v0_otg"; ++ regulator-always-on; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ clock-frequency = <400000>; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ clock-frequency = <400000>; ++}; ++ ++&i2c3 { ++ i2c-scl-rising-time-ns = <450>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++}; ++ ++&i2c4 { ++ status = "okay"; ++ clock-frequency = <400000>; ++}; ++ ++&i2c6 { ++ status = "okay"; ++ clock-frequency = <400000>; ++}; ++ ++&i2s0 { ++ status = "okay"; ++ rockchip,playback-channels = <8>; ++ rockchip,capture-channels = <8>; ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ ++&pcie_phy { ++ status = "okay"; ++}; ++ ++&pcie0 { ++ ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; ++ num-lanes = <4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_clkreqn_cpm>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&haikou_pin_hog>; ++ ++ hog { ++ haikou_pin_hog: haikou-pin-hog { ++ rockchip,pins = ++ /* LID_BTN */ ++ , ++ /* BATLOW# */ ++ , ++ /* SLP_BTN# */ ++ , ++ /* BIOS_DISABLE# */ ++ ; ++ }; ++ }; ++ ++ leds { ++ led_sd_haikou: led-sd-gpio { ++ rockchip,pins = ++ ; ++ }; ++ }; ++ ++ usb2 { ++ otg_vbus_drv: otg-vbus-drv { ++ rockchip,pins = ++ ; ++ }; ++ }; ++}; ++ ++&pwm0 { ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; ++ vmmc-supply = <&vcc3v3_baseboard>; ++ status = "okay"; ++}; ++ ++&spi5 { ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&usbdrd3_0 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&u2phy0_host { ++ phy-supply = <&vcc5v0_otg>; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +new file mode 100644 +index 000000000000..53ff3d191a1d +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +@@ -0,0 +1,547 @@ ++/* ++ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++ ++/ { ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_pin_module>; ++ ++ module-led { ++ label = "module_led"; ++ gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ panic-indicator; ++ }; ++ }; ++ ++ /* ++ * Overwrite the opp-table for CPUB as this board uses a different ++ * regulator (FAN53555) that only allows 10mV steps and therefore ++ * can't reach the operation point target voltages from rk3399-opp.dtsi ++ */ ++ /delete-node/ opp-table1; ++ cluster1_opp: opp-table1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <800000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <830000>; ++ opp-suspend; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <880000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <950000>; ++ }; ++ opp05 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <1030000>; ++ }; ++ opp06 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <1100000>; ++ }; ++ opp07 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <1200000>; ++ }; ++ opp08 { ++ opp-hz = /bits/ 64 <1992000000>; ++ opp-microvolt = <1230000>; ++ turbo-mode; ++ }; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++ vcc1v2_phy: vcc1v2-phy { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc1v2_phy"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; ++ enable-active-low; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ regulator-name = "vcc5v0_host"; ++ regulator-always-on; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vdd_log: vdd-log { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm2 0 25000 0>; ++ regulator-name = "vdd_log"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-always-on; ++ regulator-boot-on; ++ status = "okay"; ++ }; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gmac { ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc1v2_phy>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x10>; ++ rx_delay = <0x10>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ i2c-scl-rising-time-ns = <168>; ++ i2c-scl-falling-time-ns = <4>; ++ clock-frequency = <400000>; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ reg = <0x1b>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <22 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk808-clkout2"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc5v0_sys>; ++ vcc2-supply = <&vcc5v0_sys>; ++ vcc3-supply = <&vcc5v0_sys>; ++ vcc4-supply = <&vcc5v0_sys>; ++ vcc6-supply = <&vcc5v0_sys>; ++ vcc7-supply = <&vcc5v0_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc5v0_sys>; ++ vcc10-supply = <&vcc5v0_sys>; ++ vcc11-supply = <&vcc5v0_sys>; ++ vcc12-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc1v8_pmu>; ++ ++ regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-name = "vdd_center"; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-name = "vdd_cpu_l"; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-name = "vcc_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_ldo1: LDO_REG1 { ++ regulator-name = "vcc_ldo1"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_hdmi: LDO_REG2 { ++ regulator-name = "vcc1v8_hdmi"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_pmu: LDO_REG3 { ++ regulator-name = "vcc1v8_pmu"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_sd: LDO_REG4 { ++ regulator-name = "vcc_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_ldo5: LDO_REG5 { ++ regulator-name = "vcc_ldo5"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ldo6: LDO_REG6 { ++ regulator-name = "vcc_ldo6"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc0v9_hdmi: LDO_REG7 { ++ regulator-name = "vcc0v9_hdmi"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_efuse: LDO_REG8 { ++ regulator-name = "vcc_efuse"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s3: SWITCH_REG1 { ++ regulator-name = "vcc3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-name = "vcc3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_gpu: regulator@60 { ++ compatible = "fcs,fan53555"; ++ reg = <0x60>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1230000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++}; ++ ++&i2c7 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ fan: fan@18 { ++ compatible = "ti,amc6821"; ++ reg = <0x18>; ++ cooling-min-state = <0>; ++ cooling-max-state = <9>; ++ #cooling-cells = <2>; ++ }; ++ ++ rtc_twi: rtc@6f { ++ compatible = "isil,isl1208"; ++ reg = <0x6f>; ++ }; ++}; ++ ++&i2c8 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ vdd_cpu_b: regulator@60 { ++ compatible = "fcs,fan53555"; ++ reg = <0x60>; ++ vin-supply = <&vcc5v0_sys>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1230000>; ++ regulator-ramp-delay = <1000>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++}; ++ ++&io_domains { ++ status = "okay"; ++ bt656-supply = <&vcc_1v8>; ++ audio-supply = <&vcc_1v8>; ++ sdmmc-supply = <&vcc_sd>; ++ gpio1830-supply = <&vcc_1v8>; ++}; ++ ++&pmu_io_domains { ++ status = "okay"; ++ pmu1830-supply = <&vcc_1v8>; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&pinctrl { ++ i2c8 { ++ i2c8_xfer_a: i2c8-xfer { ++ rockchip,pins = ++ , ++ ; ++ }; ++ }; ++ ++ leds { ++ led_pin_module: led-module-gpio { ++ rockchip,pins = ++ ; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = ++ ; ++ }; ++ }; ++ ++ usb2 { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = ++ ; ++ }; ++ }; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ non-removable; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ vqmmc = <&vcc_sd>; ++}; ++ ++&spi1 { ++ status = "okay"; ++ ++ norflash: flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <50000000>; ++ }; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++ ++ u2phy1_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy1_host: host-port { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++ }; ++}; ++ ++&usbdrd3_1 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_1 { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts +new file mode 100644 +index 000000000000..b7bd88fb3ae3 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts +@@ -0,0 +1,240 @@ ++/* ++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include ++#include "rk3399-sapphire.dtsi" ++ ++/ { ++ model = "Excavator-RK3399 Board"; ++ compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; ++ ++ adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 1>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1800000>; ++ poll-interval = <100>; ++ ++ button-up { ++ label = "Volume Up"; ++ linux,code = ; ++ press-threshold-microvolt = <100000>; ++ }; ++ ++ button-down { ++ label = "Volume Down"; ++ linux,code = ; ++ press-threshold-microvolt = <300000>; ++ }; ++ ++ back { ++ label = "Back"; ++ linux,code = ; ++ press-threshold-microvolt = <985000>; ++ }; ++ ++ menu { ++ label = "Menu"; ++ linux,code = ; ++ press-threshold-microvolt = <1314000>; ++ }; ++ }; ++ ++ edp_panel: edp-panel { ++ compatible ="lg,lp079qx1-sp0v", "simple-panel"; ++ backlight = <&backlight>; ++ enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lcd_panel_reset>; ++ power-supply = <&vcc3v3_s0>; ++ ++ ports { ++ panel_in_edp: endpoint { ++ remote-endpoint = <&edp_out_panel>; ++ }; ++ }; ++ }; ++ ++ keys: gpio-keys { ++ compatible = "gpio-keys"; ++ autorepeat; ++ ++ power { ++ debounce-interval = <100>; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "GPIO Power"; ++ linux,code = ; ++ linux,input-type = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwr_btn>; ++ wakeup-source; ++ }; ++ }; ++ ++ rt5651-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "realtek,rt5651-codec"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,widgets = ++ "Microphone", "Mic Jack", ++ "Headphone", "Headphone Jack"; ++ simple-audio-card,routing = ++ "Mic Jack", "MICBIAS1", ++ "IN1P", "Mic Jack", ++ "Headphone Jack", "HPOL", ++ "Headphone Jack", "HPOR"; ++ simple-audio-card,cpu { ++ sound-dai = <&i2s0>; ++ }; ++ simple-audio-card,codec { ++ sound-dai = <&rt5651>; ++ }; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk808 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_enable_h>; ++ ++ /* ++ * On the module itself this is one of these (depending ++ * on the actual card populated): ++ * - SDIO_RESET_L_WL_REG_ON ++ * - PDN (power down when low) ++ */ ++ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&backlight { ++ enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&edp { ++ status = "okay"; ++ ++ ports { ++ edp_out: port@1 { ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ edp_out_panel: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&panel_in_edp>; ++ }; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ i2c-scl-rising-time-ns = <300>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++ ++ rt5651: rt5651@1a { ++ compatible = "rockchip,rt5651"; ++ reg = <0x1a>; ++ clocks = <&cru SCLK_I2S_8CH_OUT>; ++ clock-names = "mclk"; ++ hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; ++ spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; ++ #sound-dai-cells = <0>; ++ }; ++}; ++ ++&i2c4 { ++ i2c-scl-rising-time-ns = <600>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++ ++ accelerometer@68 { ++ compatible = "invensense,mpu6500"; ++ reg = <0x68>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ }; ++}; ++ ++&i2s0 { ++ rockchip,playback-channels = <8>; ++ rockchip,capture-channels = <8>; ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ ++&i2s2 { ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ buttons { ++ pwr_btn: pwr-btn { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ sdio-pwrseq { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ lcd-panel { ++ lcd_panel_reset: lcd-panel-reset { ++ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&spdif { ++ i2c-scl-rising-time-ns = <450>; ++ i2c-scl-falling-time-ns = <15>; ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +new file mode 100644 +index 000000000000..6c30bb02210d +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +@@ -0,0 +1,644 @@ ++/* ++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include "dt-bindings/pwm/pwm.h" ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++ ++/ { ++ compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ brightness-levels = < ++ 0 1 2 3 4 5 6 7 ++ 8 9 10 11 12 13 14 15 ++ 16 17 18 19 20 21 22 23 ++ 24 25 26 27 28 29 30 31 ++ 32 33 34 35 36 37 38 39 ++ 40 41 42 43 44 45 46 47 ++ 48 49 50 51 52 53 54 55 ++ 56 57 58 59 60 61 62 63 ++ 64 65 66 67 68 69 70 71 ++ 72 73 74 75 76 77 78 79 ++ 80 81 82 83 84 85 86 87 ++ 88 89 90 91 92 93 94 95 ++ 96 97 98 99 100 101 102 103 ++ 104 105 106 107 108 109 110 111 ++ 112 113 114 115 116 117 118 119 ++ 120 121 122 123 124 125 126 127 ++ 128 129 130 131 132 133 134 135 ++ 136 137 138 139 140 141 142 143 ++ 144 145 146 147 148 149 150 151 ++ 152 153 154 155 156 157 158 159 ++ 160 161 162 163 164 165 166 167 ++ 168 169 170 171 172 173 174 175 ++ 176 177 178 179 180 181 182 183 ++ 184 185 186 187 188 189 190 191 ++ 192 193 194 195 196 197 198 199 ++ 200 201 202 203 204 205 206 207 ++ 208 209 210 211 212 213 214 215 ++ 216 217 218 219 220 221 222 223 ++ 224 225 226 227 228 229 230 231 ++ 232 233 234 235 236 237 238 239 ++ 240 241 242 243 244 245 246 247 ++ 248 249 250 251 252 253 254 255>; ++ default-brightness-level = <200>; ++ pwms = <&pwm0 0 25000 0>; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++ dc_12v: dc-12v { ++ compatible = "regulator-fixed"; ++ regulator-name = "dc_12v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ /* switched by pmic_sleep */ ++ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc1v8_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_1v8>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_sys>; ++ }; ++ ++ vcc_sys: vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&dc_12v>; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ regulator-name = "vcc5v0_host"; ++ regulator-always-on; ++ vin-supply = <&vcc_sys>; ++ }; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gmac { ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc_lan>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x28>; ++ rx_delay = <0x11>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ ddc-i2c-bus = <&i2c3>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <168>; ++ i2c-scl-falling-time-ns = <4>; ++ status = "okay"; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ reg = <0x1b>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk808-clkout2"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l &pmic_dvs2>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc6-supply = <&vcc_sys>; ++ vcc7-supply = <&vcc_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc_sys>; ++ vcc10-supply = <&vcc_sys>; ++ vcc11-supply = <&vcc_sys>; ++ vcc12-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc1v8_pmu>; ++ ++ regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-name = "vdd_center"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-name = "vdd_cpu_l"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG1 { ++ regulator-name = "vcc1v8_dvp"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v0_tp: LDO_REG2 { ++ regulator-name = "vcc3v0_tp"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_pmu: LDO_REG3 { ++ regulator-name = "vcc1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_sdio: LDO_REG4 { ++ regulator-name = "vcc_sdio"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca3v0_codec: LDO_REG5 { ++ regulator-name = "vcca3v0_codec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-name = "vcc_1v5"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ vcca1v8_codec: LDO_REG7 { ++ regulator-name = "vcca1v8_codec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG8 { ++ regulator-name = "vcc_3v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc3v3_s3: vcc_lan: SWITCH_REG1 { ++ regulator-name = "vcc3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-name = "vcc3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_log: vdd-log { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm2 0 25000 1>; ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1400000>; ++ vin-supply = <&vcc_sys>; ++ }; ++}; ++ ++&i2c3 { ++ i2c-scl-rising-time-ns = <450>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++}; ++ ++&io_domains { ++ status = "okay"; ++ ++ bt656-supply = <&vcc_3v0>; ++ audio-supply = <&vcca1v8_codec>; ++ sdmmc-supply = <&vcc_sdio>; ++ gpio1830-supply = <&vcc_3v0>; ++}; ++ ++&pcie_phy { ++ status = "okay"; ++}; ++ ++&pcie0 { ++ assigned-clocks = <&cru SCLK_PCIEPHY_REF>; ++ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; ++ assigned-clock-rates = <100000000>; ++ ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; ++ num-lanes = <4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_clkreqn_cpm>; ++ status = "okay"; ++}; ++ ++&pmu_io_domains { ++ pmu1830-supply = <&vcc_3v0>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = ++ <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ pmic_dvs2: pmic-dvs2 { ++ rockchip,pins = ++ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel1_gpio: vsel1-gpio { ++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_gpio: vsel2-gpio { ++ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ usb2 { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = ++ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm0 { ++ status = "okay"; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca1v8_s3>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ keep-power-in-suspend; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ non-removable; ++ status = "okay"; ++}; ++ ++&sdio0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ clock-frequency = <50000000>; ++ disable-wp; ++ keep-power-in-suspend; ++ max-frequency = <50000000>; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ clock-frequency = <150000000>; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; ++ vqmmc-supply = <&vcc_sdio>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-mode = <1>; ++ /* tshut polarity 0:LOW 1:HIGH */ ++ rockchip,hw-tshut-polarity = <1>; ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++ ++ u2phy0_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy0_host: host-port { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++ }; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++ ++ u2phy1_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy1_host: host-port { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usbdrd3_0 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ status = "okay"; ++ dr_mode = "otg"; ++}; ++ ++&usbdrd3_1 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_1 { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopb_mmu { ++ status = "okay"; ++}; ++ ++&vopl { ++ status = "okay"; ++}; ++ ++&vopl_mmu { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 5b78ce16a87e..d79e9b3265b9 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -110,6 +110,7 @@ cpu_l0: cpu@0 { + enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + clocks = <&cru ARMCLKL>; ++ dynamic-power-coefficient = <100>; + }; + + cpu_l1: cpu@1 { +@@ -118,6 +119,7 @@ cpu_l1: cpu@1 { + reg = <0x0 0x1>; + enable-method = "psci"; + clocks = <&cru ARMCLKL>; ++ dynamic-power-coefficient = <100>; + }; + + cpu_l2: cpu@2 { +@@ -126,6 +128,7 @@ cpu_l2: cpu@2 { + reg = <0x0 0x2>; + enable-method = "psci"; + clocks = <&cru ARMCLKL>; ++ dynamic-power-coefficient = <100>; + }; + + cpu_l3: cpu@3 { +@@ -134,6 +137,7 @@ cpu_l3: cpu@3 { + reg = <0x0 0x3>; + enable-method = "psci"; + clocks = <&cru ARMCLKL>; ++ dynamic-power-coefficient = <100>; + }; + + cpu_b0: cpu@100 { +@@ -143,6 +147,7 @@ cpu_b0: cpu@100 { + enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + clocks = <&cru ARMCLKB>; ++ dynamic-power-coefficient = <436>; + }; + + cpu_b1: cpu@101 { +@@ -151,9 +156,15 @@ cpu_b1: cpu@101 { + reg = <0x0 0x101>; + enable-method = "psci"; + clocks = <&cru ARMCLKB>; ++ dynamic-power-coefficient = <436>; + }; + }; + ++ display-subsystem { ++ compatible = "rockchip,display-subsystem"; ++ ports = <&vopl_out>, <&vopb_out>; ++ }; ++ + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; +@@ -289,6 +300,7 @@ sdio0: dwmmc@fe310000 { + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; ++ power-domains = <&power RK3399_PD_SDIOAUDIO>; + resets = <&cru SRST_SDIO0>; + reset-names = "reset"; + status = "disabled"; +@@ -402,6 +414,7 @@ usbdrd_dwc3_0: dwc3 { + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + }; +@@ -429,6 +442,7 @@ usbdrd_dwc3_1: dwc3 { + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + }; +@@ -678,6 +692,7 @@ spi5: spi@ff200000 { + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; ++ power-domains = <&power RK3399_PD_SDIOAUDIO>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -950,6 +965,10 @@ pd_gpu@RK3399_PD_GPU { + }; + + /* These power domains are grouped by VD_LOGIC */ ++ pd_edp@RK3399_PD_EDP { ++ reg = ; ++ clocks = <&cru PCLK_EDP_CTRL>; ++ }; + pd_emmc@RK3399_PD_EMMC { + reg = ; + clocks = <&cru ACLK_EMMC>; +@@ -967,6 +986,11 @@ pd_sd@RK3399_PD_SD { + <&cru SCLK_SDMMC>; + pm_qos = <&qos_sd>; + }; ++ pd_sdioaudio@RK3399_PD_SDIOAUDIO { ++ reg = ; ++ clocks = <&cru HCLK_SDIO>; ++ pm_qos = <&qos_sdioaudio>; ++ }; + pd_vio@RK3399_PD_VIO { + reg = ; + #address-cells = <1>; +@@ -1153,6 +1177,33 @@ pwm3: pwm@ff420030 { + status = "disabled"; + }; + ++ vpu_mmu: iommu@ff650800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff650800 0x0 0x40>; ++ interrupts = ; ++ interrupt-names = "vpu_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ vdec_mmu: iommu@ff660480 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; ++ interrupts = ; ++ interrupt-names = "vdec_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ iep_mmu: iommu@ff670800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff670800 0x0 0x40>; ++ interrupts = ; ++ interrupt-names = "iep_mmu"; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ + efuse0: efuse@ff690000 { + compatible = "rockchip,rk3399-efuse"; + reg = <0x0 0xff690000 0x0 0x80>; +@@ -1387,6 +1438,7 @@ spdif: spdif@ff870000 { + clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_bus>; ++ power-domains = <&power RK3399_PD_SDIOAUDIO>; + status = "disabled"; + }; + +@@ -1401,6 +1453,7 @@ i2s0: i2s@ff880000 { + clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_8ch_bus>; ++ power-domains = <&power RK3399_PD_SDIOAUDIO>; + status = "disabled"; + }; + +@@ -1414,6 +1467,7 @@ i2s1: i2s@ff890000 { + clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_bus>; ++ power-domains = <&power RK3399_PD_SDIOAUDIO>; + status = "disabled"; + }; + +@@ -1425,6 +1479,224 @@ i2s2: i2s@ff8a0000 { + dma-names = "tx", "rx"; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; ++ power-domains = <&power RK3399_PD_SDIOAUDIO>; ++ status = "disabled"; ++ }; ++ ++ vopl: vop@ff8f0000 { ++ compatible = "rockchip,rk3399-vop-lit"; ++ reg = <0x0 0xff8f0000 0x0 0x3efc>; ++ interrupts = ; ++ assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; ++ assigned-clock-rates = <400000000>, <100000000>; ++ clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; ++ clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; ++ iommus = <&vopl_mmu>; ++ power-domains = <&power RK3399_PD_VOPL>; ++ resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; ++ reset-names = "axi", "ahb", "dclk"; ++ status = "disabled"; ++ ++ vopl_out: port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ vopl_out_mipi: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&mipi_in_vopl>; ++ }; ++ ++ vopl_out_edp: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&edp_in_vopl>; ++ }; ++ ++ vopl_out_hdmi: endpoint@2 { ++ reg = <2>; ++ remote-endpoint = <&hdmi_in_vopl>; ++ }; ++ }; ++ }; ++ ++ vopl_mmu: iommu@ff8f3f00 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff8f3f00 0x0 0x100>; ++ interrupts = ; ++ interrupt-names = "vopl_mmu"; ++ clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; ++ clock-names = "aclk", "hclk"; ++ power-domains = <&power RK3399_PD_VOPL>; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ vopb: vop@ff900000 { ++ compatible = "rockchip,rk3399-vop-big"; ++ reg = <0x0 0xff900000 0x0 0x3efc>; ++ interrupts = ; ++ assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; ++ assigned-clock-rates = <400000000>, <100000000>; ++ clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; ++ clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; ++ iommus = <&vopb_mmu>; ++ power-domains = <&power RK3399_PD_VOPB>; ++ resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; ++ reset-names = "axi", "ahb", "dclk"; ++ status = "disabled"; ++ ++ vopb_out: port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ vopb_out_edp: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&edp_in_vopb>; ++ }; ++ ++ vopb_out_mipi: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&mipi_in_vopb>; ++ }; ++ ++ vopb_out_hdmi: endpoint@2 { ++ reg = <2>; ++ remote-endpoint = <&hdmi_in_vopb>; ++ }; ++ }; ++ }; ++ ++ vopb_mmu: iommu@ff903f00 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff903f00 0x0 0x100>; ++ interrupts = ; ++ interrupt-names = "vopb_mmu"; ++ clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; ++ clock-names = "aclk", "hclk"; ++ power-domains = <&power RK3399_PD_VOPB>; ++ #iommu-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ isp0_mmu: iommu@ff914000 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; ++ interrupts = ; ++ interrupt-names = "isp0_mmu"; ++ #iommu-cells = <0>; ++ rockchip,disable-mmu-reset; ++ status = "disabled"; ++ }; ++ ++ isp1_mmu: iommu@ff924000 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; ++ interrupts = ; ++ interrupt-names = "isp1_mmu"; ++ #iommu-cells = <0>; ++ rockchip,disable-mmu-reset; ++ status = "disabled"; ++ }; ++ ++ hdmi: hdmi@ff940000 { ++ compatible = "rockchip,rk3399-dw-hdmi"; ++ reg = <0x0 0xff940000 0x0 0x20000>; ++ interrupts = ; ++ clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>; ++ clock-names = "iahb", "isfr", "vpll", "grf"; ++ power-domains = <&power RK3399_PD_HDCP>; ++ reg-io-width = <4>; ++ rockchip,grf = <&grf>; ++ status = "disabled"; ++ ++ ports { ++ hdmi_in: port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hdmi_in_vopb: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&vopb_out_hdmi>; ++ }; ++ hdmi_in_vopl: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&vopl_out_hdmi>; ++ }; ++ }; ++ }; ++ }; ++ ++ mipi_dsi: mipi@ff960000 { ++ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; ++ reg = <0x0 0xff960000 0x0 0x8000>; ++ interrupts = ; ++ clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, ++ <&cru SCLK_DPHY_TX0_CFG>; ++ clock-names = "ref", "pclk", "phy_cfg"; ++ power-domains = <&power RK3399_PD_VIO>; ++ rockchip,grf = <&grf>; ++ status = "disabled"; ++ ++ ports { ++ mipi_in: port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ mipi_in_vopb: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&vopb_out_mipi>; ++ }; ++ mipi_in_vopl: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&vopl_out_mipi>; ++ }; ++ }; ++ }; ++ }; ++ ++ edp: edp@ff970000 { ++ compatible = "rockchip,rk3399-edp"; ++ reg = <0x0 0xff970000 0x0 0x8000>; ++ interrupts = ; ++ clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>; ++ clock-names = "dp", "pclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&edp_hpd>; ++ power-domains = <&power RK3399_PD_EDP>; ++ resets = <&cru SRST_P_EDP_CTRL>; ++ reset-names = "dp"; ++ rockchip,grf = <&grf>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ edp_in: port@0 { ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ edp_in_vopb: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&vopb_out_edp>; ++ }; ++ ++ edp_in_vopl: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&vopl_out_edp>; ++ }; ++ }; ++ }; ++ }; ++ ++ gpu: gpu@ff9a0000 { ++ compatible = "rockchip,rk3399-mali", "arm,mali-t860"; ++ reg = <0x0 0xff9a0000 0x0 0x10000>; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "gpu", "job", "mmu"; ++ clocks = <&cru ACLK_GPU>; ++ power-domains = <&power RK3399_PD_GPU>; + status = "disabled"; + }; + +@@ -1788,7 +2060,7 @@ sdmmc_cmd: sdmmc-cmd { + <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; + }; + +- sdmmc_cd: sdmcc-cd { ++ sdmmc_cd: sdmmc-cd { + rockchip,pins = + <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; + }; +@@ -2092,16 +2364,6 @@ hdmi_cec: hdmi-cec { + }; + + pcie { +- pcie_clkreqn: pci-clkreqn { +- rockchip,pins = +- <2 26 RK_FUNC_2 &pcfg_pull_none>; +- }; +- +- pcie_clkreqnb: pci-clkreqnb { +- rockchip,pins = +- <4 24 RK_FUNC_1 &pcfg_pull_none>; +- }; +- + pcie_clkreqn_cpm: pci-clkreqn-cpm { + rockchip,pins = + <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +diff --git a/arch/arm64/boot/dts/socionext/Makefile b/arch/arm64/boot/dts/socionext/Makefile +index 4a13a3a97101..4bc091b365fd 100644 +--- a/arch/arm64/boot/dts/socionext/Makefile ++++ b/arch/arm64/boot/dts/socionext/Makefile +@@ -2,7 +2,8 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \ + uniphier-ld11-global.dtb \ + uniphier-ld11-ref.dtb \ + uniphier-ld20-global.dtb \ +- uniphier-ld20-ref.dtb ++ uniphier-ld20-ref.dtb \ ++ uniphier-pxs3-ref.dtb + + always := $(dtb-y) + clean-files := *.dtb +diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts +index 115357018ef7..2452b2243f42 100644 +--- a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts ++++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts +@@ -9,7 +9,7 @@ + */ + + /dts-v1/; +-/include/ "uniphier-ld11.dtsi" ++#include "uniphier-ld11.dtsi" + + / { + model = "UniPhier LD11 Global Board (REF_LD11_GP)"; +@@ -68,3 +68,7 @@ &usb1 { + &usb2 { + status = "okay"; + }; ++ ++&nand { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts +index cc8ebe34c27c..ffb473ad2e0f 100644 +--- a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts ++++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts +@@ -8,9 +8,9 @@ + */ + + /dts-v1/; +-/include/ "uniphier-ld11.dtsi" +-/include/ "uniphier-ref-daughter.dtsi" +-/include/ "uniphier-support-card.dtsi" ++#include "uniphier-ld11.dtsi" ++#include "uniphier-ref-daughter.dtsi" ++#include "uniphier-support-card.dtsi" + + / { + model = "UniPhier LD11 Reference Board"; +diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +index bdce5b89baec..ee4aff53a5f5 100644 +--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi ++++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +@@ -150,6 +150,17 @@ serial3: serial@54006b00 { + clocks = <&peri_clk 3>; + }; + ++ adamv@57920000 { ++ compatible = "socionext,uniphier-ld11-adamv", ++ "simple-mfd", "syscon"; ++ reg = <0x57920000 0x1000>; ++ ++ adamv_rst: reset { ++ compatible = "socionext,uniphier-ld11-adamv-reset"; ++ #reset-cells = <1>; ++ }; ++ }; ++ + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; +@@ -344,6 +355,13 @@ pinctrl: pinctrl { + }; + }; + ++ aidet: aidet@5fc20000 { ++ compatible = "socionext,uniphier-ld11-aidet"; ++ reg = <0x5fc20000 0x200>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ + gic: interrupt-controller@5fe00000 { + compatible = "arm,gic-v3"; + reg = <0x5fe00000 0x10000>, /* GICD */ +@@ -367,8 +385,23 @@ sys_rst: reset { + compatible = "socionext,uniphier-ld11-reset"; + #reset-cells = <1>; + }; ++ ++ watchdog { ++ compatible = "socionext,uniphier-wdt"; ++ }; ++ }; ++ ++ nand: nand@68000000 { ++ compatible = "socionext,uniphier-denali-nand-v5b"; ++ status = "disabled"; ++ reg-names = "nand_data", "denali_reg"; ++ reg = <0x68000000 0x20>, <0x68100000 0x1000>; ++ interrupts = <0 65 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_nand>; ++ clocks = <&sys_clk 2>; + }; + }; + }; + +-/include/ "uniphier-pinctrl.dtsi" ++#include "uniphier-pinctrl.dtsi" +diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts +index 9f620d4101b5..fc2bc9d75d35 100644 +--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts ++++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts +@@ -9,7 +9,7 @@ + */ + + /dts-v1/; +-/include/ "uniphier-ld20.dtsi" ++#include "uniphier-ld20.dtsi" + + / { + model = "UniPhier LD20 Global Board (REF_LD20_GP)"; +@@ -50,3 +50,7 @@ &serial1 { + &i2c0 { + status = "okay"; + }; ++ ++&nand { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts +index 494166aee24c..1ca0c8620dc5 100644 +--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts ++++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts +@@ -8,9 +8,9 @@ + */ + + /dts-v1/; +-/include/ "uniphier-ld20.dtsi" +-/include/ "uniphier-ref-daughter.dtsi" +-/include/ "uniphier-support-card.dtsi" ++#include "uniphier-ld20.dtsi" ++#include "uniphier-ref-daughter.dtsi" ++#include "uniphier-support-card.dtsi" + + / { + model = "UniPhier LD20 Reference Board"; +diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +index de1e75362817..a29c279b6e8e 100644 +--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi ++++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +@@ -219,6 +219,17 @@ serial3: serial@54006b00 { + clocks = <&peri_clk 3>; + }; + ++ adamv@57920000 { ++ compatible = "socionext,uniphier-ld20-adamv", ++ "simple-mfd", "syscon"; ++ reg = <0x57920000 0x1000>; ++ ++ adamv_rst: reset { ++ compatible = "socionext,uniphier-ld20-adamv-reset"; ++ #reset-cells = <1>; ++ }; ++ }; ++ + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; +@@ -309,7 +320,7 @@ smpctrl@59801000 { + sdctrl@59810000 { + compatible = "socionext,uniphier-ld20-sdctrl", + "simple-mfd", "syscon"; +- reg = <0x59810000 0x800>; ++ reg = <0x59810000 0x400>; + + sd_clk: clock { + compatible = "socionext,uniphier-ld20-sd-clock"; +@@ -365,6 +376,13 @@ pinctrl: pinctrl { + }; + }; + ++ aidet: aidet@5fc20000 { ++ compatible = "socionext,uniphier-ld20-aidet"; ++ reg = <0x5fc20000 0x200>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ + gic: interrupt-controller@5fe00000 { + compatible = "arm,gic-v3"; + reg = <0x5fe00000 0x10000>, /* GICD */ +@@ -388,8 +406,23 @@ sys_rst: reset { + compatible = "socionext,uniphier-ld20-reset"; + #reset-cells = <1>; + }; ++ ++ watchdog { ++ compatible = "socionext,uniphier-wdt"; ++ }; ++ }; ++ ++ nand: nand@68000000 { ++ compatible = "socionext,uniphier-denali-nand-v5b"; ++ status = "disabled"; ++ reg-names = "nand_data", "denali_reg"; ++ reg = <0x68000000 0x20>, <0x68100000 0x1000>; ++ interrupts = <0 65 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_nand>; ++ clocks = <&sys_clk 2>; + }; + }; + }; + +-/include/ "uniphier-pinctrl.dtsi" ++#include "uniphier-pinctrl.dtsi" +diff --git a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi +deleted file mode 120000 +index f42fb6f38bd3..000000000000 +--- a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi ++++ /dev/null +@@ -1 +0,0 @@ +-../../../../arm/boot/dts/uniphier-pinctrl.dtsi +\ No newline at end of file +diff --git a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi +new file mode 100644 +index 000000000000..9caabbb8bae3 +--- /dev/null ++++ b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi +@@ -0,0 +1 @@ ++#include +diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts +new file mode 100644 +index 000000000000..d65f746a3f9d +--- /dev/null ++++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts +@@ -0,0 +1,62 @@ ++/* ++ * Device Tree Source for UniPhier PXs3 Reference Board ++ * ++ * Copyright (C) 2017 Socionext Inc. ++ * Author: Masahiro Yamada ++ * ++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ */ ++ ++/dts-v1/; ++#include "uniphier-pxs3.dtsi" ++#include "uniphier-support-card.dtsi" ++ ++/ { ++ model = "UniPhier PXs3 Reference Board"; ++ compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ aliases { ++ serial0 = &serial0; ++ serial1 = &serial1; ++ serial2 = &serial2; ++ serial3 = &serial3; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c2 = &i2c2; ++ i2c3 = &i2c3; ++ i2c6 = &i2c6; ++ }; ++ ++ memory@80000000 { ++ device_type = "memory"; ++ reg = <0 0x80000000 0 0xa0000000>; ++ }; ++}; ++ ++ðsc { ++ interrupts = <0 52 4>; ++}; ++ ++&serial0 { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++}; ++ ++&i2c1 { ++ status = "okay"; ++}; ++ ++&i2c2 { ++ status = "okay"; ++}; ++ ++&i2c3 { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +new file mode 100644 +index 000000000000..384729fa740f +--- /dev/null ++++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +@@ -0,0 +1,367 @@ ++/* ++ * Device Tree Source for UniPhier PXs3 SoC ++ * ++ * Copyright (C) 2017 Socionext Inc. ++ * Author: Masahiro Yamada ++ * ++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ */ ++ ++/memreserve/ 0x80000000 0x02000000; ++ ++/ { ++ compatible = "socionext,uniphier-pxs3"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ interrupt-parent = <&gic>; ++ ++ cpus { ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ cpu-map { ++ cluster0 { ++ core0 { ++ cpu = <&cpu0>; ++ }; ++ core1 { ++ cpu = <&cpu1>; ++ }; ++ core2 { ++ cpu = <&cpu2>; ++ }; ++ core3 { ++ cpu = <&cpu3>; ++ }; ++ }; ++ }; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ reg = <0 0x000>; ++ clocks = <&sys_clk 33>; ++ enable-method = "psci"; ++ operating-points-v2 = <&cluster0_opp>; ++ }; ++ ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ reg = <0 0x001>; ++ clocks = <&sys_clk 33>; ++ enable-method = "psci"; ++ operating-points-v2 = <&cluster0_opp>; ++ }; ++ ++ cpu2: cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ reg = <0 0x002>; ++ clocks = <&sys_clk 33>; ++ enable-method = "psci"; ++ operating-points-v2 = <&cluster0_opp>; ++ }; ++ ++ cpu3: cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ reg = <0 0x003>; ++ clocks = <&sys_clk 33>; ++ enable-method = "psci"; ++ operating-points-v2 = <&cluster0_opp>; ++ }; ++ }; ++ ++ cluster0_opp: opp_table { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-250000000 { ++ opp-hz = /bits/ 64 <250000000>; ++ clock-latency-ns = <300>; ++ }; ++ opp-325000000 { ++ opp-hz = /bits/ 64 <325000000>; ++ clock-latency-ns = <300>; ++ }; ++ opp-500000000 { ++ opp-hz = /bits/ 64 <500000000>; ++ clock-latency-ns = <300>; ++ }; ++ opp-650000000 { ++ opp-hz = /bits/ 64 <650000000>; ++ clock-latency-ns = <300>; ++ }; ++ opp-666667000 { ++ opp-hz = /bits/ 64 <666667000>; ++ clock-latency-ns = <300>; ++ }; ++ opp-866667000 { ++ opp-hz = /bits/ 64 <866667000>; ++ clock-latency-ns = <300>; ++ }; ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ clock-latency-ns = <300>; ++ }; ++ opp-1300000000 { ++ opp-hz = /bits/ 64 <1300000000>; ++ clock-latency-ns = <300>; ++ }; ++ }; ++ ++ psci { ++ compatible = "arm,psci-1.0"; ++ method = "smc"; ++ }; ++ ++ clocks { ++ refclk: ref { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <25000000>; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = <1 13 4>, ++ <1 14 4>, ++ <1 11 4>, ++ <1 10 4>; ++ }; ++ ++ soc@0 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0 0xffffffff>; ++ ++ serial0: serial@54006800 { ++ compatible = "socionext,uniphier-uart"; ++ status = "disabled"; ++ reg = <0x54006800 0x40>; ++ interrupts = <0 33 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart0>; ++ clocks = <&peri_clk 0>; ++ }; ++ ++ serial1: serial@54006900 { ++ compatible = "socionext,uniphier-uart"; ++ status = "disabled"; ++ reg = <0x54006900 0x40>; ++ interrupts = <0 35 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1>; ++ clocks = <&peri_clk 1>; ++ }; ++ ++ serial2: serial@54006a00 { ++ compatible = "socionext,uniphier-uart"; ++ status = "disabled"; ++ reg = <0x54006a00 0x40>; ++ interrupts = <0 37 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2>; ++ clocks = <&peri_clk 2>; ++ }; ++ ++ serial3: serial@54006b00 { ++ compatible = "socionext,uniphier-uart"; ++ status = "disabled"; ++ reg = <0x54006b00 0x40>; ++ interrupts = <0 177 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart3>; ++ clocks = <&peri_clk 3>; ++ }; ++ ++ i2c0: i2c@58780000 { ++ compatible = "socionext,uniphier-fi2c"; ++ status = "disabled"; ++ reg = <0x58780000 0x80>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <0 41 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c0>; ++ clocks = <&peri_clk 4>; ++ clock-frequency = <100000>; ++ }; ++ ++ i2c1: i2c@58781000 { ++ compatible = "socionext,uniphier-fi2c"; ++ status = "disabled"; ++ reg = <0x58781000 0x80>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <0 42 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1>; ++ clocks = <&peri_clk 5>; ++ clock-frequency = <100000>; ++ }; ++ ++ i2c2: i2c@58782000 { ++ compatible = "socionext,uniphier-fi2c"; ++ status = "disabled"; ++ reg = <0x58782000 0x80>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <0 43 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ clocks = <&peri_clk 6>; ++ clock-frequency = <100000>; ++ }; ++ ++ i2c3: i2c@58783000 { ++ compatible = "socionext,uniphier-fi2c"; ++ status = "disabled"; ++ reg = <0x58783000 0x80>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <0 44 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3>; ++ clocks = <&peri_clk 7>; ++ clock-frequency = <100000>; ++ }; ++ ++ /* chip-internal connection for HDMI */ ++ i2c6: i2c@58786000 { ++ compatible = "socionext,uniphier-fi2c"; ++ reg = <0x58786000 0x80>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <0 26 4>; ++ clocks = <&peri_clk 10>; ++ clock-frequency = <400000>; ++ }; ++ ++ system_bus: system-bus@58c00000 { ++ compatible = "socionext,uniphier-system-bus"; ++ status = "disabled"; ++ reg = <0x58c00000 0x400>; ++ #address-cells = <2>; ++ #size-cells = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_system_bus>; ++ }; ++ ++ smpctrl@59801000 { ++ compatible = "socionext,uniphier-smpctrl"; ++ reg = <0x59801000 0x400>; ++ }; ++ ++ sdctrl@59810000 { ++ compatible = "socionext,uniphier-pxs3-sdctrl", ++ "simple-mfd", "syscon"; ++ reg = <0x59810000 0x400>; ++ ++ sd_clk: clock { ++ compatible = "socionext,uniphier-pxs3-sd-clock"; ++ #clock-cells = <1>; ++ }; ++ ++ sd_rst: reset { ++ compatible = "socionext,uniphier-pxs3-sd-reset"; ++ #reset-cells = <1>; ++ }; ++ }; ++ ++ perictrl@59820000 { ++ compatible = "socionext,uniphier-pxs3-perictrl", ++ "simple-mfd", "syscon"; ++ reg = <0x59820000 0x200>; ++ ++ peri_clk: clock { ++ compatible = "socionext,uniphier-pxs3-peri-clock"; ++ #clock-cells = <1>; ++ }; ++ ++ peri_rst: reset { ++ compatible = "socionext,uniphier-pxs3-peri-reset"; ++ #reset-cells = <1>; ++ }; ++ }; ++ ++ emmc: sdhc@5a000000 { ++ compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; ++ reg = <0x5a000000 0x400>; ++ interrupts = <0 78 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_emmc>; ++ clocks = <&sys_clk 4>; ++ bus-width = <8>; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ cdns,phy-input-delay-legacy = <4>; ++ cdns,phy-input-delay-mmc-highspeed = <2>; ++ cdns,phy-input-delay-mmc-ddr = <3>; ++ cdns,phy-dll-delay-sdclk = <21>; ++ cdns,phy-dll-delay-sdclk-hsmmc = <21>; ++ }; ++ ++ soc-glue@5f800000 { ++ compatible = "socionext,uniphier-pxs3-soc-glue", ++ "simple-mfd", "syscon"; ++ reg = <0x5f800000 0x2000>; ++ ++ pinctrl: pinctrl { ++ compatible = "socionext,uniphier-pxs3-pinctrl"; ++ }; ++ }; ++ ++ aidet: aidet@5fc20000 { ++ compatible = "socionext,uniphier-pxs3-aidet"; ++ reg = <0x5fc20000 0x200>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ gic: interrupt-controller@5fe00000 { ++ compatible = "arm,gic-v3"; ++ reg = <0x5fe00000 0x10000>, /* GICD */ ++ <0x5fe80000 0x80000>; /* GICR */ ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ interrupts = <1 9 4>; ++ }; ++ ++ sysctrl@61840000 { ++ compatible = "socionext,uniphier-pxs3-sysctrl", ++ "simple-mfd", "syscon"; ++ reg = <0x61840000 0x10000>; ++ ++ sys_clk: clock { ++ compatible = "socionext,uniphier-pxs3-clock"; ++ #clock-cells = <1>; ++ }; ++ ++ sys_rst: reset { ++ compatible = "socionext,uniphier-pxs3-reset"; ++ #reset-cells = <1>; ++ }; ++ ++ watchdog { ++ compatible = "socionext,uniphier-wdt"; ++ }; ++ }; ++ ++ nand: nand@68000000 { ++ compatible = "socionext,uniphier-denali-nand-v5b"; ++ status = "disabled"; ++ reg-names = "nand_data", "denali_reg"; ++ reg = <0x68000000 0x20>, <0x68100000 0x1000>; ++ interrupts = <0 65 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_nand>; ++ clocks = <&sys_clk 2>; ++ }; ++ }; ++}; ++ ++#include "uniphier-pinctrl.dtsi" +diff --git a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi +deleted file mode 120000 +index 4685a8d89cba..000000000000 +--- a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi ++++ /dev/null +@@ -1 +0,0 @@ +-../../../../arm/boot/dts/uniphier-ref-daughter.dtsi +\ No newline at end of file +diff --git a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi +new file mode 100644 +index 000000000000..e66d999d9f5d +--- /dev/null ++++ b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi +@@ -0,0 +1 @@ ++#include +diff --git a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi +deleted file mode 120000 +index 1246db9be2a1..000000000000 +--- a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi ++++ /dev/null +@@ -1 +0,0 @@ +-../../../../arm/boot/dts/uniphier-support-card.dtsi +\ No newline at end of file +diff --git a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi +new file mode 100644 +index 000000000000..28c5b4ed1d95 +--- /dev/null ++++ b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi +@@ -0,0 +1 @@ ++#include +diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi +index cdc6a437dcc7..b87b8316f4ac 100644 +--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi ++++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi +@@ -11,7 +11,7 @@ + * the License, or (at your option) any later version. + */ + +-&amba { ++/ { + misc_clk: misc_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; +@@ -29,12 +29,60 @@ sata_clk: sata_clk { + #clock-cells = <0>; + clock-frequency = <75000000>; + }; ++ ++ clk100: clk100 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <100000000>; ++ }; ++ ++ clk600: clk600 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <600000000>; ++ }; + }; + + &can0 { + clocks = <&misc_clk &misc_clk>; + }; + ++&can1 { ++ clocks = <&misc_clk &misc_clk>; ++}; ++ ++&fpd_dma_chan1 { ++ clocks = <&clk600>, <&clk100>; ++}; ++ ++&fpd_dma_chan2 { ++ clocks = <&clk600>, <&clk100>; ++}; ++ ++&fpd_dma_chan3 { ++ clocks = <&clk600>, <&clk100>; ++}; ++ ++&fpd_dma_chan4 { ++ clocks = <&clk600>, <&clk100>; ++}; ++ ++&fpd_dma_chan5 { ++ clocks = <&clk600>, <&clk100>; ++}; ++ ++&fpd_dma_chan6 { ++ clocks = <&clk600>, <&clk100>; ++}; ++ ++&fpd_dma_chan7 { ++ clocks = <&clk600>, <&clk100>; ++}; ++ ++&fpd_dma_chan8 { ++ clocks = <&clk600>, <&clk100>; ++}; ++ + &gem0 { + clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>; + }; +diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts +index ef1b9e573af0..bf552674a834 100644 +--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts ++++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts +@@ -13,13 +13,15 @@ + + /dts-v1/; + +-/include/ "zynqmp.dtsi" +-/include/ "zynqmp-ep108-clk.dtsi" ++#include "zynqmp.dtsi" ++#include "zynqmp-ep108-clk.dtsi" + + / { + model = "ZynqMP EP108"; + + aliases { ++ mmc0 = &sdhci0; ++ mmc1 = &sdhci1; + serial0 = &uart0; + }; + +@@ -37,6 +39,10 @@ &can0 { + status = "okay"; + }; + ++&can1 { ++ status = "okay"; ++}; ++ + &gem0 { + status = "okay"; + phy-handle = <&phy0>; +@@ -55,7 +61,7 @@ &i2c0 { + status = "okay"; + clock-frequency = <400000>; + eeprom@54 { +- compatible = "at,24c64"; ++ compatible = "atmel,24c64"; + reg = <0x54>; + }; + }; +@@ -64,7 +70,7 @@ &i2c1 { + status = "okay"; + clock-frequency = <400000>; + eeprom@55 { +- compatible = "at,24c64"; ++ compatible = "atmel,24c64"; + reg = <0x55>; + }; + }; +@@ -92,7 +98,7 @@ spi0_flash0: spi0_flash0@0 { + spi-max-frequency = <50000000>; + reg = <0>; + +- spi0_flash0@00000000 { ++ spi0_flash0@0 { + label = "spi0_flash0"; + reg = <0x0 0x100000>; + }; +@@ -109,7 +115,7 @@ spi1_flash0: spi1_flash0@0 { + spi-max-frequency = <50000000>; + reg = <0>; + +- spi1_flash0@00000000 { ++ spi1_flash0@0 { + label = "spi1_flash0"; + reg = <0x0 0x100000>; + }; +diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +index 54dc28351c8c..7665fbddff28 100644 +--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi ++++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +@@ -20,33 +20,84 @@ cpus { + #address-cells = <1>; + #size-cells = <0>; + +- cpu@0 { ++ cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; ++ operating-points-v2 = <&cpu_opp_table>; + reg = <0x0>; ++ cpu-idle-states = <&CPU_SLEEP_0>; + }; + +- cpu@1 { ++ cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x1>; ++ operating-points-v2 = <&cpu_opp_table>; ++ cpu-idle-states = <&CPU_SLEEP_0>; + }; + +- cpu@2 { ++ cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x2>; ++ operating-points-v2 = <&cpu_opp_table>; ++ cpu-idle-states = <&CPU_SLEEP_0>; + }; + +- cpu@3 { ++ cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x3>; ++ operating-points-v2 = <&cpu_opp_table>; ++ cpu-idle-states = <&CPU_SLEEP_0>; + }; ++ ++ idle-states { ++ entry-method = "arm,psci"; ++ ++ CPU_SLEEP_0: cpu-sleep-0 { ++ compatible = "arm,idle-state"; ++ arm,psci-suspend-param = <0x40000000>; ++ local-timer-stop; ++ entry-latency-us = <300>; ++ exit-latency-us = <600>; ++ min-residency-us = <10000>; ++ }; ++ }; ++ }; ++ ++ cpu_opp_table: cpu_opp_table { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ opp00 { ++ opp-hz = /bits/ 64 <1199999988>; ++ opp-microvolt = <1000000>; ++ clock-latency-ns = <500000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <599999994>; ++ opp-microvolt = <1000000>; ++ clock-latency-ns = <500000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <399999996>; ++ opp-microvolt = <1000000>; ++ clock-latency-ns = <500000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <299999997>; ++ opp-microvolt = <1000000>; ++ clock-latency-ns = <500000>; ++ }; ++ }; ++ ++ dcc: dcc { ++ compatible = "arm,dcc"; ++ status = "disabled"; + }; + + pmu { +@@ -119,6 +170,190 @@ can1: can@ff070000 { + rx-fifo-depth = <0x40>; + }; + ++ cci: cci@fd6e0000 { ++ compatible = "arm,cci-400"; ++ reg = <0x0 0xfd6e0000 0x0 0x9000>; ++ ranges = <0x0 0x0 0xfd6e0000 0x10000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ pmu@9000 { ++ compatible = "arm,cci-400-pmu,r1"; ++ reg = <0x9000 0x5000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 123 4>, ++ <0 123 4>, ++ <0 123 4>, ++ <0 123 4>, ++ <0 123 4>; ++ }; ++ }; ++ ++ /* GDMA */ ++ fpd_dma_chan1: dma@fd500000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xfd500000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 124 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <128>; ++ }; ++ ++ fpd_dma_chan2: dma@fd510000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xfd510000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 125 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <128>; ++ }; ++ ++ fpd_dma_chan3: dma@fd520000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xfd520000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 126 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <128>; ++ }; ++ ++ fpd_dma_chan4: dma@fd530000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xfd530000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 127 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <128>; ++ }; ++ ++ fpd_dma_chan5: dma@fd540000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xfd540000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 128 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <128>; ++ }; ++ ++ fpd_dma_chan6: dma@fd550000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xfd550000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 129 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <128>; ++ }; ++ ++ fpd_dma_chan7: dma@fd560000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xfd560000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 130 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <128>; ++ }; ++ ++ fpd_dma_chan8: dma@fd570000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xfd570000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 131 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <128>; ++ }; ++ ++ /* LPDDMA default allows only secured access. inorder to enable ++ * These dma channels, Users should ensure that these dma ++ * Channels are allowed for non secure access. ++ */ ++ lpd_dma_chan1: dma@ffa80000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xffa80000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 77 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <64>; ++ }; ++ ++ lpd_dma_chan2: dma@ffa90000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xffa90000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 78 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <64>; ++ }; ++ ++ lpd_dma_chan3: dma@ffaa0000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xffaa0000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 79 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <64>; ++ }; ++ ++ lpd_dma_chan4: dma@ffab0000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xffab0000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 80 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <64>; ++ }; ++ ++ lpd_dma_chan5: dma@ffac0000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xffac0000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 81 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <64>; ++ }; ++ ++ lpd_dma_chan6: dma@ffad0000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xffad0000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 82 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <64>; ++ }; ++ ++ lpd_dma_chan7: dma@ffae0000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xffae0000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 83 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <64>; ++ }; ++ ++ lpd_dma_chan8: dma@ffaf0000 { ++ status = "disabled"; ++ compatible = "xlnx,zynqmp-dma-1.0"; ++ reg = <0x0 0xffaf0000 0x0 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 84 4>; ++ clock-names = "clk_main", "clk_apb"; ++ xlnx,bus-width = <64>; ++ }; ++ + gem0: ethernet@ff0b0000 { + compatible = "cdns,gem"; + status = "disabled"; +@@ -215,12 +450,9 @@ pcie: pcie@fd0e0000 { + <0x0 0xfd480000 0x0 0x1000>, + <0x80 0x00000000 0x0 0x1000000>; + reg-names = "breg", "pcireg", "cfg"; +- ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 +- 0xe0000000 0x00000000 0x10000000 +- /* non-prefetchable memory */ +- 0x43000000 0x00000006 0x00000000 0x00000006 +- 0x00000000 0x00000002 0x00000000>; +- /* prefetchable memory */ ++ ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ ++ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ ++ bus-range = <0x00 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, +@@ -233,6 +465,16 @@ pcie_intc: legacy-interrupt-controller { + }; + }; + ++ rtc: rtc@ffa60000 { ++ compatible = "xlnx,zynqmp-rtc"; ++ status = "disabled"; ++ reg = <0x0 0xffa60000 0x0 0x100>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 26 4>, <0 27 4>; ++ interrupt-names = "alarm", "sec"; ++ calibration = <0x8000>; ++ }; ++ + sata: ahci@fd0c0000 { + compatible = "ceva,ahci-1v84"; + status = "disabled"; +@@ -262,13 +504,14 @@ sdhci1: sdhci@ff170000 { + smmu: smmu@fd800000 { + compatible = "arm,mmu-500"; + reg = <0x0 0xfd800000 0x0 0x20000>; ++ status = "disabled"; + #global-interrupts = <1>; + interrupt-parent = <&gic>; +- interrupts = <0 157 4>, +- <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, +- <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, +- <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, +- <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>; ++ interrupts = <0 155 4>, ++ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, ++ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, ++ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, ++ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; + }; + + spi0: spi@ff040000 { +@@ -330,7 +573,7 @@ ttc3: timer@ff140000 { + }; + + uart0: serial@ff000000 { +- compatible = "cdns,uart-r1p8"; ++ compatible = "cdns,uart-r1p12", "xlnx,xuartps"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 21 4>; +@@ -339,7 +582,7 @@ uart0: serial@ff000000 { + }; + + uart1: serial@ff010000 { +- compatible = "cdns,uart-r1p8"; ++ compatible = "cdns,uart-r1p12", "xlnx,xuartps"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 22 4>; +diff --git a/arch/arm64/boot/dts/zte/Makefile b/arch/arm64/boot/dts/zte/Makefile +index 667806620f59..d86c4def6bc9 100644 +--- a/arch/arm64/boot/dts/zte/Makefile ++++ b/arch/arm64/boot/dts/zte/Makefile +@@ -1,4 +1,5 @@ + dtb-$(CONFIG_ARCH_ZX) += zx296718-evb.dtb ++dtb-$(CONFIG_ARCH_ZX) += zx296718-pcbox.dtb + + always := $(dtb-y) + subdir-y := $(dts-dirs) +diff --git a/arch/arm64/boot/dts/zte/zx296718-evb.dts b/arch/arm64/boot/dts/zte/zx296718-evb.dts +index bb900d2bbcfb..cb2519ecd724 100644 +--- a/arch/arm64/boot/dts/zte/zx296718-evb.dts ++++ b/arch/arm64/boot/dts/zte/zx296718-evb.dts +@@ -57,16 +57,28 @@ memory@40000000 { + reg = <0x40000000 0x40000000>; + }; + +- sound0 { +- compatible = "simple-audio-card"; +- simple-audio-card,name = "zx_snd_spdif0"; ++ sound-spdif0 { ++ compatible = "audio-graph-card"; ++ dais = <&spdif0_port>; ++ }; + +- simple-audio-card,cpu { +- sound-dai = <&spdif0>; +- }; ++ sound-i2s0 { ++ compatible = "audio-graph-card"; ++ dais = <&i2s0_port>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lifier_pins>; ++ pa-gpios = <&bgpio4 0 GPIO_ACTIVE_HIGH>; ++ widgets = "Line", "Line Out Jack"; ++ routing = "Amplifier", "LINEOUTL", ++ "Amplifier", "LINEOUTR", ++ "Line Out Jack", "Amplifier"; ++ }; ++}; + +- simple-audio-card,codec { +- sound-dai = <&hdmi>; ++&aud96p22 { ++ port { ++ aud96p22_endpoint: endpoint { ++ remote-endpoint = <&i2s0_endpoint>; + }; + }; + }; +@@ -77,6 +89,36 @@ &emmc { + + &hdmi { + status = "okay"; ++ ++ port { ++ hdmi_endpoint: endpoint { ++ remote-endpoint = <&spdif0_endpoint>; ++ }; ++ }; ++}; ++ ++&i2c0 { ++ status = "okay"; ++}; ++ ++&i2s0 { ++ status = "okay"; ++ ++ i2s0_port: port { ++ i2s0_endpoint: endpoint { ++ remote-endpoint = <&aud96p22_endpoint>; ++ dai-format = "i2s"; ++ frame-master; ++ bitclock-master; ++ }; ++ }; ++}; ++ ++&pmm { ++ amplifier_pins: amplifier { ++ pins = "TSI3_DATA"; ++ function = "BGPIO"; ++ }; + }; + + &sd1 { +@@ -85,6 +127,16 @@ &sd1 { + + &spdif0 { + status = "okay"; ++ ++ spdif0_port: port { ++ spdif0_endpoint: endpoint { ++ remote-endpoint = <&hdmi_endpoint>; ++ }; ++ }; ++}; ++ ++&tvenc { ++ status = "okay"; + }; + + &uart0 { +diff --git a/arch/arm64/boot/dts/zte/zx296718-pcbox.dts b/arch/arm64/boot/dts/zte/zx296718-pcbox.dts +new file mode 100644 +index 000000000000..e02509f7082b +--- /dev/null ++++ b/arch/arm64/boot/dts/zte/zx296718-pcbox.dts +@@ -0,0 +1,143 @@ ++/* ++ * Copyright (C) 2017 Sanechips Technology Co., Ltd. ++ * Copyright 2017 Linaro Ltd. ++ * ++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ */ ++ ++/dts-v1/; ++#include "zx296718.dtsi" ++#include ++ ++/ { ++ model = "ZTE ZX296718 PCBOX Board"; ++ compatible = "zte,zx296718-pcbox", "zte,zx296718"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@80000000 { ++ device_type = "memory"; ++ reg = <0x80000000 0x80000000>; ++ }; ++ ++ a53_vdd0v9: regulator-a53 { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm 3 1250 PWM_POLARITY_INVERTED>; ++ regulator-name = "A53_VDD0V9"; ++ regulator-min-microvolt = <855000>; ++ regulator-max-microvolt = <1183000>; ++ pwm-dutycycle-unit = <100>; ++ pwm-dutycycle-range = <0 100>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ sound-spdif0 { ++ compatible = "audio-graph-card"; ++ dais = <&spdif0_port>; ++ }; ++ ++ sound-i2s0 { ++ compatible = "audio-graph-card"; ++ dais = <&i2s0_port>; ++ }; ++}; ++ ++&aud96p22 { ++ port { ++ aud96p22_endpoint: endpoint { ++ remote-endpoint = <&i2s0_endpoint>; ++ }; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&a53_vdd0v9>; ++}; ++ ++&emmc { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "disabled"; ++ ++ port { ++ hdmi_endpoint: endpoint { ++ remote-endpoint = <&spdif0_endpoint>; ++ }; ++ }; ++}; ++ ++&i2c0 { ++ status = "okay"; ++}; ++ ++&i2s0 { ++ status = "okay"; ++ ++ i2s0_port: port { ++ i2s0_endpoint: endpoint { ++ remote-endpoint = <&aud96p22_endpoint>; ++ dai-format = "i2s"; ++ frame-master; ++ bitclock-master; ++ }; ++ }; ++}; ++ ++&irdec { ++ status = "okay"; ++}; ++ ++&pmm { ++ pwm3_pins: pwm3 { ++ pins = "KEY_ROW2"; ++ function = "PWM"; ++ }; ++ ++ vga_pins: vga { ++ pins = "KEY_COL1", "KEY_COL2", "VGA_HS", "VGA_VS"; ++ function = "VGA"; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm3_pins>; ++ status = "okay"; ++}; ++ ++&sd0 { ++ status = "okay"; ++}; ++ ++&sd1 { ++ status = "okay"; ++}; ++ ++&spdif0 { ++ status = "okay"; ++ ++ spdif0_port: port { ++ spdif0_endpoint: endpoint { ++ remote-endpoint = <&hdmi_endpoint>; ++ }; ++ }; ++}; ++ ++&tvenc { ++ status = "disabled"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&vga { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vga_pins>; ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi +index d83bf789c864..6eef64761009 100644 +--- a/arch/arm64/boot/dts/zte/zx296718.dtsi ++++ b/arch/arm64/boot/dts/zte/zx296718.dtsi +@@ -53,6 +53,13 @@ / { + interrupt-parent = <&gic>; + + aliases { ++ gpio0 = &bgpio0; ++ gpio1 = &bgpio1; ++ gpio2 = &bgpio2; ++ gpio3 = &bgpio3; ++ gpio4 = &bgpio4; ++ gpio5 = &bgpio5; ++ gpio6 = &bgpio6; + serial0 = &uart0; + }; + +@@ -120,26 +127,31 @@ cluster0_opp: opp-table0 { + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <866000>; + clock-latency-ns = <500000>; + }; + + opp-648000000 { + opp-hz = /bits/ 64 <648000000>; ++ opp-microvolt = <866000>; + clock-latency-ns = <500000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <888000>; + clock-latency-ns = <500000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <898000>; + clock-latency-ns = <500000>; + }; + + opp-1188000000 { + opp-hz = /bits/ 64 <1188000000>; ++ opp-microvolt = <1015000>; + clock-latency-ns = <500000>; + }; + }; +@@ -283,11 +295,23 @@ soc { + compatible = "simple-bus"; + ranges; + ++ irdec: ir-decoder@111000 { ++ compatible = "zte,zx296718-irdec"; ++ reg = <0x111000 0x1000>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ + aon_sysctrl: aon-sysctrl@116000 { + compatible = "zte,zx296718-aon-sysctrl", "syscon"; + reg = <0x116000 0x1000>; + }; + ++ iocfg: pin-controller@119000 { ++ compatible = "zte,zx296718-iocfg"; ++ reg = <0x119000 0x1000>; ++ }; ++ + uart0: uart@11f000 { + compatible = "arm,pl011", "arm,primecell"; + arm,primecell-periphid = <0x001feffe>; +@@ -311,7 +335,6 @@ sd0: mmc@1110000 { + clock-frequency = <50000000>; + clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>; + clock-names = "biu", "ciu"; +- num-slots = <1>; + max-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; +@@ -336,7 +359,6 @@ sd1: mmc@1111000 { + clock-frequency = <167000000>; + clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>; + clock-names = "biu", "ciu"; +- num-slots = <1>; + max-frequency = <167000000>; + cap-sdio-irq; + cap-sd-highspeed; +@@ -360,12 +382,109 @@ lsp0crm: clock-controller@1420000 { + #clock-cells = <1>; + }; + ++ bgpio0: gpio@142d000 { ++ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; ++ reg = <0x142d000 0x40>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pmm 0 48 16>; ++ interrupts = ; ++ interrupt-parent = <&gic>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ bgpio1: gpio@142d040 { ++ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; ++ reg = <0x142d040 0x40>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pmm 0 80 16>; ++ interrupts = ; ++ interrupt-parent = <&gic>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ bgpio2: gpio@142d080 { ++ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; ++ reg = <0x142d080 0x40>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pmm 0 80 3 ++ &pmm 3 32 4 ++ &pmm 7 83 9>; ++ interrupts = ; ++ interrupt-parent = <&gic>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ bgpio3: gpio@142d0c0 { ++ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; ++ reg = <0x142d0c0 0x40>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pmm 0 92 16>; ++ interrupts = ; ++ interrupt-parent = <&gic>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ bgpio4: gpio@142d100 { ++ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; ++ reg = <0x142d100 0x40>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pmm 0 108 12 ++ &pmm 12 121 4>; ++ interrupts = ; ++ interrupt-parent = <&gic>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ bgpio5: gpio@142d140 { ++ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; ++ reg = <0x142d140 0x40>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pmm 0 125 16>; ++ interrupts = ; ++ interrupt-parent = <&gic>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ bgpio6: gpio@142d180 { ++ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; ++ reg = <0x142d180 0x40>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&pmm 0 141 2>; ++ interrupts = ; ++ interrupt-parent = <&gic>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ + lsp1crm: clock-controller@1430000 { + compatible = "zte,zx296718-lsp1crm"; + reg = <0x01430000 0x1000>; + #clock-cells = <1>; + }; + ++ pwm: pwm@1439000 { ++ compatible = "zte,zx296718-pwm"; ++ reg = <0x1439000 0x1000>; ++ clocks = <&lsp1crm LSP1_PWM_PCLK>, ++ <&lsp1crm LSP1_PWM_WCLK>; ++ clock-names = "pclk", "wclk"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + vou: vou@1440000 { + compatible = "zte,zx296718-vou"; + #address-cells = <1>; +@@ -387,6 +506,16 @@ dpc: dpc@0 { + "main_wclk", "aux_wclk"; + }; + ++ vga: vga@8000 { ++ compatible = "zte,zx296718-vga"; ++ reg = <0x8000 0x1000>; ++ interrupts = ; ++ clocks = <&topcrm VGA_I2C_WCLK>; ++ clock-names = "i2c_wclk"; ++ zte,vga-power-control = <&sysctrl 0x170 0xe0>; ++ status = "disabled"; ++ }; ++ + hdmi: hdmi@c000 { + compatible = "zte,zx296718-hdmi"; + reg = <0xc000 0x4000>; +@@ -413,6 +542,12 @@ topcrm: clock-controller@1461000 { + #clock-cells = <1>; + }; + ++ pmm: pin-controller@1462000 { ++ compatible = "zte,zx296718-pmm"; ++ reg = <0x1462000 0x1000>; ++ zte,auxiliary-controller = <&iocfg>; ++ }; ++ + sysctrl: sysctrl@1463000 { + compatible = "zte,zx296718-sysctrl", "syscon"; + reg = <0x1463000 0x1000>; +@@ -445,6 +580,38 @@ audiocrm: clock-controller@1480000 { + #clock-cells = <1>; + }; + ++ i2s0: i2s@1482000 { ++ compatible = "zte,zx296718-i2s", "zte,zx296702-i2s"; ++ reg = <0x01482000 0x1000>; ++ clocks = <&audiocrm AUDIO_I2S0_WCLK>, ++ <&audiocrm AUDIO_I2S0_PCLK>; ++ clock-names = "wclk", "pclk"; ++ assigned-clocks = <&audiocrm I2S0_WCLK_MUX>; ++ assigned-clock-parents = <&topcrm AUDIO_99M>; ++ interrupts = ; ++ dmas = <&dma 22>, <&dma 23>; ++ dma-names = "tx", "rx"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c0: i2c@1486000 { ++ compatible = "zte,zx296718-i2c"; ++ reg = <0x01486000 0x1000>; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&audiocrm AUDIO_I2C0_WCLK>; ++ clock-frequency = <1600000>; ++ status = "disabled"; ++ ++ aud96p22: codec@22 { ++ compatible = "zte,zx-aud96p22"; ++ #sound-dai-cells = <0>; ++ reg = <0x22>; ++ }; ++ }; ++ + spdif0: spdif@1488000 { + compatible = "zte,zx296702-spdif"; + reg = <0x1488000 0x1000>; +diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c +index a7ea5f3da89d..964489b39f6a 100644 +--- a/drivers/clk/meson/gxbb.c ++++ b/drivers/clk/meson/gxbb.c +@@ -1188,6 +1188,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = { + [CLKID_32K_CLK] = &gxbb_32k_clk.hw, + [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, + [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, ++ [NR_CLKS] = NULL, + }, + .num = NR_CLKS, + }; +@@ -1310,6 +1311,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = { + [CLKID_32K_CLK] = &gxbb_32k_clk.hw, + [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, + [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, ++ [NR_CLKS] = NULL, + }, + .num = NR_CLKS, + }; +diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h +index d63e77e8433d..5b1d4b374d1c 100644 +--- a/drivers/clk/meson/gxbb.h ++++ b/drivers/clk/meson/gxbb.h +@@ -167,130 +167,33 @@ + * CLKID index values + * + * These indices are entirely contrived and do not map onto the hardware. +- * Migrate them out of this header and into the DT header file when they need +- * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h ++ * It has now been decided to expose everything by default in the DT header: ++ * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want ++ * to expose, such as the internal muxes and dividers of composite clocks, ++ * will remain defined here. + */ +-#define CLKID_SYS_PLL 0 + /* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */ +-/* CLKID_HDMI_PLL */ +-#define CLKID_FIXED_PLL 3 +-/* CLKID_FCLK_DIV2 */ +-/* CLKID_FCLK_DIV3 */ +-/* CLKID_FCLK_DIV4 */ +-#define CLKID_FCLK_DIV5 7 +-#define CLKID_FCLK_DIV7 8 +-/* CLKID_GP0_PLL */ + #define CLKID_MPEG_SEL 10 + #define CLKID_MPEG_DIV 11 +-/* CLKID_CLK81 */ +-#define CLKID_MPLL0 13 +-#define CLKID_MPLL1 14 +-/* CLKID_MPLL2 */ +-#define CLKID_DDR 16 +-#define CLKID_DOS 17 +-#define CLKID_ISA 18 +-#define CLKID_PL301 19 +-#define CLKID_PERIPHS 20 +-/* CLKID_SPICC */ +-/* CLKID_I2C */ +-/* #define CLKID_SAR_ADC */ +-#define CLKID_SMART_CARD 24 +-/* CLKID_RNG0 */ +-/* CLKID_UART0 */ +-#define CLKID_SDHC 27 +-#define CLKID_STREAM 28 +-#define CLKID_ASYNC_FIFO 29 +-#define CLKID_SDIO 30 +-#define CLKID_ABUF 31 +-#define CLKID_HIU_IFACE 32 +-#define CLKID_ASSIST_MISC 33 +-/* CLKID_SPI */ +-#define CLKID_I2S_SPDIF 35 +-/* CLKID_ETH */ +-#define CLKID_DEMUX 37 +-/* CLKID_AIU_GLUE */ +-/* CLKID_IEC958 */ +-/* CLKID_I2S_OUT */ +-#define CLKID_AMCLK 41 +-#define CLKID_AIFIFO2 42 +-#define CLKID_MIXER 43 +-/* CLKID_MIXER_IFACE */ +-#define CLKID_ADC 45 +-#define CLKID_BLKMV 46 +-/* CLKID_AIU */ +-/* CLKID_UART1 */ +-#define CLKID_G2D 49 +-/* CLKID_USB0 */ +-/* CLKID_USB1 */ +-#define CLKID_RESET 52 +-#define CLKID_NAND 53 +-#define CLKID_DOS_PARSER 54 +-/* CLKID_USB */ +-#define CLKID_VDIN1 56 +-#define CLKID_AHB_ARB0 57 +-#define CLKID_EFUSE 58 +-#define CLKID_BOOT_ROM 59 +-#define CLKID_AHB_DATA_BUS 60 +-#define CLKID_AHB_CTRL_BUS 61 +-#define CLKID_HDMI_INTR_SYNC 62 +-/* CLKID_HDMI_PCLK */ +-/* CLKID_USB1_DDR_BRIDGE */ +-/* CLKID_USB0_DDR_BRIDGE */ +-#define CLKID_MMC_PCLK 66 +-#define CLKID_DVIN 67 +-/* CLKID_UART2 */ +-/* #define CLKID_SANA */ +-#define CLKID_VPU_INTR 70 +-#define CLKID_SEC_AHB_AHB3_BRIDGE 71 +-#define CLKID_CLK81_A53 72 +-#define CLKID_VCLK2_VENCI0 73 +-#define CLKID_VCLK2_VENCI1 74 +-#define CLKID_VCLK2_VENCP0 75 +-#define CLKID_VCLK2_VENCP1 76 +-/* CLKID_GCLK_VENCI_INT0 */ +-#define CLKID_GCLK_VENCI_INT 78 +-#define CLKID_DAC_CLK 79 +-/* CLKID_AOCLK_GATE */ +-/* CLKID_IEC958_GATE */ +-#define CLKID_ENC480P 82 +-#define CLKID_RNG1 83 +-#define CLKID_GCLK_VENCI_INT1 84 +-#define CLKID_VCLK2_VENCLMCC 85 +-#define CLKID_VCLK2_VENCL 86 +-#define CLKID_VCLK_OTHER 87 +-#define CLKID_EDP 88 +-#define CLKID_AO_MEDIA_CPU 89 +-#define CLKID_AO_AHB_SRAM 90 +-#define CLKID_AO_AHB_BUS 91 +-#define CLKID_AO_IFACE 92 +-/* CLKID_AO_I2C */ +-/* CLKID_SD_EMMC_A */ +-/* CLKID_SD_EMMC_B */ +-/* CLKID_SD_EMMC_C */ +-/* CLKID_SAR_ADC_CLK */ +-/* CLKID_SAR_ADC_SEL */ + #define CLKID_SAR_ADC_DIV 99 +-/* CLKID_MALI_0_SEL */ +-#define CLKID_MALI_0_DIV 101 +-/* CLKID_MALI_0 */ +-/* CLKID_MALI_1_SEL */ +-#define CLKID_MALI_1_DIV 104 +-/* CLKID_MALI_1 */ +-/* CLKID_MALI */ +-/* CLKID_CTS_AMCLK */ ++#define CLKID_MALI_0_DIV 101 ++#define CLKID_MALI_1_DIV 104 + #define CLKID_CTS_AMCLK_SEL 108 + #define CLKID_CTS_AMCLK_DIV 109 +-/* CLKID_CTS_MCLK_I958 */ + #define CLKID_CTS_MCLK_I958_SEL 111 + #define CLKID_CTS_MCLK_I958_DIV 112 +-/* CLKID_CTS_I958 */ +-#define CLKID_32K_CLK 114 + #define CLKID_32K_CLK_SEL 115 + #define CLKID_32K_CLK_DIV 116 ++#define CLKID_SD_EMMC_A_CLK0_SEL 117 ++#define CLKID_SD_EMMC_A_CLK0_DIV 118 ++#define CLKID_SD_EMMC_B_CLK0_SEL 120 ++#define CLKID_SD_EMMC_B_CLK0_DIV 121 ++#define CLKID_SD_EMMC_C_CLK0_SEL 123 ++#define CLKID_SD_EMMC_C_CLK0_DIV 124 + +-#define NR_CLKS 117 ++#define NR_CLKS 126 + +-/* include the CLKIDs that have been made part of the stable DT binding */ ++/* include the CLKIDs that have been made part of the DT binding */ + #include + + #endif /* __GXBB_H */ +diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c +index 6ec512ad2598..cb60a516ca82 100644 +--- a/drivers/clk/meson/meson8b.c ++++ b/drivers/clk/meson/meson8b.c +@@ -590,6 +590,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { + [CLKID_MPLL0] = &meson8b_mpll0.hw, + [CLKID_MPLL1] = &meson8b_mpll1.hw, + [CLKID_MPLL2] = &meson8b_mpll2.hw, ++ [CLK_NR_CLKS] = NULL, + }, + .num = CLK_NR_CLKS, + }; +diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h +index a687e02547dc..c139bb3273ca 100644 +--- a/drivers/clk/meson/meson8b.h ++++ b/drivers/clk/meson/meson8b.h +@@ -60,107 +60,12 @@ + * CLKID index values + * + * These indices are entirely contrived and do not map onto the hardware. +- * Migrate them out of this header and into the DT header file when they need +- * to be exposed to client nodes in DT: include/dt-bindings/clock/meson8b-clkc.h ++ * It has now been decided to expose everything by default in the DT header: ++ * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want ++ * to expose, such as the internal muxes and dividers of composite clocks, ++ * will remain defined here. + */ + +-/* CLKID_UNUSED */ +-/* CLKID_XTAL */ +-/* CLKID_PLL_FIXED */ +-/* CLKID_PLL_VID */ +-/* CLKID_PLL_SYS */ +-/* CLKID_FCLK_DIV2 */ +-/* CLKID_FCLK_DIV3 */ +-/* CLKID_FCLK_DIV4 */ +-/* CLKID_FCLK_DIV5 */ +-/* CLKID_FCLK_DIV7 */ +-/* CLKID_CLK81 */ +-/* CLKID_MALI */ +-/* CLKID_CPUCLK */ +-/* CLKID_ZERO */ +-/* CLKID_MPEG_SEL */ +-/* CLKID_MPEG_DIV */ +-#define CLKID_DDR 16 +-#define CLKID_DOS 17 +-#define CLKID_ISA 18 +-#define CLKID_PL301 19 +-#define CLKID_PERIPHS 20 +-#define CLKID_SPICC 21 +-#define CLKID_I2C 22 +-/* #define CLKID_SAR_ADC */ +-#define CLKID_SMART_CARD 24 +-/* #define CLKID_RNG0 */ +-#define CLKID_UART0 26 +-#define CLKID_SDHC 27 +-#define CLKID_STREAM 28 +-#define CLKID_ASYNC_FIFO 29 +-/* #define CLKID_SDIO */ +-#define CLKID_ABUF 31 +-#define CLKID_HIU_IFACE 32 +-#define CLKID_ASSIST_MISC 33 +-#define CLKID_SPI 34 +-#define CLKID_I2S_SPDIF 35 +-/* #define CLKID_ETH */ +-#define CLKID_DEMUX 37 +-#define CLKID_AIU_GLUE 38 +-#define CLKID_IEC958 39 +-#define CLKID_I2S_OUT 40 +-#define CLKID_AMCLK 41 +-#define CLKID_AIFIFO2 42 +-#define CLKID_MIXER 43 +-#define CLKID_MIXER_IFACE 44 +-#define CLKID_ADC 45 +-#define CLKID_BLKMV 46 +-#define CLKID_AIU 47 +-#define CLKID_UART1 48 +-#define CLKID_G2D 49 +-/* #define CLKID_USB0 */ +-/* #define CLKID_USB1 */ +-#define CLKID_RESET 52 +-#define CLKID_NAND 53 +-#define CLKID_DOS_PARSER 54 +-/* #define CLKID_USB */ +-#define CLKID_VDIN1 56 +-#define CLKID_AHB_ARB0 57 +-#define CLKID_EFUSE 58 +-#define CLKID_BOOT_ROM 59 +-#define CLKID_AHB_DATA_BUS 60 +-#define CLKID_AHB_CTRL_BUS 61 +-#define CLKID_HDMI_INTR_SYNC 62 +-#define CLKID_HDMI_PCLK 63 +-/* CLKID_USB1_DDR_BRIDGE */ +-/* CLKID_USB0_DDR_BRIDGE */ +-#define CLKID_MMC_PCLK 66 +-#define CLKID_DVIN 67 +-#define CLKID_UART2 68 +-/* #define CLKID_SANA */ +-#define CLKID_VPU_INTR 70 +-#define CLKID_SEC_AHB_AHB3_BRIDGE 71 +-#define CLKID_CLK81_A9 72 +-#define CLKID_VCLK2_VENCI0 73 +-#define CLKID_VCLK2_VENCI1 74 +-#define CLKID_VCLK2_VENCP0 75 +-#define CLKID_VCLK2_VENCP1 76 +-#define CLKID_GCLK_VENCI_INT 77 +-#define CLKID_GCLK_VENCP_INT 78 +-#define CLKID_DAC_CLK 79 +-#define CLKID_AOCLK_GATE 80 +-#define CLKID_IEC958_GATE 81 +-#define CLKID_ENC480P 82 +-#define CLKID_RNG1 83 +-#define CLKID_GCLK_VENCL_INT 84 +-#define CLKID_VCLK2_VENCLMCC 85 +-#define CLKID_VCLK2_VENCL 86 +-#define CLKID_VCLK2_OTHER 87 +-#define CLKID_EDP 88 +-#define CLKID_AO_MEDIA_CPU 89 +-#define CLKID_AO_AHB_SRAM 90 +-#define CLKID_AO_AHB_BUS 91 +-#define CLKID_AO_IFACE 92 +-#define CLKID_MPLL0 93 +-#define CLKID_MPLL1 94 +-#define CLKID_MPLL2 95 +- + #define CLK_NR_CLKS 96 + + /* include the CLKIDs that have been made part of the stable DT binding */ +diff --git a/include/dt-bindings/clock/gxbb-aoclkc.h b/include/dt-bindings/clock/gxbb-aoclkc.h +index 31751482d13c..9d15e2221fdb 100644 +--- a/include/dt-bindings/clock/gxbb-aoclkc.h ++++ b/include/dt-bindings/clock/gxbb-aoclkc.h +@@ -62,5 +62,6 @@ + #define CLKID_AO_UART1 3 + #define CLKID_AO_UART2 4 + #define CLKID_AO_IR_BLASTER 5 ++#define CLKID_AO_CEC_32K 6 + + #endif +diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h +index e3e9f7919c31..c04a76d8facf 100644 +--- a/include/dt-bindings/clock/gxbb-clkc.h ++++ b/include/dt-bindings/clock/gxbb-clkc.h +@@ -5,37 +5,96 @@ + #ifndef __GXBB_CLKC_H + #define __GXBB_CLKC_H + ++#define CLKID_SYS_PLL 0 + #define CLKID_HDMI_PLL 2 ++#define CLKID_FIXED_PLL 3 + #define CLKID_FCLK_DIV2 4 + #define CLKID_FCLK_DIV3 5 + #define CLKID_FCLK_DIV4 6 ++#define CLKID_FCLK_DIV5 7 ++#define CLKID_FCLK_DIV7 8 + #define CLKID_GP0_PLL 9 + #define CLKID_CLK81 12 ++#define CLKID_MPLL0 13 ++#define CLKID_MPLL1 14 + #define CLKID_MPLL2 15 ++#define CLKID_DDR 16 ++#define CLKID_DOS 17 ++#define CLKID_ISA 18 ++#define CLKID_PL301 19 ++#define CLKID_PERIPHS 20 + #define CLKID_SPICC 21 + #define CLKID_I2C 22 + #define CLKID_SAR_ADC 23 ++#define CLKID_SMART_CARD 24 + #define CLKID_RNG0 25 + #define CLKID_UART0 26 ++#define CLKID_SDHC 27 ++#define CLKID_STREAM 28 ++#define CLKID_ASYNC_FIFO 29 ++#define CLKID_SDIO 30 ++#define CLKID_ABUF 31 ++#define CLKID_HIU_IFACE 32 ++#define CLKID_ASSIST_MISC 33 + #define CLKID_SPI 34 + #define CLKID_ETH 36 ++#define CLKID_I2S_SPDIF 35 ++#define CLKID_DEMUX 37 + #define CLKID_AIU_GLUE 38 + #define CLKID_IEC958 39 + #define CLKID_I2S_OUT 40 ++#define CLKID_AMCLK 41 ++#define CLKID_AIFIFO2 42 ++#define CLKID_MIXER 43 + #define CLKID_MIXER_IFACE 44 ++#define CLKID_ADC 45 ++#define CLKID_BLKMV 46 + #define CLKID_AIU 47 + #define CLKID_UART1 48 ++#define CLKID_G2D 49 + #define CLKID_USB0 50 + #define CLKID_USB1 51 ++#define CLKID_RESET 52 ++#define CLKID_NAND 53 ++#define CLKID_DOS_PARSER 54 + #define CLKID_USB 55 ++#define CLKID_VDIN1 56 ++#define CLKID_AHB_ARB0 57 ++#define CLKID_EFUSE 58 ++#define CLKID_BOOT_ROM 59 ++#define CLKID_AHB_DATA_BUS 60 ++#define CLKID_AHB_CTRL_BUS 61 ++#define CLKID_HDMI_INTR_SYNC 62 + #define CLKID_HDMI_PCLK 63 + #define CLKID_USB1_DDR_BRIDGE 64 + #define CLKID_USB0_DDR_BRIDGE 65 ++#define CLKID_MMC_PCLK 66 ++#define CLKID_DVIN 67 + #define CLKID_UART2 68 + #define CLKID_SANA 69 ++#define CLKID_VPU_INTR 70 ++#define CLKID_SEC_AHB_AHB3_BRIDGE 71 ++#define CLKID_CLK81_A53 72 ++#define CLKID_VCLK2_VENCI0 73 ++#define CLKID_VCLK2_VENCI1 74 ++#define CLKID_VCLK2_VENCP0 75 ++#define CLKID_VCLK2_VENCP1 76 + #define CLKID_GCLK_VENCI_INT0 77 ++#define CLKID_GCLK_VENCI_INT 78 ++#define CLKID_DAC_CLK 79 + #define CLKID_AOCLK_GATE 80 + #define CLKID_IEC958_GATE 81 ++#define CLKID_ENC480P 82 ++#define CLKID_RNG1 83 ++#define CLKID_GCLK_VENCI_INT1 84 ++#define CLKID_VCLK2_VENCLMCC 85 ++#define CLKID_VCLK2_VENCL 86 ++#define CLKID_VCLK_OTHER 87 ++#define CLKID_EDP 88 ++#define CLKID_AO_MEDIA_CPU 89 ++#define CLKID_AO_AHB_SRAM 90 ++#define CLKID_AO_AHB_BUS 91 ++#define CLKID_AO_IFACE 92 + #define CLKID_AO_I2C 93 + #define CLKID_SD_EMMC_A 94 + #define CLKID_SD_EMMC_B 95 +@@ -50,5 +109,9 @@ + #define CLKID_CTS_AMCLK 107 + #define CLKID_CTS_MCLK_I958 110 + #define CLKID_CTS_I958 113 ++#define CLKID_32K_CLK 114 ++#define CLKID_SD_EMMC_A_CLK0 119 ++#define CLKID_SD_EMMC_B_CLK0 122 ++#define CLKID_SD_EMMC_C_CLK0 125 + + #endif /* __GXBB_CLKC_H */ +diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h +index e29227fb52a1..a9c0306330b6 100644 +--- a/include/dt-bindings/clock/meson8b-clkc.h ++++ b/include/dt-bindings/clock/meson8b-clkc.h +@@ -21,15 +21,85 @@ + #define CLKID_ZERO 13 + #define CLKID_MPEG_SEL 14 + #define CLKID_MPEG_DIV 15 ++#define CLKID_DDR 16 ++#define CLKID_DOS 17 ++#define CLKID_ISA 18 ++#define CLKID_PL301 19 ++#define CLKID_PERIPHS 20 ++#define CLKID_SPICC 21 ++#define CLKID_I2C 22 + #define CLKID_SAR_ADC 23 ++#define CLKID_SMART_CARD 24 + #define CLKID_RNG0 25 ++#define CLKID_UART0 26 ++#define CLKID_SDHC 27 ++#define CLKID_STREAM 28 ++#define CLKID_ASYNC_FIFO 29 + #define CLKID_SDIO 30 ++#define CLKID_ABUF 31 ++#define CLKID_HIU_IFACE 32 ++#define CLKID_ASSIST_MISC 33 ++#define CLKID_SPI 34 ++#define CLKID_I2S_SPDIF 35 + #define CLKID_ETH 36 ++#define CLKID_DEMUX 37 ++#define CLKID_AIU_GLUE 38 ++#define CLKID_IEC958 39 ++#define CLKID_I2S_OUT 40 ++#define CLKID_AMCLK 41 ++#define CLKID_AIFIFO2 42 ++#define CLKID_MIXER 43 ++#define CLKID_MIXER_IFACE 44 ++#define CLKID_ADC 45 ++#define CLKID_BLKMV 46 ++#define CLKID_AIU 47 ++#define CLKID_UART1 48 ++#define CLKID_G2D 49 + #define CLKID_USB0 50 + #define CLKID_USB1 51 ++#define CLKID_RESET 52 ++#define CLKID_NAND 53 ++#define CLKID_DOS_PARSER 54 + #define CLKID_USB 55 ++#define CLKID_VDIN1 56 ++#define CLKID_AHB_ARB0 57 ++#define CLKID_EFUSE 58 ++#define CLKID_BOOT_ROM 59 ++#define CLKID_AHB_DATA_BUS 60 ++#define CLKID_AHB_CTRL_BUS 61 ++#define CLKID_HDMI_INTR_SYNC 62 ++#define CLKID_HDMI_PCLK 63 + #define CLKID_USB1_DDR_BRIDGE 64 + #define CLKID_USB0_DDR_BRIDGE 65 ++#define CLKID_MMC_PCLK 66 ++#define CLKID_DVIN 67 ++#define CLKID_UART2 68 + #define CLKID_SANA 69 ++#define CLKID_VPU_INTR 70 ++#define CLKID_SEC_AHB_AHB3_BRIDGE 71 ++#define CLKID_CLK81_A9 72 ++#define CLKID_VCLK2_VENCI0 73 ++#define CLKID_VCLK2_VENCI1 74 ++#define CLKID_VCLK2_VENCP0 75 ++#define CLKID_VCLK2_VENCP1 76 ++#define CLKID_GCLK_VENCI_INT 77 ++#define CLKID_GCLK_VENCP_INT 78 ++#define CLKID_DAC_CLK 79 ++#define CLKID_AOCLK_GATE 80 ++#define CLKID_IEC958_GATE 81 ++#define CLKID_ENC480P 82 ++#define CLKID_RNG1 83 ++#define CLKID_GCLK_VENCL_INT 84 ++#define CLKID_VCLK2_VENCLMCC 85 ++#define CLKID_VCLK2_VENCL 86 ++#define CLKID_VCLK2_OTHER 87 ++#define CLKID_EDP 88 ++#define CLKID_AO_MEDIA_CPU 89 ++#define CLKID_AO_AHB_SRAM 90 ++#define CLKID_AO_AHB_BUS 91 ++#define CLKID_AO_IFACE 92 ++#define CLKID_MPLL0 93 ++#define CLKID_MPLL1 94 ++#define CLKID_MPLL2 95 + + #endif /* __MESON8B_CLKC_H */ +diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h +index ae26f8105914..f269d833e41a 100644 +--- a/include/dt-bindings/clock/rv1108-cru.h ++++ b/include/dt-bindings/clock/rv1108-cru.h +@@ -43,12 +43,73 @@ + #define SCLK_SDMMC_SAMPLE 84 + #define SCLK_SDIO_SAMPLE 85 + #define SCLK_EMMC_SAMPLE 86 ++#define SCLK_VENC_CORE 87 ++#define SCLK_HEVC_CORE 88 ++#define SCLK_HEVC_CABAC 89 ++#define SCLK_PWM0_PMU 90 ++#define SCLK_I2C0_PMU 91 ++#define SCLK_WIFI 92 ++#define SCLK_CIFOUT 93 ++#define SCLK_MIPI_CSI_OUT 94 ++#define SCLK_CIF0 95 ++#define SCLK_CIF1 96 ++#define SCLK_CIF2 97 ++#define SCLK_CIF3 98 ++#define SCLK_DSP 99 ++#define SCLK_DSP_IOP 100 ++#define SCLK_DSP_EPP 101 ++#define SCLK_DSP_EDP 102 ++#define SCLK_DSP_EDAP 103 ++#define SCLK_CVBS_HOST 104 ++#define SCLK_HDMI_SFR 105 ++#define SCLK_HDMI_CEC 106 ++#define SCLK_CRYPTO 107 ++#define SCLK_SPI 108 ++#define SCLK_SARADC 109 ++#define SCLK_TSADC 110 ++#define SCLK_MACPHY_PRE 111 ++#define SCLK_MACPHY 112 ++#define SCLK_MACPHY_RX 113 ++#define SCLK_MAC_REF 114 ++#define SCLK_MAC_REFOUT 115 ++#define SCLK_DSP_PFM 116 ++#define SCLK_RGA 117 ++#define SCLK_I2C1 118 ++#define SCLK_I2C2 119 ++#define SCLK_I2C3 120 ++#define SCLK_PWM 121 ++#define SCLK_ISP 122 ++#define SCLK_USBPHY 123 ++#define SCLK_I2S0_SRC 124 ++#define SCLK_I2S1_SRC 125 ++#define SCLK_I2S2_SRC 126 ++#define SCLK_UART0_SRC 127 ++#define SCLK_UART1_SRC 128 ++#define SCLK_UART2_SRC 129 ++ ++#define DCLK_VOP_SRC 185 ++#define DCLK_HDMIPHY 186 ++#define DCLK_VOP 187 + + /* aclk gates */ + #define ACLK_DMAC 192 + #define ACLK_PRE 193 + #define ACLK_CORE 194 + #define ACLK_ENMCORE 195 ++#define ACLK_RKVENC 196 ++#define ACLK_RKVDEC 197 ++#define ACLK_VPU 198 ++#define ACLK_CIF0 199 ++#define ACLK_VIO0 200 ++#define ACLK_VIO1 201 ++#define ACLK_VOP 202 ++#define ACLK_IEP 203 ++#define ACLK_RGA 204 ++#define ACLK_ISP 205 ++#define ACLK_CIF1 206 ++#define ACLK_CIF2 207 ++#define ACLK_CIF3 208 ++#define ACLK_PERI 209 + + /* pclk gates */ + #define PCLK_GPIO1 256 +@@ -67,10 +128,23 @@ + #define PCLK_PWM 269 + #define PCLK_TIMER 270 + #define PCLK_PERI 271 ++#define PCLK_GPIO0_PMU 272 ++#define PCLK_I2C0_PMU 273 ++#define PCLK_PWM0_PMU 274 ++#define PCLK_ISP 275 ++#define PCLK_VIO 276 ++#define PCLK_MIPI_DSI 277 ++#define PCLK_HDMI_CTRL 278 ++#define PCLK_SARADC 279 ++#define PCLK_DSP_CFG 280 ++#define PCLK_BUS 281 ++#define PCLK_EFUSE0 282 ++#define PCLK_EFUSE1 283 ++#define PCLK_WDT 284 + + /* hclk gates */ + #define HCLK_I2S0_8CH 320 +-#define HCLK_I2S1_8CH 321 ++#define HCLK_I2S1_2CH 321 + #define HCLK_I2S2_2CH 322 + #define HCLK_NANDC 323 + #define HCLK_SDMMC 324 +@@ -78,20 +152,37 @@ + #define HCLK_EMMC 326 + #define HCLK_PERI 327 + #define HCLK_SFC 328 ++#define HCLK_RKVENC 329 ++#define HCLK_RKVDEC 330 ++#define HCLK_CIF0 331 ++#define HCLK_VIO 332 ++#define HCLK_VOP 333 ++#define HCLK_IEP 334 ++#define HCLK_RGA 335 ++#define HCLK_ISP 336 ++#define HCLK_CRYPTO_MST 337 ++#define HCLK_CRYPTO_SLV 338 ++#define HCLK_HOST0 339 ++#define HCLK_OTG 340 ++#define HCLK_CIF1 341 ++#define HCLK_CIF2 342 ++#define HCLK_CIF3 343 ++#define HCLK_BUS 344 ++#define HCLK_VPU 345 + +-#define CLK_NR_CLKS (HCLK_SFC + 1) ++#define CLK_NR_CLKS (HCLK_VPU + 1) + + /* reset id */ +-#define SRST_CORE_PO_AD 0 ++#define SRST_CORE_PO_AD 0 + #define SRST_CORE_AD 1 + #define SRST_L2_AD 2 +-#define SRST_CPU_NIU_AD 3 ++#define SRST_CPU_NIU_AD 3 + #define SRST_CORE_PO 4 + #define SRST_CORE 5 +-#define SRST_L2 6 ++#define SRST_L2 6 + #define SRST_CORE_DBG 8 + #define PRST_DBG 9 +-#define RST_DAP 10 ++#define RST_DAP 10 + #define PRST_DBG_NIU 11 + #define ARST_STRC_SYS_AD 15 + +@@ -158,9 +249,9 @@ + #define HRST_SYSBUS 75 + #define PRST_USBGRF 76 + +-#define ARST_PERIPH_NIU 80 +-#define HRST_PERIPH_NIU 81 +-#define PRST_PERIPH_NIU 82 ++#define ARST_PERIPH_NIU 80 ++#define HRST_PERIPH_NIU 81 ++#define PRST_PERIPH_NIU 82 + #define HRST_PERIPH 83 + #define HRST_SDMMC 84 + #define HRST_SDIO 85 +@@ -178,7 +269,7 @@ + #define HRST_HOST0_AUX 96 + #define HRST_HOST0_ARB 97 + #define SRST_HOST0_EHCIPHY 98 +-#define SRST_HOST0_UTMI 99 ++#define SRST_HOST0_UTMI 99 + #define SRST_USBPOR 100 + #define SRST_UTMI0 101 + #define SRST_UTMI1 102 +@@ -225,21 +316,21 @@ + #define HRST_VPU_NIU 141 + #define ARST_VPU 142 + #define HRST_VPU 143 +-#define ARST_RKVDEC_NIU 144 +-#define HRST_RKVDEC_NIU 145 ++#define ARST_RKVDEC_NIU 144 ++#define HRST_RKVDEC_NIU 145 + #define ARST_RKVDEC 146 + #define HRST_RKVDEC 147 + #define SRST_RKVDEC_CABAC 148 + #define SRST_RKVDEC_CORE 149 +-#define ARST_RKVENC_NIU 150 +-#define HRST_RKVENC_NIU 151 ++#define ARST_RKVENC_NIU 150 ++#define HRST_RKVENC_NIU 151 + #define ARST_RKVENC 152 + #define HRST_RKVENC 153 + #define SRST_RKVENC_CORE 154 + + #define SRST_DSP_CORE 156 + #define SRST_DSP_SYS 157 +-#define SRST_DSP_GLOBAL 158 ++#define SRST_DSP_GLOBAL 158 + #define SRST_DSP_OECM 159 + #define PRST_DSP_IOP_NIU 160 + #define ARST_DSP_EPP_NIU 161 +@@ -257,7 +348,7 @@ + #define SRST_PMU_I2C0 173 + #define PRST_PMU_I2C0 174 + #define PRST_PMU_GPIO0 175 +-#define PRST_PMU_INTMEM 176 ++#define PRST_PMU_INTMEM 176 + #define PRST_PMU_PWM0 177 + #define SRST_PMU_PWM0 178 + #define PRST_PMU_GRF 179 +diff --git a/include/dt-bindings/genpd/k2g.h b/include/dt-bindings/genpd/k2g.h +deleted file mode 100644 +index 1f31f17e19eb..000000000000 +--- a/include/dt-bindings/genpd/k2g.h ++++ /dev/null +@@ -1,90 +0,0 @@ +-/* +- * TI K2G SoC Device definitions +- * +- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#ifndef _DT_BINDINGS_GENPD_K2G_H +-#define _DT_BINDINGS_GENPD_K2G_H +- +-/* Documented in http://processors.wiki.ti.com/index.php/TISCI */ +- +-#define K2G_DEV_PMMC0 0x0000 +-#define K2G_DEV_MLB0 0x0001 +-#define K2G_DEV_DSS0 0x0002 +-#define K2G_DEV_MCBSP0 0x0003 +-#define K2G_DEV_MCASP0 0x0004 +-#define K2G_DEV_MCASP1 0x0005 +-#define K2G_DEV_MCASP2 0x0006 +-#define K2G_DEV_DCAN0 0x0008 +-#define K2G_DEV_DCAN1 0x0009 +-#define K2G_DEV_EMIF0 0x000a +-#define K2G_DEV_MMCHS0 0x000b +-#define K2G_DEV_MMCHS1 0x000c +-#define K2G_DEV_GPMC0 0x000d +-#define K2G_DEV_ELM0 0x000e +-#define K2G_DEV_SPI0 0x0010 +-#define K2G_DEV_SPI1 0x0011 +-#define K2G_DEV_SPI2 0x0012 +-#define K2G_DEV_SPI3 0x0013 +-#define K2G_DEV_ICSS0 0x0014 +-#define K2G_DEV_ICSS1 0x0015 +-#define K2G_DEV_USB0 0x0016 +-#define K2G_DEV_USB1 0x0017 +-#define K2G_DEV_NSS0 0x0018 +-#define K2G_DEV_PCIE0 0x0019 +-#define K2G_DEV_GPIO0 0x001b +-#define K2G_DEV_GPIO1 0x001c +-#define K2G_DEV_TIMER64_0 0x001d +-#define K2G_DEV_TIMER64_1 0x001e +-#define K2G_DEV_TIMER64_2 0x001f +-#define K2G_DEV_TIMER64_3 0x0020 +-#define K2G_DEV_TIMER64_4 0x0021 +-#define K2G_DEV_TIMER64_5 0x0022 +-#define K2G_DEV_TIMER64_6 0x0023 +-#define K2G_DEV_MSGMGR0 0x0025 +-#define K2G_DEV_BOOTCFG0 0x0026 +-#define K2G_DEV_ARM_BOOTROM0 0x0027 +-#define K2G_DEV_DSP_BOOTROM0 0x0029 +-#define K2G_DEV_DEBUGSS0 0x002b +-#define K2G_DEV_UART0 0x002c +-#define K2G_DEV_UART1 0x002d +-#define K2G_DEV_UART2 0x002e +-#define K2G_DEV_EHRPWM0 0x002f +-#define K2G_DEV_EHRPWM1 0x0030 +-#define K2G_DEV_EHRPWM2 0x0031 +-#define K2G_DEV_EHRPWM3 0x0032 +-#define K2G_DEV_EHRPWM4 0x0033 +-#define K2G_DEV_EHRPWM5 0x0034 +-#define K2G_DEV_EQEP0 0x0035 +-#define K2G_DEV_EQEP1 0x0036 +-#define K2G_DEV_EQEP2 0x0037 +-#define K2G_DEV_ECAP0 0x0038 +-#define K2G_DEV_ECAP1 0x0039 +-#define K2G_DEV_I2C0 0x003a +-#define K2G_DEV_I2C1 0x003b +-#define K2G_DEV_I2C2 0x003c +-#define K2G_DEV_EDMA0 0x003f +-#define K2G_DEV_SEMAPHORE0 0x0040 +-#define K2G_DEV_INTC0 0x0041 +-#define K2G_DEV_GIC0 0x0042 +-#define K2G_DEV_QSPI0 0x0043 +-#define K2G_DEV_ARM_64B_COUNTER0 0x0044 +-#define K2G_DEV_TETRIS0 0x0045 +-#define K2G_DEV_CGEM0 0x0046 +-#define K2G_DEV_MSMC0 0x0047 +-#define K2G_DEV_CBASS0 0x0049 +-#define K2G_DEV_BOARD0 0x004c +-#define K2G_DEV_EDMA1 0x004f +- +-#endif +diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h +index 5c75e80915fc..18ec5df5a581 100644 +--- a/include/dt-bindings/pinctrl/dra.h ++++ b/include/dt-bindings/pinctrl/dra.h +@@ -73,5 +73,8 @@ + */ + #define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val) + ++/* DRA7 IODELAY configuration parameters */ ++#define A_DELAY_PS(val) ((val) & 0xffff) ++#define G_DELAY_PS(val) ((val) & 0xffff) + #endif + +diff --git a/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h b/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h +new file mode 100644 +index 000000000000..1f1b56e57346 +--- /dev/null ++++ b/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h +@@ -0,0 +1,27 @@ ++/* ++ * Copyright (c) 2017 Martin Blumenstingl . ++ * ++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ */ ++ ++#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H ++#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H ++ ++#define CLKC_RESET_L2_CACHE_SOFT_RESET 0 ++#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET 1 ++#define CLKC_RESET_SCU_SOFT_RESET 2 ++#define CLKC_RESET_CPU0_SOFT_RESET 3 ++#define CLKC_RESET_CPU1_SOFT_RESET 4 ++#define CLKC_RESET_CPU2_SOFT_RESET 5 ++#define CLKC_RESET_CPU3_SOFT_RESET 6 ++#define CLKC_RESET_A5_GLOBAL_RESET 7 ++#define CLKC_RESET_A5_AXI_SOFT_RESET 8 ++#define CLKC_RESET_A5_ABP_SOFT_RESET 9 ++#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET 10 ++#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET 11 ++#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST 12 ++#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE 13 ++#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST 14 ++#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE 15 ++ ++#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */ -- 2.54.0